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fpga/mqnic/Alveo: Fix Alveo flash format register

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-11-20 00:18:39 -08:00
parent 179fd275b5
commit 2e8e24f446
2 changed files with 8 additions and 8 deletions
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8
fpga/mqnic/Alveo/fpga_100g/rtl/fpga_core.v
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@ -726,10 +726,10 @@ always @(posedge clk_250mhz) begin
RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // SPI flash ctrl: Next header RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // SPI flash ctrl: Next header
RBB+8'h2C: begin RBB+8'h2C: begin
// SPI flash ctrl: format // SPI flash ctrl: format
ctrl_reg_rd_data_reg[3:0] <= FLASH_SEG_COUNT; // configuration ctrl_reg_rd_data_reg[3:0] <= FLASH_SEG_COUNT; // configuration
ctrl_reg_rd_data_reg[7:4] <= FLASH_SEG_DEFAULT; // default segment ctrl_reg_rd_data_reg[7:4] <= FLASH_SEG_DEFAULT; // default segment
ctrl_reg_rd_data_reg[11:8] <= FLASH_SEG_FALLBACK; // fallback segment ctrl_reg_rd_data_reg[11:8] <= FLASH_SEG_FALLBACK; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= FLASH_SEG0_SIZE; // first segment size ctrl_reg_rd_data_reg[31:12] <= FLASH_SEG0_SIZE >> 12; // first segment size
end end
RBB+8'h30: begin RBB+8'h30: begin
// SPI flash ctrl: control 0 // SPI flash ctrl: control 0

8
fpga/mqnic/Alveo/fpga_25g/rtl/fpga_core.v
View File

@ -727,10 +727,10 @@ always @(posedge clk_250mhz) begin
RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // SPI flash ctrl: Next header RBB+8'h28: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h40; // SPI flash ctrl: Next header
RBB+8'h2C: begin RBB+8'h2C: begin
// SPI flash ctrl: format // SPI flash ctrl: format
ctrl_reg_rd_data_reg[3:0] <= FLASH_SEG_COUNT; // configuration ctrl_reg_rd_data_reg[3:0] <= FLASH_SEG_COUNT; // configuration
ctrl_reg_rd_data_reg[7:4] <= FLASH_SEG_DEFAULT; // default segment ctrl_reg_rd_data_reg[7:4] <= FLASH_SEG_DEFAULT; // default segment
ctrl_reg_rd_data_reg[11:8] <= FLASH_SEG_FALLBACK; // fallback segment ctrl_reg_rd_data_reg[11:8] <= FLASH_SEG_FALLBACK; // fallback segment
ctrl_reg_rd_data_reg[31:12] <= FLASH_SEG0_SIZE; // first segment size ctrl_reg_rd_data_reg[31:12] <= FLASH_SEG0_SIZE >> 12; // first segment size
end end
RBB+8'h30: begin RBB+8'h30: begin
// SPI flash ctrl: control 0 // SPI flash ctrl: control 0