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fpga/mqnic/ZCU102/fpga_zynqmp: Add support for Ubuntu for ZCU102 MPSoC
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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Alex Forencich
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@ -1,28 +1,51 @@
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# Corundum mqnic for ZCU102 using ZynqMP PS as host system
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# Corundum mqnic for ZCU102
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## Introduction
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This design targets the Xilinx ZCU102 FPGA board. The host system of the NIC is
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the Zynq US+ MPSoC.
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This design targets the Xilinx ZCU102 FPGA board.
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* FPGA: xczu9eg-ffvb1156-2-e
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* PHY: 10G BASE-R PHY IP core and internal GTH transceiver
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* RAM: 512 MB DDR4 2400 (256M x16)
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## How to build
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## Quick start for Ubuntu
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Run make in this directory to build the bitstream and the .xsa
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file. Ensure that the Xilinx Vivado toolchain components are in PATH.
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### Build FPGA bitstream
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Then change into sub-directory ps/petalinux/ and build the PetaLinux project.
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Ensure that the Xilinx PetaLinux toolchain components are in PATH.
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Run `make app` in the `fpga` subdirectory to build the bitstream, `.xsa` file, and device tree overlay. Ensure that the Xilinx Vivado toolchain components are in PATH (source `settings64.sh` in Vivado installation directory).
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make -C ps/petalinux/ build-boot
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### Installation
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## How to test
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Download an Ubuntu image for the ZCU102 here: https://ubuntu.com/download/amd-xilinx. Write the image to an SD card with `dd`, for example:
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Copy the following, resulting files of building the PetaLinux project onto an
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SDcard suitable for then booting the ZCU102 in SDcard boot mode.
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xzcat ubuntu.img.xz | dd of=/dev/sdX
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Copy files in `fpga/app` to `/lib/firmware/xilinx/mqnic` on the ZCU102. Also make a copy of the source repo on the ZCU102 from which the kernel module and userspace tools can be built.
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### Build driver and userspace tools
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On the ZCU102, run `make` in `modules/mqnic` to build the driver. Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled. Then run `make` in `utils` to build the userspace tools.
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### Testing
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On the ZCU102, run `sudo xmutil unloadapp` to unload the FPGA, then `sudo xmutil loadapp mqnic` to load the configuration. Then, build the kernel module and userspace tools by running `make` in `modules/mqnic` and `utils`. Finally, load the kernel module with `insmod mqnic.ko`. Check `dmesg` for output from driver initialization. Run `mqnic-dump -d /dev/mqnic0` to dump the internal state.
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## Quick start for PetaLinux
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### Build FPGA bitstream
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Run `make` in the `fpga` subdirectory to build the bitstream and the `.xsa`
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file. Ensure that the Xilinx Vivado toolchain components are in PATH (source `settings64.sh` in Vivado installation directory).
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### Build PetaLinux image
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Then change into sub-directory `ps/petalinux/` and build the PetaLinux project. Ensure that the Xilinx PetaLinux toolchain components are in PATH.
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make -C ps/petalinux/ build-boot
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### Testing
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Copy the following, resulting files of building the PetaLinux project onto an SDcard suitable for then booting the ZCU102 in SDcard boot mode.
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ps/petalinux/images/linux/:
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BOOT.BIN
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@ -31,7 +31,7 @@
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.PHONY: fpga vivado tmpclean clean distclean
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.mcs %.prm
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.PRECIOUS: %.xpr %.bit %.bin %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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@ -71,7 +71,7 @@ tmpclean::
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-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean:: tmpclean
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-rm -rf *.bit *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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-rm -rf *.bit *.bin *.ltx *.xsa program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
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distclean:: clean
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@ -121,19 +121,21 @@ $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT)
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# bit file
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$(PROJECT).bit $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
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$(PROJECT).bit $(PROJECT).bin $(PROJECT).ltx $(PROJECT).xsa: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
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echo "open_project $(PROJECT).xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
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echo "write_bitstream -force -bin_file $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
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echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
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echo "write_hw_platform -fixed -force -include_bit $(PROJECT).xsa" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bin .
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bin rev/$(PROJECT)_rev$$COUNT.bin; \
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi; \
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cp -pv $(PROJECT).xsa rev/$(PROJECT)_rev$$COUNT.xsa;
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@ -139,3 +139,23 @@ program: $(FPGA_TOP).bit
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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APP_DIR = app
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$(APP_DIR)/shell.json:
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@mkdir -p $(@D)
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echo '{"shell_type": "XRT_FLAT", "num_slots": "1"}' > $@
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$(APP_DIR)/$(FPGA_TOP).bin: $(FPGA_TOP).bin
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@mkdir -p $(@D)
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cp $< $@
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$(APP_DIR)/overlay.dtbo: ../ps/overlay.dtsi
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@mkdir -p $(@D)
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dtc -@ -O dtb -o $@ $^
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.PHONY: app
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app: $(APP_DIR)/$(FPGA_TOP).bin $(APP_DIR)/shell.json $(APP_DIR)/overlay.dtbo
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clean::
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-rm -rf $(APP_DIR)
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@ -149,3 +149,23 @@ program: $(FPGA_TOP).bit
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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APP_DIR = app
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$(APP_DIR)/shell.json:
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@mkdir -p $(@D)
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echo '{"shell_type": "XRT_FLAT", "num_slots": "1"}' > $@
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$(APP_DIR)/$(FPGA_TOP).bin: $(FPGA_TOP).bin
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@mkdir -p $(@D)
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cp $< $@
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$(APP_DIR)/overlay.dtbo: ../ps/overlay.dtsi
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@mkdir -p $(@D)
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dtc -@ -O dtb -o $@ $^
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.PHONY: app
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app: $(APP_DIR)/$(FPGA_TOP).bin $(APP_DIR)/shell.json $(APP_DIR)/overlay.dtbo
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clean::
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-rm -rf $(APP_DIR)
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129
fpga/mqnic/ZCU102/fpga/ps/overlay.dtsi
Normal file
129
fpga/mqnic/ZCU102/fpga/ps/overlay.dtsi
Normal file
@ -0,0 +1,129 @@
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/dts-v1/;
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/plugin/;
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/ {
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fragment@0 {
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target = <&fpga_full>;
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__overlay__ {
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#address-cells = <2>;
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#size-cells = <2>;
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firmware-name = "fpga.bin";
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};
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};
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fragment@1 {
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target = <&amba>;
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__overlay__ {
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#address-cells = <2>;
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#size-cells = <2>;
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afi0: afi0 {
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compatible = "xlnx,afi-fpga";
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config-afi =
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// PL-to-PS AXI
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// 0: 128-bit, 1: 64-bit, 2: 32-bit
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<0 0>, // AFIFM0_RDCTRL [1:0] S_AXI_HPC0_FPD
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<1 0>, // AFIFM0_WRCTRL [1:0] S_AXI_HPC0_FPD
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<2 0>, // AFIFM1_RDCTRL [1:0] S_AXI_HPC1_FPD
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<3 0>, // AFIFM1_WRCTRL [1:0] S_AXI_HPC1_FPD
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<4 0>, // AFIFM2_RDCTRL [1:0] S_AXI_HP0_FPD
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<5 0>, // AFIFM2_WRCTRL [1:0] S_AXI_HP0_FPD
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<6 0>, // AFIFM3_RDCTRL [1:0] S_AXI_HP1_FPD
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<7 0>, // AFIFM3_WRCTRL [1:0] S_AXI_HP1_FPD
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<8 0>, // AFIFM4_RDCTRL [1:0] S_AXI_HP2_FPD
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<9 0>, // AFIFM4_WRCTRL [1:0] S_AXI_HP2_FPD
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<10 0>, // AFIFM5_RDCTRL [1:0] S_AXI_HP3_FPD
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<11 0>, // AFIFM5_WRCTRL [1:0] S_AXI_HP3_FPD
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<12 0>, // AFIFM6_RDCTRL [1:0] S_AXI_LPD
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<13 0>, // AFIFM6_WRCTRL [1:0] S_AXI_LPD
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// PS-to-PL AXI
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// 0: 32-bit, 1: 64-bit, 2: 128-bit
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<14 0x000>, // FPD_SLCR [9:8] AFIFS0 M_AXI_HPM0_FPD [11:10] AFIFS1 M_AXI_HPM1_FPD
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<15 0x000>; // LPD_SLCR [9:8] AFIFS2 M_AXI_HPM0_LPD
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};
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mqnic0: ethernet@a0000000 {
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compatible = "corundum,mqnic";
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reg = <0x0 0xa0000000 0x0 0x1000000>,
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<0x0 0xa8000000 0x0 0x1000000>;
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reg-names = "csr", "app";
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interrupt-parent = <&gic>;
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interrupts = <0x0 0x59 0x1>, <0x0 0x5a 0x1>, <0x0 0x5b 0x1>,
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<0x0 0x5c 0x1>;
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assigned-clocks = <&zynqmp_clk 71>, // PL0_REF
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<&si570_2 0>; // MGT SI570 (U56)
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assigned-clock-rates = <300000000>,
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<156250000>;
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resets = <&zynqmp_reset 116>; // ZYNQMP_RESET_PS_PL0
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reset-names = "reset";
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nvmem-cells = <&macaddress>;
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nvmem-cell-names = "mac-address";
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/* NOTE: The nvmem-cells property provides us with a base MAC
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* address. We increment its last byte (default) by 0x1. And we
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* mark the derived address as "locally administrated". The
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* result is used to derive MAC addresses for mqnic interfaces.
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*/
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mac-address-increment = <0x1>;
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mac-address-local;
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module-eeproms = <&module_eeprom_sfp0>, <&module_eeprom_sfp1>,
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<&module_eeprom_sfp2>, <&module_eeprom_sfp3>;
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};
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};
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};
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fragment@2 {
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target = <&eeprom>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <1>;
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macaddress: macaddress@20 {
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/* NOTE: On Xilinx Zynq boards there usually is an
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* EEPROM with a MAC address for one of the PS GEMs at
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* offset 0x20. So we take that address as our base
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* address.
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*/
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reg = <0x20 0x06>;
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};
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};
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};
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fragment@3 {
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target = <&i2c1>;
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__overlay__ {
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i2c-mux@75 {
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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module_eeprom_sfp3: eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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module_eeprom_sfp2: eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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module_eeprom_sfp1: eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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i2c@7 {
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#address-cells = <1>;
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#size-cells = <0>;
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module_eeprom_sfp0: eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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};
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};
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};
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};
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