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Fix backpressure bug in TX checksum module

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This commit is contained in:
Alex Forencich 2020-12-12 21:51:54 -08:00
parent 3240be1dd4
commit 3003b3228d
1 changed files with 1 additions and 1 deletions
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fpga/common/rtl/tx_checksum.v
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@ -185,7 +185,7 @@ wire [USER_WIDTH-1:0] data_out_axis_tuser;
assign s_axis_tready = data_in_axis_tready && csum_in_ready && transfer_in_reg; assign s_axis_tready = data_in_axis_tready && csum_in_ready && transfer_in_reg;
assign s_axis_cmd_ready = !transfer_in_reg; assign s_axis_cmd_ready = csum_in_ready && !transfer_in_reg;
// data FIFO // data FIFO
assign data_in_axis_tdata = s_axis_tdata; assign data_in_axis_tdata = s_axis_tdata;