From 314ea7dbf917f4e81da168cb20ce1bfa8ef64acf Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 12 Apr 2021 22:55:49 -0700 Subject: [PATCH] Update readme --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 51c0897d3..6b27e8ee5 100644 --- a/README.md +++ b/README.md @@ -9,8 +9,8 @@ GitHub repository: https://github.com/alexforencich/verilog-axi ## Introduction Collection of AXI4 and AXI4 lite bus components. Most components are fully -parametrizable in interface widths. Includes full cocotb testbench that -utilizes [cocotbext-axi](https://github.com/alexforencich/cocotbext-axi). +parametrizable in interface widths. Includes full cocotb testbenches that +utilize [cocotbext-axi](https://github.com/alexforencich/cocotbext-axi). ## Documentation