FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

Add pipeline registers, floorplanning constraints for AU250 100G design

Browse Source
This commit is contained in:
Alex Forencich 2020-12-03 15:08:57 -08:00
parent 91edbbf3dc
commit 3240be1dd4
4 changed files with 131 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
fpga/mqnic/AU250/fpga_100g/fpga.xdc
View File

@ -212,3 +212,28 @@ set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_re
create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p]
# Floorplanning constraints
#create_pblock pblock_slr0
#add_cells_to_pblock [get_pblocks pblock_slr0] [get_cells -quiet [list ]]
#resize_pblock [get_pblocks pblock_slr0] -add {SLR0}
create_pblock pblock_slr1
add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list pcie4_uscale_plus_inst]]
add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list core_inst/dma_if_pcie_us_inst]]
add_cells_to_pblock [get_pblocks pblock_slr1] [get_cells -quiet [list core_inst/dma_if_mux_inst]]
resize_pblock [get_pblocks pblock_slr1] -add {SLR1}
create_pblock pblock_slr2
add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet [list qsfp0_cmac_inst qsfp0_cmac_pad_inst]]
add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet [list core_inst/iface[0].mac[0].mac_tx_fifo_inst core_inst/iface[0].mac[0].mac_rx_fifo_inst]]
add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet [list core_inst/iface[0].mac[0].tx_reg/pipe_reg[1].reg_inst core_inst/iface[0].mac[0].rx_reg/pipe_reg[0].reg_inst]]
add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet [list qsfp1_cmac_inst qsfp1_cmac_pad_inst]]
add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet [list core_inst/iface[1].mac[0].mac_tx_fifo_inst core_inst/iface[1].mac[0].mac_rx_fifo_inst]]
add_cells_to_pblock [get_pblocks pblock_slr2] [get_cells -quiet [list core_inst/iface[1].mac[0].tx_reg/pipe_reg[1].reg_inst core_inst/iface[1].mac[0].rx_reg/pipe_reg[0].reg_inst]]
resize_pblock [get_pblocks pblock_slr2] -add {SLR2}
#create_pblock pblock_slr3
#add_cells_to_pblock [get_pblocks pblock_slr3] [get_cells -quiet [list ]]
#resize_pblock [get_pblocks pblock_slr3] -add {SLR3}

1
fpga/mqnic/AU250/fpga_100g/fpga/Makefile
View File

@ -35,6 +35,7 @@ SYN_FILES += lib/axi/rtl/priority_encoder.v
SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_pipeline_register.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v

116
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -2235,6 +2235,98 @@ generate
for (m = 0; m < PORTS_PER_IF; m = m + 1) begin : mac
wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata_pipe;
wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep_pipe;
wire tx_axis_tvalid_pipe;
wire tx_axis_tready_pipe;
wire tx_axis_tlast_pipe;
wire tx_axis_tuser_pipe;
// wire [PTP_TS_WIDTH-1:0] tx_ptp_ts_96_pipe;
// wire tx_ptp_ts_valid_pipe;
// wire tx_ptp_ts_ready_pipe;
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata_pipe;
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep_pipe;
wire rx_axis_tvalid_pipe;
wire rx_axis_tready_pipe;
wire rx_axis_tlast_pipe;
wire rx_axis_tuser_pipe;
// wire [PTP_TS_WIDTH-1:0] rx_ptp_ts_96_pipe;
// wire rx_ptp_ts_valid_pipe;
// wire rx_ptp_ts_ready_pipe;
axis_pipeline_register #(
.DATA_WIDTH(AXIS_DATA_WIDTH),
.KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.KEEP_WIDTH(AXIS_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.REG_TYPE(2),
.LENGTH(2)
)
tx_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
// AXI input
.s_axis_tdata(tx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.s_axis_tkeep(tx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.s_axis_tvalid(tx_axis_tvalid[m +: 1]),
.s_axis_tready(tx_axis_tready[m +: 1]),
.s_axis_tlast(tx_axis_tlast[m +: 1]),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser[m +: 1]),
// AXI output
.m_axis_tdata(tx_axis_tdata_pipe),
.m_axis_tkeep(tx_axis_tkeep_pipe),
.m_axis_tvalid(tx_axis_tvalid_pipe),
.m_axis_tready(tx_axis_tready_pipe),
.m_axis_tlast(tx_axis_tlast_pipe),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_axis_tuser_pipe)
);
axis_pipeline_register #(
.DATA_WIDTH(AXIS_DATA_WIDTH),
.KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.KEEP_WIDTH(AXIS_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.REG_TYPE(2),
.LENGTH(2)
)
rx_reg (
.clk(clk_250mhz),
.rst(rst_250mhz),
// AXI input
.s_axis_tdata(rx_axis_tdata_pipe),
.s_axis_tkeep(rx_axis_tkeep_pipe),
.s_axis_tvalid(rx_axis_tvalid_pipe),
.s_axis_tready(rx_axis_tready_pipe),
.s_axis_tlast(rx_axis_tlast_pipe),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_axis_tuser_pipe),
// AXI output
.m_axis_tdata(rx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.m_axis_tkeep(rx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.m_axis_tvalid(rx_axis_tvalid[m +: 1]),
.m_axis_tready(rx_axis_tready[m +: 1]),
.m_axis_tlast(rx_axis_tlast[m +: 1]),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser[m +: 1])
);
axis_async_fifo #(
.DEPTH(TX_FIFO_DEPTH),
.DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
@ -2256,14 +2348,14 @@ generate
.async_rst(rst_250mhz | port_tx_rst[n*PORTS_PER_IF+m]),
// AXI input
.s_clk(clk_250mhz),
.s_axis_tdata(tx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.s_axis_tkeep(tx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.s_axis_tvalid(tx_axis_tvalid[m +: 1]),
.s_axis_tready(tx_axis_tready[m +: 1]),
.s_axis_tlast(tx_axis_tlast[m +: 1]),
.s_axis_tdata(tx_axis_tdata_pipe),
.s_axis_tkeep(tx_axis_tkeep_pipe),
.s_axis_tvalid(tx_axis_tvalid_pipe),
.s_axis_tready(tx_axis_tready_pipe),
.s_axis_tlast(tx_axis_tlast_pipe),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(tx_axis_tuser[m +: 1]),
.s_axis_tuser(tx_axis_tuser_pipe),
// AXI output
.m_clk(port_tx_clk[n*PORTS_PER_IF+m]),
.m_axis_tdata(port_tx_axis_tdata[(n*PORTS_PER_IF+m)*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]),
@ -2314,14 +2406,14 @@ generate
.s_axis_tuser(port_rx_axis_tuser[n*PORTS_PER_IF+m]),
// AXI output
.m_clk(clk_250mhz),
.m_axis_tdata(rx_axis_tdata[m*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]),
.m_axis_tkeep(rx_axis_tkeep[m*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]),
.m_axis_tvalid(rx_axis_tvalid[m +: 1]),
.m_axis_tready(rx_axis_tready[m +: 1]),
.m_axis_tlast(rx_axis_tlast[m +: 1]),
.m_axis_tdata(rx_axis_tdata_pipe),
.m_axis_tkeep(rx_axis_tkeep_pipe),
.m_axis_tvalid(rx_axis_tvalid_pipe),
.m_axis_tready(rx_axis_tready_pipe),
.m_axis_tlast(rx_axis_tlast_pipe),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(rx_axis_tuser[m +: 1]),
.m_axis_tuser(rx_axis_tuser_pipe),
// Status
.s_status_overflow(),
.s_status_bad_frame(),

1
fpga/mqnic/AU250/fpga_100g/tb/test_fpga_core.py
View File

@ -76,6 +76,7 @@ srcs.append("../lib/axi/rtl/priority_encoder.v")
srcs.append("../lib/axis/rtl/axis_adapter.v")
srcs.append("../lib/axis/rtl/axis_async_fifo.v")
srcs.append("../lib/axis/rtl/axis_fifo.v")
srcs.append("../lib/axis/rtl/axis_pipeline_register.v")
srcs.append("../lib/axis/rtl/axis_register.v")
srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v")
srcs.append("../lib/pcie/rtl/dma_if_pcie_us.v")