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Add Ultrascle PCIe MSI shim
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Alex Forencich
parent
8b3c9ca794
commit
3250740f96
156
rtl/pcie_us_msi.v
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156
rtl/pcie_us_msi.v
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/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* Ultrascale PCIe MSI shim
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*/
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module pcie_us_msi #
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(
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parameter MSI_COUNT = 32
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)
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(
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input wire clk,
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input wire rst,
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/*
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* Interrupt request inputs
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*/
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input wire [MSI_COUNT-1:0] msi_irq,
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/*
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* Interface to Ultrascale PCIe IP core
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*/
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input wire [3:0] cfg_interrupt_msi_enable,
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input wire [7:0] cfg_interrupt_msi_vf_enable,
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input wire [11:0] cfg_interrupt_msi_mmenable,
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input wire cfg_interrupt_msi_mask_update,
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input wire [31:0] cfg_interrupt_msi_data,
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output wire [3:0] cfg_interrupt_msi_select,
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output wire [31:0] cfg_interrupt_msi_int,
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output wire [31:0] cfg_interrupt_msi_pending_status,
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output wire cfg_interrupt_msi_pending_status_data_enable,
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output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
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input wire cfg_interrupt_msi_sent,
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input wire cfg_interrupt_msi_fail,
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output wire [2:0] cfg_interrupt_msi_attr,
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output wire cfg_interrupt_msi_tph_present,
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output wire [1:0] cfg_interrupt_msi_tph_type,
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output wire [8:0] cfg_interrupt_msi_tph_st_tag,
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output wire [3:0] cfg_interrupt_msi_function_number
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);
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reg active_reg = 1'b0, active_next;
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reg [MSI_COUNT-1:0] msi_irq_reg = {MSI_COUNT{1'b0}};
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reg [MSI_COUNT-1:0] msi_irq_last_reg = {MSI_COUNT{1'b0}};
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reg [MSI_COUNT-1:0] msi_irq_active_reg = {MSI_COUNT{1'b0}}, msi_irq_active_next;
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reg [MSI_COUNT-1:0] msi_irq_mask_reg = {MSI_COUNT{1'b0}}, msi_irq_mask_next;
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reg [MSI_COUNT-1:0] msi_int_reg = {MSI_COUNT{1'b0}}, msi_int_next;
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assign cfg_interrupt_msi_select = 4'd0; // request PF0 mask on cfg_interrupt_msi_data
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assign cfg_interrupt_msi_int = msi_int_reg;
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assign cfg_interrupt_msi_pending_status = msi_irq_reg;
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assign cfg_interrupt_msi_pending_status_data_enable = 1'b1; // set PF0 pending status
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assign cfg_interrupt_msi_pending_status_function_num = 4'd0; // set PF0 pending status
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assign cfg_interrupt_msi_attr = 3'd0;
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assign cfg_interrupt_msi_tph_present = 1'b0; // no TPH
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assign cfg_interrupt_msi_tph_type = 2'd0;
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assign cfg_interrupt_msi_tph_st_tag = 9'd0;
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assign cfg_interrupt_msi_function_number = 4'd0; // send MSI for PF0
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wire [MSI_COUNT-1:0] message_enable_mask = cfg_interrupt_msi_mmenable[2:0] > 3'd4 ? {32{1'b1}} : {32{1'b1}} >> (32 - (1 << cfg_interrupt_msi_mmenable[2:0]));
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reg acknowledge;
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wire [MSI_COUNT-1:0] grant;
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wire grant_valid;
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// arbiter instance
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arbiter #(
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.PORTS(MSI_COUNT),
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.TYPE("ROUND_ROBIN"),
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.BLOCK("ACKNOWLEDGE"),
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.LSB_PRIORITY("HIGH")
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)
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arb_inst (
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.clk(clk),
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.rst(rst),
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.request(msi_irq_active_reg & msi_irq_mask_reg & ~grant),
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.acknowledge(acknowledge),
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.grant(grant),
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.grant_valid(grant_valid),
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.grant_encoded()
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);
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always @* begin
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active_next = active_reg;
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msi_irq_active_next = (msi_irq_active_reg | (msi_irq_reg & ~msi_irq_last_reg));
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msi_irq_mask_next = ~cfg_interrupt_msi_data & message_enable_mask & {32{cfg_interrupt_msi_enable}};
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msi_int_next = {MSI_COUNT{1'b0}};
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acknowledge = {MSI_COUNT{1'b0}};
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if (!active_reg) begin
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if (cfg_interrupt_msi_enable && grant_valid) begin
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msi_int_next = grant;
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active_next = 1'b1;
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end
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end else begin
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if (cfg_interrupt_msi_sent || cfg_interrupt_msi_fail) begin
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if (cfg_interrupt_msi_sent) begin
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msi_irq_active_next = msi_irq_active_next & ~grant;
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end
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acknowledge = grant;
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active_next = 1'b0;
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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active_reg <= 1'b0;
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msi_irq_reg <= {MSI_COUNT{1'b0}};
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msi_irq_last_reg <= {MSI_COUNT{1'b0}};
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msi_irq_active_reg <= {MSI_COUNT{1'b0}};
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msi_irq_mask_reg <= {MSI_COUNT{1'b0}};
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msi_int_reg <= {MSI_COUNT{1'b0}};
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end else begin
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active_reg <= active_next;
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msi_irq_reg <= msi_irq;
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msi_irq_last_reg <= msi_irq_reg;
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msi_irq_active_reg <= msi_irq_active_next;
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msi_irq_mask_reg <= msi_irq_mask_next;
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msi_int_reg <= msi_int_next;
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end
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end
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endmodule
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