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Don't reimplement mem_write for MSI and MSI-X

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This commit is contained in:
Alex Forencich 2018-10-15 11:39:33 -07:00
parent 15fdbfeba7
commit 325df5152f
1 changed files with 5 additions and 21 deletions
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26
tb/pcie.py
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@ -1327,7 +1327,7 @@ class MSICapability(object):
# Mask bits
self.msi_mask_bits = byte_mask_update(self.msi_mask_bits, mask, data) & 0xffffffff
def issue_msi_interrupt(self, number=0, attr=0):
def issue_msi_interrupt(self, number=0, attr=0, tc=0):
if not self.msi_enable:
print("MSI disabled")
return
@ -1335,16 +1335,8 @@ class MSICapability(object):
print("MSI message number out of range")
return
tlp = TLP()
tlp.fmt_type = TLP_MEM_WRITE
tlp.requester_id = self.get_id()
tlp.attr = attr
addr = self.msi_message_address
if addr > 0xffffffff:
tlp.fmt_type = TLP_MEM_WRITE_64
tlp.data = [self.msi_message_data & ~(2**self.msi_multiple_message_enable-1) | number]
tlp.set_be(addr, 4)
yield self.send(tlp)
data = self.msi_message_data & ~(2**self.msi_multiple_message_enable-1) | number
yield self.mem_write(self.msi_message_address, struct.pack('<L', data), attr=attr, tc=tc)
class MSIXCapability(object):
@ -1398,20 +1390,12 @@ class MSIXCapability(object):
if mask & 0x8: self.msix_function_mask = (data & 1 << 30 != 0)
if mask & 0x8: self.msix_enable = (data & 1 << 31 != 0)
def issue_msix_interrupt(self, addr, data, attr=0):
def issue_msix_interrupt(self, addr, data, attr=0, tc=0):
if not self.msix_enable:
print("MSI-X disabled")
return
tlp = TLP()
tlp.fmt_type = TLP_MEM_WRITE
tlp.requester_id = self.get_id()
tlp.attr = attr
if addr > 0xffffffff:
tlp.fmt_type = TLP_MEM_WRITE_64
tlp.data = [data]
tlp.set_be(addr, 4)
yield self.send(tlp)
yield self.mem_write(addr, struct.pack('<L', data), attr=attr, tc=tc)
class Function(PMCapability, PCIECapability):