From 32a66ed014662284bbf810ddd4b222893fbbf07d Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Fri, 21 Nov 2014 00:15:30 -0800
Subject: [PATCH] Update readme

---
 README.md | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/README.md b/README.md
index 6914809dd..f976d72d5 100644
--- a/README.md
+++ b/README.md
@@ -14,6 +14,19 @@ intelligent bus cosimulation endpoints.
 
 ## Documentation
 
+### arp module
+
+ARP handling logic with parametrizable retry timeout parameters.
+
+### arp_64 module
+
+ARP handling logic with parametrizable retry timeout parameters and 64 bit
+datapath for 10G Ethernet.
+
+### arp_cache module
+
+Basic LRU cache for ARP entries.  Parametrizable depth.  
+
 ### arp_eth_rx module
 
 ARP frame receiver.
@@ -112,6 +125,18 @@ Supports priority and round-robin arbitration.
 
 Can be generated with arbitrary port counts with ip_arb_mux_64.py.
 
+### ip_complete module
+
+IPv4 module with ARP integration.
+
+Top level for gigabit IP stack.
+
+### ip_complete_64 module
+
+IPv4 module with ARP integration and 64 bit data width for 10G Ethernet.
+
+Top level for 10G IP stack.
+
 ### ip_eth_rx module
 
 IP frame receiver.