FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-02-06 08:38:23 +08:00
Code Issues Projects Releases Wiki Activity

Update readme

Browse Source
This commit is contained in:
Alex Forencich 2014-11-21 00:15:30 -08:00
parent 4a228f06c5
commit 32a66ed014
1 changed files with 25 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
README.md
View File

@ -14,6 +14,19 @@ intelligent bus cosimulation endpoints.
## Documentation ## Documentation
### arp module
ARP handling logic with parametrizable retry timeout parameters.
### arp_64 module
ARP handling logic with parametrizable retry timeout parameters and 64 bit
datapath for 10G Ethernet.
### arp_cache module
Basic LRU cache for ARP entries. Parametrizable depth.
### arp_eth_rx module ### arp_eth_rx module
ARP frame receiver. ARP frame receiver.
@ -112,6 +125,18 @@ Supports priority and round-robin arbitration.
Can be generated with arbitrary port counts with ip_arb_mux_64.py. Can be generated with arbitrary port counts with ip_arb_mux_64.py.
### ip_complete module
IPv4 module with ARP integration.
Top level for gigabit IP stack.
### ip_complete_64 module
IPv4 module with ARP integration and 64 bit data width for 10G Ethernet.
Top level for 10G IP stack.
### ip_eth_rx module ### ip_eth_rx module
IP frame receiver. IP frame receiver.