From 335a5e890badaebb34cefd463fb993d03fa97055 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 31 Dec 2021 14:33:31 -0800 Subject: [PATCH] Initial implementation of shared interface datapath --- fpga/app/template/rtl/mqnic_app_block.v | 82 +- .../template/tb/mqnic_core_pcie_us/Makefile | 10 +- .../test_mqnic_core_pcie_us.py | 10 +- fpga/common/rtl/mqnic_core.v | 883 +++++---- fpga/common/rtl/mqnic_core_axi.v | 6 +- fpga/common/rtl/mqnic_core_pcie.v | 6 +- fpga/common/rtl/mqnic_core_pcie_s10.v | 2 + fpga/common/rtl/mqnic_core_pcie_us.v | 4 +- fpga/common/rtl/mqnic_egress.v | 218 +++ fpga/common/rtl/mqnic_ingress.v | 396 ++++ fpga/common/rtl/mqnic_interface.v | 1383 ++++++------- fpga/common/rtl/mqnic_interface_rx.v | 666 +++++++ fpga/common/rtl/mqnic_interface_tx.v | 659 +++++++ fpga/common/rtl/mqnic_port.v | 1738 ----------------- fpga/common/rtl/mqnic_tx_scheduler_block_rr.v | 16 +- .../rtl/mqnic_tx_scheduler_block_rr_tdma.v | 16 +- fpga/common/rtl/rx_engine.v | 76 +- fpga/common/rtl/rx_fifo.v | 244 +++ fpga/common/rtl/tx_engine.v | 109 +- fpga/common/rtl/tx_fifo.v | 246 +++ fpga/common/rtl/tx_req_mux.v | 284 +++ fpga/common/tb/mqnic_core_axi/Makefile | 10 +- .../tb/mqnic_core_axi/test_mqnic_core_axi.py | 14 +- fpga/common/tb/mqnic_core_pcie_s10/Makefile | 10 +- .../test_mqnic_core_pcie_s10.py | 10 +- fpga/common/tb/mqnic_core_pcie_us/Makefile | 10 +- .../test_mqnic_core_pcie_us.py | 10 +- .../tb/mqnic_core_pcie_us_tdma/Makefile | 10 +- .../test_mqnic_core_pcie_us.py | 10 +- .../ADM_PCIE_9V3/fpga_100g/fpga/Makefile | 10 +- .../ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile | 10 +- .../fpga_100g/tb/fpga_core/Makefile | 10 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 10 +- .../mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile | 10 +- .../ADM_PCIE_9V3/fpga_10g/fpga_tdma/Makefile | 10 +- .../fpga_10g/tb/fpga_core/Makefile | 10 +- .../fpga_10g/tb/fpga_core/test_fpga_core.py | 10 +- .../mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile | 10 +- .../ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile | 10 +- .../fpga_25g/tb/fpga_core/Makefile | 10 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/AU200/fpga_100g/fpga/Makefile | 10 +- .../AU200/fpga_100g/tb/fpga_core/Makefile | 10 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/AU200/fpga_10g/fpga/Makefile | 10 +- .../AU200/fpga_10g/tb/fpga_core/Makefile | 10 +- .../fpga_10g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/AU250/fpga_100g/fpga/Makefile | 10 +- .../AU250/fpga_100g/tb/fpga_core/Makefile | 10 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/AU250/fpga_10g/fpga/Makefile | 10 +- .../AU250/fpga_10g/tb/fpga_core/Makefile | 10 +- .../fpga_10g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/AU280/fpga_100g/fpga/Makefile | 10 +- .../AU280/fpga_100g/tb/fpga_core/Makefile | 10 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/AU280/fpga_10g/fpga/Makefile | 10 +- .../AU280/fpga_10g/tb/fpga_core/Makefile | 10 +- .../fpga_10g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/AU50/fpga_100g/fpga/Makefile | 10 +- .../AU50/fpga_100g/tb/fpga_core/Makefile | 10 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/AU50/fpga_10g/fpga/Makefile | 10 +- .../mqnic/AU50/fpga_10g/tb/fpga_core/Makefile | 10 +- .../fpga_10g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile | 10 +- .../ExaNIC_X10/fpga/tb/fpga_core/Makefile | 10 +- .../fpga/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile | 10 +- .../ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile | 10 +- .../fpga_10g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile | 10 +- .../ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile | 10 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile | 10 +- .../NetFPGA_SUME/fpga/tb/fpga_core/Makefile | 10 +- .../fpga/tb/fpga_core/test_fpga_core.py | 10 +- .../S10MX_DK/fpga_10g/fpga_1sm21b/Makefile | 11 +- .../S10MX_DK/fpga_10g/fpga_1sm21c/Makefile | 11 +- .../S10MX_DK/fpga_10g/tb/fpga_core/Makefile | 10 +- .../fpga_10g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/VCU108/fpga_10g/fpga/Makefile | 10 +- .../VCU108/fpga_10g/tb/fpga_core/Makefile | 10 +- .../fpga_10g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/VCU118/fpga_100g/fpga/Makefile | 10 +- .../VCU118/fpga_100g/tb/fpga_core/Makefile | 10 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/VCU118/fpga_10g/fpga/Makefile | 10 +- .../VCU118/fpga_10g/tb/fpga_core/Makefile | 10 +- .../fpga_10g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile | 10 +- .../VCU1525/fpga_100g/tb/fpga_core/Makefile | 10 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile | 10 +- .../VCU1525/fpga_10g/tb/fpga_core/Makefile | 10 +- .../fpga_10g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile | 10 +- .../ZCU106/fpga_pcie/tb/fpga_core/Makefile | 10 +- .../fpga_pcie/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile | 10 +- fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile | 10 +- .../fb2CG/fpga_100g/tb/fpga_core/Makefile | 10 +- .../fpga_100g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile | 11 +- fpga/mqnic/fb2CG/fpga_10g/fpga_tdma/Makefile | 11 +- .../fb2CG/fpga_10g/tb/fpga_core/Makefile | 10 +- .../fpga_10g/tb/fpga_core/test_fpga_core.py | 10 +- fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile | 11 +- fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile | 11 +- .../fb2CG/fpga_25g/tb/fpga_core/Makefile | 10 +- .../fpga_25g/tb/fpga_core/test_fpga_core.py | 10 +- modules/mqnic/mqnic_hw.h | 2 +- 112 files changed, 4956 insertions(+), 3010 deletions(-) create mode 100644 fpga/common/rtl/mqnic_egress.v create mode 100644 fpga/common/rtl/mqnic_ingress.v create mode 100644 fpga/common/rtl/mqnic_interface_rx.v create mode 100644 fpga/common/rtl/mqnic_interface_tx.v delete mode 100644 fpga/common/rtl/mqnic_port.v create mode 100644 fpga/common/rtl/rx_fifo.v create mode 100644 fpga/common/rtl/tx_fifo.v create mode 100644 fpga/common/rtl/tx_req_mux.v diff --git a/fpga/app/template/rtl/mqnic_app_block.v b/fpga/app/template/rtl/mqnic_app_block.v index a62128927..056b33e10 100644 --- a/fpga/app/template/rtl/mqnic_app_block.v +++ b/fpga/app/template/rtl/mqnic_app_block.v @@ -105,8 +105,12 @@ module mqnic_app_block # parameter AXIS_SYNC_RX_USER_WIDTH = AXIS_RX_USER_WIDTH, // Ethernet interface configuration (interface) - parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH, + parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF), parameter AXIS_IF_KEEP_WIDTH = AXIS_IF_DATA_WIDTH/8, + parameter AXIS_IF_TX_ID_WIDTH = 12, + parameter AXIS_IF_RX_ID_WIDTH = PORTS_PER_IF > 1 ? $clog2(PORTS_PER_IF) : 1, + parameter AXIS_IF_TX_DEST_WIDTH = $clog2(PORTS_PER_IF)+4, + parameter AXIS_IF_RX_DEST_WIDTH = 8, parameter AXIS_IF_TX_USER_WIDTH = AXIS_SYNC_TX_USER_WIDTH, parameter AXIS_IF_RX_USER_WIDTH = AXIS_SYNC_RX_USER_WIDTH, @@ -375,43 +379,51 @@ module mqnic_app_block # /* * Ethernet (internal at interface module) */ - input wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] s_axis_if_tx_tdata, - input wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] s_axis_if_tx_tkeep, - input wire [PORT_COUNT-1:0] s_axis_if_tx_tvalid, - output wire [PORT_COUNT-1:0] s_axis_if_tx_tready, - input wire [PORT_COUNT-1:0] s_axis_if_tx_tlast, - input wire [PORT_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] s_axis_if_tx_tuser, + input wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] s_axis_if_tx_tdata, + input wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] s_axis_if_tx_tkeep, + input wire [IF_COUNT-1:0] s_axis_if_tx_tvalid, + output wire [IF_COUNT-1:0] s_axis_if_tx_tready, + input wire [IF_COUNT-1:0] s_axis_if_tx_tlast, + input wire [IF_COUNT*AXIS_IF_TX_ID_WIDTH-1:0] s_axis_if_tx_tid, + input wire [IF_COUNT*AXIS_IF_TX_DEST_WIDTH-1:0] s_axis_if_tx_tdest, + input wire [IF_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] s_axis_if_tx_tuser, - output wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] m_axis_if_tx_tdata, - output wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] m_axis_if_tx_tkeep, - output wire [PORT_COUNT-1:0] m_axis_if_tx_tvalid, - input wire [PORT_COUNT-1:0] m_axis_if_tx_tready, - output wire [PORT_COUNT-1:0] m_axis_if_tx_tlast, - output wire [PORT_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] m_axis_if_tx_tuser, + output wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] m_axis_if_tx_tdata, + output wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] m_axis_if_tx_tkeep, + output wire [IF_COUNT-1:0] m_axis_if_tx_tvalid, + input wire [IF_COUNT-1:0] m_axis_if_tx_tready, + output wire [IF_COUNT-1:0] m_axis_if_tx_tlast, + output wire [IF_COUNT*AXIS_IF_TX_ID_WIDTH-1:0] m_axis_if_tx_tid, + output wire [IF_COUNT*AXIS_IF_TX_DEST_WIDTH-1:0] m_axis_if_tx_tdest, + output wire [IF_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] m_axis_if_tx_tuser, - input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_if_tx_ptp_ts, - input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_if_tx_ptp_ts_tag, - input wire [PORT_COUNT-1:0] s_axis_if_tx_ptp_ts_valid, - output wire [PORT_COUNT-1:0] s_axis_if_tx_ptp_ts_ready, + input wire [IF_COUNT*PTP_TS_WIDTH-1:0] s_axis_if_tx_ptp_ts, + input wire [IF_COUNT*PTP_TAG_WIDTH-1:0] s_axis_if_tx_ptp_ts_tag, + input wire [IF_COUNT-1:0] s_axis_if_tx_ptp_ts_valid, + output wire [IF_COUNT-1:0] s_axis_if_tx_ptp_ts_ready, - output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] m_axis_if_tx_ptp_ts, - output wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] m_axis_if_tx_ptp_ts_tag, - output wire [PORT_COUNT-1:0] m_axis_if_tx_ptp_ts_valid, - input wire [PORT_COUNT-1:0] m_axis_if_tx_ptp_ts_ready, + output wire [IF_COUNT*PTP_TS_WIDTH-1:0] m_axis_if_tx_ptp_ts, + output wire [IF_COUNT*PTP_TAG_WIDTH-1:0] m_axis_if_tx_ptp_ts_tag, + output wire [IF_COUNT-1:0] m_axis_if_tx_ptp_ts_valid, + input wire [IF_COUNT-1:0] m_axis_if_tx_ptp_ts_ready, - input wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] s_axis_if_rx_tdata, - input wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] s_axis_if_rx_tkeep, - input wire [PORT_COUNT-1:0] s_axis_if_rx_tvalid, - output wire [PORT_COUNT-1:0] s_axis_if_rx_tready, - input wire [PORT_COUNT-1:0] s_axis_if_rx_tlast, - input wire [PORT_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] s_axis_if_rx_tuser, + input wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] s_axis_if_rx_tdata, + input wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] s_axis_if_rx_tkeep, + input wire [IF_COUNT-1:0] s_axis_if_rx_tvalid, + output wire [IF_COUNT-1:0] s_axis_if_rx_tready, + input wire [IF_COUNT-1:0] s_axis_if_rx_tlast, + input wire [IF_COUNT*AXIS_IF_RX_ID_WIDTH-1:0] s_axis_if_rx_tid, + input wire [IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0] s_axis_if_rx_tdest, + input wire [IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] s_axis_if_rx_tuser, - output wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] m_axis_if_rx_tdata, - output wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] m_axis_if_rx_tkeep, - output wire [PORT_COUNT-1:0] m_axis_if_rx_tvalid, - input wire [PORT_COUNT-1:0] m_axis_if_rx_tready, - output wire [PORT_COUNT-1:0] m_axis_if_rx_tlast, - output wire [PORT_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] m_axis_if_rx_tuser, + output wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] m_axis_if_rx_tdata, + output wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] m_axis_if_rx_tkeep, + output wire [IF_COUNT-1:0] m_axis_if_rx_tvalid, + input wire [IF_COUNT-1:0] m_axis_if_rx_tready, + output wire [IF_COUNT-1:0] m_axis_if_rx_tlast, + output wire [IF_COUNT*AXIS_IF_RX_ID_WIDTH-1:0] m_axis_if_rx_tid, + output wire [IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0] m_axis_if_rx_tdest, + output wire [IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] m_axis_if_rx_tuser, /* * Statistics increment output @@ -523,6 +535,8 @@ assign m_axis_if_tx_tkeep = s_axis_if_tx_tkeep; assign m_axis_if_tx_tvalid = s_axis_if_tx_tvalid; assign s_axis_if_tx_tready = m_axis_if_tx_tready; assign m_axis_if_tx_tlast = s_axis_if_tx_tlast; +assign m_axis_if_tx_tid = s_axis_if_tx_tid; +assign m_axis_if_tx_tdest = s_axis_if_tx_tdest; assign m_axis_if_tx_tuser = s_axis_if_tx_tuser; assign m_axis_if_tx_ptp_ts = s_axis_if_tx_ptp_ts; @@ -535,6 +549,8 @@ assign m_axis_if_rx_tkeep = s_axis_if_rx_tkeep; assign m_axis_if_rx_tvalid = s_axis_if_rx_tvalid; assign s_axis_if_rx_tready = m_axis_if_rx_tready; assign m_axis_if_rx_tlast = s_axis_if_rx_tlast; +assign m_axis_if_rx_tid = s_axis_if_rx_tid; +assign m_axis_if_rx_tdest = s_axis_if_rx_tdest; assign m_axis_if_rx_tuser = s_axis_if_rx_tuser; /* diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile index 9e154e81a..8d5425e17 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile @@ -42,7 +42,10 @@ VERILOG_SOURCES += ../../rtl/common/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -53,6 +56,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index b6bfd55dc..d5aab6832 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -594,7 +594,10 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -605,6 +608,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -639,7 +645,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v index 9450ac4fb..3f7a826ce 100644 --- a/fpga/common/rtl/mqnic_core.v +++ b/fpga/common/rtl/mqnic_core.v @@ -38,7 +38,7 @@ either expressed or implied, of The Regents of the University of California. `default_nettype none /* - * FPGA core logic + * mqnic core logic */ module mqnic_core # ( @@ -130,7 +130,7 @@ module mqnic_core # parameter RAM_SEG_DATA_WIDTH = 256*2/RAM_SEG_COUNT, parameter RAM_SEG_ADDR_WIDTH = 12, parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8, - parameter IF_RAM_SEL_WIDTH = PORTS_PER_IF > 1 ? $clog2(PORTS_PER_IF) : 1, + parameter IF_RAM_SEL_WIDTH = 1, parameter RAM_SEL_WIDTH = $clog2(IF_COUNT+(APP_ENABLE && APP_DMA_ENABLE ? 1 : 0))+IF_RAM_SEL_WIDTH+1, parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH), parameter RAM_PIPELINE = 2, @@ -155,6 +155,7 @@ module mqnic_core # parameter AXIS_DATA_WIDTH = 512, parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH, + parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF), parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1, parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, parameter AXIS_RX_USE_READY = 0, @@ -376,10 +377,18 @@ parameter IF_COUNT_INT = IF_COUNT+(APP_ENABLE && APP_DMA_ENABLE ? 1 : 0); parameter IF_DMA_TAG_WIDTH = DMA_TAG_WIDTH-$clog2(IF_COUNT_INT)-1; +parameter AXIS_TX_ID_WIDTH = TX_QUEUE_INDEX_WIDTH; +parameter AXIS_TX_DEST_WIDTH = 4; +parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH; + parameter AXIS_SYNC_KEEP_WIDTH = AXIS_SYNC_DATA_WIDTH/(AXIS_DATA_WIDTH/AXIS_KEEP_WIDTH); -parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH; -parameter AXIS_IF_KEEP_WIDTH = AXIS_SYNC_KEEP_WIDTH; +parameter AXIS_IF_KEEP_WIDTH = AXIS_IF_DATA_WIDTH/(AXIS_DATA_WIDTH/AXIS_KEEP_WIDTH); + +parameter AXIS_IF_TX_ID_WIDTH = AXIS_TX_ID_WIDTH; +parameter AXIS_IF_RX_ID_WIDTH = PORTS_PER_IF > 1 ? $clog2(PORTS_PER_IF) : 1; +parameter AXIS_IF_TX_DEST_WIDTH = $clog2(PORTS_PER_IF)+AXIS_TX_DEST_WIDTH; +parameter AXIS_IF_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH; parameter AXIS_IF_TX_USER_WIDTH = AXIS_TX_USER_WIDTH; parameter AXIS_IF_RX_USER_WIDTH = AXIS_RX_USER_WIDTH; @@ -2057,74 +2066,79 @@ wire [PORT_COUNT-1:0] app_m_axis_sync_rx_tready; wire [PORT_COUNT-1:0] app_m_axis_sync_rx_tlast; wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] app_m_axis_sync_rx_tuser; -wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] app_s_axis_if_tx_tdata; -wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] app_s_axis_if_tx_tkeep; -wire [PORT_COUNT-1:0] app_s_axis_if_tx_tvalid; -wire [PORT_COUNT-1:0] app_s_axis_if_tx_tready; -wire [PORT_COUNT-1:0] app_s_axis_if_tx_tlast; -wire [PORT_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] app_s_axis_if_tx_tuser; +wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] app_s_axis_if_tx_tdata; +wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] app_s_axis_if_tx_tkeep; +wire [IF_COUNT-1:0] app_s_axis_if_tx_tvalid; +wire [IF_COUNT-1:0] app_s_axis_if_tx_tready; +wire [IF_COUNT-1:0] app_s_axis_if_tx_tlast; +wire [IF_COUNT*AXIS_IF_TX_ID_WIDTH-1:0] app_s_axis_if_tx_tid; +wire [IF_COUNT*AXIS_IF_TX_DEST_WIDTH-1:0] app_s_axis_if_tx_tdest; +wire [IF_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] app_s_axis_if_tx_tuser; -wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] app_m_axis_if_tx_tdata; -wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] app_m_axis_if_tx_tkeep; -wire [PORT_COUNT-1:0] app_m_axis_if_tx_tvalid; -wire [PORT_COUNT-1:0] app_m_axis_if_tx_tready; -wire [PORT_COUNT-1:0] app_m_axis_if_tx_tlast; -wire [PORT_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] app_m_axis_if_tx_tuser; +wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] app_m_axis_if_tx_tdata; +wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] app_m_axis_if_tx_tkeep; +wire [IF_COUNT-1:0] app_m_axis_if_tx_tvalid; +wire [IF_COUNT-1:0] app_m_axis_if_tx_tready; +wire [IF_COUNT-1:0] app_m_axis_if_tx_tlast; +wire [IF_COUNT*AXIS_IF_TX_ID_WIDTH-1:0] app_m_axis_if_tx_tid; +wire [IF_COUNT*AXIS_IF_TX_DEST_WIDTH-1:0] app_m_axis_if_tx_tdest; +wire [IF_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] app_m_axis_if_tx_tuser; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_s_axis_if_tx_ptp_ts; -wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] app_s_axis_if_tx_ptp_ts_tag; -wire [PORT_COUNT-1:0] app_s_axis_if_tx_ptp_ts_valid; -wire [PORT_COUNT-1:0] app_s_axis_if_tx_ptp_ts_ready; +wire [IF_COUNT*PTP_TS_WIDTH-1:0] app_s_axis_if_tx_ptp_ts; +wire [IF_COUNT*PTP_TAG_WIDTH-1:0] app_s_axis_if_tx_ptp_ts_tag; +wire [IF_COUNT-1:0] app_s_axis_if_tx_ptp_ts_valid; +wire [IF_COUNT-1:0] app_s_axis_if_tx_ptp_ts_ready; -wire [PORT_COUNT*PTP_TS_WIDTH-1:0] app_m_axis_if_tx_ptp_ts; -wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] app_m_axis_if_tx_ptp_ts_tag; -wire [PORT_COUNT-1:0] app_m_axis_if_tx_ptp_ts_valid; -wire [PORT_COUNT-1:0] app_m_axis_if_tx_ptp_ts_ready; +wire [IF_COUNT*PTP_TS_WIDTH-1:0] app_m_axis_if_tx_ptp_ts; +wire [IF_COUNT*PTP_TAG_WIDTH-1:0] app_m_axis_if_tx_ptp_ts_tag; +wire [IF_COUNT-1:0] app_m_axis_if_tx_ptp_ts_valid; +wire [IF_COUNT-1:0] app_m_axis_if_tx_ptp_ts_ready; -wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] app_s_axis_if_rx_tdata; -wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] app_s_axis_if_rx_tkeep; -wire [PORT_COUNT-1:0] app_s_axis_if_rx_tvalid; -wire [PORT_COUNT-1:0] app_s_axis_if_rx_tready; -wire [PORT_COUNT-1:0] app_s_axis_if_rx_tlast; -wire [PORT_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] app_s_axis_if_rx_tuser; +wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] app_s_axis_if_rx_tdata; +wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] app_s_axis_if_rx_tkeep; +wire [IF_COUNT-1:0] app_s_axis_if_rx_tvalid; +wire [IF_COUNT-1:0] app_s_axis_if_rx_tready; +wire [IF_COUNT-1:0] app_s_axis_if_rx_tlast; +wire [IF_COUNT*AXIS_IF_RX_ID_WIDTH-1:0] app_s_axis_if_rx_tid; +wire [IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0] app_s_axis_if_rx_tdest; +wire [IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] app_s_axis_if_rx_tuser; -wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] app_m_axis_if_rx_tdata; -wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] app_m_axis_if_rx_tkeep; -wire [PORT_COUNT-1:0] app_m_axis_if_rx_tvalid; -wire [PORT_COUNT-1:0] app_m_axis_if_rx_tready; -wire [PORT_COUNT-1:0] app_m_axis_if_rx_tlast; -wire [PORT_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] app_m_axis_if_rx_tuser; +wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] app_m_axis_if_rx_tdata; +wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] app_m_axis_if_rx_tkeep; +wire [IF_COUNT-1:0] app_m_axis_if_rx_tvalid; +wire [IF_COUNT-1:0] app_m_axis_if_rx_tready; +wire [IF_COUNT-1:0] app_m_axis_if_rx_tlast; +wire [IF_COUNT*AXIS_IF_RX_ID_WIDTH-1:0] app_m_axis_if_rx_tid; +wire [IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0] app_m_axis_if_rx_tdest; +wire [IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] app_m_axis_if_rx_tuser; generate genvar m, n; for (n = 0; n < IF_COUNT; n = n + 1) begin : iface - wire [PORTS_PER_IF*AXIS_SYNC_DATA_WIDTH-1:0] if_tx_axis_tdata; - wire [PORTS_PER_IF*AXIS_SYNC_KEEP_WIDTH-1:0] if_tx_axis_tkeep; - wire [PORTS_PER_IF-1:0] if_tx_axis_tvalid; - wire [PORTS_PER_IF-1:0] if_tx_axis_tready; - wire [PORTS_PER_IF-1:0] if_tx_axis_tlast; - // wire [PORTS_PER_IF*AXIS_TX_USER_WIDTH-1:0] if_tx_axis_tuser; - wire [PORTS_PER_IF-1:0] if_tx_axis_tuser; + wire [AXIS_IF_DATA_WIDTH-1:0] if_tx_axis_tdata; + wire [AXIS_IF_KEEP_WIDTH-1:0] if_tx_axis_tkeep; + wire if_tx_axis_tvalid; + wire if_tx_axis_tready; + wire if_tx_axis_tlast; + wire [AXIS_IF_TX_ID_WIDTH-1:0] if_tx_axis_tid; + wire [AXIS_IF_TX_DEST_WIDTH-1:0] if_tx_axis_tdest; + wire [AXIS_IF_TX_USER_WIDTH-1:0] if_tx_axis_tuser; - wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] if_tx_ptp_ts_96; - wire [PORTS_PER_IF*PTP_TAG_WIDTH-1:0] if_tx_ptp_ts_tag; - wire [PORTS_PER_IF-1:0] if_tx_ptp_ts_valid; - wire [PORTS_PER_IF-1:0] if_tx_ptp_ts_ready; + wire [PTP_TS_WIDTH-1:0] if_tx_ptp_ts; + wire [PTP_TAG_WIDTH-1:0] if_tx_ptp_ts_tag; + wire if_tx_ptp_ts_valid; + wire if_tx_ptp_ts_ready; - wire [PORTS_PER_IF*AXIS_SYNC_DATA_WIDTH-1:0] if_rx_axis_tdata; - wire [PORTS_PER_IF*AXIS_SYNC_KEEP_WIDTH-1:0] if_rx_axis_tkeep; - wire [PORTS_PER_IF-1:0] if_rx_axis_tvalid; - wire [PORTS_PER_IF-1:0] if_rx_axis_tready; - wire [PORTS_PER_IF-1:0] if_rx_axis_tlast; - // wire [PORTS_PER_IF*AXIS_RX_USER_WIDTH-1:0] if_rx_axis_tuser; - wire [PORTS_PER_IF-1:0] if_rx_axis_tuser; - wire [PORTS_PER_IF*AXIS_RX_USER_WIDTH-1:0] if_rx_axis_tuser_int; - - wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] if_rx_ptp_ts_96; - wire [PORTS_PER_IF-1:0] if_rx_ptp_ts_valid; - wire [PORTS_PER_IF-1:0] if_rx_ptp_ts_ready; + wire [AXIS_IF_DATA_WIDTH-1:0] if_rx_axis_tdata; + wire [AXIS_IF_KEEP_WIDTH-1:0] if_rx_axis_tkeep; + wire if_rx_axis_tvalid; + wire if_rx_axis_tready; + wire if_rx_axis_tlast; + wire [AXIS_IF_RX_ID_WIDTH-1:0] if_rx_axis_tid; + wire [AXIS_IF_RX_DEST_WIDTH-1:0] if_rx_axis_tdest; + wire [AXIS_IF_RX_USER_WIDTH-1:0] if_rx_axis_tuser; mqnic_interface #( .PORTS(PORTS_PER_IF), @@ -2147,12 +2161,17 @@ generate .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .TX_MAX_DESC_REQ(16), + .TX_DESC_FIFO_SIZE(16*8), + .RX_MAX_DESC_REQ(16), + .RX_DESC_FIFO_SIZE(16*8), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), .INT_WIDTH(8), .QUEUE_PTR_WIDTH(16), .LOG_QUEUE_SIZE_WIDTH(4), + .LOG_BLOCK_SIZE_WIDTH(2), .PTP_TS_ENABLE(PTP_TS_ENABLE), .PTP_TS_WIDTH(PTP_TS_WIDTH), .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), @@ -2169,8 +2188,14 @@ generate .RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH), .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), .RAM_PIPELINE(RAM_PIPELINE), - .AXIS_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH), - .AXIS_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH), + .AXIS_DATA_WIDTH(AXIS_IF_DATA_WIDTH), + .AXIS_KEEP_WIDTH(AXIS_IF_KEEP_WIDTH), + .AXIS_TX_ID_WIDTH(AXIS_IF_TX_ID_WIDTH), + .AXIS_RX_ID_WIDTH(AXIS_IF_RX_ID_WIDTH), + .AXIS_TX_DEST_WIDTH(AXIS_IF_TX_DEST_WIDTH), + .AXIS_RX_DEST_WIDTH(AXIS_IF_RX_DEST_WIDTH), + .AXIS_TX_USER_WIDTH(AXIS_IF_TX_USER_WIDTH), + .AXIS_RX_USER_WIDTH(AXIS_IF_RX_USER_WIDTH), .MAX_TX_SIZE(MAX_TX_SIZE), .MAX_RX_SIZE(MAX_RX_SIZE), .TX_RAM_SIZE(TX_RAM_SIZE), @@ -2342,12 +2367,15 @@ generate .tx_axis_tvalid(if_tx_axis_tvalid), .tx_axis_tready(if_tx_axis_tready), .tx_axis_tlast(if_tx_axis_tlast), + .tx_axis_tid(if_tx_axis_tid), + .tx_axis_tdest(if_tx_axis_tdest), .tx_axis_tuser(if_tx_axis_tuser), /* * Transmit timestamp input */ - .s_axis_tx_ptp_ts_96(if_tx_ptp_ts_96), + .s_axis_tx_ptp_ts(if_tx_ptp_ts), + .s_axis_tx_ptp_ts_tag(if_tx_ptp_ts_tag), .s_axis_tx_ptp_ts_valid(if_tx_ptp_ts_valid), .s_axis_tx_ptp_ts_ready(if_tx_ptp_ts_ready), @@ -2359,15 +2387,10 @@ generate .rx_axis_tvalid(if_rx_axis_tvalid), .rx_axis_tready(if_rx_axis_tready), .rx_axis_tlast(if_rx_axis_tlast), + .rx_axis_tid(if_rx_axis_tid), + .rx_axis_tdest(if_rx_axis_tdest), .rx_axis_tuser(if_rx_axis_tuser), - /* - * Receive timestamp input - */ - .s_axis_rx_ptp_ts_96(if_rx_ptp_ts_96), - .s_axis_rx_ptp_ts_valid(if_rx_ptp_ts_valid), - .s_axis_rx_ptp_ts_ready(if_rx_ptp_ts_ready), - /* * PTP clock */ @@ -2380,6 +2403,338 @@ generate .msi_irq(if_msi_irq[n]) ); + wire [PORTS_PER_IF*PTP_TS_WIDTH-1:0] axis_tx_if_ptp_ts; + wire [PORTS_PER_IF*PTP_TAG_WIDTH-1:0] axis_tx_if_ptp_ts_tag; + wire [PORTS_PER_IF-1:0] axis_tx_if_ptp_ts_valid; + wire [PORTS_PER_IF-1:0] axis_tx_if_ptp_ts_ready; + + if (PTP_TS_ENABLE) begin: ptp + + wire [PTP_TS_WIDTH-1:0] axis_tx_ptp_ts; + wire [PTP_TAG_WIDTH-1:0] axis_tx_ptp_ts_tag; + wire axis_tx_ptp_ts_valid; + wire axis_tx_ptp_ts_ready; + + if (PORTS_PER_IF > 1) begin + + axis_arb_mux #( + .S_COUNT(PORTS_PER_IF), + .DATA_WIDTH(PTP_TS_WIDTH), + .KEEP_ENABLE(0), + .ID_ENABLE(1), + .S_ID_WIDTH(PTP_TAG_WIDTH), + .M_ID_WIDTH(PTP_TAG_WIDTH), + .DEST_ENABLE(0), + .USER_ENABLE(0), + .LAST_ENABLE(0), + .UPDATE_TID(0), + .ARB_TYPE_ROUND_ROBIN(1'b1), + .ARB_LSB_HIGH_PRIORITY(1'b1) + ) + tx_ptp_ts_mux_inst ( + .clk(clk), + .rst(rst), + + // AXI Stream inputs + .s_axis_tdata(axis_tx_if_ptp_ts), + .s_axis_tkeep(0), + .s_axis_tvalid(axis_tx_if_ptp_ts_valid), + .s_axis_tready(axis_tx_if_ptp_ts_ready), + .s_axis_tlast(0), + .s_axis_tid(axis_tx_if_ptp_ts_tag), + .s_axis_tdest(0), + .s_axis_tuser(0), + + // AXI Stream output + .m_axis_tdata(axis_tx_ptp_ts), + .m_axis_tkeep(), + .m_axis_tvalid(axis_tx_ptp_ts_valid), + .m_axis_tready(axis_tx_ptp_ts_ready), + .m_axis_tlast(), + .m_axis_tid(axis_tx_ptp_ts_tag), + .m_axis_tdest(), + .m_axis_tuser() + ); + + end else begin + + assign axis_tx_ptp_ts = axis_tx_if_ptp_ts; + assign axis_tx_ptp_ts_tag = axis_tx_if_ptp_ts_tag; + assign axis_tx_ptp_ts_valid = axis_tx_if_ptp_ts_valid; + assign axis_tx_if_ptp_ts_ready = axis_tx_ptp_ts_ready; + + end + + if (APP_ENABLE && APP_AXIS_IF_ENABLE) begin + + assign app_s_axis_if_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = axis_tx_ptp_ts; + assign app_s_axis_if_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = axis_tx_ptp_ts_tag; + assign app_s_axis_if_tx_ptp_ts_valid[n] = axis_tx_ptp_ts_valid; + assign axis_tx_ptp_ts_ready = app_s_axis_if_tx_ptp_ts_ready[n]; + + assign if_tx_ptp_ts = app_m_axis_if_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]; + assign if_tx_ptp_ts_tag = app_m_axis_if_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; + assign if_tx_ptp_ts_valid = app_m_axis_if_tx_ptp_ts_valid[n]; + assign app_m_axis_if_tx_ptp_ts_ready[n] = if_tx_ptp_ts_ready; + + end else begin + + assign app_s_axis_if_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = 0; + assign app_s_axis_if_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = 0; + assign app_s_axis_if_tx_ptp_ts_valid[n] = 0; + + assign app_m_axis_if_tx_ptp_ts_ready[n] = 0; + + assign if_tx_ptp_ts = axis_tx_ptp_ts; + assign if_tx_ptp_ts_tag = axis_tx_ptp_ts_tag; + assign if_tx_ptp_ts_valid = axis_tx_ptp_ts_valid; + assign axis_tx_ptp_ts_ready = if_tx_ptp_ts_ready; + + end + + end else begin + + assign if_tx_ptp_ts = 0; + assign if_tx_ptp_ts_tag = 0; + assign if_tx_ptp_ts_valid = 0; + + assign app_s_axis_if_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = 0; + assign app_s_axis_if_tx_ptp_ts_tag[n*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = 0; + assign app_s_axis_if_tx_ptp_ts_valid[n] = 0; + + assign app_m_axis_if_tx_ptp_ts_ready[n] = 0; + + end + + // TX FIFO + + wire [AXIS_IF_DATA_WIDTH-1:0] axis_if_tx_tdata; + wire [AXIS_IF_KEEP_WIDTH-1:0] axis_if_tx_tkeep; + wire axis_if_tx_tvalid; + wire axis_if_tx_tready; + wire axis_if_tx_tlast; + wire [AXIS_IF_TX_ID_WIDTH-1:0] axis_if_tx_tid; + wire [AXIS_IF_TX_DEST_WIDTH-1:0] axis_if_tx_tdest; + wire [AXIS_IF_TX_USER_WIDTH-1:0] axis_if_tx_tuser; + + wire [PORTS_PER_IF*AXIS_SYNC_DATA_WIDTH-1:0] axis_if_tx_fifo_tdata; + wire [PORTS_PER_IF*AXIS_SYNC_KEEP_WIDTH-1:0] axis_if_tx_fifo_tkeep; + wire [PORTS_PER_IF-1:0] axis_if_tx_fifo_tvalid; + wire [PORTS_PER_IF-1:0] axis_if_tx_fifo_tready; + wire [PORTS_PER_IF-1:0] axis_if_tx_fifo_tlast; + wire [PORTS_PER_IF*AXIS_TX_ID_WIDTH-1:0] axis_if_tx_fifo_tid; + wire [PORTS_PER_IF*AXIS_TX_USER_WIDTH-1:0] axis_if_tx_fifo_tuser; + + if (APP_ENABLE && APP_AXIS_IF_ENABLE) begin + + assign app_s_axis_if_tx_tdata[n*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH] = if_tx_axis_tdata; + assign app_s_axis_if_tx_tkeep[n*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH] = if_tx_axis_tkeep; + assign app_s_axis_if_tx_tvalid[n +: 1] = if_tx_axis_tvalid; + assign if_tx_axis_tready = app_s_axis_if_tx_tready[n +: 1]; + assign app_s_axis_if_tx_tlast[n +: 1] = if_tx_axis_tlast; + assign app_s_axis_if_tx_tid[n*AXIS_IF_TX_ID_WIDTH +: AXIS_IF_TX_ID_WIDTH] = if_tx_axis_tid; + assign app_s_axis_if_tx_tdest[n*AXIS_IF_TX_DEST_WIDTH +: AXIS_IF_TX_DEST_WIDTH] = if_tx_axis_tdest; + assign app_s_axis_if_tx_tuser[n*AXIS_IF_TX_USER_WIDTH +: AXIS_IF_TX_USER_WIDTH] = if_tx_axis_tuser; + + assign axis_if_tx_tdata = app_m_axis_if_tx_tdata[n*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH]; + assign axis_if_tx_tkeep = app_m_axis_if_tx_tkeep[n*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH]; + assign axis_if_tx_tvalid = app_m_axis_if_tx_tvalid[n]; + assign app_m_axis_if_tx_tready[n +: 1] = axis_if_tx_tready; + assign axis_if_tx_tlast = app_m_axis_if_tx_tlast[n]; + assign axis_if_tx_tid = app_m_axis_if_tx_tid[n*AXIS_IF_TX_ID_WIDTH +: AXIS_IF_TX_ID_WIDTH]; + assign axis_if_tx_tdest = app_m_axis_if_tx_tdest[n*AXIS_IF_TX_DEST_WIDTH +: AXIS_IF_TX_DEST_WIDTH]; + assign axis_if_tx_tuser = app_m_axis_if_tx_tuser[n*AXIS_IF_TX_USER_WIDTH +: AXIS_IF_TX_USER_WIDTH]; + + end else begin + + assign app_s_axis_if_tx_tdata[n*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH] = 0; + assign app_s_axis_if_tx_tkeep[n*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH] = 0; + assign app_s_axis_if_tx_tvalid[n +: 1] = 0; + assign app_s_axis_if_tx_tlast[n +: 1] = 0; + assign app_s_axis_if_tx_tid[n*AXIS_IF_TX_ID_WIDTH +: AXIS_IF_TX_ID_WIDTH] = 0; + assign app_s_axis_if_tx_tdest[n*AXIS_IF_TX_DEST_WIDTH +: AXIS_IF_TX_DEST_WIDTH] = 0; + assign app_s_axis_if_tx_tuser[n*AXIS_IF_TX_USER_WIDTH +: AXIS_IF_TX_USER_WIDTH] = 0; + + assign app_m_axis_if_tx_tready[n +: 1] = 0; + + assign axis_if_tx_tdata = if_tx_axis_tdata; + assign axis_if_tx_tkeep = if_tx_axis_tkeep; + assign axis_if_tx_tvalid = if_tx_axis_tvalid; + assign if_tx_axis_tready = axis_if_tx_tready; + assign axis_if_tx_tlast = if_tx_axis_tlast; + assign axis_if_tx_tid = if_tx_axis_tid; + assign axis_if_tx_tdest = if_tx_axis_tdest; + assign axis_if_tx_tuser = if_tx_axis_tuser; + + end + + tx_fifo #( + .FIFO_DEPTH(TX_FIFO_DEPTH), + .PORTS(PORTS_PER_IF), + .S_DATA_WIDTH(AXIS_IF_DATA_WIDTH), + .S_KEEP_ENABLE(AXIS_IF_KEEP_WIDTH > 1), + .S_KEEP_WIDTH(AXIS_IF_KEEP_WIDTH), + .M_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH), + .M_KEEP_ENABLE(AXIS_SYNC_KEEP_WIDTH > 1), + .M_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH), + .ID_ENABLE(1), + .ID_WIDTH(AXIS_IF_TX_ID_WIDTH), + .S_DEST_WIDTH(AXIS_IF_TX_DEST_WIDTH), + .M_DEST_WIDTH(AXIS_TX_DEST_WIDTH), + .USER_ENABLE(1), + .USER_WIDTH(AXIS_IF_TX_USER_WIDTH), + .PIPELINE_OUTPUT(AXIS_TX_FIFO_PIPELINE) + ) + tx_fifo_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI Stream input + */ + .s_axis_tdata(axis_if_tx_tdata), + .s_axis_tkeep(axis_if_tx_tkeep), + .s_axis_tvalid(axis_if_tx_tvalid), + .s_axis_tready(axis_if_tx_tready), + .s_axis_tlast(axis_if_tx_tlast), + .s_axis_tid(axis_if_tx_tid), + .s_axis_tdest(axis_if_tx_tdest), + .s_axis_tuser(axis_if_tx_tuser), + + /* + * AXI Stream outputs + */ + .m_axis_tdata(axis_if_tx_fifo_tdata), + .m_axis_tkeep(axis_if_tx_fifo_tkeep), + .m_axis_tvalid(axis_if_tx_fifo_tvalid), + .m_axis_tready(axis_if_tx_fifo_tready), + .m_axis_tlast(axis_if_tx_fifo_tlast), + .m_axis_tid(axis_if_tx_fifo_tid), + .m_axis_tdest(), + .m_axis_tuser(axis_if_tx_fifo_tuser), + + /* + * Status + */ + .status_overflow(), + .status_bad_frame(), + .status_good_frame() + ); + + // RX FIFO + + wire [PORTS_PER_IF*AXIS_SYNC_DATA_WIDTH-1:0] axis_if_rx_fifo_tdata; + wire [PORTS_PER_IF*AXIS_SYNC_KEEP_WIDTH-1:0] axis_if_rx_fifo_tkeep; + wire [PORTS_PER_IF-1:0] axis_if_rx_fifo_tvalid; + wire [PORTS_PER_IF-1:0] axis_if_rx_fifo_tready; + wire [PORTS_PER_IF-1:0] axis_if_rx_fifo_tlast; + wire [PORTS_PER_IF*AXIS_RX_DEST_WIDTH-1:0] axis_if_rx_fifo_tdest = 0; + wire [PORTS_PER_IF*AXIS_IF_RX_USER_WIDTH-1:0] axis_if_rx_fifo_tuser; + + wire [AXIS_IF_DATA_WIDTH-1:0] axis_if_rx_tdata; + wire [AXIS_IF_KEEP_WIDTH-1:0] axis_if_rx_tkeep; + wire axis_if_rx_tvalid; + wire axis_if_rx_tready; + wire axis_if_rx_tlast; + wire [AXIS_IF_RX_ID_WIDTH-1:0] axis_if_rx_tid; + wire [AXIS_IF_RX_DEST_WIDTH-1:0] axis_if_rx_tdest; + wire [AXIS_IF_RX_USER_WIDTH-1:0] axis_if_rx_tuser; + + rx_fifo #( + .FIFO_DEPTH(RX_FIFO_DEPTH), + .PORTS(PORTS_PER_IF), + .S_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH), + .S_KEEP_ENABLE(AXIS_SYNC_KEEP_WIDTH > 1), + .S_KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH), + .M_DATA_WIDTH(AXIS_IF_DATA_WIDTH), + .M_KEEP_ENABLE(AXIS_IF_KEEP_WIDTH > 1), + .M_KEEP_WIDTH(AXIS_IF_KEEP_WIDTH), + .ID_ENABLE(1), + .M_ID_WIDTH(AXIS_IF_RX_ID_WIDTH), + .DEST_WIDTH(AXIS_IF_RX_DEST_WIDTH), + .USER_ENABLE(1), + .USER_WIDTH(AXIS_IF_RX_USER_WIDTH), + .PIPELINE_OUTPUT(AXIS_RX_FIFO_PIPELINE) + ) + rx_fifo_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI Stream input + */ + .s_axis_tdata(axis_if_rx_fifo_tdata), + .s_axis_tkeep(axis_if_rx_fifo_tkeep), + .s_axis_tvalid(axis_if_rx_fifo_tvalid), + .s_axis_tready(axis_if_rx_fifo_tready), + .s_axis_tlast(axis_if_rx_fifo_tlast), + .s_axis_tid(0), + .s_axis_tdest(axis_if_rx_fifo_tdest), + .s_axis_tuser(axis_if_rx_fifo_tuser), + + /* + * AXI Stream outputs + */ + .m_axis_tdata(axis_if_rx_tdata), + .m_axis_tkeep(axis_if_rx_tkeep), + .m_axis_tvalid(axis_if_rx_tvalid), + .m_axis_tready(axis_if_rx_tready), + .m_axis_tlast(axis_if_rx_tlast), + .m_axis_tid(axis_if_rx_tid), + .m_axis_tdest(axis_if_rx_tdest), + .m_axis_tuser(axis_if_rx_tuser), + + /* + * Status + */ + .status_overflow(), + .status_bad_frame(), + .status_good_frame() + ); + + if (APP_ENABLE && APP_AXIS_IF_ENABLE) begin + + assign app_s_axis_if_rx_tdata[n*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH] = axis_if_rx_tdata; + assign app_s_axis_if_rx_tkeep[n*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH] = axis_if_rx_tkeep; + assign app_s_axis_if_rx_tvalid[n +: 1] = axis_if_rx_tvalid; + assign axis_if_rx_tready = app_s_axis_if_rx_tready[n +: 1]; + assign app_s_axis_if_rx_tlast[n +: 1] = axis_if_rx_tlast; + assign app_s_axis_if_rx_tid[n*AXIS_IF_RX_ID_WIDTH +: AXIS_IF_RX_ID_WIDTH] = axis_if_rx_tid; + assign app_s_axis_if_rx_tdest[n*AXIS_IF_RX_DEST_WIDTH +: AXIS_IF_RX_DEST_WIDTH] = axis_if_rx_tdest; + assign app_s_axis_if_rx_tuser[n*AXIS_IF_RX_USER_WIDTH +: AXIS_IF_RX_USER_WIDTH] = axis_if_rx_tuser; + + assign if_rx_axis_tdata = app_m_axis_if_rx_tdata[n*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH]; + assign if_rx_axis_tkeep = app_m_axis_if_rx_tkeep[n*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH]; + assign if_rx_axis_tvalid = app_m_axis_if_rx_tvalid[n +: 1]; + assign app_m_axis_if_rx_tready[n +: 1] = if_rx_axis_tready; + assign if_rx_axis_tlast = app_m_axis_if_rx_tlast[n +: 1]; + assign if_rx_axis_tid = app_m_axis_if_rx_tid[n*AXIS_IF_RX_ID_WIDTH +: AXIS_IF_RX_ID_WIDTH]; + assign if_rx_axis_tdest = app_m_axis_if_rx_tdest[n*AXIS_IF_RX_DEST_WIDTH +: AXIS_IF_RX_DEST_WIDTH]; + assign if_rx_axis_tuser = app_m_axis_if_rx_tuser[n*AXIS_IF_RX_USER_WIDTH +: AXIS_IF_RX_USER_WIDTH]; + + end else begin + + assign app_s_axis_if_rx_tdata[n*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH] = 0; + assign app_s_axis_if_rx_tkeep[n*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH] = 0; + assign app_s_axis_if_rx_tvalid[n +: 1] = 0; + assign app_s_axis_if_rx_tlast[n +: 1] = 0; + assign app_s_axis_if_rx_tid[n*AXIS_IF_RX_ID_WIDTH +: AXIS_IF_RX_ID_WIDTH] = 0; + assign app_s_axis_if_rx_tdest[n*AXIS_IF_RX_DEST_WIDTH +: AXIS_IF_RX_DEST_WIDTH] = 0; + assign app_s_axis_if_rx_tuser[n*AXIS_IF_RX_USER_WIDTH +: AXIS_IF_RX_USER_WIDTH] = 0; + + assign app_m_axis_if_rx_tready[n +: 1] = 0; + + assign if_rx_axis_tdata = axis_if_rx_tdata; + assign if_rx_axis_tkeep = axis_if_rx_tkeep; + assign if_rx_axis_tvalid = axis_if_rx_tvalid; + assign axis_if_rx_tready = if_rx_axis_tready; + assign if_rx_axis_tlast = axis_if_rx_tlast; + assign if_rx_axis_tid = axis_if_rx_tid; + assign if_rx_axis_tdest = axis_if_rx_tdest; + assign if_rx_axis_tuser = axis_if_rx_tuser; + + end + for (m = 0; m < PORTS_PER_IF; m = m + 1) begin : port wire port_tx_clk = tx_clk[n*PORTS_PER_IF+m]; @@ -2605,95 +2960,10 @@ generate end - if (APP_ENABLE && APP_AXIS_IF_ENABLE) begin - - assign app_s_axis_if_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = axis_tx_pipe_2_ptp_ts; - assign app_s_axis_if_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = axis_tx_pipe_2_ptp_ts_tag; - assign app_s_axis_if_tx_ptp_ts_valid[n*PORTS_PER_IF+m] = axis_tx_pipe_2_ptp_ts_valid; - assign axis_tx_pipe_2_ptp_ts_ready = app_s_axis_if_tx_ptp_ts_ready[n*PORTS_PER_IF+m]; - - assign if_tx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH] = app_m_axis_if_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH]; - assign if_tx_ptp_ts_tag[m*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = app_m_axis_if_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH]; - assign if_tx_ptp_ts_valid[m +: 1] = app_m_axis_if_tx_ptp_ts_valid[n*PORTS_PER_IF+m]; - assign app_m_axis_if_tx_ptp_ts_ready[n*PORTS_PER_IF+m] = if_tx_ptp_ts_ready[m +: 1]; - - end else begin - - assign app_s_axis_if_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = 0; - assign app_s_axis_if_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = 0; - assign app_s_axis_if_tx_ptp_ts_valid[n*PORTS_PER_IF+m] = 0; - - assign app_m_axis_if_tx_ptp_ts_ready[n*PORTS_PER_IF+m] = 0; - - assign if_tx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH] = axis_tx_pipe_2_ptp_ts; - assign if_tx_ptp_ts_tag[m*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = axis_tx_pipe_2_ptp_ts_tag; - assign if_tx_ptp_ts_valid[m +: 1] = axis_tx_pipe_2_ptp_ts_valid; - assign axis_tx_pipe_2_ptp_ts_ready = if_tx_ptp_ts_ready[m +: 1]; - - end - - wire [PTP_TS_WIDTH-1:0] rx_ts; - wire rx_ts_valid; - - ptp_ts_extract #( - .TS_WIDTH(PTP_TS_WIDTH), - .TS_OFFSET(1), - .USER_WIDTH(PTP_TS_WIDTH+1) - ) - rx_ptp_ts_extract_inst ( - .clk(clk), - .rst(rst), - - // AXI stream input - .s_axis_tvalid(if_rx_axis_tvalid[m +: 1] && if_rx_axis_tready[m +: 1]), - .s_axis_tlast(if_rx_axis_tlast[m +: 1]), - .s_axis_tuser(if_rx_axis_tuser_int[m*(PTP_TS_WIDTH+1) +: (PTP_TS_WIDTH+1)]), - - // Timestamp output - .m_axis_ts(rx_ts), - .m_axis_ts_valid(rx_ts_valid) - ); - - // PTP TS FIFO (RX) - axis_fifo #( - .DEPTH(RX_PTP_TS_FIFO_DEPTH), - .DATA_WIDTH(PTP_TS_WIDTH), - .KEEP_ENABLE(0), - .LAST_ENABLE(0), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(0), - .FRAME_FIFO(0) - ) - rx_ptp_ts_fifo_inst ( - .clk(clk), - .rst(rst), - - // AXI input - .s_axis_tdata(rx_ts), - .s_axis_tkeep(0), - .s_axis_tvalid(rx_ts_valid), - .s_axis_tready(), - .s_axis_tlast(0), - .s_axis_tid(0), - .s_axis_tdest(0), - .s_axis_tuser(0), - - // AXI output - .m_axis_tdata(if_rx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .m_axis_tkeep(), - .m_axis_tvalid(if_rx_ptp_ts_valid[m +: 1]), - .m_axis_tready(if_rx_ptp_ts_ready[m +: 1]), - .m_axis_tlast(), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(), - - // Status - .status_overflow(), - .status_bad_frame(), - .status_good_frame() - ); + assign axis_tx_if_ptp_ts[m*PTP_TS_WIDTH +: PTP_TS_WIDTH] = axis_tx_pipe_2_ptp_ts; + assign axis_tx_if_ptp_ts_tag[m*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = axis_tx_pipe_2_ptp_ts_tag; + assign axis_tx_if_ptp_ts_valid[m] = axis_tx_pipe_2_ptp_ts_valid; + assign axis_tx_pipe_2_ptp_ts_ready = axis_tx_if_ptp_ts_ready[m]; end else begin @@ -2703,13 +2973,6 @@ generate assign rx_ptp_ts_96[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = {PTP_TS_WIDTH{1'b0}}; assign rx_ptp_ts_step[n*PORTS_PER_IF+m] = 1'b0; - assign if_tx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH] = {PTP_TS_WIDTH{1'b0}}; - assign if_tx_ptp_ts_tag[m*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = {PTP_TAG_WIDTH{1'b0}}; - assign if_tx_ptp_ts_valid = 1'b0; - - assign if_rx_ptp_ts_96[m*PTP_TS_WIDTH +: PTP_TS_WIDTH] = {PTP_TS_WIDTH{1'b0}}; - assign if_rx_ptp_ts_valid[m +: 1] = 1'b0; - assign app_s_axis_direct_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = 0; assign app_s_axis_direct_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = 0; assign app_s_axis_direct_tx_ptp_ts_valid[n*PORTS_PER_IF+m] = 0; @@ -2722,28 +2985,19 @@ generate assign app_m_axis_sync_tx_ptp_ts_ready[n*PORTS_PER_IF+m] = 0; - assign app_s_axis_if_tx_ptp_ts[(n*PORTS_PER_IF+m)*PTP_TS_WIDTH +: PTP_TS_WIDTH] = 0; - assign app_s_axis_if_tx_ptp_ts_tag[(n*PORTS_PER_IF+m)*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = 0; - assign app_s_axis_if_tx_ptp_ts_valid[n*PORTS_PER_IF+m] = 0; - - assign app_m_axis_if_tx_ptp_ts_ready[n*PORTS_PER_IF+m] = 0; + assign axis_tx_if_ptp_ts[m*PTP_TS_WIDTH +: PTP_TS_WIDTH] = 0; + assign axis_tx_if_ptp_ts_tag[m*PTP_TAG_WIDTH +: PTP_TAG_WIDTH] = 0; + assign axis_tx_if_ptp_ts_valid[m] = 0; end // TX FIFOs - wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_if_tx_tdata; - wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_if_tx_tkeep; - wire axis_if_tx_tvalid; - wire axis_if_tx_tready; - wire axis_if_tx_tlast; - wire [AXIS_TX_USER_WIDTH-1:0] axis_if_tx_tuser; - - wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_tx_fifo_tdata; - wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_tx_fifo_tkeep; - wire axis_tx_fifo_tvalid; - wire axis_tx_fifo_tready; - wire axis_tx_fifo_tlast; - wire [AXIS_TX_USER_WIDTH-1:0] axis_tx_fifo_tuser; + wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_tx_if_tdata; + wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_tx_if_tkeep; + wire axis_tx_if_tvalid; + wire axis_tx_if_tready; + wire axis_tx_if_tlast; + wire [AXIS_TX_USER_WIDTH-1:0] axis_tx_if_tuser; wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_tx_pipe_tdata; wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_tx_pipe_tkeep; @@ -2773,98 +3027,21 @@ generate wire axis_tx_tlast; wire [AXIS_TX_USER_WIDTH-1:0] axis_tx_tuser; - if (APP_ENABLE && APP_AXIS_IF_ENABLE) begin - - assign app_s_axis_if_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH] = if_tx_axis_tdata[m*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]; - assign app_s_axis_if_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH] = if_tx_axis_tkeep[m*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]; - assign app_s_axis_if_tx_tvalid[n*PORTS_PER_IF+m +: 1] = if_tx_axis_tvalid[m +: 1]; - assign if_tx_axis_tready[m +: 1] = app_s_axis_if_tx_tready[n*PORTS_PER_IF+m +: 1]; - assign app_s_axis_if_tx_tlast[n*PORTS_PER_IF+m +: 1] = if_tx_axis_tlast[m +: 1]; - // assign app_s_axis_if_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_TX_USER_WIDTH +: AXIS_IF_TX_USER_WIDTH] = if_tx_axis_tuser[m*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]; - assign app_s_axis_if_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_TX_USER_WIDTH +: AXIS_IF_TX_USER_WIDTH] = {{PTP_TAG_WIDTH{1'b0}}, if_tx_axis_tuser[m +: 1]}; - - assign axis_if_tx_tdata = app_m_axis_if_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH]; - assign axis_if_tx_tkeep = app_m_axis_if_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH]; - assign axis_if_tx_tvalid = app_m_axis_if_tx_tvalid[n*PORTS_PER_IF+m]; - assign app_m_axis_if_tx_tready[n*PORTS_PER_IF+m +: 1] = axis_if_tx_tready; - assign axis_if_tx_tlast = app_m_axis_if_tx_tlast[n*PORTS_PER_IF+m]; - assign axis_if_tx_tuser = app_m_axis_if_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_TX_USER_WIDTH +: AXIS_IF_TX_USER_WIDTH]; - - end else begin - - assign app_s_axis_if_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH] = 0; - assign app_s_axis_if_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH] = 0; - assign app_s_axis_if_tx_tvalid[n*PORTS_PER_IF+m +: 1] = 0; - assign app_s_axis_if_tx_tlast[n*PORTS_PER_IF+m +: 1] = 0; - assign app_s_axis_if_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_TX_USER_WIDTH +: AXIS_IF_TX_USER_WIDTH] = 0; - - assign app_m_axis_if_tx_tready[n*PORTS_PER_IF+m +: 1] = 0; - - assign axis_if_tx_tdata = if_tx_axis_tdata[m*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]; - assign axis_if_tx_tkeep = if_tx_axis_tkeep[m*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]; - assign axis_if_tx_tvalid = if_tx_axis_tvalid[m +: 1]; - assign if_tx_axis_tready[m +: 1] = axis_if_tx_tready; - assign axis_if_tx_tlast = if_tx_axis_tlast[m +: 1]; - // assign axis_if_tx_tuser = if_tx_axis_tuser[m*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]; - assign axis_if_tx_tuser = {{PTP_TAG_WIDTH{1'b0}}, if_tx_axis_tuser[m +: 1]}; - - end - - axis_fifo #( - .DEPTH(TX_FIFO_DEPTH), - .DATA_WIDTH(AXIS_SYNC_DATA_WIDTH), - .KEEP_ENABLE(AXIS_SYNC_KEEP_WIDTH > 1), - .KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH), - .LAST_ENABLE(1), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(1), - .USER_WIDTH(AXIS_TX_USER_WIDTH), - .PIPELINE_OUTPUT(AXIS_TX_FIFO_PIPELINE), - .FRAME_FIFO(1), - .USER_BAD_FRAME_VALUE(1'b1), - .USER_BAD_FRAME_MASK(1'b1), - .DROP_BAD_FRAME(1), - .DROP_WHEN_FULL(0) - ) - tx_fifo_inst ( - .clk(clk), - .rst(rst), - - // AXI input - .s_axis_tdata(axis_if_tx_tdata), - .s_axis_tkeep(axis_if_tx_tkeep), - .s_axis_tvalid(axis_if_tx_tvalid), - .s_axis_tready(axis_if_tx_tready), - .s_axis_tlast(axis_if_tx_tlast), - .s_axis_tid(0), - .s_axis_tdest(0), - .s_axis_tuser(axis_if_tx_tuser), - - // AXI output - .m_axis_tdata(axis_tx_fifo_tdata), - .m_axis_tkeep(axis_tx_fifo_tkeep), - .m_axis_tvalid(axis_tx_fifo_tvalid), - .m_axis_tready(axis_tx_fifo_tready), - .m_axis_tlast(axis_tx_fifo_tlast), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(axis_tx_fifo_tuser), - - // Status - .status_overflow(), - .status_bad_frame(), - .status_good_frame() - ); + assign axis_tx_if_tdata = axis_if_tx_fifo_tdata[m*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]; + assign axis_tx_if_tkeep = axis_if_tx_fifo_tkeep[m*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]; + assign axis_tx_if_tvalid = axis_if_tx_fifo_tvalid[m +: 1]; + assign axis_if_tx_fifo_tready[m +: 1] = axis_tx_if_tready; + assign axis_tx_if_tlast = axis_if_tx_fifo_tlast[m +: 1]; + assign axis_tx_if_tuser = axis_if_tx_fifo_tuser[m*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]; if (APP_ENABLE && APP_AXIS_SYNC_ENABLE) begin - assign app_s_axis_sync_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH] = axis_tx_fifo_tdata; - assign app_s_axis_sync_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH] = axis_tx_fifo_tkeep; - assign app_s_axis_sync_tx_tvalid[n*PORTS_PER_IF+m] = axis_tx_fifo_tvalid; - assign axis_tx_fifo_tready = app_s_axis_sync_tx_tready[n*PORTS_PER_IF+m +: 1]; - assign app_s_axis_sync_tx_tlast[n*PORTS_PER_IF+m] = axis_tx_fifo_tlast; - assign app_s_axis_sync_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH] = axis_tx_fifo_tuser; + assign app_s_axis_sync_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH] = axis_tx_if_tdata; + assign app_s_axis_sync_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH] = axis_tx_if_tkeep; + assign app_s_axis_sync_tx_tvalid[n*PORTS_PER_IF+m] = axis_tx_if_tvalid; + assign axis_tx_if_tready = app_s_axis_sync_tx_tready[n*PORTS_PER_IF+m +: 1]; + assign app_s_axis_sync_tx_tlast[n*PORTS_PER_IF+m] = axis_tx_if_tlast; + assign app_s_axis_sync_tx_tuser[(n*PORTS_PER_IF+m)*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH] = axis_tx_if_tuser; assign axis_tx_pipe_tdata = app_m_axis_sync_tx_tdata[(n*PORTS_PER_IF+m)*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]; assign axis_tx_pipe_tkeep = app_m_axis_sync_tx_tkeep[(n*PORTS_PER_IF+m)*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]; @@ -2883,12 +3060,12 @@ generate assign app_m_axis_sync_tx_tready[n*PORTS_PER_IF+m +: 1] = 0; - assign axis_tx_pipe_tdata = axis_tx_fifo_tdata; - assign axis_tx_pipe_tkeep = axis_tx_fifo_tkeep; - assign axis_tx_pipe_tvalid = axis_tx_fifo_tvalid; - assign axis_tx_fifo_tready = axis_tx_pipe_tready; - assign axis_tx_pipe_tlast = axis_tx_fifo_tlast; - assign axis_tx_pipe_tuser = axis_tx_fifo_tuser; + assign axis_tx_pipe_tdata = axis_tx_if_tdata; + assign axis_tx_pipe_tkeep = axis_tx_if_tkeep; + assign axis_tx_pipe_tvalid = axis_tx_if_tvalid; + assign axis_tx_if_tready = axis_tx_pipe_tready; + assign axis_tx_pipe_tlast = axis_tx_if_tlast; + assign axis_tx_pipe_tuser = axis_tx_if_tuser; end @@ -3051,19 +3228,12 @@ generate wire axis_rx_pipe_tlast; wire [AXIS_RX_USER_WIDTH-1:0] axis_rx_pipe_tuser; - wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_rx_fifo_tdata; - wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_rx_fifo_tkeep; - wire axis_rx_fifo_tvalid; - wire axis_rx_fifo_tready; - wire axis_rx_fifo_tlast; - wire [AXIS_RX_USER_WIDTH-1:0] axis_rx_fifo_tuser; - - wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_if_rx_tdata; - wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_if_rx_tkeep; - wire axis_if_rx_tvalid; - wire axis_if_rx_tready; - wire axis_if_rx_tlast; - wire [AXIS_RX_USER_WIDTH-1:0] axis_if_rx_tuser; + wire [AXIS_SYNC_DATA_WIDTH-1:0] axis_rx_if_tdata; + wire [AXIS_SYNC_KEEP_WIDTH-1:0] axis_rx_if_tkeep; + wire axis_rx_if_tvalid; + wire axis_rx_if_tready; + wire axis_rx_if_tlast; + wire [AXIS_RX_USER_WIDTH-1:0] axis_rx_if_tuser; assign axis_rx_tdata = s_axis_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]; assign axis_rx_tkeep = s_axis_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]; @@ -3204,12 +3374,12 @@ generate assign app_s_axis_sync_rx_tlast[n*PORTS_PER_IF+m] = axis_rx_pipe_tlast; assign app_s_axis_sync_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH] = axis_rx_pipe_tuser; - assign axis_rx_fifo_tdata = app_m_axis_sync_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]; - assign axis_rx_fifo_tkeep = app_m_axis_sync_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]; - assign axis_rx_fifo_tvalid = app_m_axis_sync_rx_tvalid[n*PORTS_PER_IF+m +: 1]; - assign app_m_axis_sync_rx_tready[n*PORTS_PER_IF+m +: 1] = axis_rx_fifo_tready; - assign axis_rx_fifo_tlast = app_m_axis_sync_rx_tlast[n*PORTS_PER_IF+m +: 1]; - assign axis_rx_fifo_tuser = app_m_axis_sync_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]; + assign axis_rx_if_tdata = app_m_axis_sync_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH]; + assign axis_rx_if_tkeep = app_m_axis_sync_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH]; + assign axis_rx_if_tvalid = app_m_axis_sync_rx_tvalid[n*PORTS_PER_IF+m +: 1]; + assign app_m_axis_sync_rx_tready[n*PORTS_PER_IF+m +: 1] = axis_rx_if_tready; + assign axis_rx_if_tlast = app_m_axis_sync_rx_tlast[n*PORTS_PER_IF+m +: 1]; + assign axis_rx_if_tuser = app_m_axis_sync_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]; end else begin @@ -3221,100 +3391,21 @@ generate assign app_m_axis_sync_rx_tready[n*PORTS_PER_IF+m +: 1] = 0; - assign axis_rx_fifo_tdata = axis_rx_pipe_tdata; - assign axis_rx_fifo_tkeep = axis_rx_pipe_tkeep; - assign axis_rx_fifo_tvalid = axis_rx_pipe_tvalid; - assign axis_rx_pipe_tready = axis_rx_fifo_tready; - assign axis_rx_fifo_tlast = axis_rx_pipe_tlast; - assign axis_rx_fifo_tuser = axis_rx_pipe_tuser; + assign axis_rx_if_tdata = axis_rx_pipe_tdata; + assign axis_rx_if_tkeep = axis_rx_pipe_tkeep; + assign axis_rx_if_tvalid = axis_rx_pipe_tvalid; + assign axis_rx_pipe_tready = axis_rx_if_tready; + assign axis_rx_if_tlast = axis_rx_pipe_tlast; + assign axis_rx_if_tuser = axis_rx_pipe_tuser; end - axis_fifo #( - .DEPTH(RX_FIFO_DEPTH), - .DATA_WIDTH(AXIS_SYNC_DATA_WIDTH), - .KEEP_ENABLE(AXIS_SYNC_KEEP_WIDTH > 1), - .KEEP_WIDTH(AXIS_SYNC_KEEP_WIDTH), - .LAST_ENABLE(1), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(1), - .USER_WIDTH(AXIS_RX_USER_WIDTH), - .PIPELINE_OUTPUT(AXIS_RX_FIFO_PIPELINE), - .FRAME_FIFO(1), - .USER_BAD_FRAME_VALUE(1'b1), - .USER_BAD_FRAME_MASK(1'b1), - .DROP_BAD_FRAME(1), - .DROP_WHEN_FULL(0) - ) - rx_fifo_inst ( - .clk(clk), - .rst(rst), - - // AXI input - .s_axis_tdata(axis_rx_fifo_tdata), - .s_axis_tkeep(axis_rx_fifo_tkeep), - .s_axis_tvalid(axis_rx_fifo_tvalid), - .s_axis_tready(axis_rx_fifo_tready), - .s_axis_tlast(axis_rx_fifo_tlast), - .s_axis_tid(0), - .s_axis_tdest(0), - .s_axis_tuser(axis_rx_fifo_tuser), - - // AXI output - .m_axis_tdata(axis_if_rx_tdata), - .m_axis_tkeep(axis_if_rx_tkeep), - .m_axis_tvalid(axis_if_rx_tvalid), - .m_axis_tready(axis_if_rx_tready), - .m_axis_tlast(axis_if_rx_tlast), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(axis_if_rx_tuser), - - // Status - .status_overflow(), - .status_bad_frame(), - .status_good_frame() - ); - - if (APP_ENABLE && APP_AXIS_IF_ENABLE) begin - - assign app_s_axis_if_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH] = axis_if_rx_tdata; - assign app_s_axis_if_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH] = axis_if_rx_tkeep; - assign app_s_axis_if_rx_tvalid[n*PORTS_PER_IF+m +: 1] = axis_if_rx_tvalid; - assign axis_if_rx_tready = app_s_axis_if_rx_tready[n*PORTS_PER_IF+m +: 1]; - assign app_s_axis_if_rx_tlast[n*PORTS_PER_IF+m +: 1] = axis_if_rx_tlast; - assign app_s_axis_if_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_RX_USER_WIDTH +: AXIS_IF_RX_USER_WIDTH] = axis_if_rx_tuser; - - assign if_rx_axis_tdata[m*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH] = app_m_axis_if_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH]; - assign if_rx_axis_tkeep[m*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH] = app_m_axis_if_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH]; - assign if_rx_axis_tvalid[m +: 1] = app_m_axis_if_rx_tvalid[n*PORTS_PER_IF+m +: 1]; - assign app_m_axis_if_rx_tready[n*PORTS_PER_IF+m +: 1] = if_rx_axis_tready[m +: 1]; - assign if_rx_axis_tlast[m +: 1] = app_m_axis_if_rx_tlast[n*PORTS_PER_IF+m +: 1]; - // assign if_rx_axis_tuser[m*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH] = app_m_axis_if_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_RX_USER_WIDTH +: AXIS_IF_RX_USER_WIDTH]; - assign if_rx_axis_tuser_int[m*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH] = app_m_axis_if_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_RX_USER_WIDTH +: AXIS_IF_RX_USER_WIDTH]; - - end else begin - - assign app_s_axis_if_rx_tdata[(n*PORTS_PER_IF+m)*AXIS_IF_DATA_WIDTH +: AXIS_IF_DATA_WIDTH] = 0; - assign app_s_axis_if_rx_tkeep[(n*PORTS_PER_IF+m)*AXIS_IF_KEEP_WIDTH +: AXIS_IF_KEEP_WIDTH] = 0; - assign app_s_axis_if_rx_tvalid[n*PORTS_PER_IF+m +: 1] = 0; - assign app_s_axis_if_rx_tlast[n*PORTS_PER_IF+m +: 1] = 0; - assign app_s_axis_if_rx_tuser[(n*PORTS_PER_IF+m)*AXIS_IF_RX_USER_WIDTH +: AXIS_IF_RX_USER_WIDTH] = 0; - - assign app_m_axis_if_rx_tready[n*PORTS_PER_IF+m +: 1] = 0; - - assign if_rx_axis_tdata[m*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH] = axis_if_rx_tdata; - assign if_rx_axis_tkeep[m*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH] = axis_if_rx_tkeep; - assign if_rx_axis_tvalid[m +: 1] = axis_if_rx_tvalid; - assign axis_if_rx_tready = if_rx_axis_tready[m +: 1]; - assign if_rx_axis_tlast[m +: 1] = axis_if_rx_tlast; - // assign if_rx_axis_tuser[m*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH] = axis_if_rx_tuser; - assign if_rx_axis_tuser_int[m*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH] = axis_if_rx_tuser; - - end - - assign if_rx_axis_tuser[m +: 1] = if_rx_axis_tuser_int[m*AXIS_RX_USER_WIDTH +: 1]; + assign axis_if_rx_fifo_tdata[m*AXIS_SYNC_DATA_WIDTH +: AXIS_SYNC_DATA_WIDTH] = axis_rx_if_tdata; + assign axis_if_rx_fifo_tkeep[m*AXIS_SYNC_KEEP_WIDTH +: AXIS_SYNC_KEEP_WIDTH] = axis_rx_if_tkeep; + assign axis_if_rx_fifo_tvalid[m +: 1] = axis_rx_if_tvalid; + assign axis_rx_if_tready = axis_if_rx_fifo_tready[m +: 1]; + assign axis_if_rx_fifo_tlast[m +: 1] = axis_rx_if_tlast; + assign axis_if_rx_fifo_tuser[m*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH] = axis_rx_if_tuser; end @@ -3392,6 +3483,10 @@ if (APP_ENABLE) begin : app // Ethernet interface configuration (interface) .AXIS_IF_DATA_WIDTH(AXIS_IF_DATA_WIDTH), .AXIS_IF_KEEP_WIDTH(AXIS_IF_KEEP_WIDTH), + .AXIS_IF_TX_ID_WIDTH(AXIS_IF_TX_ID_WIDTH), + .AXIS_IF_RX_ID_WIDTH(AXIS_IF_RX_ID_WIDTH), + .AXIS_IF_TX_DEST_WIDTH(AXIS_IF_TX_DEST_WIDTH), + .AXIS_IF_RX_DEST_WIDTH(AXIS_IF_RX_DEST_WIDTH), .AXIS_IF_TX_USER_WIDTH(AXIS_IF_TX_USER_WIDTH), .AXIS_IF_RX_USER_WIDTH(AXIS_IF_RX_USER_WIDTH), @@ -3665,6 +3760,8 @@ if (APP_ENABLE) begin : app .s_axis_if_tx_tvalid(app_s_axis_if_tx_tvalid), .s_axis_if_tx_tready(app_s_axis_if_tx_tready), .s_axis_if_tx_tlast(app_s_axis_if_tx_tlast), + .s_axis_if_tx_tid(app_s_axis_if_tx_tid), + .s_axis_if_tx_tdest(app_s_axis_if_tx_tdest), .s_axis_if_tx_tuser(app_s_axis_if_tx_tuser), .m_axis_if_tx_tdata(app_m_axis_if_tx_tdata), @@ -3672,6 +3769,8 @@ if (APP_ENABLE) begin : app .m_axis_if_tx_tvalid(app_m_axis_if_tx_tvalid), .m_axis_if_tx_tready(app_m_axis_if_tx_tready), .m_axis_if_tx_tlast(app_m_axis_if_tx_tlast), + .m_axis_if_tx_tid(app_m_axis_if_tx_tid), + .m_axis_if_tx_tdest(app_m_axis_if_tx_tdest), .m_axis_if_tx_tuser(app_m_axis_if_tx_tuser), .s_axis_if_tx_ptp_ts(app_s_axis_if_tx_ptp_ts), @@ -3689,6 +3788,8 @@ if (APP_ENABLE) begin : app .s_axis_if_rx_tvalid(app_s_axis_if_rx_tvalid), .s_axis_if_rx_tready(app_s_axis_if_rx_tready), .s_axis_if_rx_tlast(app_s_axis_if_rx_tlast), + .s_axis_if_rx_tid(app_s_axis_if_rx_tid), + .s_axis_if_rx_tdest(app_s_axis_if_rx_tdest), .s_axis_if_rx_tuser(app_s_axis_if_rx_tuser), .m_axis_if_rx_tdata(app_m_axis_if_rx_tdata), @@ -3696,6 +3797,8 @@ if (APP_ENABLE) begin : app .m_axis_if_rx_tvalid(app_m_axis_if_rx_tvalid), .m_axis_if_rx_tready(app_m_axis_if_rx_tready), .m_axis_if_rx_tlast(app_m_axis_if_rx_tlast), + .m_axis_if_rx_tid(app_m_axis_if_rx_tid), + .m_axis_if_rx_tdest(app_m_axis_if_rx_tdest), .m_axis_if_rx_tuser(app_m_axis_if_rx_tuser), /* @@ -3820,6 +3923,8 @@ end else begin assign app_m_axis_if_tx_tkeep = 0; assign app_m_axis_if_tx_tvalid = 0; assign app_m_axis_if_tx_tlast = 0; + assign app_m_axis_if_tx_tid = 0; + assign app_m_axis_if_tx_tdest = 0; assign app_m_axis_if_tx_tuser = 0; assign app_s_axis_if_tx_ptp_ts_ready = 0; @@ -3834,6 +3939,8 @@ end else begin assign app_m_axis_if_rx_tkeep = 0; assign app_m_axis_if_rx_tvalid = 0; assign app_m_axis_if_rx_tlast = 0; + assign app_m_axis_if_rx_tid = 0; + assign app_m_axis_if_rx_tdest = 0; assign app_m_axis_if_rx_tuser = 0; assign axis_app_stat_tdata = 0; diff --git a/fpga/common/rtl/mqnic_core_axi.v b/fpga/common/rtl/mqnic_core_axi.v index 0c82d95e7..a04c84fc1 100644 --- a/fpga/common/rtl/mqnic_core_axi.v +++ b/fpga/common/rtl/mqnic_core_axi.v @@ -38,7 +38,7 @@ either expressed or implied, of The Regents of the University of California. `default_nettype none /* - * FPGA core logic + * mqnic core logic - AXI DMA wrapper */ module mqnic_core_axi # ( @@ -158,6 +158,7 @@ module mqnic_core_axi # parameter AXIS_DATA_WIDTH = 64, parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH, + parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF), parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1, parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, parameter AXIS_RX_USE_READY = 0, @@ -368,7 +369,7 @@ parameter RAM_SEG_COUNT = 2; parameter RAM_SEG_DATA_WIDTH = AXI_DATA_WIDTH*2/RAM_SEG_COUNT; parameter RAM_SEG_ADDR_WIDTH = 12; parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8; -parameter IF_RAM_SEL_WIDTH = PORTS_PER_IF > 1 ? $clog2(PORTS_PER_IF) : 1; +parameter IF_RAM_SEL_WIDTH = 1; parameter RAM_SEL_WIDTH = $clog2(IF_COUNT+(APP_ENABLE && APP_DMA_ENABLE ? 1 : 0))+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH); @@ -651,6 +652,7 @@ mqnic_core #( .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), .AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH), + .AXIS_IF_DATA_WIDTH(AXIS_IF_DATA_WIDTH), .AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH), .AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH), .AXIS_RX_USE_READY(AXIS_RX_USE_READY), diff --git a/fpga/common/rtl/mqnic_core_pcie.v b/fpga/common/rtl/mqnic_core_pcie.v index 23acb0900..790cdf914 100644 --- a/fpga/common/rtl/mqnic_core_pcie.v +++ b/fpga/common/rtl/mqnic_core_pcie.v @@ -38,7 +38,7 @@ either expressed or implied, of The Regents of the University of California. `default_nettype none /* - * FPGA core logic + * mqnic core logic - Generic PCIe DMA wrapper */ module mqnic_core_pcie # ( @@ -166,6 +166,7 @@ module mqnic_core_pcie # parameter AXIS_DATA_WIDTH = 512, parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH, + parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF), parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1, parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, parameter AXIS_RX_USE_READY = 0, @@ -380,7 +381,7 @@ parameter RAM_SEG_COUNT = TLP_SEG_COUNT*2; parameter RAM_SEG_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH*2/RAM_SEG_COUNT; parameter RAM_SEG_ADDR_WIDTH = 12; parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8; -parameter IF_RAM_SEL_WIDTH = PORTS_PER_IF > 1 ? $clog2(PORTS_PER_IF) : 1; +parameter IF_RAM_SEL_WIDTH = 1; parameter RAM_SEL_WIDTH = $clog2(IF_COUNT+(APP_ENABLE && APP_DMA_ENABLE ? 1 : 0))+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH); @@ -1407,6 +1408,7 @@ mqnic_core #( .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), .AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH), + .AXIS_IF_DATA_WIDTH(AXIS_IF_DATA_WIDTH), .AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH), .AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH), .AXIS_RX_USE_READY(AXIS_RX_USE_READY), diff --git a/fpga/common/rtl/mqnic_core_pcie_s10.v b/fpga/common/rtl/mqnic_core_pcie_s10.v index 0d5450c90..17f381534 100644 --- a/fpga/common/rtl/mqnic_core_pcie_s10.v +++ b/fpga/common/rtl/mqnic_core_pcie_s10.v @@ -163,6 +163,7 @@ module mqnic_core_pcie_s10 # parameter AXIS_ETH_DATA_WIDTH = 512, parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH, + parameter AXIS_ETH_IF_DATA_WIDTH = AXIS_ETH_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF), parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1, parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, parameter AXIS_ETH_RX_USE_READY = 0, @@ -687,6 +688,7 @@ mqnic_core_pcie #( .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), .AXIS_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), + .AXIS_IF_DATA_WIDTH(AXIS_ETH_IF_DATA_WIDTH), .AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), .AXIS_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), .AXIS_RX_USE_READY(AXIS_ETH_RX_USE_READY), diff --git a/fpga/common/rtl/mqnic_core_pcie_us.v b/fpga/common/rtl/mqnic_core_pcie_us.v index b48c77d8b..da3b988fc 100644 --- a/fpga/common/rtl/mqnic_core_pcie_us.v +++ b/fpga/common/rtl/mqnic_core_pcie_us.v @@ -38,7 +38,7 @@ either expressed or implied, of The Regents of the University of California. `default_nettype none /* - * FPGA core logic + * mqnic core logic - Xilinx UltraScale/UltraScale+ wrapper */ module mqnic_core_pcie_us # ( @@ -164,6 +164,7 @@ module mqnic_core_pcie_us # parameter AXIS_ETH_DATA_WIDTH = 512, parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8, parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH, + parameter AXIS_ETH_IF_DATA_WIDTH = AXIS_ETH_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF), parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1, parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, parameter AXIS_ETH_RX_USE_READY = 0, @@ -777,6 +778,7 @@ mqnic_core_pcie #( .AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH), .AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH), .AXIS_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH), + .AXIS_IF_DATA_WIDTH(AXIS_ETH_IF_DATA_WIDTH), .AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH), .AXIS_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH), .AXIS_RX_USE_READY(AXIS_ETH_RX_USE_READY), diff --git a/fpga/common/rtl/mqnic_egress.v b/fpga/common/rtl/mqnic_egress.v new file mode 100644 index 000000000..658217d8b --- /dev/null +++ b/fpga/common/rtl/mqnic_egress.v @@ -0,0 +1,218 @@ +/* + +Copyright 2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * NIC egress processing + */ +module mqnic_egress # +( + // Enable TX checksum offload + parameter TX_CHECKSUM_ENABLE = 1, + // Width of AXI stream interfaces in bits + parameter AXIS_DATA_WIDTH = 256, + // AXI stream tkeep signal width (words per cycle) + parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, + // AXI stream tid signal width + parameter AXIS_ID_WIDTH = 8, + // AXI stream tdest signal width + parameter AXIS_DEST_WIDTH = 8, + // AXI stream tuser signal width + parameter AXIS_USER_WIDTH = 1, + // Max transmit packet size + parameter MAX_TX_SIZE = 2048 +) +( + input wire clk, + input wire rst, + + /* + * Transmit data input + */ + input wire [AXIS_DATA_WIDTH-1:0] s_axis_tdata, + input wire [AXIS_KEEP_WIDTH-1:0] s_axis_tkeep, + input wire s_axis_tvalid, + output wire s_axis_tready, + input wire s_axis_tlast, + input wire [AXIS_ID_WIDTH-1:0] s_axis_tid, + input wire [AXIS_DEST_WIDTH-1:0] s_axis_tdest, + input wire [AXIS_USER_WIDTH-1:0] s_axis_tuser, + + /* + * Transmit data output + */ + output wire [AXIS_DATA_WIDTH-1:0] m_axis_tdata, + output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tkeep, + output wire m_axis_tvalid, + input wire m_axis_tready, + output wire m_axis_tlast, + output wire [AXIS_ID_WIDTH-1:0] m_axis_tid, + output wire [AXIS_DEST_WIDTH-1:0] m_axis_tdest, + output wire [AXIS_USER_WIDTH-1:0] m_axis_tuser, + + /* + * Transmit checksum command + */ + input wire tx_csum_cmd_csum_enable, + input wire [7:0] tx_csum_cmd_csum_start, + input wire [7:0] tx_csum_cmd_csum_offset, + input wire tx_csum_cmd_valid, + output wire tx_csum_cmd_ready +); + +generate + +if (TX_CHECKSUM_ENABLE) begin + + wire tx_csum_cmd_csum_enable_int; + wire [7:0] tx_csum_cmd_csum_start_int; + wire [7:0] tx_csum_cmd_csum_offset_int; + wire tx_csum_cmd_valid_int; + wire tx_csum_cmd_ready_int; + + axis_fifo #( + .DEPTH(32), + .DATA_WIDTH(1+8+8), + .KEEP_ENABLE(0), + .LAST_ENABLE(0), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(0), + .FRAME_FIFO(0) + ) + tx_csum_cmd_fifo ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata({tx_csum_cmd_csum_enable, tx_csum_cmd_csum_start, tx_csum_cmd_csum_offset}), + .s_axis_tkeep(0), + .s_axis_tvalid(tx_csum_cmd_valid), + .s_axis_tready(tx_csum_cmd_ready), + .s_axis_tlast(0), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(0), + + // AXI output + .m_axis_tdata({tx_csum_cmd_csum_enable_int, tx_csum_cmd_csum_start_int, tx_csum_cmd_csum_offset_int}), + .m_axis_tkeep(), + .m_axis_tvalid(tx_csum_cmd_valid_int), + .m_axis_tready(tx_csum_cmd_ready_int), + .m_axis_tlast(), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(), + + // Status + .status_overflow(), + .status_bad_frame(), + .status_good_frame() + ); + + tx_checksum #( + .DATA_WIDTH(AXIS_DATA_WIDTH), + .ID_ENABLE(1), + .ID_WIDTH(AXIS_ID_WIDTH), + .DEST_ENABLE(1), + .DEST_WIDTH(AXIS_DEST_WIDTH), + .USER_ENABLE(1), + .USER_WIDTH(AXIS_USER_WIDTH), + .USE_INIT_VALUE(0), + .DATA_FIFO_DEPTH(MAX_TX_SIZE), + .CHECKSUM_FIFO_DEPTH(64) + ) + tx_checksum_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI input + */ + .s_axis_tdata(s_axis_tdata), + .s_axis_tkeep(s_axis_tkeep), + .s_axis_tvalid(s_axis_tvalid), + .s_axis_tready(s_axis_tready), + .s_axis_tlast(s_axis_tlast), + .s_axis_tid(s_axis_tid), + .s_axis_tdest(s_axis_tdest), + .s_axis_tuser(s_axis_tuser), + + /* + * AXI output + */ + .m_axis_tdata(m_axis_tdata), + .m_axis_tkeep(m_axis_tkeep), + .m_axis_tvalid(m_axis_tvalid), + .m_axis_tready(m_axis_tready), + .m_axis_tlast(m_axis_tlast), + .m_axis_tid(m_axis_tid), + .m_axis_tdest(m_axis_tdest), + .m_axis_tuser(m_axis_tuser), + + /* + * Control + */ + .s_axis_cmd_csum_enable(tx_csum_cmd_csum_enable_int), + .s_axis_cmd_csum_start(tx_csum_cmd_csum_start_int), + .s_axis_cmd_csum_offset(tx_csum_cmd_csum_offset_int), + .s_axis_cmd_csum_init(16'd0), + .s_axis_cmd_valid(tx_csum_cmd_valid_int), + .s_axis_cmd_ready(tx_csum_cmd_ready_int) + ); + +end else begin + + assign m_axis_tdata = s_axis_tdata; + assign m_axis_tkeep = s_axis_tkeep; + assign m_axis_tvalid = s_axis_tvalid; + assign s_axis_tready = m_axis_tready; + assign m_axis_tlast = s_axis_tlast; + assign m_axis_tid = s_axis_tid; + assign m_axis_tdest = s_axis_tdest; + assign m_axis_tuser = s_axis_tuser; + + assign tx_csum_cmd_ready = 1'b1; + +end + +endgenerate + +endmodule + +`resetall diff --git a/fpga/common/rtl/mqnic_ingress.v b/fpga/common/rtl/mqnic_ingress.v new file mode 100644 index 000000000..a80c2c7e5 --- /dev/null +++ b/fpga/common/rtl/mqnic_ingress.v @@ -0,0 +1,396 @@ +/* + +Copyright 2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * NIC ingress processing + */ +module mqnic_ingress # +( + // Request tag field width + parameter REQ_TAG_WIDTH = 8, + // Receive queue index width + parameter RX_QUEUE_INDEX_WIDTH = 8, + // Enable RX RSS + parameter RX_RSS_ENABLE = 1, + // Enable RX hashing + parameter RX_HASH_ENABLE = 1, + // Enable RX checksum offload + parameter RX_CHECKSUM_ENABLE = 1, + // Width of AXI stream interfaces in bits + parameter AXIS_DATA_WIDTH = 256, + // AXI stream tkeep signal width (words per cycle) + parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, + // AXI stream tid signal width + parameter AXIS_ID_WIDTH = 8, + // AXI stream tdest signal width + parameter AXIS_DEST_WIDTH = 8, + // AXI stream tuser signal width + parameter AXIS_USER_WIDTH = 1, + // Max receive packet size + parameter MAX_RX_SIZE = 2048 +) +( + input wire clk, + input wire rst, + + /* + * Receive data input + */ + input wire [AXIS_DATA_WIDTH-1:0] s_axis_tdata, + input wire [AXIS_KEEP_WIDTH-1:0] s_axis_tkeep, + input wire s_axis_tvalid, + output wire s_axis_tready, + input wire s_axis_tlast, + input wire [AXIS_ID_WIDTH-1:0] s_axis_tid, + input wire [AXIS_DEST_WIDTH-1:0] s_axis_tdest, + input wire [AXIS_USER_WIDTH-1:0] s_axis_tuser, + + /* + * Receive data output + */ + output wire [AXIS_DATA_WIDTH-1:0] m_axis_tdata, + output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tkeep, + output wire m_axis_tvalid, + input wire m_axis_tready, + output wire m_axis_tlast, + output wire [AXIS_ID_WIDTH-1:0] m_axis_tid, + output wire [AXIS_DEST_WIDTH-1:0] m_axis_tdest, + output wire [AXIS_USER_WIDTH-1:0] m_axis_tuser, + + /* + * RX command output + */ + output wire [RX_QUEUE_INDEX_WIDTH-1:0] rx_req_queue, + output wire [REQ_TAG_WIDTH-1:0] rx_req_tag, + output wire rx_req_valid, + input wire rx_req_ready, + + /* + * RX hash output + */ + output wire [31:0] rx_hash, + output wire [3:0] rx_hash_type, + output wire rx_hash_valid, + input wire rx_hash_ready, + + /* + * RX checksum output + */ + output wire [15:0] rx_csum, + output wire rx_csum_valid, + input wire rx_csum_ready, + + /* + * Configuration + */ + input wire [31:0] rss_mask +); + +generate + +wire [31:0] rx_hash_int; +wire [3:0] rx_hash_type_int; +wire rx_hash_valid_int; + +if (RX_HASH_ENABLE) begin + + + rx_hash #( + .DATA_WIDTH(AXIS_DATA_WIDTH) + ) + rx_hash_inst ( + .clk(clk), + .rst(rst), + .s_axis_tdata(s_axis_tdata), + .s_axis_tkeep(s_axis_tkeep), + .s_axis_tvalid(s_axis_tvalid & s_axis_tready), + .s_axis_tlast(s_axis_tlast), + .hash_key(320'h6d5a56da255b0ec24167253d43a38fb0d0ca2bcbae7b30b477cb2da38030f20c6a42b73bbeac01fa), + .m_axis_hash(rx_hash_int), + .m_axis_hash_type(rx_hash_type_int), + .m_axis_hash_valid(rx_hash_valid_int) + ); + + axis_fifo #( + .DEPTH(32), + .DATA_WIDTH(32+4), + .KEEP_ENABLE(0), + .LAST_ENABLE(0), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(0), + .FRAME_FIFO(0) + ) + rx_hash_fifo ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata({rx_hash_type_int, rx_hash_int}), + .s_axis_tkeep(0), + .s_axis_tvalid(rx_hash_valid_int), + .s_axis_tready(), + .s_axis_tlast(0), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(0), + + // AXI output + .m_axis_tdata({rx_hash_type, rx_hash}), + .m_axis_tkeep(), + .m_axis_tvalid(rx_hash_valid), + .m_axis_tready(rx_hash_ready), + .m_axis_tlast(), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(), + + // Status + .status_overflow(), + .status_bad_frame(), + .status_good_frame() + ); + +end else begin + + assign rx_hash = 32'd0; + assign rx_hash_type = 4'd0; + assign rx_hash_valid = 1'b0; + +end + +if (RX_RSS_ENABLE && RX_HASH_ENABLE) begin + + axis_fifo #( + .DEPTH(AXIS_KEEP_WIDTH*32), + .DATA_WIDTH(AXIS_DATA_WIDTH), + .KEEP_ENABLE(AXIS_KEEP_WIDTH > 1), + .KEEP_WIDTH(AXIS_KEEP_WIDTH), + .LAST_ENABLE(1), + .ID_ENABLE(1), + .ID_WIDTH(AXIS_ID_WIDTH), + .DEST_ENABLE(1), + .DEST_WIDTH(AXIS_DEST_WIDTH), + .USER_ENABLE(1), + .USER_WIDTH(AXIS_USER_WIDTH), + .FRAME_FIFO(0) + ) + rx_hash_data_fifo ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata(s_axis_tdata), + .s_axis_tkeep(s_axis_tkeep), + .s_axis_tvalid(s_axis_tvalid), + .s_axis_tready(s_axis_tready), + .s_axis_tlast(s_axis_tlast), + .s_axis_tid(s_axis_tid), + .s_axis_tdest(s_axis_tdest), + .s_axis_tuser(s_axis_tuser), + + // AXI output + .m_axis_tdata(m_axis_tdata), + .m_axis_tkeep(m_axis_tkeep), + .m_axis_tvalid(m_axis_tvalid), + .m_axis_tready(m_axis_tready), + .m_axis_tlast(m_axis_tlast), + .m_axis_tid(m_axis_tid), + .m_axis_tdest(m_axis_tdest), + .m_axis_tuser(m_axis_tuser), + + // Status + .status_overflow(), + .status_bad_frame(), + .status_good_frame() + ); + + // Generate RX requests (RSS) + assign rx_req_tag = 0; + + axis_fifo #( + .DEPTH(32), + .DATA_WIDTH(RX_QUEUE_INDEX_WIDTH), + .KEEP_ENABLE(0), + .LAST_ENABLE(0), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(0), + .FRAME_FIFO(0) + ) + rx_req_fifo ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata(rx_hash_int & rss_mask), + .s_axis_tkeep(0), + .s_axis_tvalid(rx_hash_valid_int), + .s_axis_tready(), + .s_axis_tlast(0), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(0), + + // AXI output + .m_axis_tdata(rx_req_queue), + .m_axis_tkeep(), + .m_axis_tvalid(rx_req_valid), + .m_axis_tready(rx_req_ready), + .m_axis_tlast(), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(), + + // Status + .status_overflow(), + .status_bad_frame(), + .status_good_frame() + ); + +end else begin + + assign m_axis_tdata = s_axis_tdata; + assign m_axis_tkeep = s_axis_tkeep; + assign m_axis_tvalid = s_axis_tvalid; + assign s_axis_tready = m_axis_tready; + assign m_axis_tlast = s_axis_tlast; + assign m_axis_tid = s_axis_tid; + assign m_axis_tdest = s_axis_tdest; + assign m_axis_tuser = s_axis_tuser; + + // Generate RX requests (no RSS) + reg rx_frame_reg = 1'b0; + reg rx_req_valid_reg = 1'b0; + + assign rx_req_queue = 0; + assign rx_req_tag = 0; + assign rx_req_valid = s_axis_tvalid && !rx_frame_reg; + + always @(posedge clk) begin + if (rx_req_ready) begin + rx_req_valid_reg <= 1'b0; + end + + if (s_axis_tready && s_axis_tvalid) begin + if (!rx_frame_reg) begin + rx_req_valid_reg <= 1'b1; + end + rx_frame_reg <= !s_axis_tlast; + end + + if (rst) begin + rx_frame_reg <= 1'b0; + rx_req_valid_reg <= 1'b0; + end + end + +end + +if (RX_CHECKSUM_ENABLE) begin + + wire [15:0] rx_csum_int; + wire rx_csum_valid_int; + + rx_checksum #( + .DATA_WIDTH(AXIS_DATA_WIDTH) + ) + rx_checksum_inst ( + .clk(clk), + .rst(rst), + .s_axis_tdata(s_axis_tdata), + .s_axis_tkeep(s_axis_tkeep), + .s_axis_tvalid(s_axis_tvalid & s_axis_tready), + .s_axis_tlast(s_axis_tlast), + .m_axis_csum(rx_csum_int), + .m_axis_csum_valid(rx_csum_valid_int) + ); + + axis_fifo #( + .DEPTH(32), + .DATA_WIDTH(16), + .KEEP_ENABLE(0), + .LAST_ENABLE(0), + .ID_ENABLE(0), + .DEST_ENABLE(0), + .USER_ENABLE(0), + .FRAME_FIFO(0) + ) + rx_csum_fifo ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata(rx_csum_int), + .s_axis_tkeep(0), + .s_axis_tvalid(rx_csum_valid_int), + .s_axis_tready(), + .s_axis_tlast(0), + .s_axis_tid(0), + .s_axis_tdest(0), + .s_axis_tuser(0), + + // AXI output + .m_axis_tdata(rx_csum), + .m_axis_tkeep(), + .m_axis_tvalid(rx_csum_valid), + .m_axis_tready(rx_csum_ready), + .m_axis_tlast(), + .m_axis_tid(), + .m_axis_tdest(), + .m_axis_tuser(), + + // Status + .status_overflow(), + .status_bad_frame(), + .status_good_frame() + ); + +end else begin + + assign rx_csum = 16'd0; + assign rx_csum_valid = 1'b0; + +end + +endgenerate + +endmodule + +`resetall diff --git a/fpga/common/rtl/mqnic_interface.v b/fpga/common/rtl/mqnic_interface.v index 6281dae96..24b34f62b 100644 --- a/fpga/common/rtl/mqnic_interface.v +++ b/fpga/common/rtl/mqnic_interface.v @@ -86,8 +86,12 @@ module mqnic_interface # parameter RX_DESC_TABLE_SIZE = 16, // Max number of in-flight descriptor requests (transmit) parameter TX_MAX_DESC_REQ = 16, - // Max number of in-flight descriptor requests (transmit) + // Transmit descriptor FIFO size + parameter TX_DESC_FIFO_SIZE = TX_MAX_DESC_REQ*8, + // Max number of in-flight descriptor requests (receive) parameter RX_MAX_DESC_REQ = 16, + // Receive descriptor FIFO size + parameter RX_DESC_FIFO_SIZE = RX_MAX_DESC_REQ*8, // Scheduler operation table size parameter TX_SCHEDULER_OP_TABLE_SIZE = 32, // Scheduler pipeline setting @@ -106,6 +110,8 @@ module mqnic_interface # parameter PTP_TS_ENABLE = 1, // PTP timestamp width parameter PTP_TS_WIDTH = 96, + // PTP tag width + parameter PTP_TAG_WIDTH = 16, // Enable TX checksum offload parameter TX_CHECKSUM_ENABLE = 1, // Enable RX RSS @@ -138,6 +144,18 @@ module mqnic_interface # parameter AXIS_DATA_WIDTH = 256, // AXI stream tkeep signal width (words per cycle) parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, + // AXI stream tid signal width + parameter AXIS_TX_ID_WIDTH = TX_QUEUE_INDEX_WIDTH, + // AXI stream tid signal width + parameter AXIS_RX_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1, + // AXI stream tdest signal width + parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4, + // AXI stream tdest signal width + parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH, + // AXI stream tuser signal width + parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1, + // AXI stream tuser signal width + parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, // Max transmit packet size parameter MAX_TX_SIZE = 2048, // Max receive packet size @@ -308,36 +326,34 @@ module mqnic_interface # /* * Transmit data output */ - output wire [PORTS*AXIS_DATA_WIDTH-1:0] tx_axis_tdata, - output wire [PORTS*AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep, - output wire [PORTS-1:0] tx_axis_tvalid, - input wire [PORTS-1:0] tx_axis_tready, - output wire [PORTS-1:0] tx_axis_tlast, - output wire [PORTS-1:0] tx_axis_tuser, + output wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata, + output wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep, + output wire tx_axis_tvalid, + input wire tx_axis_tready, + output wire tx_axis_tlast, + output wire [AXIS_TX_ID_WIDTH-1:0] tx_axis_tid, + output wire [AXIS_TX_DEST_WIDTH-1:0] tx_axis_tdest, + output wire [AXIS_TX_USER_WIDTH-1:0] tx_axis_tuser, /* * Transmit timestamp input */ - input wire [PORTS*PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts_96, - input wire [PORTS-1:0] s_axis_tx_ptp_ts_valid, - output wire [PORTS-1:0] s_axis_tx_ptp_ts_ready, + input wire [PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts, + input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag, + input wire s_axis_tx_ptp_ts_valid, + output wire s_axis_tx_ptp_ts_ready, /* * Receive data input */ - input wire [PORTS*AXIS_DATA_WIDTH-1:0] rx_axis_tdata, - input wire [PORTS*AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep, - input wire [PORTS-1:0] rx_axis_tvalid, - output wire [PORTS-1:0] rx_axis_tready, - input wire [PORTS-1:0] rx_axis_tlast, - input wire [PORTS-1:0] rx_axis_tuser, - - /* - * Receive timestamp input - */ - input wire [PORTS*PTP_TS_WIDTH-1:0] s_axis_rx_ptp_ts_96, - input wire [PORTS-1:0] s_axis_rx_ptp_ts_valid, - output wire [PORTS-1:0] s_axis_rx_ptp_ts_ready, + input wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata, + input wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep, + input wire rx_axis_tvalid, + output wire rx_axis_tready, + input wire rx_axis_tlast, + input wire [AXIS_RX_ID_WIDTH-1:0] rx_axis_tid, + input wire [AXIS_RX_DEST_WIDTH-1:0] rx_axis_tdest, + input wire [AXIS_RX_USER_WIDTH-1:0] rx_axis_tuser, /* * PTP clock @@ -363,7 +379,9 @@ parameter EVENT_TYPE_WIDTH = 16; parameter MAX_DESC_TABLE_SIZE = TX_DESC_TABLE_SIZE > RX_DESC_TABLE_SIZE ? TX_DESC_TABLE_SIZE : RX_DESC_TABLE_SIZE; -parameter REQ_TAG_WIDTH = $clog2(MAX_DESC_TABLE_SIZE) + 1 + $clog2(PORTS+1); +parameter REQ_TAG_WIDTH = $clog2(MAX_DESC_TABLE_SIZE) + $clog2(PORTS); +parameter REQ_TAG_WIDTH_INT = REQ_TAG_WIDTH - $clog2(PORTS); + parameter DESC_REQ_TAG_WIDTH = $clog2(MAX_DESC_TABLE_SIZE) + 1 + $clog2(PORTS+1); parameter QUEUE_REQ_TAG_WIDTH = $clog2(MAX_DESC_TABLE_SIZE) + 1 + $clog2(PORTS+1); @@ -375,7 +393,7 @@ parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH; parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH; parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH > RX_CPL_QUEUE_INDEX_WIDTH ? TX_CPL_QUEUE_INDEX_WIDTH : RX_CPL_QUEUE_INDEX_WIDTH; -parameter PORT_DESC_REQ_TAG_WIDTH = DESC_REQ_TAG_WIDTH - $clog2(PORTS+1); +parameter DESC_REQ_TAG_WIDTH_INT = DESC_REQ_TAG_WIDTH - $clog2(3); parameter AXIL_CSR_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((PORTS+3)/8); parameter AXIL_CTRL_ADDR_WIDTH = AXIL_ADDR_WIDTH-5-$clog2((PORTS+3)/8); @@ -547,42 +565,6 @@ wire [PORTS*2-1:0] axil_port_rresp; wire [PORTS-1:0] axil_port_rvalid; wire [PORTS-1:0] axil_port_rready; -// DMA -wire [PORTS*DMA_ADDR_WIDTH-1:0] port_dma_read_desc_dma_addr; -wire [PORTS*RAM_ADDR_WIDTH-1:0] port_dma_read_desc_ram_addr; -wire [PORTS*DMA_LEN_WIDTH-1:0] port_dma_read_desc_len; -wire [PORTS*DMA_TAG_WIDTH_INT-1:0] port_dma_read_desc_tag; -wire [PORTS-1:0] port_dma_read_desc_valid; -wire [PORTS-1:0] port_dma_read_desc_ready; - -wire [PORTS*DMA_TAG_WIDTH_INT-1:0] port_dma_read_desc_status_tag; -wire [PORTS*4-1:0] port_dma_read_desc_status_error; -wire [PORTS-1:0] port_dma_read_desc_status_valid; - -wire [PORTS*DMA_ADDR_WIDTH-1:0] port_dma_write_desc_dma_addr; -wire [PORTS*RAM_ADDR_WIDTH-1:0] port_dma_write_desc_ram_addr; -wire [PORTS*DMA_LEN_WIDTH-1:0] port_dma_write_desc_len; -wire [PORTS*DMA_TAG_WIDTH_INT-1:0] port_dma_write_desc_tag; -wire [PORTS-1:0] port_dma_write_desc_valid; -wire [PORTS-1:0] port_dma_write_desc_ready; - -wire [PORTS*DMA_TAG_WIDTH_INT-1:0] port_dma_write_desc_status_tag; -wire [PORTS*4-1:0] port_dma_write_desc_status_error; -wire [PORTS-1:0] port_dma_write_desc_status_valid; - -wire [PORTS*SEG_COUNT*SEG_BE_WIDTH-1:0] port_dma_ram_wr_cmd_be; -wire [PORTS*SEG_COUNT*SEG_ADDR_WIDTH-1:0] port_dma_ram_wr_cmd_addr; -wire [PORTS*SEG_COUNT*SEG_DATA_WIDTH-1:0] port_dma_ram_wr_cmd_data; -wire [PORTS*SEG_COUNT-1:0] port_dma_ram_wr_cmd_valid; -wire [PORTS*SEG_COUNT-1:0] port_dma_ram_wr_cmd_ready; -wire [PORTS*SEG_COUNT-1:0] port_dma_ram_wr_done; -wire [PORTS*SEG_COUNT*SEG_ADDR_WIDTH-1:0] port_dma_ram_rd_cmd_addr; -wire [PORTS*SEG_COUNT-1:0] port_dma_ram_rd_cmd_valid; -wire [PORTS*SEG_COUNT-1:0] port_dma_ram_rd_cmd_ready; -wire [PORTS*SEG_COUNT*SEG_DATA_WIDTH-1:0] port_dma_ram_rd_resp_data; -wire [PORTS*SEG_COUNT-1:0] port_dma_ram_rd_resp_valid; -wire [PORTS*SEG_COUNT-1:0] port_dma_ram_rd_resp_ready; - // Queue management wire [CPL_QUEUE_INDEX_WIDTH-1:0] event_enqueue_req_queue; wire [QUEUE_REQ_TAG_WIDTH-1:0] event_enqueue_req_tag; @@ -680,86 +662,121 @@ wire [QUEUE_OP_TAG_WIDTH-1:0] rx_cpl_enqueue_commit_op_tag; wire rx_cpl_enqueue_commit_valid; wire rx_cpl_enqueue_commit_ready; -// descriptor and completion -wire [0:0] desc_req_sel; -wire [QUEUE_INDEX_WIDTH-1:0] desc_req_queue; -wire [DESC_REQ_TAG_WIDTH-1:0] desc_req_tag; -wire desc_req_valid; -wire desc_req_ready; +// descriptors +wire [0:0] desc_req_sel; +wire [QUEUE_INDEX_WIDTH-1:0] desc_req_queue; +wire [DESC_REQ_TAG_WIDTH-1:0] desc_req_tag; +wire desc_req_valid; +wire desc_req_ready; -wire [QUEUE_INDEX_WIDTH-1:0] desc_req_status_queue; -wire [QUEUE_PTR_WIDTH-1:0] desc_req_status_ptr; -wire [CPL_QUEUE_INDEX_WIDTH-1:0] desc_req_status_cpl; -wire [DESC_REQ_TAG_WIDTH-1:0] desc_req_status_tag; -wire desc_req_status_empty; -wire desc_req_status_error; -wire desc_req_status_valid; +wire [QUEUE_INDEX_WIDTH-1:0] desc_req_status_queue; +wire [QUEUE_PTR_WIDTH-1:0] desc_req_status_ptr; +wire [CPL_QUEUE_INDEX_WIDTH-1:0] desc_req_status_cpl; +wire [DESC_REQ_TAG_WIDTH-1:0] desc_req_status_tag; +wire desc_req_status_empty; +wire desc_req_status_error; +wire desc_req_status_valid; -wire [AXIS_DESC_DATA_WIDTH-1:0] axis_desc_tdata; -wire [AXIS_DESC_KEEP_WIDTH-1:0] axis_desc_tkeep; -wire axis_desc_tvalid; -wire axis_desc_tready; -wire axis_desc_tlast; -wire [DESC_REQ_TAG_WIDTH-1:0] axis_desc_tid; -wire axis_desc_tuser; +wire [AXIS_DESC_DATA_WIDTH-1:0] axis_desc_tdata; +wire [AXIS_DESC_KEEP_WIDTH-1:0] axis_desc_tkeep; +wire axis_desc_tvalid; +wire axis_desc_tready; +wire axis_desc_tlast; +wire [DESC_REQ_TAG_WIDTH-1:0] axis_desc_tid; +wire axis_desc_tuser; -wire [PORTS*1-1:0] port_desc_req_sel; -wire [PORTS*QUEUE_INDEX_WIDTH-1:0] port_desc_req_queue; -wire [PORTS*PORT_DESC_REQ_TAG_WIDTH-1:0] port_desc_req_tag; -wire [PORTS-1:0] port_desc_req_valid; -wire [PORTS-1:0] port_desc_req_ready; +wire [0:0] rx_desc_req_sel = 1'b1; +wire [QUEUE_INDEX_WIDTH-1:0] rx_desc_req_queue; +wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_desc_req_tag; +wire rx_desc_req_valid; +wire rx_desc_req_ready; -wire [PORTS*QUEUE_INDEX_WIDTH-1:0] port_desc_req_status_queue; -wire [PORTS*QUEUE_PTR_WIDTH-1:0] port_desc_req_status_ptr; -wire [PORTS*CPL_QUEUE_INDEX_WIDTH-1:0] port_desc_req_status_cpl; -wire [PORTS*PORT_DESC_REQ_TAG_WIDTH-1:0] port_desc_req_status_tag; -wire [PORTS-1:0] port_desc_req_status_empty; -wire [PORTS-1:0] port_desc_req_status_error; -wire [PORTS-1:0] port_desc_req_status_valid; +wire [QUEUE_INDEX_WIDTH-1:0] rx_desc_req_status_queue; +wire [QUEUE_PTR_WIDTH-1:0] rx_desc_req_status_ptr; +wire [CPL_QUEUE_INDEX_WIDTH-1:0] rx_desc_req_status_cpl; +wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_desc_req_status_tag; +wire rx_desc_req_status_empty; +wire rx_desc_req_status_error; +wire rx_desc_req_status_valid; -wire [PORTS*AXIS_DESC_DATA_WIDTH-1:0] port_axis_desc_tdata; -wire [PORTS*AXIS_DESC_KEEP_WIDTH-1:0] port_axis_desc_tkeep; -wire [PORTS-1:0] port_axis_desc_tvalid; -wire [PORTS-1:0] port_axis_desc_tready; -wire [PORTS-1:0] port_axis_desc_tlast; -wire [PORTS*PORT_DESC_REQ_TAG_WIDTH-1:0] port_axis_desc_tid; -wire [PORTS-1:0] port_axis_desc_tuser; +wire [AXIS_DESC_DATA_WIDTH-1:0] rx_desc_tdata; +wire [AXIS_DESC_KEEP_WIDTH-1:0] rx_desc_tkeep; +wire rx_desc_tvalid; +wire rx_desc_tready; +wire rx_desc_tlast; +wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_desc_tid; +wire rx_desc_tuser; -wire [1:0] cpl_req_sel; -wire [QUEUE_INDEX_WIDTH-1:0] cpl_req_queue; -wire [DESC_REQ_TAG_WIDTH-1:0] cpl_req_tag; -wire [CPL_SIZE*8-1:0] cpl_req_data; -wire cpl_req_valid; -wire cpl_req_ready; +wire [0:0] tx_desc_req_sel = 1'b0; +wire [QUEUE_INDEX_WIDTH-1:0] tx_desc_req_queue; +wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_desc_req_tag; +wire tx_desc_req_valid; +wire tx_desc_req_ready; -wire [DESC_REQ_TAG_WIDTH-1:0] cpl_req_status_tag; -wire cpl_req_status_full; -wire cpl_req_status_error; -wire cpl_req_status_valid; +wire [QUEUE_INDEX_WIDTH-1:0] tx_desc_req_status_queue; +wire [QUEUE_PTR_WIDTH-1:0] tx_desc_req_status_ptr; +wire [CPL_QUEUE_INDEX_WIDTH-1:0] tx_desc_req_status_cpl; +wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_desc_req_status_tag; +wire tx_desc_req_status_empty; +wire tx_desc_req_status_error; +wire tx_desc_req_status_valid; -wire [1:0] event_cpl_req_sel = 2'd2; -wire [QUEUE_INDEX_WIDTH-1:0] event_cpl_req_queue; -wire [PORT_DESC_REQ_TAG_WIDTH-1:0] event_cpl_req_tag; -wire [CPL_SIZE*8-1:0] event_cpl_req_data; -wire event_cpl_req_valid; -wire event_cpl_req_ready; +wire [AXIS_DESC_DATA_WIDTH-1:0] tx_desc_tdata; +wire [AXIS_DESC_KEEP_WIDTH-1:0] tx_desc_tkeep; +wire tx_desc_tvalid; +wire tx_desc_tready; +wire tx_desc_tlast; +wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_desc_tid; +wire tx_desc_tuser; -wire [PORT_DESC_REQ_TAG_WIDTH-1:0] event_cpl_req_status_tag; -wire event_cpl_req_status_full; -wire event_cpl_req_status_error; -wire event_cpl_req_status_valid; +// completions +wire [1:0] cpl_req_sel; +wire [QUEUE_INDEX_WIDTH-1:0] cpl_req_queue; +wire [DESC_REQ_TAG_WIDTH-1:0] cpl_req_tag; +wire [CPL_SIZE*8-1:0] cpl_req_data; +wire cpl_req_valid; +wire cpl_req_ready; -wire [PORTS*2-1:0] port_cpl_req_sel; -wire [PORTS*QUEUE_INDEX_WIDTH-1:0] port_cpl_req_queue; -wire [PORTS*PORT_DESC_REQ_TAG_WIDTH-1:0] port_cpl_req_tag; -wire [PORTS*CPL_SIZE*8-1:0] port_cpl_req_data; -wire [PORTS-1:0] port_cpl_req_valid; -wire [PORTS-1:0] port_cpl_req_ready; +wire [DESC_REQ_TAG_WIDTH-1:0] cpl_req_status_tag; +wire cpl_req_status_full; +wire cpl_req_status_error; +wire cpl_req_status_valid; -wire [PORTS*PORT_DESC_REQ_TAG_WIDTH-1:0] port_cpl_req_status_tag; -wire [PORTS-1:0] port_cpl_req_status_full; -wire [PORTS-1:0] port_cpl_req_status_error; -wire [PORTS-1:0] port_cpl_req_status_valid; +wire [1:0] event_cpl_req_sel = 2'd2; +wire [QUEUE_INDEX_WIDTH-1:0] event_cpl_req_queue; +wire [DESC_REQ_TAG_WIDTH_INT-1:0] event_cpl_req_tag; +wire [CPL_SIZE*8-1:0] event_cpl_req_data; +wire event_cpl_req_valid; +wire event_cpl_req_ready; + +wire [DESC_REQ_TAG_WIDTH_INT-1:0] event_cpl_req_status_tag; +wire event_cpl_req_status_full; +wire event_cpl_req_status_error; +wire event_cpl_req_status_valid; + +wire [1:0] rx_cpl_req_sel = 2'd1; +wire [QUEUE_INDEX_WIDTH-1:0] rx_cpl_req_queue; +wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_cpl_req_tag; +wire [CPL_SIZE*8-1:0] rx_cpl_req_data; +wire rx_cpl_req_valid; +wire rx_cpl_req_ready; + +wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_cpl_req_status_tag; +wire rx_cpl_req_status_full; +wire rx_cpl_req_status_error; +wire rx_cpl_req_status_valid; + +wire [1:0] tx_cpl_req_sel = 2'd0; +wire [QUEUE_INDEX_WIDTH-1:0] tx_cpl_req_queue; +wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_cpl_req_tag; +wire [CPL_SIZE*8-1:0] tx_cpl_req_data; +wire tx_cpl_req_valid; +wire tx_cpl_req_ready; + +wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_cpl_req_status_tag; +wire tx_cpl_req_status_full; +wire tx_cpl_req_status_error; +wire tx_cpl_req_status_valid; // events wire [EVENT_QUEUE_INDEX_WIDTH-1:0] axis_event_queue; @@ -1491,113 +1508,85 @@ rx_cpl_queue_manager_inst ( .enable(1'b1) ); -if (PORTS > 1) begin +desc_op_mux #( + .PORTS(2), + .SELECT_WIDTH(1), + .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), + .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), + .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH), + .S_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT), + .M_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH), + .AXIS_DATA_WIDTH(AXIS_DESC_DATA_WIDTH), + .AXIS_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH), + .ARB_TYPE_ROUND_ROBIN(1), + .ARB_LSB_HIGH_PRIORITY(1) +) +desc_op_mux_inst ( + .clk(clk), + .rst(rst), - desc_op_mux #( - .PORTS(PORTS), - .SELECT_WIDTH(1), - .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), - .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), - .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH), - .S_REQ_TAG_WIDTH(PORT_DESC_REQ_TAG_WIDTH), - .M_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH), - .AXIS_DATA_WIDTH(AXIS_DESC_DATA_WIDTH), - .AXIS_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH), - .ARB_TYPE_ROUND_ROBIN(1), - .ARB_LSB_HIGH_PRIORITY(1) - ) - desc_op_mux_inst ( - .clk(clk), - .rst(rst), + /* + * Descriptor request output + */ + .m_axis_req_sel(desc_req_sel), + .m_axis_req_queue(desc_req_queue), + .m_axis_req_tag(desc_req_tag), + .m_axis_req_valid(desc_req_valid), + .m_axis_req_ready(desc_req_ready), - /* - * Descriptor request output - */ - .m_axis_req_sel(desc_req_sel), - .m_axis_req_queue(desc_req_queue), - .m_axis_req_tag(desc_req_tag), - .m_axis_req_valid(desc_req_valid), - .m_axis_req_ready(desc_req_ready), + /* + * Descriptor request status input + */ + .s_axis_req_status_queue(desc_req_status_queue), + .s_axis_req_status_ptr(desc_req_status_ptr), + .s_axis_req_status_cpl(desc_req_status_cpl), + .s_axis_req_status_tag(desc_req_status_tag), + .s_axis_req_status_empty(desc_req_status_empty), + .s_axis_req_status_error(desc_req_status_error), + .s_axis_req_status_valid(desc_req_status_valid), - /* - * Descriptor request status input - */ - .s_axis_req_status_queue(desc_req_status_queue), - .s_axis_req_status_ptr(desc_req_status_ptr), - .s_axis_req_status_cpl(desc_req_status_cpl), - .s_axis_req_status_tag(desc_req_status_tag), - .s_axis_req_status_empty(desc_req_status_empty), - .s_axis_req_status_error(desc_req_status_error), - .s_axis_req_status_valid(desc_req_status_valid), + /* + * Descriptor data input + */ + .s_axis_desc_tdata(axis_desc_tdata), + .s_axis_desc_tkeep(axis_desc_tkeep), + .s_axis_desc_tvalid(axis_desc_tvalid), + .s_axis_desc_tready(axis_desc_tready), + .s_axis_desc_tlast(axis_desc_tlast), + .s_axis_desc_tid(axis_desc_tid), + .s_axis_desc_tuser(axis_desc_tuser), - /* - * Descriptor data input - */ - .s_axis_desc_tdata(axis_desc_tdata), - .s_axis_desc_tkeep(axis_desc_tkeep), - .s_axis_desc_tvalid(axis_desc_tvalid), - .s_axis_desc_tready(axis_desc_tready), - .s_axis_desc_tlast(axis_desc_tlast), - .s_axis_desc_tid(axis_desc_tid), - .s_axis_desc_tuser(axis_desc_tuser), + /* + * Descriptor request input + */ + .s_axis_req_sel({rx_desc_req_sel, tx_desc_req_sel}), + .s_axis_req_queue({rx_desc_req_queue, tx_desc_req_queue}), + .s_axis_req_tag({rx_desc_req_tag, tx_desc_req_tag}), + .s_axis_req_valid({rx_desc_req_valid, tx_desc_req_valid}), + .s_axis_req_ready({rx_desc_req_ready, tx_desc_req_ready}), - /* - * Descriptor request input - */ - .s_axis_req_sel(port_desc_req_sel), - .s_axis_req_queue(port_desc_req_queue), - .s_axis_req_tag(port_desc_req_tag), - .s_axis_req_valid(port_desc_req_valid), - .s_axis_req_ready(port_desc_req_ready), + /* + * Descriptor response output + */ + .m_axis_req_status_queue({rx_desc_req_status_queue, tx_desc_req_status_queue}), + .m_axis_req_status_ptr({rx_desc_req_status_ptr, tx_desc_req_status_ptr}), + .m_axis_req_status_cpl({rx_desc_req_status_cpl, tx_desc_req_status_cpl}), + .m_axis_req_status_tag({rx_desc_req_status_tag, tx_desc_req_status_tag}), + .m_axis_req_status_empty({rx_desc_req_status_empty, tx_desc_req_status_empty}), + .m_axis_req_status_error({rx_desc_req_status_error, tx_desc_req_status_error}), + .m_axis_req_status_valid({rx_desc_req_status_valid, tx_desc_req_status_valid}), - /* - * Descriptor request status output - */ - .m_axis_req_status_queue(port_desc_req_status_queue), - .m_axis_req_status_ptr(port_desc_req_status_ptr), - .m_axis_req_status_cpl(port_desc_req_status_cpl), - .m_axis_req_status_tag(port_desc_req_status_tag), - .m_axis_req_status_empty(port_desc_req_status_empty), - .m_axis_req_status_error(port_desc_req_status_error), - .m_axis_req_status_valid(port_desc_req_status_valid), - - /* - * Descriptor data output - */ - .m_axis_desc_tdata(port_axis_desc_tdata), - .m_axis_desc_tkeep(port_axis_desc_tkeep), - .m_axis_desc_tvalid(port_axis_desc_tvalid), - .m_axis_desc_tready(port_axis_desc_tready), - .m_axis_desc_tlast(port_axis_desc_tlast), - .m_axis_desc_tid(port_axis_desc_tid), - .m_axis_desc_tuser(port_axis_desc_tuser) - ); - -end else begin - - assign desc_req_sel = port_desc_req_sel; - assign desc_req_queue = port_desc_req_queue; - assign desc_req_tag = port_desc_req_tag; - assign desc_req_valid = port_desc_req_valid; - assign port_desc_req_ready = desc_req_ready; - - assign port_desc_req_status_queue = desc_req_status_queue; - assign port_desc_req_status_ptr = desc_req_status_ptr; - assign port_desc_req_status_cpl = desc_req_status_cpl; - assign port_desc_req_status_tag = desc_req_status_tag; - assign port_desc_req_status_empty = desc_req_status_empty; - assign port_desc_req_status_error = desc_req_status_error; - assign port_desc_req_status_valid = desc_req_status_valid; - - assign port_axis_desc_tdata = axis_desc_tdata; - assign port_axis_desc_tkeep = axis_desc_tkeep; - assign port_axis_desc_tvalid = axis_desc_tvalid; - assign axis_desc_tready = port_axis_desc_tready; - assign port_axis_desc_tlast = axis_desc_tlast; - assign port_axis_desc_tid = axis_desc_tid; - assign port_axis_desc_tuser = axis_desc_tuser; - -end + /* + * Descriptor data output + */ + .m_axis_desc_tdata({rx_desc_tdata, tx_desc_tdata}), + .m_axis_desc_tkeep({rx_desc_tkeep, tx_desc_tkeep}), + .m_axis_desc_tvalid({rx_desc_tvalid, tx_desc_tvalid}), + .m_axis_desc_tready({rx_desc_tready, tx_desc_tready}), + .m_axis_desc_tlast({rx_desc_tlast, tx_desc_tlast}), + .m_axis_desc_tid({rx_desc_tid, tx_desc_tid}), + .m_axis_desc_tuser({rx_desc_tuser, tx_desc_tuser}) +); desc_fetch #( .PORTS(2), @@ -1724,10 +1713,10 @@ desc_fetch_inst ( assign m_axis_ctrl_dma_read_desc_ram_sel = 0; cpl_op_mux #( - .PORTS(PORTS+1), + .PORTS(3), .SELECT_WIDTH(2), .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), - .S_REQ_TAG_WIDTH(PORT_DESC_REQ_TAG_WIDTH), + .S_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT), .M_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH), .CPL_SIZE(CPL_SIZE), .ARB_TYPE_ROUND_ROBIN(1), @@ -1758,20 +1747,20 @@ cpl_op_mux_inst ( /* * Completion request input */ - .s_axis_req_sel({port_cpl_req_sel, event_cpl_req_sel}), - .s_axis_req_queue({port_cpl_req_queue, event_cpl_req_queue}), - .s_axis_req_tag({port_cpl_req_tag, event_cpl_req_tag}), - .s_axis_req_data({port_cpl_req_data, event_cpl_req_data}), - .s_axis_req_valid({port_cpl_req_valid, event_cpl_req_valid}), - .s_axis_req_ready({port_cpl_req_ready, event_cpl_req_ready}), + .s_axis_req_sel({event_cpl_req_sel, rx_cpl_req_sel, tx_cpl_req_sel}), + .s_axis_req_queue({event_cpl_req_queue, rx_cpl_req_queue, tx_cpl_req_queue}), + .s_axis_req_tag({event_cpl_req_tag, rx_cpl_req_tag, tx_cpl_req_tag}), + .s_axis_req_data({event_cpl_req_data, rx_cpl_req_data, tx_cpl_req_data}), + .s_axis_req_valid({event_cpl_req_valid, rx_cpl_req_valid, tx_cpl_req_valid}), + .s_axis_req_ready({event_cpl_req_ready, rx_cpl_req_ready, tx_cpl_req_ready}), /* * Completion response output */ - .m_axis_req_status_tag({port_cpl_req_status_tag, event_cpl_req_status_tag}), - .m_axis_req_status_full({port_cpl_req_status_full, event_cpl_req_status_full}), - .m_axis_req_status_error({port_cpl_req_status_error, event_cpl_req_status_error}), - .m_axis_req_status_valid({port_cpl_req_status_valid, event_cpl_req_status_valid}) + .m_axis_req_status_tag({event_cpl_req_status_tag, rx_cpl_req_status_tag, tx_cpl_req_status_tag}), + .m_axis_req_status_full({event_cpl_req_status_full, rx_cpl_req_status_full, tx_cpl_req_status_full}), + .m_axis_req_status_error({event_cpl_req_status_error, rx_cpl_req_status_error, tx_cpl_req_status_error}), + .m_axis_req_status_valid({event_cpl_req_status_valid, rx_cpl_req_status_valid, tx_cpl_req_status_valid}) ); cpl_write #( @@ -1876,179 +1865,6 @@ cpl_write_inst ( assign m_axis_ctrl_dma_write_desc_ram_sel = 0; -if (PORTS > 1) begin - - dma_if_mux # - ( - .PORTS(PORTS), - .SEG_COUNT(SEG_COUNT), - .SEG_DATA_WIDTH(SEG_DATA_WIDTH), - .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), - .SEG_BE_WIDTH(SEG_BE_WIDTH), - .S_RAM_SEL_WIDTH(0), - .M_RAM_SEL_WIDTH(RAM_SEL_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), - .LEN_WIDTH(DMA_LEN_WIDTH), - .S_TAG_WIDTH(DMA_TAG_WIDTH_INT), - .M_TAG_WIDTH(DMA_TAG_WIDTH), - .ARB_TYPE_ROUND_ROBIN(1), - .ARB_LSB_HIGH_PRIORITY(1) - ) - dma_if_mux_inst ( - .clk(clk), - .rst(rst), - - /* - * Read descriptor output (to DMA interface) - */ - .m_axis_read_desc_dma_addr(m_axis_data_dma_read_desc_dma_addr), - .m_axis_read_desc_ram_sel(m_axis_data_dma_read_desc_ram_sel), - .m_axis_read_desc_ram_addr(m_axis_data_dma_read_desc_ram_addr), - .m_axis_read_desc_len(m_axis_data_dma_read_desc_len), - .m_axis_read_desc_tag(m_axis_data_dma_read_desc_tag), - .m_axis_read_desc_valid(m_axis_data_dma_read_desc_valid), - .m_axis_read_desc_ready(m_axis_data_dma_read_desc_ready), - - /* - * Read descriptor status input (from DMA interface) - */ - .s_axis_read_desc_status_tag(s_axis_data_dma_read_desc_status_tag), - .s_axis_read_desc_status_error(s_axis_data_dma_read_desc_status_error), - .s_axis_read_desc_status_valid(s_axis_data_dma_read_desc_status_valid), - - /* - * Read descriptor input - */ - .s_axis_read_desc_dma_addr(port_dma_read_desc_dma_addr), - .s_axis_read_desc_ram_sel(0), - .s_axis_read_desc_ram_addr(port_dma_read_desc_ram_addr), - .s_axis_read_desc_len(port_dma_read_desc_len), - .s_axis_read_desc_tag(port_dma_read_desc_tag), - .s_axis_read_desc_valid(port_dma_read_desc_valid), - .s_axis_read_desc_ready(port_dma_read_desc_ready), - - /* - * Read descriptor status output - */ - .m_axis_read_desc_status_tag(port_dma_read_desc_status_tag), - .m_axis_read_desc_status_error(port_dma_read_desc_status_error), - .m_axis_read_desc_status_valid(port_dma_read_desc_status_valid), - - /* - * Write descriptor output (to DMA interface) - */ - .m_axis_write_desc_dma_addr(m_axis_data_dma_write_desc_dma_addr), - .m_axis_write_desc_ram_sel(m_axis_data_dma_write_desc_ram_sel), - .m_axis_write_desc_ram_addr(m_axis_data_dma_write_desc_ram_addr), - .m_axis_write_desc_len(m_axis_data_dma_write_desc_len), - .m_axis_write_desc_tag(m_axis_data_dma_write_desc_tag), - .m_axis_write_desc_valid(m_axis_data_dma_write_desc_valid), - .m_axis_write_desc_ready(m_axis_data_dma_write_desc_ready), - - /* - * Write descriptor status input (from DMA interface) - */ - .s_axis_write_desc_status_tag(s_axis_data_dma_write_desc_status_tag), - .s_axis_write_desc_status_error(s_axis_data_dma_write_desc_status_error), - .s_axis_write_desc_status_valid(s_axis_data_dma_write_desc_status_valid), - - /* - * Write descriptor input - */ - .s_axis_write_desc_dma_addr(port_dma_write_desc_dma_addr), - .s_axis_write_desc_ram_sel(0), - .s_axis_write_desc_ram_addr(port_dma_write_desc_ram_addr), - .s_axis_write_desc_len(port_dma_write_desc_len), - .s_axis_write_desc_tag(port_dma_write_desc_tag), - .s_axis_write_desc_valid(port_dma_write_desc_valid), - .s_axis_write_desc_ready(port_dma_write_desc_ready), - - /* - * Write descriptor status output - */ - .m_axis_write_desc_status_tag(port_dma_write_desc_status_tag), - .m_axis_write_desc_status_error(port_dma_write_desc_status_error), - .m_axis_write_desc_status_valid(port_dma_write_desc_status_valid), - - /* - * RAM interface (from DMA interface) - */ - .if_ram_wr_cmd_sel(data_dma_ram_wr_cmd_sel), - .if_ram_wr_cmd_be(data_dma_ram_wr_cmd_be), - .if_ram_wr_cmd_addr(data_dma_ram_wr_cmd_addr), - .if_ram_wr_cmd_data(data_dma_ram_wr_cmd_data), - .if_ram_wr_cmd_valid(data_dma_ram_wr_cmd_valid), - .if_ram_wr_cmd_ready(data_dma_ram_wr_cmd_ready), - .if_ram_wr_done(data_dma_ram_wr_done), - .if_ram_rd_cmd_sel(data_dma_ram_rd_cmd_sel), - .if_ram_rd_cmd_addr(data_dma_ram_rd_cmd_addr), - .if_ram_rd_cmd_valid(data_dma_ram_rd_cmd_valid), - .if_ram_rd_cmd_ready(data_dma_ram_rd_cmd_ready), - .if_ram_rd_resp_data(data_dma_ram_rd_resp_data), - .if_ram_rd_resp_valid(data_dma_ram_rd_resp_valid), - .if_ram_rd_resp_ready(data_dma_ram_rd_resp_ready), - - /* - * RAM interface - */ - .ram_wr_cmd_sel(), - .ram_wr_cmd_be(port_dma_ram_wr_cmd_be), - .ram_wr_cmd_addr(port_dma_ram_wr_cmd_addr), - .ram_wr_cmd_data(port_dma_ram_wr_cmd_data), - .ram_wr_cmd_valid(port_dma_ram_wr_cmd_valid), - .ram_wr_cmd_ready(port_dma_ram_wr_cmd_ready), - .ram_wr_done(port_dma_ram_wr_done), - .ram_rd_cmd_sel(), - .ram_rd_cmd_addr(port_dma_ram_rd_cmd_addr), - .ram_rd_cmd_valid(port_dma_ram_rd_cmd_valid), - .ram_rd_cmd_ready(port_dma_ram_rd_cmd_ready), - .ram_rd_resp_data(port_dma_ram_rd_resp_data), - .ram_rd_resp_valid(port_dma_ram_rd_resp_valid), - .ram_rd_resp_ready(port_dma_ram_rd_resp_ready) - ); - -end else begin - - assign m_axis_data_dma_read_desc_dma_addr = port_dma_read_desc_dma_addr; - assign m_axis_data_dma_read_desc_ram_sel = 0; - assign m_axis_data_dma_read_desc_ram_addr = port_dma_read_desc_ram_addr; - assign m_axis_data_dma_read_desc_len = port_dma_read_desc_len; - assign m_axis_data_dma_read_desc_tag = port_dma_read_desc_tag; - assign m_axis_data_dma_read_desc_valid = port_dma_read_desc_valid; - assign port_dma_read_desc_ready = m_axis_data_dma_read_desc_ready; - - assign port_dma_read_desc_status_tag = s_axis_data_dma_read_desc_status_tag; - assign port_dma_read_desc_status_error = s_axis_data_dma_read_desc_status_error; - assign port_dma_read_desc_status_valid = s_axis_data_dma_read_desc_status_valid; - - assign m_axis_data_dma_write_desc_dma_addr = port_dma_write_desc_dma_addr; - assign m_axis_data_dma_write_desc_ram_sel = 0; - assign m_axis_data_dma_write_desc_ram_addr = port_dma_write_desc_ram_addr; - assign m_axis_data_dma_write_desc_len = port_dma_write_desc_len; - assign m_axis_data_dma_write_desc_tag = port_dma_write_desc_tag; - assign m_axis_data_dma_write_desc_valid = port_dma_write_desc_valid; - assign port_dma_write_desc_ready = m_axis_data_dma_write_desc_ready; - - assign port_dma_write_desc_status_tag = s_axis_data_dma_write_desc_status_tag; - assign port_dma_write_desc_status_error = s_axis_data_dma_write_desc_status_error; - assign port_dma_write_desc_status_valid = s_axis_data_dma_write_desc_status_valid; - - assign port_dma_ram_wr_cmd_be = data_dma_ram_wr_cmd_be; - assign port_dma_ram_wr_cmd_addr = data_dma_ram_wr_cmd_addr; - assign port_dma_ram_wr_cmd_data = data_dma_ram_wr_cmd_data; - assign port_dma_ram_wr_cmd_valid = data_dma_ram_wr_cmd_valid; - assign data_dma_ram_wr_cmd_ready = port_dma_ram_wr_cmd_ready; - assign data_dma_ram_wr_done = port_dma_ram_wr_done; - assign port_dma_ram_rd_cmd_addr = data_dma_ram_rd_cmd_addr; - assign port_dma_ram_rd_cmd_valid = data_dma_ram_rd_cmd_valid; - assign data_dma_ram_rd_cmd_ready = port_dma_ram_rd_cmd_ready; - assign data_dma_ram_rd_resp_data = port_dma_ram_rd_resp_data; - assign data_dma_ram_rd_resp_valid = port_dma_ram_rd_resp_valid; - assign port_dma_ram_rd_resp_ready = data_dma_ram_rd_resp_ready; - -end - event_mux #( .PORTS(2), .QUEUE_INDEX_WIDTH(EVENT_QUEUE_INDEX_WIDTH), @@ -2168,270 +1984,527 @@ rx_event_fifo ( .status_good_frame() ); +// TX + +wire [PORTS*TX_QUEUE_INDEX_WIDTH-1:0] tx_sched_req_queue; +wire [PORTS*REQ_TAG_WIDTH_INT-1:0] tx_sched_req_tag; +wire [PORTS*AXIS_TX_DEST_WIDTH-1:0] tx_sched_req_dest; +wire [PORTS-1:0] tx_sched_req_valid; +wire [PORTS-1:0] tx_sched_req_ready; + +wire [PORTS*DMA_CLIENT_LEN_WIDTH-1:0] tx_sched_req_status_len; +wire [PORTS*REQ_TAG_WIDTH_INT-1:0] tx_sched_req_status_tag; +wire [PORTS-1:0] tx_sched_req_status_valid; + +wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_req_queue; +wire [REQ_TAG_WIDTH-1:0] tx_req_tag; +wire [AXIS_TX_DEST_WIDTH-1:0] tx_req_dest; +wire tx_req_valid; +wire tx_req_ready; + +wire [DMA_CLIENT_LEN_WIDTH-1:0] tx_req_status_len; +wire [REQ_TAG_WIDTH-1:0] tx_req_status_tag; +wire tx_req_status_valid; + generate - genvar n; - for (n = 0; n < PORTS; n = n + 1) begin : port +genvar n; - assign port_cpl_req_sel[n*2+1 +: 1] = 1'b0; +for (n = 0; n < PORTS; n = n + 1) begin : port - mqnic_port #( - .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH_INT), - .REQ_TAG_WIDTH(REQ_TAG_WIDTH), - .DESC_REQ_TAG_WIDTH(PORT_DESC_REQ_TAG_WIDTH), - .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), - .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), - .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), - .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH), - .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .DESC_TABLE_DMA_OP_COUNT_WIDTH(((2**LOG_BLOCK_SIZE_WIDTH)-1)+1), - .TX_MAX_DESC_REQ(TX_MAX_DESC_REQ), - .TX_DESC_FIFO_SIZE(TX_MAX_DESC_REQ*(2**((2**LOG_BLOCK_SIZE_WIDTH)-1))), - .RX_MAX_DESC_REQ(RX_MAX_DESC_REQ), - .RX_DESC_FIFO_SIZE(RX_MAX_DESC_REQ*(2**((2**LOG_BLOCK_SIZE_WIDTH)-1))), - .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), - .RX_RSS_ENABLE(RX_RSS_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), - .REG_DATA_WIDTH(AXIL_DATA_WIDTH), - .REG_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), - .REG_STRB_WIDTH(AXIL_STRB_WIDTH), - .RB_BASE_ADDR(PORT_RB_BASE_ADDR + PORT_RB_STRIDE*n), - .RB_NEXT_PTR(n < PORTS-1 ? PORT_RB_BASE_ADDR + PORT_RB_STRIDE*(n+1) : 0), - .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(AXIL_PORT_ADDR_WIDTH), - .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), - .AXIL_OFFSET(AXIL_PORT_BASE_ADDR + (2**AXIL_PORT_ADDR_WIDTH)*n), - .SEG_COUNT(SEG_COUNT), - .SEG_DATA_WIDTH(SEG_DATA_WIDTH), - .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), - .SEG_BE_WIDTH(SEG_BE_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .RAM_PIPELINE(RAM_PIPELINE), - .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), - .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .MAX_RX_SIZE(MAX_RX_SIZE), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE), - .DESC_SIZE(DESC_SIZE), - .CPL_SIZE(CPL_SIZE), - .AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH), - .AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH) - ) - port_inst ( - .clk(clk), - .rst(rst), + mqnic_tx_scheduler_block #( + .PORTS(PORTS), + .INDEX(n), + .REG_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_STRB_WIDTH), + .RB_BASE_ADDR(PORT_RB_BASE_ADDR + PORT_RB_STRIDE*n), + .RB_NEXT_PTR(n < PORTS-1 ? PORT_RB_BASE_ADDR + PORT_RB_STRIDE*(n+1) : 0), + .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(AXIL_PORT_ADDR_WIDTH), + .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), + .AXIL_OFFSET(AXIL_PORT_BASE_ADDR + (2**AXIL_PORT_ADDR_WIDTH)*n), + .LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), + .REQ_TAG_WIDTH(REQ_TAG_WIDTH_INT), + .OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .AXIS_TX_DEST_WIDTH(AXIS_TX_DEST_WIDTH), + .MAX_TX_SIZE(MAX_TX_SIZE) + ) + scheduler_block ( + .clk(clk), + .rst(rst), - /* - * Descriptor request output - */ - .m_axis_desc_req_sel(port_desc_req_sel[n*1 +: 1]), - .m_axis_desc_req_queue(port_desc_req_queue[n*QUEUE_INDEX_WIDTH +: QUEUE_INDEX_WIDTH]), - .m_axis_desc_req_tag(port_desc_req_tag[n*PORT_DESC_REQ_TAG_WIDTH +: PORT_DESC_REQ_TAG_WIDTH]), - .m_axis_desc_req_valid(port_desc_req_valid[n +: 1]), - .m_axis_desc_req_ready(port_desc_req_ready[n +: 1]), + /* + * Control register interface + */ + .ctrl_reg_wr_addr(ctrl_reg_wr_addr), + .ctrl_reg_wr_data(ctrl_reg_wr_data), + .ctrl_reg_wr_strb(ctrl_reg_wr_strb), + .ctrl_reg_wr_en(ctrl_reg_wr_en), + .ctrl_reg_wr_wait(port_ctrl_reg_wr_wait[n]), + .ctrl_reg_wr_ack(port_ctrl_reg_wr_ack[n]), + .ctrl_reg_rd_addr(ctrl_reg_rd_addr), + .ctrl_reg_rd_en(ctrl_reg_rd_en), + .ctrl_reg_rd_data(port_ctrl_reg_rd_data[n]), + .ctrl_reg_rd_wait(port_ctrl_reg_rd_wait[n]), + .ctrl_reg_rd_ack(port_ctrl_reg_rd_ack[n]), - /* - * Descriptor response input - */ - .s_axis_desc_req_status_queue(port_desc_req_status_queue[n*QUEUE_INDEX_WIDTH +: QUEUE_INDEX_WIDTH]), - .s_axis_desc_req_status_ptr(port_desc_req_status_ptr[n*QUEUE_PTR_WIDTH +: QUEUE_PTR_WIDTH]), - .s_axis_desc_req_status_cpl(port_desc_req_status_cpl[n*CPL_QUEUE_INDEX_WIDTH +: CPL_QUEUE_INDEX_WIDTH]), - .s_axis_desc_req_status_tag(port_desc_req_status_tag[n*PORT_DESC_REQ_TAG_WIDTH +: PORT_DESC_REQ_TAG_WIDTH]), - .s_axis_desc_req_status_empty(port_desc_req_status_empty[n +: 1]), - .s_axis_desc_req_status_error(port_desc_req_status_error[n +: 1]), - .s_axis_desc_req_status_valid(port_desc_req_status_valid[n +: 1]), + /* + * AXI-Lite slave interface + */ + .s_axil_awaddr(axil_port_awaddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]), + .s_axil_awprot(axil_port_awprot[n*3 +: 3]), + .s_axil_awvalid(axil_port_awvalid[n +: 1]), + .s_axil_awready(axil_port_awready[n +: 1]), + .s_axil_wdata(axil_port_wdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]), + .s_axil_wstrb(axil_port_wstrb[n*AXIL_STRB_WIDTH +: AXIL_STRB_WIDTH]), + .s_axil_wvalid(axil_port_wvalid[n +: 1]), + .s_axil_wready(axil_port_wready[n +: 1]), + .s_axil_bresp(axil_port_bresp[n*2 +: 2]), + .s_axil_bvalid(axil_port_bvalid[n +: 1]), + .s_axil_bready(axil_port_bready[n +: 1]), + .s_axil_araddr(axil_port_araddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]), + .s_axil_arprot(axil_port_arprot[n*3 +: 3]), + .s_axil_arvalid(axil_port_arvalid[n +: 1]), + .s_axil_arready(axil_port_arready[n +: 1]), + .s_axil_rdata(axil_port_rdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]), + .s_axil_rresp(axil_port_rresp[n*2 +: 2]), + .s_axil_rvalid(axil_port_rvalid[n +: 1]), + .s_axil_rready(axil_port_rready[n +: 1]), - /* - * Descriptor data input - */ - .s_axis_desc_tdata(port_axis_desc_tdata[n*AXIS_DESC_DATA_WIDTH +: AXIS_DESC_DATA_WIDTH]), - .s_axis_desc_tkeep(port_axis_desc_tkeep[n*AXIS_DESC_KEEP_WIDTH +: AXIS_DESC_KEEP_WIDTH]), - .s_axis_desc_tvalid(port_axis_desc_tvalid[n +: 1]), - .s_axis_desc_tready(port_axis_desc_tready[n +: 1]), - .s_axis_desc_tlast(port_axis_desc_tlast[n +: 1]), - .s_axis_desc_tid(port_axis_desc_tid[n*PORT_DESC_REQ_TAG_WIDTH +: PORT_DESC_REQ_TAG_WIDTH]), - .s_axis_desc_tuser(port_axis_desc_tuser[n +: 1]), + /* + * Transmit request output (queue index) + */ + .m_axis_tx_req_queue(tx_sched_req_queue[n*TX_QUEUE_INDEX_WIDTH +: TX_QUEUE_INDEX_WIDTH]), + .m_axis_tx_req_tag(tx_sched_req_tag[n*REQ_TAG_WIDTH_INT +: REQ_TAG_WIDTH_INT]), + .m_axis_tx_req_dest(tx_sched_req_dest[n*AXIS_TX_DEST_WIDTH +: AXIS_TX_DEST_WIDTH]), + .m_axis_tx_req_valid(tx_sched_req_valid[n +: 1]), + .m_axis_tx_req_ready(tx_sched_req_ready[n +: 1]), - /* - * Completion request output - */ - .m_axis_cpl_req_sel(port_cpl_req_sel[n*2 +: 1]), - .m_axis_cpl_req_queue(port_cpl_req_queue[n*QUEUE_INDEX_WIDTH +: QUEUE_INDEX_WIDTH]), - .m_axis_cpl_req_tag(port_cpl_req_tag[n*PORT_DESC_REQ_TAG_WIDTH +: PORT_DESC_REQ_TAG_WIDTH]), - .m_axis_cpl_req_data(port_cpl_req_data[n*CPL_SIZE*8 +: CPL_SIZE*8]), - .m_axis_cpl_req_valid(port_cpl_req_valid[n +: 1]), - .m_axis_cpl_req_ready(port_cpl_req_ready[n +: 1]), + /* + * Transmit request status input + */ + .s_axis_tx_req_status_len(tx_sched_req_status_len[n*DMA_CLIENT_LEN_WIDTH +: DMA_CLIENT_LEN_WIDTH]), + .s_axis_tx_req_status_tag(tx_sched_req_status_tag[n*REQ_TAG_WIDTH_INT +: REQ_TAG_WIDTH_INT]), + .s_axis_tx_req_status_valid(tx_sched_req_status_valid[n +: 1]), - /* - * Completion response input - */ - .s_axis_cpl_req_status_tag(port_cpl_req_status_tag[n*PORT_DESC_REQ_TAG_WIDTH +: PORT_DESC_REQ_TAG_WIDTH]), - .s_axis_cpl_req_status_full(port_cpl_req_status_full[n +: 1]), - .s_axis_cpl_req_status_error(port_cpl_req_status_error[n +: 1]), - .s_axis_cpl_req_status_valid(port_cpl_req_status_valid[n +: 1]), + /* + * Doorbell input + */ + .s_axis_doorbell_queue(tx_doorbell_queue), + .s_axis_doorbell_valid(tx_doorbell_valid), - /* - * TX doorbell input - */ - .s_axis_tx_doorbell_queue(tx_doorbell_queue), - .s_axis_tx_doorbell_valid(tx_doorbell_valid), + /* + * PTP clock + */ + .ptp_ts_96(ptp_ts_96), + .ptp_ts_step(ptp_ts_step), - /* - * DMA read descriptor output - */ - .m_axis_dma_read_desc_dma_addr(port_dma_read_desc_dma_addr[n*DMA_ADDR_WIDTH +: DMA_ADDR_WIDTH]), - .m_axis_dma_read_desc_ram_addr(port_dma_read_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]), - .m_axis_dma_read_desc_len(port_dma_read_desc_len[n*DMA_LEN_WIDTH +: DMA_LEN_WIDTH]), - .m_axis_dma_read_desc_tag(port_dma_read_desc_tag[n*DMA_TAG_WIDTH_INT +: DMA_TAG_WIDTH_INT]), - .m_axis_dma_read_desc_valid(port_dma_read_desc_valid[n +: 1]), - .m_axis_dma_read_desc_ready(port_dma_read_desc_ready[n +: 1]), + /* + * Configuration + */ + .mtu(tx_mtu_reg) + ); - /* - * DMA read descriptor status input - */ - .s_axis_dma_read_desc_status_tag(port_dma_read_desc_status_tag[n*DMA_TAG_WIDTH_INT +: DMA_TAG_WIDTH_INT]), - .s_axis_dma_read_desc_status_error(port_dma_read_desc_status_error[n*4 +: 4]), - .s_axis_dma_read_desc_status_valid(port_dma_read_desc_status_valid[n +: 1]), +end - /* - * DMA write descriptor output - */ - .m_axis_dma_write_desc_dma_addr(port_dma_write_desc_dma_addr[n*DMA_ADDR_WIDTH +: DMA_ADDR_WIDTH]), - .m_axis_dma_write_desc_ram_addr(port_dma_write_desc_ram_addr[n*RAM_ADDR_WIDTH +: RAM_ADDR_WIDTH]), - .m_axis_dma_write_desc_len(port_dma_write_desc_len[n*DMA_LEN_WIDTH +: DMA_LEN_WIDTH]), - .m_axis_dma_write_desc_tag(port_dma_write_desc_tag[n*DMA_TAG_WIDTH_INT +: DMA_TAG_WIDTH_INT]), - .m_axis_dma_write_desc_valid(port_dma_write_desc_valid[n +: 1]), - .m_axis_dma_write_desc_ready(port_dma_write_desc_ready[n +: 1]), +if (PORTS > 1) begin - /* - * DMA write descriptor status input - */ - .s_axis_dma_write_desc_status_tag(port_dma_write_desc_status_tag[n*DMA_TAG_WIDTH_INT +: DMA_TAG_WIDTH_INT]), - .s_axis_dma_write_desc_status_error(port_dma_write_desc_status_error[n*4 +: 4]), - .s_axis_dma_write_desc_status_valid(port_dma_write_desc_status_valid[n +: 1]), + tx_req_mux #( + .PORTS(PORTS), + .QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .S_REQ_TAG_WIDTH(REQ_TAG_WIDTH_INT), + .M_REQ_TAG_WIDTH(REQ_TAG_WIDTH), + .DEST_WIDTH(AXIS_TX_DEST_WIDTH), + .LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), + .ARB_TYPE_ROUND_ROBIN(1), + .ARB_LSB_HIGH_PRIORITY(0) + ) + tx_req_mux_inst ( + .clk(clk), + .rst(rst), - /* - * Control register interface - */ - .ctrl_reg_wr_addr(ctrl_reg_wr_addr), - .ctrl_reg_wr_data(ctrl_reg_wr_data), - .ctrl_reg_wr_strb(ctrl_reg_wr_strb), - .ctrl_reg_wr_en(ctrl_reg_wr_en), - .ctrl_reg_wr_wait(port_ctrl_reg_wr_wait[n]), - .ctrl_reg_wr_ack(port_ctrl_reg_wr_ack[n]), - .ctrl_reg_rd_addr(ctrl_reg_rd_addr), - .ctrl_reg_rd_en(ctrl_reg_rd_en), - .ctrl_reg_rd_data(port_ctrl_reg_rd_data[n]), - .ctrl_reg_rd_wait(port_ctrl_reg_rd_wait[n]), - .ctrl_reg_rd_ack(port_ctrl_reg_rd_ack[n]), + /* + * Transmit request output (to transmit engine) + */ + .m_axis_req_queue(tx_req_queue), + .m_axis_req_tag(tx_req_tag), + .m_axis_req_dest(tx_req_dest), + .m_axis_req_valid(tx_req_valid), + .m_axis_req_ready(tx_req_ready), - /* - * AXI-Lite slave interface (schedulers) - */ - .s_axil_awaddr(axil_port_awaddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]), - .s_axil_awprot(axil_port_awprot[n*3 +: 3]), - .s_axil_awvalid(axil_port_awvalid[n +: 1]), - .s_axil_awready(axil_port_awready[n +: 1]), - .s_axil_wdata(axil_port_wdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]), - .s_axil_wstrb(axil_port_wstrb[n*AXIL_STRB_WIDTH +: AXIL_STRB_WIDTH]), - .s_axil_wvalid(axil_port_wvalid[n +: 1]), - .s_axil_wready(axil_port_wready[n +: 1]), - .s_axil_bresp(axil_port_bresp[n*2 +: 2]), - .s_axil_bvalid(axil_port_bvalid[n +: 1]), - .s_axil_bready(axil_port_bready[n +: 1]), - .s_axil_araddr(axil_port_araddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]), - .s_axil_arprot(axil_port_arprot[n*3 +: 3]), - .s_axil_arvalid(axil_port_arvalid[n +: 1]), - .s_axil_arready(axil_port_arready[n +: 1]), - .s_axil_rdata(axil_port_rdata[n*AXIL_DATA_WIDTH +: AXIL_DATA_WIDTH]), - .s_axil_rresp(axil_port_rresp[n*2 +: 2]), - .s_axil_rvalid(axil_port_rvalid[n +: 1]), - .s_axil_rready(axil_port_rready[n +: 1]), + /* + * Transmit request status input (from transmit engine) + */ + .s_axis_req_status_len(tx_req_status_len), + .s_axis_req_status_tag(tx_req_status_tag), + // .s_axis_req_status_empty(tx_req_status_empty), + // .s_axis_req_status_error(tx_req_status_error), + .s_axis_req_status_valid(tx_req_status_valid), - /* - * RAM interface - */ - .dma_ram_wr_cmd_be(port_dma_ram_wr_cmd_be[SEG_COUNT*SEG_BE_WIDTH*n +: SEG_COUNT*SEG_BE_WIDTH]), - .dma_ram_wr_cmd_addr(port_dma_ram_wr_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]), - .dma_ram_wr_cmd_data(port_dma_ram_wr_cmd_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]), - .dma_ram_wr_cmd_valid(port_dma_ram_wr_cmd_valid[SEG_COUNT*n +: SEG_COUNT]), - .dma_ram_wr_cmd_ready(port_dma_ram_wr_cmd_ready[SEG_COUNT*n +: SEG_COUNT]), - .dma_ram_wr_done(port_dma_ram_wr_done[SEG_COUNT*n +: SEG_COUNT]), - .dma_ram_rd_cmd_addr(port_dma_ram_rd_cmd_addr[SEG_COUNT*SEG_ADDR_WIDTH*n +: SEG_COUNT*SEG_ADDR_WIDTH]), - .dma_ram_rd_cmd_valid(port_dma_ram_rd_cmd_valid[SEG_COUNT*n +: SEG_COUNT]), - .dma_ram_rd_cmd_ready(port_dma_ram_rd_cmd_ready[SEG_COUNT*n +: SEG_COUNT]), - .dma_ram_rd_resp_data(port_dma_ram_rd_resp_data[SEG_COUNT*SEG_DATA_WIDTH*n +: SEG_COUNT*SEG_DATA_WIDTH]), - .dma_ram_rd_resp_valid(port_dma_ram_rd_resp_valid[SEG_COUNT*n +: SEG_COUNT]), - .dma_ram_rd_resp_ready(port_dma_ram_rd_resp_ready[SEG_COUNT*n +: SEG_COUNT]), + /* + * Transmit request input + */ + .s_axis_req_queue(tx_sched_req_queue), + .s_axis_req_tag(tx_sched_req_tag), + .s_axis_req_dest(tx_sched_req_dest), + .s_axis_req_valid(tx_sched_req_valid), + .s_axis_req_ready(tx_sched_req_ready), - /* - * Transmit data output - */ - .tx_axis_tdata(tx_axis_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]), - .tx_axis_tkeep(tx_axis_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]), - .tx_axis_tvalid(tx_axis_tvalid[n +: 1]), - .tx_axis_tready(tx_axis_tready[n +: 1]), - .tx_axis_tlast(tx_axis_tlast[n +: 1]), - .tx_axis_tuser(tx_axis_tuser[n +: 1]), + /* + * Transmit request status output + */ + .m_axis_req_status_len(tx_sched_req_status_len), + .m_axis_req_status_tag(tx_sched_req_status_tag), + // .m_axis_req_status_empty(tx_sched_req_status_empty), + // .m_axis_req_status_error(tx_sched_req_status_error), + .m_axis_req_status_valid(tx_sched_req_status_valid) + ); - /* - * Transmit timestamp input - */ - .s_axis_tx_ptp_ts_96(s_axis_tx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid[n +: 1]), - .s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready[n +: 1]), +end else begin - /* - * Receive data input - */ - .rx_axis_tdata(rx_axis_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]), - .rx_axis_tkeep(rx_axis_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]), - .rx_axis_tvalid(rx_axis_tvalid[n +: 1]), - .rx_axis_tready(rx_axis_tready[n +: 1]), - .rx_axis_tlast(rx_axis_tlast[n +: 1]), - .rx_axis_tuser(rx_axis_tuser[n +: 1]), + assign tx_req_queue = tx_sched_req_queue; + assign tx_req_tag = tx_sched_req_tag; + assign tx_req_dest = tx_sched_req_dest; + assign tx_req_valid = tx_sched_req_valid; + assign tx_sched_req_ready = tx_req_ready; - /* - * Receive timestamp input - */ - .s_axis_rx_ptp_ts_96(s_axis_rx_ptp_ts_96[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), - .s_axis_rx_ptp_ts_valid(s_axis_rx_ptp_ts_valid[n +: 1]), - .s_axis_rx_ptp_ts_ready(s_axis_rx_ptp_ts_ready[n +: 1]), + assign tx_sched_req_status_len = tx_req_status_len; + assign tx_sched_req_status_tag = tx_req_status_tag; + assign tx_sched_req_status_valid = tx_req_status_valid; - /* - * PTP clock - */ - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step), - - /* - * Configuration - */ - .tx_mtu(tx_mtu_reg), - .rx_mtu(rx_mtu_reg), - .rss_mask(rss_mask_reg) - ); - - end +end endgenerate +mqnic_interface_tx #( + .PORTS(PORTS), + .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .REQ_TAG_WIDTH(REQ_TAG_WIDTH), + .DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT), + .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), + .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), + .TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), + .TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), + .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH), + .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .DESC_TABLE_DMA_OP_COUNT_WIDTH(((2**LOG_BLOCK_SIZE_WIDTH)-1)+1), + .TX_MAX_DESC_REQ(TX_MAX_DESC_REQ), + .TX_DESC_FIFO_SIZE(TX_DESC_FIFO_SIZE), + .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), + .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), + .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), + .INT_WIDTH(INT_WIDTH), + .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), + .LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH), + .LOG_BLOCK_SIZE_WIDTH(LOG_BLOCK_SIZE_WIDTH), + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_TAG_WIDTH(PTP_TAG_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), + .SEG_BE_WIDTH(SEG_BE_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .AXIS_TX_ID_WIDTH(AXIS_TX_ID_WIDTH), + .AXIS_TX_DEST_WIDTH(AXIS_TX_DEST_WIDTH), + .AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .DESC_SIZE(DESC_SIZE), + .CPL_SIZE(CPL_SIZE), + .AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH), + .AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH) +) +interface_tx_inst ( + .clk(clk), + .rst(rst), + + /* + * Transmit request input (queue index) + */ + .s_axis_tx_req_queue(tx_req_queue), + .s_axis_tx_req_tag(tx_req_tag), + .s_axis_tx_req_dest(tx_req_dest), + .s_axis_tx_req_valid(tx_req_valid), + .s_axis_tx_req_ready(tx_req_ready), + + /* + * Transmit request status output + */ + .m_axis_tx_req_status_len(tx_req_status_len), + .m_axis_tx_req_status_tag(tx_req_status_tag), + .m_axis_tx_req_status_valid(tx_req_status_valid), + + /* + * Descriptor request output + */ + .m_axis_desc_req_queue(tx_desc_req_queue), + .m_axis_desc_req_tag(tx_desc_req_tag), + .m_axis_desc_req_valid(tx_desc_req_valid), + .m_axis_desc_req_ready(tx_desc_req_ready), + + /* + * Descriptor request status input + */ + .s_axis_desc_req_status_queue(tx_desc_req_status_queue), + .s_axis_desc_req_status_ptr(tx_desc_req_status_ptr), + .s_axis_desc_req_status_cpl(tx_desc_req_status_cpl), + .s_axis_desc_req_status_tag(tx_desc_req_status_tag), + .s_axis_desc_req_status_empty(tx_desc_req_status_empty), + .s_axis_desc_req_status_error(tx_desc_req_status_error), + .s_axis_desc_req_status_valid(tx_desc_req_status_valid), + + /* + * Descriptor data input + */ + .s_axis_desc_tdata(tx_desc_tdata), + .s_axis_desc_tkeep(tx_desc_tkeep), + .s_axis_desc_tvalid(tx_desc_tvalid), + .s_axis_desc_tready(tx_desc_tready), + .s_axis_desc_tlast(tx_desc_tlast), + .s_axis_desc_tid(tx_desc_tid), + .s_axis_desc_tuser(tx_desc_tuser), + + /* + * Completion request output + */ + .m_axis_cpl_req_queue(tx_cpl_req_queue), + .m_axis_cpl_req_tag(tx_cpl_req_tag), + .m_axis_cpl_req_data(tx_cpl_req_data), + .m_axis_cpl_req_valid(tx_cpl_req_valid), + .m_axis_cpl_req_ready(tx_cpl_req_ready), + + /* + * Completion request status input + */ + .s_axis_cpl_req_status_tag(tx_cpl_req_status_tag), + .s_axis_cpl_req_status_full(tx_cpl_req_status_full), + .s_axis_cpl_req_status_error(tx_cpl_req_status_error), + .s_axis_cpl_req_status_valid(tx_cpl_req_status_valid), + + /* + * DMA read descriptor output (data) + */ + .m_axis_dma_read_desc_dma_addr(m_axis_data_dma_read_desc_dma_addr), + .m_axis_dma_read_desc_ram_addr(m_axis_data_dma_read_desc_ram_addr), + .m_axis_dma_read_desc_len(m_axis_data_dma_read_desc_len), + .m_axis_dma_read_desc_tag(m_axis_data_dma_read_desc_tag), + .m_axis_dma_read_desc_valid(m_axis_data_dma_read_desc_valid), + .m_axis_dma_read_desc_ready(m_axis_data_dma_read_desc_ready), + + /* + * DMA read descriptor status input (data) + */ + .s_axis_dma_read_desc_status_tag(s_axis_data_dma_read_desc_status_tag), + .s_axis_dma_read_desc_status_error(s_axis_data_dma_read_desc_status_error), + .s_axis_dma_read_desc_status_valid(s_axis_data_dma_read_desc_status_valid), + + /* + * RAM interface (data) + */ + .dma_ram_wr_cmd_be(data_dma_ram_wr_cmd_be), + .dma_ram_wr_cmd_addr(data_dma_ram_wr_cmd_addr), + .dma_ram_wr_cmd_data(data_dma_ram_wr_cmd_data), + .dma_ram_wr_cmd_valid(data_dma_ram_wr_cmd_valid), + .dma_ram_wr_cmd_ready(data_dma_ram_wr_cmd_ready), + .dma_ram_wr_done(data_dma_ram_wr_done), + + /* + * Transmit data output + */ + .tx_axis_tdata(tx_axis_tdata), + .tx_axis_tkeep(tx_axis_tkeep), + .tx_axis_tvalid(tx_axis_tvalid), + .tx_axis_tready(tx_axis_tready), + .tx_axis_tlast(tx_axis_tlast), + .tx_axis_tid(tx_axis_tid), + .tx_axis_tdest(tx_axis_tdest), + .tx_axis_tuser(tx_axis_tuser), + + /* + * Transmit timestamp input + */ + .s_axis_tx_ptp_ts(s_axis_tx_ptp_ts), + .s_axis_tx_ptp_ts_tag(s_axis_tx_ptp_ts_tag), + .s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid), + .s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready), + + /* + * PTP clock + */ + .ptp_ts_96(ptp_ts_96), + .ptp_ts_step(ptp_ts_step), + + /* + * Configuration + */ + .mtu(tx_mtu_reg) +); + +assign m_axis_data_dma_read_desc_ram_sel = 0; + +// RX + +mqnic_interface_rx #( + .PORTS(PORTS), + .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT), + .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), + .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), + .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), + .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH), + .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .DESC_TABLE_DMA_OP_COUNT_WIDTH(((2**LOG_BLOCK_SIZE_WIDTH)-1)+1), + .RX_MAX_DESC_REQ(RX_MAX_DESC_REQ), + .RX_DESC_FIFO_SIZE(RX_DESC_FIFO_SIZE), + .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), + .LOG_QUEUE_SIZE_WIDTH(LOG_QUEUE_SIZE_WIDTH), + .LOG_BLOCK_SIZE_WIDTH(LOG_BLOCK_SIZE_WIDTH), + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_TAG_WIDTH(PTP_TAG_WIDTH), + .RX_RSS_ENABLE(RX_RSS_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), + .SEG_BE_WIDTH(SEG_BE_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .RAM_PIPELINE(RAM_PIPELINE), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .AXIS_RX_ID_WIDTH(AXIS_RX_ID_WIDTH), + .AXIS_RX_DEST_WIDTH(AXIS_RX_DEST_WIDTH), + .AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH), + .MAX_RX_SIZE(MAX_RX_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE), + .DESC_SIZE(DESC_SIZE), + .CPL_SIZE(CPL_SIZE), + .AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH), + .AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH) +) +interface_rx_inst ( + .clk(clk), + .rst(rst), + + /* + * Descriptor request output + */ + .m_axis_desc_req_queue(rx_desc_req_queue), + .m_axis_desc_req_tag(rx_desc_req_tag), + .m_axis_desc_req_valid(rx_desc_req_valid), + .m_axis_desc_req_ready(rx_desc_req_ready), + + /* + * Descriptor request status input + */ + .s_axis_desc_req_status_queue(rx_desc_req_status_queue), + .s_axis_desc_req_status_ptr(rx_desc_req_status_ptr), + .s_axis_desc_req_status_cpl(rx_desc_req_status_cpl), + .s_axis_desc_req_status_tag(rx_desc_req_status_tag), + .s_axis_desc_req_status_empty(rx_desc_req_status_empty), + .s_axis_desc_req_status_error(rx_desc_req_status_error), + .s_axis_desc_req_status_valid(rx_desc_req_status_valid), + + /* + * Descriptor data input + */ + .s_axis_desc_tdata(rx_desc_tdata), + .s_axis_desc_tkeep(rx_desc_tkeep), + .s_axis_desc_tvalid(rx_desc_tvalid), + .s_axis_desc_tready(rx_desc_tready), + .s_axis_desc_tlast(rx_desc_tlast), + .s_axis_desc_tid(rx_desc_tid), + .s_axis_desc_tuser(rx_desc_tuser), + + /* + * Completion request output + */ + .m_axis_cpl_req_queue(rx_cpl_req_queue), + .m_axis_cpl_req_tag(rx_cpl_req_tag), + .m_axis_cpl_req_data(rx_cpl_req_data), + .m_axis_cpl_req_valid(rx_cpl_req_valid), + .m_axis_cpl_req_ready(rx_cpl_req_ready), + + /* + * Completion request status input + */ + .s_axis_cpl_req_status_tag(rx_cpl_req_status_tag), + .s_axis_cpl_req_status_full(rx_cpl_req_status_full), + .s_axis_cpl_req_status_error(rx_cpl_req_status_error), + .s_axis_cpl_req_status_valid(rx_cpl_req_status_valid), + + /* + * DMA write descriptor output (data) + */ + .m_axis_dma_write_desc_dma_addr(m_axis_data_dma_write_desc_dma_addr), + .m_axis_dma_write_desc_ram_addr(m_axis_data_dma_write_desc_ram_addr), + .m_axis_dma_write_desc_len(m_axis_data_dma_write_desc_len), + .m_axis_dma_write_desc_tag(m_axis_data_dma_write_desc_tag), + .m_axis_dma_write_desc_valid(m_axis_data_dma_write_desc_valid), + .m_axis_dma_write_desc_ready(m_axis_data_dma_write_desc_ready), + + /* + * DMA write descriptor status input (data) + */ + .s_axis_dma_write_desc_status_tag(s_axis_data_dma_write_desc_status_tag), + .s_axis_dma_write_desc_status_error(s_axis_data_dma_write_desc_status_error), + .s_axis_dma_write_desc_status_valid(s_axis_data_dma_write_desc_status_valid), + + /* + * RAM interface (data) + */ + .dma_ram_rd_cmd_addr(data_dma_ram_rd_cmd_addr), + .dma_ram_rd_cmd_valid(data_dma_ram_rd_cmd_valid), + .dma_ram_rd_cmd_ready(data_dma_ram_rd_cmd_ready), + .dma_ram_rd_resp_data(data_dma_ram_rd_resp_data), + .dma_ram_rd_resp_valid(data_dma_ram_rd_resp_valid), + .dma_ram_rd_resp_ready(data_dma_ram_rd_resp_ready), + + /* + * Receive data input + */ + .rx_axis_tdata(rx_axis_tdata), + .rx_axis_tkeep(rx_axis_tkeep), + .rx_axis_tvalid(rx_axis_tvalid), + .rx_axis_tready(rx_axis_tready), + .rx_axis_tlast(rx_axis_tlast), + .rx_axis_tid(rx_axis_tid), + .rx_axis_tdest(rx_axis_tdest), + .rx_axis_tuser(rx_axis_tuser), + + /* + * PTP clock + */ + .ptp_ts_96(ptp_ts_96), + .ptp_ts_step(ptp_ts_step), + + /* + * Configuration + */ + .mtu(rx_mtu_reg), + .rss_mask(rss_mask_reg) +); + +assign m_axis_data_dma_write_desc_ram_sel = 0; + endmodule `resetall diff --git a/fpga/common/rtl/mqnic_interface_rx.v b/fpga/common/rtl/mqnic_interface_rx.v new file mode 100644 index 000000000..6fea17cff --- /dev/null +++ b/fpga/common/rtl/mqnic_interface_rx.v @@ -0,0 +1,666 @@ +/* + +Copyright 2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * NIC Interface RX path + */ +module mqnic_interface_rx # +( + // Number of ports + parameter PORTS = 1, + // DMA address width + parameter DMA_ADDR_WIDTH = 64, + // DMA length field width + parameter DMA_LEN_WIDTH = 16, + // DMA tag field width + parameter DMA_TAG_WIDTH = 8, + // Descriptor request tag field width + parameter DESC_REQ_TAG_WIDTH = 8, + // Queue request tag field width + parameter QUEUE_REQ_TAG_WIDTH = 8, + // Queue operation tag field width + parameter QUEUE_OP_TAG_WIDTH = 8, + // Receive queue index width + parameter RX_QUEUE_INDEX_WIDTH = 8, + // Max queue index width + parameter QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH, + // Receive completion queue index width + parameter RX_CPL_QUEUE_INDEX_WIDTH = 8, + // Max completion queue index width + parameter CPL_QUEUE_INDEX_WIDTH = RX_CPL_QUEUE_INDEX_WIDTH, + // Receive descriptor table size (number of in-flight operations) + parameter RX_DESC_TABLE_SIZE = 16, + // Width of descriptor table field for tracking outstanding DMA operations + parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4, + // Max number of in-flight descriptor requests (transmit) + parameter RX_MAX_DESC_REQ = 16, + // Receive descriptor FIFO size + parameter RX_DESC_FIFO_SIZE = RX_MAX_DESC_REQ*8, + // Queue element pointer width + parameter QUEUE_PTR_WIDTH = 16, + // Queue log size field width + parameter LOG_QUEUE_SIZE_WIDTH = 4, + // Log desc block size field width + parameter LOG_BLOCK_SIZE_WIDTH = 2, + // Enable PTP timestamping + parameter PTP_TS_ENABLE = 1, + // PTP timestamp width + parameter PTP_TS_WIDTH = 96, + // PTP tag width + parameter PTP_TAG_WIDTH = 16, + // Enable RX RSS + parameter RX_RSS_ENABLE = 1, + // Enable RX hashing + parameter RX_HASH_ENABLE = 1, + // Enable RX checksum offload + parameter RX_CHECKSUM_ENABLE = 1, + // DMA RAM segment count + parameter SEG_COUNT = 2, + // DMA RAM segment data width + parameter SEG_DATA_WIDTH = 64, + // DMA RAM segment address width + parameter SEG_ADDR_WIDTH = 8, + // DMA RAM segment byte enable width + parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8, + // DMA RAM address width + parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH), + // DMA RAM pipeline stages + parameter RAM_PIPELINE = 2, + // Width of AXI stream interfaces in bits + parameter AXIS_DATA_WIDTH = 256, + // AXI stream tkeep signal width (words per cycle) + parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, + // AXI stream tid signal width + parameter AXIS_RX_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1, + // AXI stream tdest signal width + parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH, + // AXI stream tuser signal width + parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, + // Max receive packet size + parameter MAX_RX_SIZE = 2048, + // DMA RX RAM size + parameter RX_RAM_SIZE = 8*MAX_RX_SIZE, + // Descriptor size (in bytes) + parameter DESC_SIZE = 16, + // Descriptor size (in bytes) + parameter CPL_SIZE = 32, + // Width of AXI stream descriptor interfaces in bits + parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8, + // AXI stream descriptor tkeep signal width (words per cycle) + parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8 +) +( + input wire clk, + input wire rst, + + /* + * Descriptor request output + */ + output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue, + output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag, + output wire m_axis_desc_req_valid, + input wire m_axis_desc_req_ready, + + /* + * Descriptor request status input + */ + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue, + input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr, + input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl, + input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag, + input wire s_axis_desc_req_status_empty, + input wire s_axis_desc_req_status_error, + input wire s_axis_desc_req_status_valid, + + /* + * Descriptor data input + */ + input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata, + input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep, + input wire s_axis_desc_tvalid, + output wire s_axis_desc_tready, + input wire s_axis_desc_tlast, + input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_tid, + input wire s_axis_desc_tuser, + + /* + * Completion request output + */ + output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue, + output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, + output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data, + output wire m_axis_cpl_req_valid, + input wire m_axis_cpl_req_ready, + + /* + * Completion request status input + */ + input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag, + input wire s_axis_cpl_req_status_full, + input wire s_axis_cpl_req_status_error, + input wire s_axis_cpl_req_status_valid, + + /* + * DMA write descriptor output (data) + */ + output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr, + output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr, + output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len, + output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag, + output wire m_axis_dma_write_desc_valid, + input wire m_axis_dma_write_desc_ready, + + /* + * DMA write descriptor status input (data) + */ + input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag, + input wire [3:0] s_axis_dma_write_desc_status_error, + input wire s_axis_dma_write_desc_status_valid, + + /* + * RAM interface (data) + */ + input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr, + input wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid, + output wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready, + output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data, + output wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid, + input wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready, + + /* + * Receive data input + */ + input wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata, + input wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep, + input wire rx_axis_tvalid, + output wire rx_axis_tready, + input wire rx_axis_tlast, + input wire [AXIS_RX_ID_WIDTH-1:0] rx_axis_tid, + input wire [AXIS_RX_DEST_WIDTH-1:0] rx_axis_tdest, + input wire [AXIS_RX_USER_WIDTH-1:0] rx_axis_tuser, + + /* + * PTP clock + */ + input wire [95:0] ptp_ts_96, + input wire ptp_ts_step, + + /* + * Configuration + */ + input wire [DMA_CLIENT_LEN_WIDTH-1:0] mtu, + input wire [31:0] rss_mask +); + +parameter DMA_CLIENT_TAG_WIDTH = $clog2(RX_DESC_TABLE_SIZE); +parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH; + +parameter REQ_TAG_WIDTH = $clog2(RX_DESC_TABLE_SIZE); + +wire [AXIS_DESC_DATA_WIDTH-1:0] rx_fifo_desc_tdata; +wire [AXIS_DESC_KEEP_WIDTH-1:0] rx_fifo_desc_tkeep; +wire rx_fifo_desc_tvalid; +wire rx_fifo_desc_tready; +wire rx_fifo_desc_tlast; +wire [DESC_REQ_TAG_WIDTH-1:0] rx_fifo_desc_tid; +wire rx_fifo_desc_tuser; + +axis_fifo #( + .DEPTH(RX_DESC_FIFO_SIZE*DESC_SIZE), + .DATA_WIDTH(AXIS_DESC_DATA_WIDTH), + .KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH), + .LAST_ENABLE(1), + .ID_ENABLE(1), + .ID_WIDTH(DESC_REQ_TAG_WIDTH), + .DEST_ENABLE(0), + .USER_ENABLE(0), + .PIPELINE_OUTPUT(3), + .FRAME_FIFO(0) +) +rx_desc_fifo ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata(s_axis_desc_tdata), + .s_axis_tkeep(s_axis_desc_tkeep), + .s_axis_tvalid(s_axis_desc_tvalid), + .s_axis_tready(s_axis_desc_tready), + .s_axis_tlast(s_axis_desc_tlast), + .s_axis_tid(s_axis_desc_tid), + .s_axis_tdest(0), + .s_axis_tuser(s_axis_desc_tuser), + + // AXI output + .m_axis_tdata(rx_fifo_desc_tdata), + .m_axis_tkeep(rx_fifo_desc_tkeep), + .m_axis_tvalid(rx_fifo_desc_tvalid), + .m_axis_tready(rx_fifo_desc_tready), + .m_axis_tlast(rx_fifo_desc_tlast), + .m_axis_tid(rx_fifo_desc_tid), + .m_axis_tdest(), + .m_axis_tuser(rx_fifo_desc_tuser), + + // Status + .status_overflow(), + .status_bad_frame(), + .status_good_frame() +); + +wire [RX_QUEUE_INDEX_WIDTH-1:0] rx_req_queue; +wire [REQ_TAG_WIDTH-1:0] rx_req_tag; +wire rx_req_valid; +wire rx_req_ready; + +wire [31:0] rx_hash; +wire [3:0] rx_hash_type; +wire rx_hash_valid; +wire rx_hash_ready; + +wire [15:0] rx_csum; +wire rx_csum_valid; +wire rx_csum_ready; + +wire [RAM_ADDR_WIDTH-1:0] dma_rx_desc_addr; +wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_len; +wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_tag; +wire dma_rx_desc_valid; +wire dma_rx_desc_ready; + +wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_status_len; +wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_status_tag; +wire [AXIS_RX_ID_WIDTH-1:0] dma_rx_desc_status_id; +wire [AXIS_RX_DEST_WIDTH-1:0] dma_rx_desc_status_dest; +wire [AXIS_RX_USER_WIDTH-1:0] dma_rx_desc_status_user; +wire [3:0] dma_rx_desc_status_error; +wire dma_rx_desc_status_valid; + +rx_engine #( + .PORTS(PORTS), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), + .REQ_TAG_WIDTH(REQ_TAG_WIDTH), + .DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH), + .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), + .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), + .QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), + .CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), + .DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), + .DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH), + .MAX_RX_SIZE(MAX_RX_SIZE), + .RX_BUFFER_OFFSET(0), + .RX_BUFFER_SIZE(RX_RAM_SIZE), + .RX_BUFFER_STEP_SIZE(SEG_COUNT*SEG_BE_WIDTH), + .DESC_SIZE(DESC_SIZE), + .CPL_SIZE(CPL_SIZE), + .MAX_DESC_REQ(RX_MAX_DESC_REQ), + .AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH), + .AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH), + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .AXIS_RX_ID_WIDTH(AXIS_RX_ID_WIDTH), + .AXIS_RX_DEST_WIDTH(AXIS_RX_DEST_WIDTH), + .AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH) +) +rx_engine_inst ( + .clk(clk), + .rst(rst), + + /* + * Receive request input (queue index) + */ + .s_axis_rx_req_queue(rx_req_queue), + .s_axis_rx_req_tag(rx_req_tag), + .s_axis_rx_req_valid(rx_req_valid), + .s_axis_rx_req_ready(rx_req_ready), + + /* + * Receive request status output + */ + .m_axis_rx_req_status_tag(), + .m_axis_rx_req_status_len(), + .m_axis_rx_req_status_valid(), + + /* + * Descriptor request output + */ + .m_axis_desc_req_queue(m_axis_desc_req_queue), + .m_axis_desc_req_tag(m_axis_desc_req_tag), + .m_axis_desc_req_valid(m_axis_desc_req_valid), + .m_axis_desc_req_ready(m_axis_desc_req_ready), + + /* + * Descriptor request status input + */ + .s_axis_desc_req_status_queue(s_axis_desc_req_status_queue), + .s_axis_desc_req_status_ptr(s_axis_desc_req_status_ptr), + .s_axis_desc_req_status_cpl(s_axis_desc_req_status_cpl), + .s_axis_desc_req_status_tag(s_axis_desc_req_status_tag), + .s_axis_desc_req_status_empty(s_axis_desc_req_status_empty), + .s_axis_desc_req_status_error(s_axis_desc_req_status_error), + .s_axis_desc_req_status_valid(s_axis_desc_req_status_valid), + + /* + * Descriptor data input + */ + .s_axis_desc_tdata(rx_fifo_desc_tdata), + .s_axis_desc_tkeep(rx_fifo_desc_tkeep), + .s_axis_desc_tvalid(rx_fifo_desc_tvalid), + .s_axis_desc_tready(rx_fifo_desc_tready), + .s_axis_desc_tlast(rx_fifo_desc_tlast), + .s_axis_desc_tid(rx_fifo_desc_tid), + .s_axis_desc_tuser(rx_fifo_desc_tuser), + + /* + * Completion request output + */ + .m_axis_cpl_req_queue(m_axis_cpl_req_queue), + .m_axis_cpl_req_tag(m_axis_cpl_req_tag), + .m_axis_cpl_req_data(m_axis_cpl_req_data), + .m_axis_cpl_req_valid(m_axis_cpl_req_valid), + .m_axis_cpl_req_ready(m_axis_cpl_req_ready), + + /* + * Completion request status input + */ + .s_axis_cpl_req_status_tag(s_axis_cpl_req_status_tag), + .s_axis_cpl_req_status_full(s_axis_cpl_req_status_full), + .s_axis_cpl_req_status_error(s_axis_cpl_req_status_error), + .s_axis_cpl_req_status_valid(s_axis_cpl_req_status_valid), + + /* + * DMA write descriptor output + */ + .m_axis_dma_write_desc_dma_addr(m_axis_dma_write_desc_dma_addr), + .m_axis_dma_write_desc_ram_addr(m_axis_dma_write_desc_ram_addr), + .m_axis_dma_write_desc_len(m_axis_dma_write_desc_len), + .m_axis_dma_write_desc_tag(m_axis_dma_write_desc_tag), + .m_axis_dma_write_desc_valid(m_axis_dma_write_desc_valid), + .m_axis_dma_write_desc_ready(m_axis_dma_write_desc_ready), + + /* + * DMA write descriptor status input + */ + .s_axis_dma_write_desc_status_tag(s_axis_dma_write_desc_status_tag), + .s_axis_dma_write_desc_status_error(s_axis_dma_write_desc_status_error), + .s_axis_dma_write_desc_status_valid(s_axis_dma_write_desc_status_valid), + + /* + * Receive descriptor output + */ + .m_axis_rx_desc_addr(dma_rx_desc_addr), + .m_axis_rx_desc_len(dma_rx_desc_len), + .m_axis_rx_desc_tag(dma_rx_desc_tag), + .m_axis_rx_desc_valid(dma_rx_desc_valid), + .m_axis_rx_desc_ready(dma_rx_desc_ready), + + /* + * Receive descriptor status input + */ + .s_axis_rx_desc_status_len(dma_rx_desc_status_len), + .s_axis_rx_desc_status_tag(dma_rx_desc_status_tag), + .s_axis_rx_desc_status_id(dma_rx_desc_status_id), + .s_axis_rx_desc_status_dest(dma_rx_desc_status_dest), + .s_axis_rx_desc_status_user(dma_rx_desc_status_user), + .s_axis_rx_desc_status_error(dma_rx_desc_status_error), + .s_axis_rx_desc_status_valid(dma_rx_desc_status_valid), + + /* + * Receive hash input + */ + .s_axis_rx_hash(rx_hash), + .s_axis_rx_hash_type(rx_hash_type), + .s_axis_rx_hash_valid(rx_hash_valid), + .s_axis_rx_hash_ready(rx_hash_ready), + + /* + * Receive checksum input + */ + .s_axis_rx_csum(rx_csum), + .s_axis_rx_csum_valid(rx_csum_valid), + .s_axis_rx_csum_ready(rx_csum_ready), + + /* + * Configuration + */ + .mtu(mtu), + .enable(1'b1) +); + +wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be_int; +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr_int; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data_int; +wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid_int; +wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready_int; +wire [SEG_COUNT-1:0] dma_ram_wr_done_int; + +dma_psdpram #( + .SIZE(RX_RAM_SIZE), + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), + .SEG_BE_WIDTH(SEG_BE_WIDTH), + .PIPELINE(RAM_PIPELINE) +) +dma_psdpram_rx_inst ( + .clk(clk), + .rst(rst), + + /* + * Write port + */ + .wr_cmd_be(dma_ram_wr_cmd_be_int), + .wr_cmd_addr(dma_ram_wr_cmd_addr_int), + .wr_cmd_data(dma_ram_wr_cmd_data_int), + .wr_cmd_valid(dma_ram_wr_cmd_valid_int), + .wr_cmd_ready(dma_ram_wr_cmd_ready_int), + .wr_done(dma_ram_wr_done_int), + + /* + * Read port + */ + .rd_cmd_addr(dma_ram_rd_cmd_addr), + .rd_cmd_valid(dma_ram_rd_cmd_valid), + .rd_cmd_ready(dma_ram_rd_cmd_ready), + .rd_resp_data(dma_ram_rd_resp_data), + .rd_resp_valid(dma_ram_rd_resp_valid), + .rd_resp_ready(dma_ram_rd_resp_ready) +); + +wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata_int; +wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep_int; +wire rx_axis_tvalid_int; +wire rx_axis_tready_int; +wire rx_axis_tlast_int; +wire [AXIS_RX_ID_WIDTH-1:0] rx_axis_tid_int; +wire [AXIS_RX_DEST_WIDTH-1:0] rx_axis_tdest_int; +wire [AXIS_RX_USER_WIDTH-1:0] rx_axis_tuser_int; + +mqnic_ingress #( + .REQ_TAG_WIDTH(REQ_TAG_WIDTH), + .RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), + .RX_RSS_ENABLE(RX_RSS_ENABLE), + .RX_HASH_ENABLE(RX_HASH_ENABLE), + .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .AXIS_ID_WIDTH(AXIS_RX_ID_WIDTH), + .AXIS_DEST_WIDTH(AXIS_RX_DEST_WIDTH), + .AXIS_USER_WIDTH(AXIS_RX_USER_WIDTH), + .MAX_RX_SIZE(MAX_RX_SIZE) +) +ingress_inst ( + .clk(clk), + .rst(rst), + + /* + * Receive data input + */ + .s_axis_tdata(rx_axis_tdata), + .s_axis_tkeep(rx_axis_tkeep), + .s_axis_tvalid(rx_axis_tvalid), + .s_axis_tready(rx_axis_tready), + .s_axis_tlast(rx_axis_tlast), + .s_axis_tid(rx_axis_tid), + .s_axis_tdest(rx_axis_tdest), + .s_axis_tuser(rx_axis_tuser), + + /* + * Receive data output + */ + .m_axis_tdata(rx_axis_tdata_int), + .m_axis_tkeep(rx_axis_tkeep_int), + .m_axis_tvalid(rx_axis_tvalid_int), + .m_axis_tready(rx_axis_tready_int), + .m_axis_tlast(rx_axis_tlast_int), + .m_axis_tid(rx_axis_tid_int), + .m_axis_tdest(rx_axis_tdest_int), + .m_axis_tuser(rx_axis_tuser_int), + + /* + * RX command output + */ + .rx_req_queue(rx_req_queue), + .rx_req_tag(rx_req_tag), + .rx_req_valid(rx_req_valid), + .rx_req_ready(rx_req_ready), + + /* + * RX hash output + */ + .rx_hash(rx_hash), + .rx_hash_type(rx_hash_type), + .rx_hash_valid(rx_hash_valid), + .rx_hash_ready(rx_hash_ready), + + /* + * RX checksum output + */ + .rx_csum(rx_csum), + .rx_csum_valid(rx_csum_valid), + .rx_csum_ready(rx_csum_ready), + + /* + * Configuration + */ + .rss_mask(rss_mask) +); + +dma_client_axis_sink #( + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), + .SEG_BE_WIDTH(SEG_BE_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .AXIS_LAST_ENABLE(1), + .AXIS_ID_ENABLE(1), + .AXIS_ID_WIDTH(AXIS_RX_ID_WIDTH), + .AXIS_DEST_ENABLE(1), + .AXIS_DEST_WIDTH(AXIS_RX_DEST_WIDTH), + .AXIS_USER_ENABLE(1), + .AXIS_USER_WIDTH(AXIS_RX_USER_WIDTH), + .LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), + .TAG_WIDTH(DMA_CLIENT_TAG_WIDTH) +) +dma_client_axis_sink_inst ( + .clk(clk), + .rst(rst), + + /* + * DMA write descriptor input + */ + .s_axis_write_desc_ram_addr(dma_rx_desc_addr), + .s_axis_write_desc_len(dma_rx_desc_len), + .s_axis_write_desc_tag(dma_rx_desc_tag), + .s_axis_write_desc_valid(dma_rx_desc_valid), + .s_axis_write_desc_ready(dma_rx_desc_ready), + + /* + * DMA write descriptor status output + */ + .m_axis_write_desc_status_len(dma_rx_desc_status_len), + .m_axis_write_desc_status_tag(dma_rx_desc_status_tag), + .m_axis_write_desc_status_id(dma_rx_desc_status_id), + .m_axis_write_desc_status_dest(dma_rx_desc_status_dest), + .m_axis_write_desc_status_user(dma_rx_desc_status_user), + .m_axis_write_desc_status_error(dma_rx_desc_status_error), + .m_axis_write_desc_status_valid(dma_rx_desc_status_valid), + + /* + * AXI stream write data input + */ + .s_axis_write_data_tdata(rx_axis_tdata_int), + .s_axis_write_data_tkeep(rx_axis_tkeep_int), + .s_axis_write_data_tvalid(rx_axis_tvalid_int), + .s_axis_write_data_tready(rx_axis_tready_int), + .s_axis_write_data_tlast(rx_axis_tlast_int), + .s_axis_write_data_tid(rx_axis_tid_int), + .s_axis_write_data_tdest(rx_axis_tdest_int), + .s_axis_write_data_tuser(rx_axis_tuser_int), + + /* + * RAM interface + */ + .ram_wr_cmd_be(dma_ram_wr_cmd_be_int), + .ram_wr_cmd_addr(dma_ram_wr_cmd_addr_int), + .ram_wr_cmd_data(dma_ram_wr_cmd_data_int), + .ram_wr_cmd_valid(dma_ram_wr_cmd_valid_int), + .ram_wr_cmd_ready(dma_ram_wr_cmd_ready_int), + .ram_wr_done(dma_ram_wr_done_int), + + /* + * Configuration + */ + .enable(1'b1), + .abort(1'b0) +); + +endmodule + +`resetall diff --git a/fpga/common/rtl/mqnic_interface_tx.v b/fpga/common/rtl/mqnic_interface_tx.v new file mode 100644 index 000000000..f0d4224f0 --- /dev/null +++ b/fpga/common/rtl/mqnic_interface_tx.v @@ -0,0 +1,659 @@ +/* + +Copyright 2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * NIC Interface TX path + */ +module mqnic_interface_tx # +( + // Number of ports + parameter PORTS = 1, + // DMA address width + parameter DMA_ADDR_WIDTH = 64, + // DMA length field width + parameter DMA_LEN_WIDTH = 16, + // DMA tag field width + parameter DMA_TAG_WIDTH = 8, + // Transmit request tag field width + parameter REQ_TAG_WIDTH = 8, + // Descriptor request tag field width + parameter DESC_REQ_TAG_WIDTH = 8, + // Queue request tag field width + parameter QUEUE_REQ_TAG_WIDTH = 8, + // Queue operation tag field width + parameter QUEUE_OP_TAG_WIDTH = 8, + // Transmit queue index width + parameter TX_QUEUE_INDEX_WIDTH = 8, + // Max queue index width + parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH, + // Transmit completion queue index width + parameter TX_CPL_QUEUE_INDEX_WIDTH = 8, + // Max completion queue index width + parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH, + // Transmit descriptor table size (number of in-flight operations) + parameter TX_DESC_TABLE_SIZE = 16, + // Width of descriptor table field for tracking outstanding DMA operations + parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4, + // Max number of in-flight descriptor requests (transmit) + parameter TX_MAX_DESC_REQ = 16, + // Transmit descriptor FIFO size + parameter TX_DESC_FIFO_SIZE = TX_MAX_DESC_REQ*8, + // Scheduler operation table size + parameter TX_SCHEDULER_OP_TABLE_SIZE = 32, + // Scheduler pipeline setting + parameter TX_SCHEDULER_PIPELINE = 3, + // Scheduler TDMA index width + parameter TDMA_INDEX_WIDTH = 8, + // Interrupt number width + parameter INT_WIDTH = 8, + // Queue element pointer width + parameter QUEUE_PTR_WIDTH = 16, + // Queue log size field width + parameter LOG_QUEUE_SIZE_WIDTH = 4, + // Log desc block size field width + parameter LOG_BLOCK_SIZE_WIDTH = 2, + // Enable PTP timestamping + parameter PTP_TS_ENABLE = 1, + // PTP timestamp width + parameter PTP_TS_WIDTH = 96, + // PTP tag width + parameter PTP_TAG_WIDTH = 16, + // Enable TX checksum offload + parameter TX_CHECKSUM_ENABLE = 1, + // DMA RAM segment count + parameter SEG_COUNT = 2, + // DMA RAM segment data width + parameter SEG_DATA_WIDTH = 64, + // DMA RAM segment address width + parameter SEG_ADDR_WIDTH = 8, + // DMA RAM segment byte enable width + parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8, + // DMA RAM address width + parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH), + // DMA RAM pipeline stages + parameter RAM_PIPELINE = 2, + // Width of AXI stream interfaces in bits + parameter AXIS_DATA_WIDTH = 256, + // AXI stream tkeep signal width (words per cycle) + parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, + // AXI stream tid signal width + parameter AXIS_TX_ID_WIDTH = TX_QUEUE_INDEX_WIDTH, + // AXI stream tdest signal width + parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4, + // AXI stream tuser signal width + parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1, + // Max transmit packet size + parameter MAX_TX_SIZE = 2048, + // DMA TX RAM size + parameter TX_RAM_SIZE = 8*MAX_TX_SIZE, + // Descriptor size (in bytes) + parameter DESC_SIZE = 16, + // Descriptor size (in bytes) + parameter CPL_SIZE = 32, + // Width of AXI stream descriptor interfaces in bits + parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8, + // AXI stream descriptor tkeep signal width (words per cycle) + parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8 +) +( + input wire clk, + input wire rst, + + /* + * Transmit request input (queue index) + */ + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_req_queue, + input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_req_tag, + input wire [AXIS_TX_DEST_WIDTH-1:0] s_axis_tx_req_dest, + input wire s_axis_tx_req_valid, + output wire s_axis_tx_req_ready, + + /* + * Transmit request status output + */ + output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_req_status_len, + output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_status_tag, + output wire m_axis_tx_req_status_valid, + + /* + * Descriptor request output + */ + output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue, + output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag, + output wire m_axis_desc_req_valid, + input wire m_axis_desc_req_ready, + + /* + * Descriptor request status input + */ + input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue, + input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr, + input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl, + input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag, + input wire s_axis_desc_req_status_empty, + input wire s_axis_desc_req_status_error, + input wire s_axis_desc_req_status_valid, + + /* + * Descriptor data input + */ + input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata, + input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep, + input wire s_axis_desc_tvalid, + output wire s_axis_desc_tready, + input wire s_axis_desc_tlast, + input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_tid, + input wire s_axis_desc_tuser, + + /* + * Completion request output + */ + output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue, + output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, + output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data, + output wire m_axis_cpl_req_valid, + input wire m_axis_cpl_req_ready, + + /* + * Completion request status input + */ + input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag, + input wire s_axis_cpl_req_status_full, + input wire s_axis_cpl_req_status_error, + input wire s_axis_cpl_req_status_valid, + + /* + * DMA read descriptor output (data) + */ + output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_read_desc_dma_addr, + output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_read_desc_ram_addr, + output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_read_desc_len, + output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_read_desc_tag, + output wire m_axis_dma_read_desc_valid, + input wire m_axis_dma_read_desc_ready, + + /* + * DMA read descriptor status input (data) + */ + input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag, + input wire [3:0] s_axis_dma_read_desc_status_error, + input wire s_axis_dma_read_desc_status_valid, + + /* + * RAM interface (data) + */ + input wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be, + input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr, + input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data, + input wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid, + output wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready, + output wire [SEG_COUNT-1:0] dma_ram_wr_done, + + /* + * Transmit data output + */ + output wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata, + output wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep, + output wire tx_axis_tvalid, + input wire tx_axis_tready, + output wire tx_axis_tlast, + output wire [AXIS_TX_ID_WIDTH-1:0] tx_axis_tid, + output wire [AXIS_TX_DEST_WIDTH-1:0] tx_axis_tdest, + output wire [AXIS_TX_USER_WIDTH-1:0] tx_axis_tuser, + + /* + * Transmit timestamp input + */ + input wire [PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts, + input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag, + input wire s_axis_tx_ptp_ts_valid, + output wire s_axis_tx_ptp_ts_ready, + + /* + * PTP clock + */ + input wire [95:0] ptp_ts_96, + input wire ptp_ts_step, + + /* + * Configuration + */ + input wire [DMA_CLIENT_LEN_WIDTH-1:0] mtu +); + +parameter DMA_CLIENT_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE); +parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH; + +wire [AXIS_DESC_DATA_WIDTH-1:0] tx_fifo_desc_tdata; +wire [AXIS_DESC_KEEP_WIDTH-1:0] tx_fifo_desc_tkeep; +wire tx_fifo_desc_tvalid; +wire tx_fifo_desc_tready; +wire tx_fifo_desc_tlast; +wire [DESC_REQ_TAG_WIDTH-1:0] tx_fifo_desc_tid; +wire tx_fifo_desc_tuser; + +axis_fifo #( + .DEPTH(TX_DESC_FIFO_SIZE*DESC_SIZE), + .DATA_WIDTH(AXIS_DESC_DATA_WIDTH), + .KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH), + .LAST_ENABLE(1), + .ID_ENABLE(1), + .ID_WIDTH(DESC_REQ_TAG_WIDTH), + .DEST_ENABLE(0), + .USER_ENABLE(0), + .PIPELINE_OUTPUT(3), + .FRAME_FIFO(0) +) +tx_desc_fifo ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata(s_axis_desc_tdata), + .s_axis_tkeep(s_axis_desc_tkeep), + .s_axis_tvalid(s_axis_desc_tvalid), + .s_axis_tready(s_axis_desc_tready), + .s_axis_tlast(s_axis_desc_tlast), + .s_axis_tid(s_axis_desc_tid), + .s_axis_tdest(0), + .s_axis_tuser(s_axis_desc_tuser), + + // AXI output + .m_axis_tdata(tx_fifo_desc_tdata), + .m_axis_tkeep(tx_fifo_desc_tkeep), + .m_axis_tvalid(tx_fifo_desc_tvalid), + .m_axis_tready(tx_fifo_desc_tready), + .m_axis_tlast(tx_fifo_desc_tlast), + .m_axis_tid(tx_fifo_desc_tid), + .m_axis_tdest(), + .m_axis_tuser(tx_fifo_desc_tuser), + + // Status + .status_overflow(), + .status_bad_frame(), + .status_good_frame() +); + +wire tx_csum_cmd_csum_enable; +wire [7:0] tx_csum_cmd_csum_start; +wire [7:0] tx_csum_cmd_csum_offset; +wire tx_csum_cmd_valid; +wire tx_csum_cmd_ready; + +wire [RAM_ADDR_WIDTH-1:0] dma_tx_desc_addr; +wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_tx_desc_len; +wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_tx_desc_tag; +wire [AXIS_TX_ID_WIDTH-1:0] dma_tx_desc_id; +wire [AXIS_TX_DEST_WIDTH-1:0] dma_tx_desc_dest; +wire [AXIS_TX_USER_WIDTH-1:0] dma_tx_desc_user; +wire dma_tx_desc_valid; +wire dma_tx_desc_ready; + +wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_tx_desc_status_tag; +wire [3:0] dma_tx_desc_status_error; +wire dma_tx_desc_status_valid; + +tx_engine #( + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), + .DMA_LEN_WIDTH(DMA_LEN_WIDTH), + .DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), + .REQ_TAG_WIDTH(REQ_TAG_WIDTH), + .DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH), + .DMA_TAG_WIDTH(DMA_TAG_WIDTH), + .DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH), + .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), + .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), + .QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), + .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), + .CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), + .DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), + .DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH), + .MAX_TX_SIZE(MAX_TX_SIZE), + .TX_BUFFER_OFFSET(0), + .TX_BUFFER_SIZE(TX_RAM_SIZE), + .TX_BUFFER_STEP_SIZE(SEG_COUNT*SEG_BE_WIDTH), + .DESC_SIZE(DESC_SIZE), + .CPL_SIZE(CPL_SIZE), + .MAX_DESC_REQ(TX_MAX_DESC_REQ), + .AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH), + .AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH), + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .PTP_TAG_WIDTH(PTP_TAG_WIDTH), + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .AXIS_TX_ID_WIDTH(AXIS_TX_ID_WIDTH), + .AXIS_TX_DEST_WIDTH(AXIS_TX_DEST_WIDTH), + .AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH) +) +tx_engine_inst ( + .clk(clk), + .rst(rst), + + /* + * Transmit request input (queue index) + */ + .s_axis_tx_req_queue(s_axis_tx_req_queue), + .s_axis_tx_req_tag(s_axis_tx_req_tag), + .s_axis_tx_req_dest(s_axis_tx_req_dest), + .s_axis_tx_req_valid(s_axis_tx_req_valid), + .s_axis_tx_req_ready(s_axis_tx_req_ready), + + /* + * Transmit request status output + */ + .m_axis_tx_req_status_len(m_axis_tx_req_status_len), + .m_axis_tx_req_status_tag(m_axis_tx_req_status_tag), + .m_axis_tx_req_status_valid(m_axis_tx_req_status_valid), + + /* + * Descriptor request output + */ + .m_axis_desc_req_queue(m_axis_desc_req_queue), + .m_axis_desc_req_tag(m_axis_desc_req_tag), + .m_axis_desc_req_valid(m_axis_desc_req_valid), + .m_axis_desc_req_ready(m_axis_desc_req_ready), + + /* + * Descriptor request status input + */ + .s_axis_desc_req_status_queue(s_axis_desc_req_status_queue), + .s_axis_desc_req_status_ptr(s_axis_desc_req_status_ptr), + .s_axis_desc_req_status_cpl(s_axis_desc_req_status_cpl), + .s_axis_desc_req_status_tag(s_axis_desc_req_status_tag), + .s_axis_desc_req_status_empty(s_axis_desc_req_status_empty), + .s_axis_desc_req_status_error(s_axis_desc_req_status_error), + .s_axis_desc_req_status_valid(s_axis_desc_req_status_valid), + + /* + * Descriptor data input + */ + .s_axis_desc_tdata(tx_fifo_desc_tdata), + .s_axis_desc_tkeep(tx_fifo_desc_tkeep), + .s_axis_desc_tvalid(tx_fifo_desc_tvalid), + .s_axis_desc_tready(tx_fifo_desc_tready), + .s_axis_desc_tlast(tx_fifo_desc_tlast), + .s_axis_desc_tid(tx_fifo_desc_tid), + .s_axis_desc_tuser(tx_fifo_desc_tuser), + + /* + * Completion request output + */ + .m_axis_cpl_req_queue(m_axis_cpl_req_queue), + .m_axis_cpl_req_tag(m_axis_cpl_req_tag), + .m_axis_cpl_req_data(m_axis_cpl_req_data), + .m_axis_cpl_req_valid(m_axis_cpl_req_valid), + .m_axis_cpl_req_ready(m_axis_cpl_req_ready), + + /* + * Completion request status input + */ + .s_axis_cpl_req_status_tag(s_axis_cpl_req_status_tag), + .s_axis_cpl_req_status_full(s_axis_cpl_req_status_full), + .s_axis_cpl_req_status_error(s_axis_cpl_req_status_error), + .s_axis_cpl_req_status_valid(s_axis_cpl_req_status_valid), + + /* + * DMA read descriptor output + */ + .m_axis_dma_read_desc_dma_addr(m_axis_dma_read_desc_dma_addr), + .m_axis_dma_read_desc_ram_addr(m_axis_dma_read_desc_ram_addr), + .m_axis_dma_read_desc_len(m_axis_dma_read_desc_len), + .m_axis_dma_read_desc_tag(m_axis_dma_read_desc_tag), + .m_axis_dma_read_desc_valid(m_axis_dma_read_desc_valid), + .m_axis_dma_read_desc_ready(m_axis_dma_read_desc_ready), + + /* + * DMA read descriptor status input + */ + .s_axis_dma_read_desc_status_tag(s_axis_dma_read_desc_status_tag), + .s_axis_dma_read_desc_status_error(s_axis_dma_read_desc_status_error), + .s_axis_dma_read_desc_status_valid(s_axis_dma_read_desc_status_valid), + + /* + * Transmit descriptor output + */ + .m_axis_tx_desc_addr(dma_tx_desc_addr), + .m_axis_tx_desc_len(dma_tx_desc_len), + .m_axis_tx_desc_tag(dma_tx_desc_tag), + .m_axis_tx_desc_id(dma_tx_desc_id), + .m_axis_tx_desc_dest(dma_tx_desc_dest), + .m_axis_tx_desc_user(dma_tx_desc_user), + .m_axis_tx_desc_valid(dma_tx_desc_valid), + .m_axis_tx_desc_ready(dma_tx_desc_ready), + + /* + * Transmit descriptor status input + */ + .s_axis_tx_desc_status_tag(dma_tx_desc_status_tag), + .s_axis_tx_desc_status_error(dma_tx_desc_status_error), + .s_axis_tx_desc_status_valid(dma_tx_desc_status_valid), + + /* + * Transmit checksum command output + */ + .m_axis_tx_csum_cmd_csum_enable(tx_csum_cmd_csum_enable), + .m_axis_tx_csum_cmd_csum_start(tx_csum_cmd_csum_start), + .m_axis_tx_csum_cmd_csum_offset(tx_csum_cmd_csum_offset), + .m_axis_tx_csum_cmd_valid(tx_csum_cmd_valid), + .m_axis_tx_csum_cmd_ready(tx_csum_cmd_ready), + + /* + * Transmit timestamp input + */ + .s_axis_tx_ptp_ts(s_axis_tx_ptp_ts), + .s_axis_tx_ptp_ts_tag(s_axis_tx_ptp_ts_tag), + .s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid), + .s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready), + + /* + * Configuration + */ + .enable(1'b1) +); + +wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr_int; +wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid_int; +wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready_int; +wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data_int; +wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid_int; +wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready_int; + +dma_psdpram #( + .SIZE(TX_RAM_SIZE), + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), + .SEG_BE_WIDTH(SEG_BE_WIDTH), + .PIPELINE(RAM_PIPELINE) +) +dma_psdpram_tx_inst ( + .clk(clk), + .rst(rst), + + /* + * Write port + */ + .wr_cmd_be(dma_ram_wr_cmd_be), + .wr_cmd_addr(dma_ram_wr_cmd_addr), + .wr_cmd_data(dma_ram_wr_cmd_data), + .wr_cmd_valid(dma_ram_wr_cmd_valid), + .wr_cmd_ready(dma_ram_wr_cmd_ready), + .wr_done(dma_ram_wr_done), + + /* + * Read port + */ + .rd_cmd_addr(dma_ram_rd_cmd_addr_int), + .rd_cmd_valid(dma_ram_rd_cmd_valid_int), + .rd_cmd_ready(dma_ram_rd_cmd_ready_int), + .rd_resp_data(dma_ram_rd_resp_data_int), + .rd_resp_valid(dma_ram_rd_resp_valid_int), + .rd_resp_ready(dma_ram_rd_resp_ready_int) +); + +wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata_int; +wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep_int; +wire tx_axis_tvalid_int; +wire tx_axis_tready_int; +wire tx_axis_tlast_int; +wire [AXIS_TX_ID_WIDTH-1:0] tx_axis_tid_int; +wire [AXIS_TX_DEST_WIDTH-1:0] tx_axis_tdest_int; +wire [AXIS_TX_USER_WIDTH-1:0] tx_axis_tuser_int; + +dma_client_axis_source #( + .SEG_COUNT(SEG_COUNT), + .SEG_DATA_WIDTH(SEG_DATA_WIDTH), + .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), + .SEG_BE_WIDTH(SEG_BE_WIDTH), + .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .AXIS_LAST_ENABLE(1), + .AXIS_ID_ENABLE(1), + .AXIS_ID_WIDTH(AXIS_TX_ID_WIDTH), + .AXIS_DEST_ENABLE(1), + .AXIS_DEST_WIDTH(AXIS_TX_DEST_WIDTH), + .AXIS_USER_ENABLE(1), + .AXIS_USER_WIDTH(AXIS_TX_USER_WIDTH), + .LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), + .TAG_WIDTH(DMA_CLIENT_TAG_WIDTH) +) +dma_client_axis_source_inst ( + .clk(clk), + .rst(rst), + + /* + * DMA read descriptor input + */ + .s_axis_read_desc_ram_addr(dma_tx_desc_addr), + .s_axis_read_desc_len(dma_tx_desc_len), + .s_axis_read_desc_tag(dma_tx_desc_tag), + .s_axis_read_desc_id(dma_tx_desc_id), + .s_axis_read_desc_dest(dma_tx_desc_dest), + .s_axis_read_desc_user(dma_tx_desc_user), + .s_axis_read_desc_valid(dma_tx_desc_valid), + .s_axis_read_desc_ready(dma_tx_desc_ready), + + /* + * DMA read descriptor status output + */ + .m_axis_read_desc_status_tag(dma_tx_desc_status_tag), + .m_axis_read_desc_status_error(dma_tx_desc_status_error), + .m_axis_read_desc_status_valid(dma_tx_desc_status_valid), + + /* + * AXI stream read data output + */ + .m_axis_read_data_tdata(tx_axis_tdata_int), + .m_axis_read_data_tkeep(tx_axis_tkeep_int), + .m_axis_read_data_tvalid(tx_axis_tvalid_int), + .m_axis_read_data_tready(tx_axis_tready_int), + .m_axis_read_data_tlast(tx_axis_tlast_int), + .m_axis_read_data_tid(tx_axis_tid_int), + .m_axis_read_data_tdest(tx_axis_tdest_int), + .m_axis_read_data_tuser(tx_axis_tuser_int), + + /* + * RAM interface + */ + .ram_rd_cmd_addr(dma_ram_rd_cmd_addr_int), + .ram_rd_cmd_valid(dma_ram_rd_cmd_valid_int), + .ram_rd_cmd_ready(dma_ram_rd_cmd_ready_int), + .ram_rd_resp_data(dma_ram_rd_resp_data_int), + .ram_rd_resp_valid(dma_ram_rd_resp_valid_int), + .ram_rd_resp_ready(dma_ram_rd_resp_ready_int), + + /* + * Configuration + */ + .enable(1'b1) +); + +mqnic_egress #( + .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE), + .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), + .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), + .AXIS_ID_WIDTH(AXIS_TX_ID_WIDTH), + .AXIS_DEST_WIDTH(AXIS_TX_DEST_WIDTH), + .AXIS_USER_WIDTH(AXIS_TX_USER_WIDTH), + .MAX_TX_SIZE(MAX_TX_SIZE) +) +egress_inst ( + .clk(clk), + .rst(rst), + + /* + * Transmit data input + */ + .s_axis_tdata(tx_axis_tdata_int), + .s_axis_tkeep(tx_axis_tkeep_int), + .s_axis_tvalid(tx_axis_tvalid_int), + .s_axis_tready(tx_axis_tready_int), + .s_axis_tlast(tx_axis_tlast_int), + .s_axis_tid(tx_axis_tid_int), + .s_axis_tdest(tx_axis_tdest_int), + .s_axis_tuser(tx_axis_tuser_int), + + /* + * Transmit data output + */ + .m_axis_tdata(tx_axis_tdata), + .m_axis_tkeep(tx_axis_tkeep), + .m_axis_tvalid(tx_axis_tvalid), + .m_axis_tready(tx_axis_tready), + .m_axis_tlast(tx_axis_tlast), + .m_axis_tid(tx_axis_tid), + .m_axis_tdest(tx_axis_tdest), + .m_axis_tuser(tx_axis_tuser), + + /* + * Transmit checksum command + */ + .tx_csum_cmd_csum_enable(tx_csum_cmd_csum_enable), + .tx_csum_cmd_csum_start(tx_csum_cmd_csum_start), + .tx_csum_cmd_csum_offset(tx_csum_cmd_csum_offset), + .tx_csum_cmd_valid(tx_csum_cmd_valid), + .tx_csum_cmd_ready(tx_csum_cmd_ready) +); + +endmodule + +`resetall diff --git a/fpga/common/rtl/mqnic_port.v b/fpga/common/rtl/mqnic_port.v deleted file mode 100644 index b26591a10..000000000 --- a/fpga/common/rtl/mqnic_port.v +++ /dev/null @@ -1,1738 +0,0 @@ -/* - -Copyright 2019, The Regents of the University of California. -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - -THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS -IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR -CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT -OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING -IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. - -The views and conclusions contained in the software and documentation are those -of the authors and should not be interpreted as representing official policies, -either expressed or implied, of The Regents of the University of California. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * NIC Port - */ -module mqnic_port # -( - // DMA address width - parameter DMA_ADDR_WIDTH = 64, - // DMA length field width - parameter DMA_LEN_WIDTH = 16, - // DMA client length field width - parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH, - // DMA tag field width - parameter DMA_TAG_WIDTH = 8, - // Request tag field width - parameter REQ_TAG_WIDTH = 8, - // Descriptor request tag field width - parameter DESC_REQ_TAG_WIDTH = 8, - // Queue request tag field width - parameter QUEUE_REQ_TAG_WIDTH = 8, - // Queue operation tag field width - parameter QUEUE_OP_TAG_WIDTH = 8, - // Transmit queue index width - parameter TX_QUEUE_INDEX_WIDTH = 8, - // Receive queue index width - parameter RX_QUEUE_INDEX_WIDTH = 8, - // Max queue index width - parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH, - // Transmit completion queue index width - parameter TX_CPL_QUEUE_INDEX_WIDTH = 8, - // Receive completion queue index width - parameter RX_CPL_QUEUE_INDEX_WIDTH = 8, - // Max completion queue index width - parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH > RX_CPL_QUEUE_INDEX_WIDTH ? TX_CPL_QUEUE_INDEX_WIDTH : RX_CPL_QUEUE_INDEX_WIDTH, - // Transmit descriptor table size (number of in-flight operations) - parameter TX_DESC_TABLE_SIZE = 16, - // Receive descriptor table size (number of in-flight operations) - parameter RX_DESC_TABLE_SIZE = 16, - // Width of descriptor table field for tracking outstanding DMA operations - parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4, - // Max number of in-flight descriptor requests (transmit) - parameter TX_MAX_DESC_REQ = 16, - // Transmit descriptor FIFO size - parameter TX_DESC_FIFO_SIZE = TX_MAX_DESC_REQ*8, - // Max number of in-flight descriptor requests (transmit) - parameter RX_MAX_DESC_REQ = 16, - // Receive descriptor FIFO size - parameter RX_DESC_FIFO_SIZE = RX_MAX_DESC_REQ*8, - // Scheduler operation table size - parameter TX_SCHEDULER_OP_TABLE_SIZE = 32, - // Scheduler pipeline setting - parameter TX_SCHEDULER_PIPELINE = 3, - // Scheduler TDMA index width - parameter TDMA_INDEX_WIDTH = 8, - // Queue element pointer width - parameter QUEUE_PTR_WIDTH = 16, - // Enable PTP timestamping - parameter PTP_TS_ENABLE = 1, - // PTP timestamp width - parameter PTP_TS_WIDTH = 96, - // Enable TX checksum offload - parameter TX_CHECKSUM_ENABLE = 1, - // Enable RX RSS - parameter RX_RSS_ENABLE = 1, - // Enable RX hashing - parameter RX_HASH_ENABLE = 1, - // Enable RX checksum offload - parameter RX_CHECKSUM_ENABLE = 1, - // Width of control register interface address in bits - parameter REG_ADDR_WIDTH = 16, - // Width of control register interface data in bits - parameter REG_DATA_WIDTH = 32, - // Width of control register interface strb - parameter REG_STRB_WIDTH = (REG_DATA_WIDTH/8), - // Register block base address - parameter RB_BASE_ADDR = 0, - // Register block next pointer - parameter RB_NEXT_PTR = 0, - // Width of AXI lite data bus in bits - parameter AXIL_DATA_WIDTH = 32, - // Width of AXI lite address bus in bits - parameter AXIL_ADDR_WIDTH = 16, - // Width of AXI lite wstrb (width of data bus in words) - parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8), - // Offset to AXI lite interface - parameter AXIL_OFFSET = 0, - // DMA RAM segment count - parameter SEG_COUNT = 2, - // DMA RAM segment data width - parameter SEG_DATA_WIDTH = 64, - // DMA RAM segment address width - parameter SEG_ADDR_WIDTH = 8, - // DMA RAM segment byte enable width - parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8, - // DMA RAM address width - parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH), - // DMA RAM pipeline stages - parameter RAM_PIPELINE = 2, - // Width of AXI stream interfaces in bits - parameter AXIS_DATA_WIDTH = 256, - // AXI stream tkeep signal width (words per cycle) - parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, - // Max transmit packet size - parameter MAX_TX_SIZE = 2048, - // Max receive packet size - parameter MAX_RX_SIZE = 2048, - // DMA TX RAM size - parameter TX_RAM_SIZE = 8*MAX_TX_SIZE, - // DMA RX RAM size - parameter RX_RAM_SIZE = 8*MAX_RX_SIZE, - // Descriptor size (in bytes) - parameter DESC_SIZE = 16, - // Descriptor size (in bytes) - parameter CPL_SIZE = 32, - // Width of AXI stream descriptor interfaces in bits - parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8, - // AXI stream descriptor tkeep signal width (words per cycle) - parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8 -) -( - input wire clk, - input wire rst, - - /* - * Descriptor request output - */ - output wire [0:0] m_axis_desc_req_sel, - output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue, - output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag, - output wire m_axis_desc_req_valid, - input wire m_axis_desc_req_ready, - - /* - * Descriptor request status input - */ - input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue, - input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr, - input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl, - input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag, - input wire s_axis_desc_req_status_empty, - input wire s_axis_desc_req_status_error, - input wire s_axis_desc_req_status_valid, - - /* - * Descriptor data input - */ - input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata, - input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep, - input wire s_axis_desc_tvalid, - output wire s_axis_desc_tready, - input wire s_axis_desc_tlast, - input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_tid, - input wire s_axis_desc_tuser, - - /* - * Completion request output - */ - output wire [0:0] m_axis_cpl_req_sel, - output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue, - output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag, - output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data, - output wire m_axis_cpl_req_valid, - input wire m_axis_cpl_req_ready, - - /* - * Completion request status input - */ - input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag, - input wire s_axis_cpl_req_status_full, - input wire s_axis_cpl_req_status_error, - input wire s_axis_cpl_req_status_valid, - - /* - * TX doorbell input - */ - input wire [TX_QUEUE_INDEX_WIDTH-1:0] s_axis_tx_doorbell_queue, - input wire s_axis_tx_doorbell_valid, - - /* - * DMA read descriptor output - */ - output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_read_desc_dma_addr, - output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_read_desc_ram_addr, - output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_read_desc_len, - output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_read_desc_tag, - output wire m_axis_dma_read_desc_valid, - input wire m_axis_dma_read_desc_ready, - - /* - * DMA read descriptor status input - */ - input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag, - input wire [3:0] s_axis_dma_read_desc_status_error, - input wire s_axis_dma_read_desc_status_valid, - - /* - * DMA write descriptor output - */ - output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr, - output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr, - output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len, - output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag, - output wire m_axis_dma_write_desc_valid, - input wire m_axis_dma_write_desc_ready, - - /* - * DMA write descriptor status input - */ - input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag, - input wire [3:0] s_axis_dma_write_desc_status_error, - input wire s_axis_dma_write_desc_status_valid, - - /* - * Control register interface - */ - input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_wr_addr, - input wire [REG_DATA_WIDTH-1:0] ctrl_reg_wr_data, - input wire [REG_STRB_WIDTH-1:0] ctrl_reg_wr_strb, - input wire ctrl_reg_wr_en, - output wire ctrl_reg_wr_wait, - output wire ctrl_reg_wr_ack, - input wire [REG_ADDR_WIDTH-1:0] ctrl_reg_rd_addr, - input wire ctrl_reg_rd_en, - output wire [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data, - output wire ctrl_reg_rd_wait, - output wire ctrl_reg_rd_ack, - - /* - * AXI-Lite slave interface (schedulers) - */ - input wire [AXIL_ADDR_WIDTH-1:0] s_axil_awaddr, - input wire [2:0] s_axil_awprot, - input wire s_axil_awvalid, - output wire s_axil_awready, - input wire [AXIL_DATA_WIDTH-1:0] s_axil_wdata, - input wire [AXIL_STRB_WIDTH-1:0] s_axil_wstrb, - input wire s_axil_wvalid, - output wire s_axil_wready, - output wire [1:0] s_axil_bresp, - output wire s_axil_bvalid, - input wire s_axil_bready, - input wire [AXIL_ADDR_WIDTH-1:0] s_axil_araddr, - input wire [2:0] s_axil_arprot, - input wire s_axil_arvalid, - output wire s_axil_arready, - output wire [AXIL_DATA_WIDTH-1:0] s_axil_rdata, - output wire [1:0] s_axil_rresp, - output wire s_axil_rvalid, - input wire s_axil_rready, - - /* - * RAM interface - */ - input wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be, - input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr, - input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data, - input wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid, - output wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready, - output wire [SEG_COUNT-1:0] dma_ram_wr_done, - input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr, - input wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid, - output wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready, - output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data, - output wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid, - input wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready, - - /* - * Transmit data output - */ - output wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata, - output wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep, - output wire tx_axis_tvalid, - input wire tx_axis_tready, - output wire tx_axis_tlast, - output wire tx_axis_tuser, - - /* - * Transmit PTP timestamp input - */ - input wire [PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts_96, - input wire s_axis_tx_ptp_ts_valid, - output wire s_axis_tx_ptp_ts_ready, - - /* - * Receive data input - */ - input wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata, - input wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep, - input wire rx_axis_tvalid, - output wire rx_axis_tready, - input wire rx_axis_tlast, - input wire rx_axis_tuser, - - /* - * Receive PTP timestamp input - */ - input wire [PTP_TS_WIDTH-1:0] s_axis_rx_ptp_ts_96, - input wire s_axis_rx_ptp_ts_valid, - output wire s_axis_rx_ptp_ts_ready, - - /* - * PTP clock - */ - input wire [PTP_TS_WIDTH-1:0] ptp_ts_96, - input wire ptp_ts_step, - - /* - * Configuration - */ - input wire [DMA_CLIENT_LEN_WIDTH-1:0] tx_mtu, - input wire [DMA_CLIENT_LEN_WIDTH-1:0] rx_mtu, - input wire [RX_QUEUE_INDEX_WIDTH-1:0] rss_mask -); - -parameter DMA_CLIENT_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE > RX_DESC_TABLE_SIZE ? TX_DESC_TABLE_SIZE : RX_DESC_TABLE_SIZE); - -parameter DESC_REQ_TAG_WIDTH_INT = DESC_REQ_TAG_WIDTH - $clog2(2); - -// Checksumming and RSS -wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata_int; -wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep_int; -wire rx_axis_tvalid_int; -wire rx_axis_tready_int; -wire rx_axis_tlast_int; -wire rx_axis_tuser_int; - -wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata_int; -wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep_int; -wire tx_axis_tvalid_int; -wire tx_axis_tready_int; -wire tx_axis_tlast_int; -wire tx_axis_tuser_int; - -// Descriptor and completion -wire [0:0] rx_desc_req_sel = 1'b1; -wire [QUEUE_INDEX_WIDTH-1:0] rx_desc_req_queue; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_desc_req_tag; -wire rx_desc_req_valid; -wire rx_desc_req_ready; - -wire [QUEUE_INDEX_WIDTH-1:0] rx_desc_req_status_queue; -wire [QUEUE_PTR_WIDTH-1:0] rx_desc_req_status_ptr; -wire [CPL_QUEUE_INDEX_WIDTH-1:0] rx_desc_req_status_cpl; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_desc_req_status_tag; -wire rx_desc_req_status_empty; -wire rx_desc_req_status_error; -wire rx_desc_req_status_valid; - -wire [AXIS_DESC_DATA_WIDTH-1:0] rx_desc_tdata; -wire [AXIS_DESC_KEEP_WIDTH-1:0] rx_desc_tkeep; -wire rx_desc_tvalid; -wire rx_desc_tready; -wire rx_desc_tlast; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_desc_tid; -wire rx_desc_tuser; - -wire [AXIS_DESC_DATA_WIDTH-1:0] rx_fifo_desc_tdata; -wire [AXIS_DESC_KEEP_WIDTH-1:0] rx_fifo_desc_tkeep; -wire rx_fifo_desc_tvalid; -wire rx_fifo_desc_tready; -wire rx_fifo_desc_tlast; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_fifo_desc_tid; -wire rx_fifo_desc_tuser; - -wire [0:0] tx_desc_req_sel = 1'b0; -wire [QUEUE_INDEX_WIDTH-1:0] tx_desc_req_queue; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_desc_req_tag; -wire tx_desc_req_valid; -wire tx_desc_req_ready; - -wire [QUEUE_INDEX_WIDTH-1:0] tx_desc_req_status_queue; -wire [QUEUE_PTR_WIDTH-1:0] tx_desc_req_status_ptr; -wire [CPL_QUEUE_INDEX_WIDTH-1:0] tx_desc_req_status_cpl; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_desc_req_status_tag; -wire tx_desc_req_status_empty; -wire tx_desc_req_status_error; -wire tx_desc_req_status_valid; - -wire [AXIS_DESC_DATA_WIDTH-1:0] tx_desc_tdata; -wire [AXIS_DESC_KEEP_WIDTH-1:0] tx_desc_tkeep; -wire tx_desc_tvalid; -wire tx_desc_tready; -wire tx_desc_tlast; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_desc_tid; -wire tx_desc_tuser; - -wire [AXIS_DESC_DATA_WIDTH-1:0] tx_fifo_desc_tdata; -wire [AXIS_DESC_KEEP_WIDTH-1:0] tx_fifo_desc_tkeep; -wire tx_fifo_desc_tvalid; -wire tx_fifo_desc_tready; -wire tx_fifo_desc_tlast; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_fifo_desc_tid; -wire tx_fifo_desc_tuser; - -wire [0:0] rx_cpl_req_sel = 1'b1; -wire [QUEUE_INDEX_WIDTH-1:0] rx_cpl_req_queue; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_cpl_req_tag; -wire [CPL_SIZE*8-1:0] rx_cpl_req_data; -wire rx_cpl_req_valid; -wire rx_cpl_req_ready; - -wire [DESC_REQ_TAG_WIDTH_INT-1:0] rx_cpl_req_status_tag; -wire rx_cpl_req_status_full; -wire rx_cpl_req_status_error; -wire rx_cpl_req_status_valid; - -wire [0:0] tx_cpl_req_sel = 1'b0; -wire [QUEUE_INDEX_WIDTH-1:0] tx_cpl_req_queue; -wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_cpl_req_tag; -wire [CPL_SIZE*8-1:0] tx_cpl_req_data; -wire tx_cpl_req_valid; -wire tx_cpl_req_ready; - -wire [DESC_REQ_TAG_WIDTH_INT-1:0] tx_cpl_req_status_tag; -wire tx_cpl_req_status_full; -wire tx_cpl_req_status_error; -wire tx_cpl_req_status_valid; - -// Scheduler -wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_sched_ctrl_queue; -wire tx_sched_ctrl_enable; -wire tx_sched_ctrl_valid; -wire tx_sched_ctrl_ready; - -// TX engine -wire [TX_QUEUE_INDEX_WIDTH-1:0] tx_req_queue; -wire [REQ_TAG_WIDTH-1:0] tx_req_tag; -wire tx_req_valid; -wire tx_req_ready; - -wire [DMA_CLIENT_LEN_WIDTH-1:0] tx_req_status_len; -wire [REQ_TAG_WIDTH-1:0] tx_req_status_tag; -wire tx_req_status_valid; - -// RX engine -wire [RX_QUEUE_INDEX_WIDTH-1:0] rx_req_queue; -wire [REQ_TAG_WIDTH-1:0] rx_req_tag; -wire rx_req_valid; -wire rx_req_ready; - -wire [REQ_TAG_WIDTH-1:0] rx_req_status_tag; -wire rx_req_status_valid; - -// Timestamps -wire [95:0] rx_ptp_ts_96; -wire rx_ptp_ts_valid; -wire rx_ptp_ts_ready; - -wire [95:0] tx_ptp_ts_96; -wire tx_ptp_ts_valid; -wire tx_ptp_ts_ready; - -// RX hashing -wire [31:0] rx_hash; -wire [3:0] rx_hash_type; -wire rx_hash_valid; - -wire [31:0] rx_fifo_hash; -wire [3:0] rx_fifo_hash_type; -wire rx_fifo_hash_valid; -wire rx_fifo_hash_ready; - -// Checksums -wire [15:0] rx_csum; -wire rx_csum_valid; - -wire [15:0] rx_fifo_csum; -wire rx_fifo_csum_valid; -wire rx_fifo_csum_ready; - -wire tx_csum_cmd_csum_enable; -wire [7:0] tx_csum_cmd_csum_start; -wire [7:0] tx_csum_cmd_csum_offset; -wire tx_csum_cmd_valid; -wire tx_csum_cmd_ready; - -wire tx_fifo_csum_cmd_csum_enable; -wire [7:0] tx_fifo_csum_cmd_csum_start; -wire [7:0] tx_fifo_csum_cmd_csum_offset; -wire tx_fifo_csum_cmd_valid; -wire tx_fifo_csum_cmd_ready; - -// Interface DMA control -wire [RAM_ADDR_WIDTH-1:0] dma_tx_desc_addr; -wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_tx_desc_len; -wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_tx_desc_tag; -wire dma_tx_desc_user; -wire dma_tx_desc_valid; -wire dma_tx_desc_ready; - -wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_tx_desc_status_tag; -wire [3:0] dma_tx_desc_status_error; -wire dma_tx_desc_status_valid; - -wire [RAM_ADDR_WIDTH-1:0] dma_rx_desc_addr; -wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_len; -wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_tag; -wire dma_rx_desc_valid; -wire dma_rx_desc_ready; - -wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_status_len; -wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_status_tag; -wire dma_rx_desc_status_user; -wire [3:0] dma_rx_desc_status_error; -wire dma_rx_desc_status_valid; - -desc_op_mux #( - .PORTS(2), - .SELECT_WIDTH(1), - .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), - .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), - .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH), - .S_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT), - .M_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH), - .AXIS_DATA_WIDTH(AXIS_DESC_DATA_WIDTH), - .AXIS_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH), - .ARB_TYPE_ROUND_ROBIN(1), - .ARB_LSB_HIGH_PRIORITY(1) -) -desc_op_mux_inst ( - .clk(clk), - .rst(rst), - - /* - * Descriptor request output - */ - .m_axis_req_sel(m_axis_desc_req_sel), - .m_axis_req_queue(m_axis_desc_req_queue), - .m_axis_req_tag(m_axis_desc_req_tag), - .m_axis_req_valid(m_axis_desc_req_valid), - .m_axis_req_ready(m_axis_desc_req_ready), - - /* - * Descriptor request status input - */ - .s_axis_req_status_queue(s_axis_desc_req_status_queue), - .s_axis_req_status_ptr(s_axis_desc_req_status_ptr), - .s_axis_req_status_cpl(s_axis_desc_req_status_cpl), - .s_axis_req_status_tag(s_axis_desc_req_status_tag), - .s_axis_req_status_empty(s_axis_desc_req_status_empty), - .s_axis_req_status_error(s_axis_desc_req_status_error), - .s_axis_req_status_valid(s_axis_desc_req_status_valid), - - /* - * Descriptor data input - */ - .s_axis_desc_tdata(s_axis_desc_tdata), - .s_axis_desc_tkeep(s_axis_desc_tkeep), - .s_axis_desc_tvalid(s_axis_desc_tvalid), - .s_axis_desc_tready(s_axis_desc_tready), - .s_axis_desc_tlast(s_axis_desc_tlast), - .s_axis_desc_tid(s_axis_desc_tid), - .s_axis_desc_tuser(s_axis_desc_tuser), - - /* - * Descriptor request input - */ - .s_axis_req_sel({rx_desc_req_sel, tx_desc_req_sel}), - .s_axis_req_queue({rx_desc_req_queue, tx_desc_req_queue}), - .s_axis_req_tag({rx_desc_req_tag, tx_desc_req_tag}), - .s_axis_req_valid({rx_desc_req_valid, tx_desc_req_valid}), - .s_axis_req_ready({rx_desc_req_ready, tx_desc_req_ready}), - - /* - * Descriptor response output - */ - .m_axis_req_status_queue({rx_desc_req_status_queue, tx_desc_req_status_queue}), - .m_axis_req_status_ptr({rx_desc_req_status_ptr, tx_desc_req_status_ptr}), - .m_axis_req_status_cpl({rx_desc_req_status_cpl, tx_desc_req_status_cpl}), - .m_axis_req_status_tag({rx_desc_req_status_tag, tx_desc_req_status_tag}), - .m_axis_req_status_empty({rx_desc_req_status_empty, tx_desc_req_status_empty}), - .m_axis_req_status_error({rx_desc_req_status_error, tx_desc_req_status_error}), - .m_axis_req_status_valid({rx_desc_req_status_valid, tx_desc_req_status_valid}), - - /* - * Descriptor data output - */ - .m_axis_desc_tdata({rx_desc_tdata, tx_desc_tdata}), - .m_axis_desc_tkeep({rx_desc_tkeep, tx_desc_tkeep}), - .m_axis_desc_tvalid({rx_desc_tvalid, tx_desc_tvalid}), - .m_axis_desc_tready({rx_desc_tready, tx_desc_tready}), - .m_axis_desc_tlast({rx_desc_tlast, tx_desc_tlast}), - .m_axis_desc_tid({rx_desc_tid, tx_desc_tid}), - .m_axis_desc_tuser({rx_desc_tuser, tx_desc_tuser}) -); - -cpl_op_mux #( - .PORTS(2), - .SELECT_WIDTH(1), - .QUEUE_INDEX_WIDTH(QUEUE_INDEX_WIDTH), - .S_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT), - .M_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH), - .CPL_SIZE(CPL_SIZE), - .ARB_TYPE_ROUND_ROBIN(1), - .ARB_LSB_HIGH_PRIORITY(1) -) -cpl_op_mux_inst ( - .clk(clk), - .rst(rst), - - /* - * Completion request output - */ - .m_axis_req_sel(m_axis_cpl_req_sel), - .m_axis_req_queue(m_axis_cpl_req_queue), - .m_axis_req_tag(m_axis_cpl_req_tag), - .m_axis_req_data(m_axis_cpl_req_data), - .m_axis_req_valid(m_axis_cpl_req_valid), - .m_axis_req_ready(m_axis_cpl_req_ready), - - /* - * Completion request status input - */ - .s_axis_req_status_tag(s_axis_cpl_req_status_tag), - .s_axis_req_status_full(s_axis_cpl_req_status_full), - .s_axis_req_status_error(s_axis_cpl_req_status_error), - .s_axis_req_status_valid(s_axis_cpl_req_status_valid), - - /* - * Completion request input - */ - .s_axis_req_sel({rx_cpl_req_sel, tx_cpl_req_sel}), - .s_axis_req_queue({rx_cpl_req_queue, tx_cpl_req_queue}), - .s_axis_req_tag({rx_cpl_req_tag, tx_cpl_req_tag}), - .s_axis_req_data({rx_cpl_req_data, tx_cpl_req_data}), - .s_axis_req_valid({rx_cpl_req_valid, tx_cpl_req_valid}), - .s_axis_req_ready({rx_cpl_req_ready, tx_cpl_req_ready}), - - /* - * Completion response output - */ - .m_axis_req_status_tag({rx_cpl_req_status_tag, tx_cpl_req_status_tag}), - .m_axis_req_status_full({rx_cpl_req_status_full, tx_cpl_req_status_full}), - .m_axis_req_status_error({rx_cpl_req_status_error, tx_cpl_req_status_error}), - .m_axis_req_status_valid({rx_cpl_req_status_valid, tx_cpl_req_status_valid}) -); - -mqnic_tx_scheduler_block #( - .REG_DATA_WIDTH(REG_DATA_WIDTH), - .REG_ADDR_WIDTH(REG_ADDR_WIDTH), - .REG_STRB_WIDTH(REG_STRB_WIDTH), - .RB_BASE_ADDR(RB_BASE_ADDR), - .RB_NEXT_PTR(RB_NEXT_PTR), - .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH), - .AXIL_STRB_WIDTH(AXIL_STRB_WIDTH), - .AXIL_OFFSET(AXIL_OFFSET), - .LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), - .REQ_TAG_WIDTH(REQ_TAG_WIDTH), - .OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), - .QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .PIPELINE(TX_SCHEDULER_PIPELINE), - .TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH), - .PTP_TS_WIDTH(PTP_TS_WIDTH), - .MAX_TX_SIZE(MAX_TX_SIZE) -) -scheduler_block ( - .clk(clk), - .rst(rst), - - /* - * Control register interface - */ - .ctrl_reg_wr_addr(ctrl_reg_wr_addr), - .ctrl_reg_wr_data(ctrl_reg_wr_data), - .ctrl_reg_wr_strb(ctrl_reg_wr_strb), - .ctrl_reg_wr_en(ctrl_reg_wr_en), - .ctrl_reg_wr_wait(ctrl_reg_wr_wait), - .ctrl_reg_wr_ack(ctrl_reg_wr_ack), - .ctrl_reg_rd_addr(ctrl_reg_rd_addr), - .ctrl_reg_rd_en(ctrl_reg_rd_en), - .ctrl_reg_rd_data(ctrl_reg_rd_data), - .ctrl_reg_rd_wait(ctrl_reg_rd_wait), - .ctrl_reg_rd_ack(ctrl_reg_rd_ack), - - /* - * AXI-Lite slave interface - */ - .s_axil_awaddr(s_axil_awaddr), - .s_axil_awprot(s_axil_awprot), - .s_axil_awvalid(s_axil_awvalid), - .s_axil_awready(s_axil_awready), - .s_axil_wdata(s_axil_wdata), - .s_axil_wstrb(s_axil_wstrb), - .s_axil_wvalid(s_axil_wvalid), - .s_axil_wready(s_axil_wready), - .s_axil_bresp(s_axil_bresp), - .s_axil_bvalid(s_axil_bvalid), - .s_axil_bready(s_axil_bready), - .s_axil_araddr(s_axil_araddr), - .s_axil_arprot(s_axil_arprot), - .s_axil_arvalid(s_axil_arvalid), - .s_axil_arready(s_axil_arready), - .s_axil_rdata(s_axil_rdata), - .s_axil_rresp(s_axil_rresp), - .s_axil_rvalid(s_axil_rvalid), - .s_axil_rready(s_axil_rready), - - /* - * Transmit request output (queue index) - */ - .m_axis_tx_req_queue(tx_req_queue), - .m_axis_tx_req_tag(tx_req_tag), - .m_axis_tx_req_valid(tx_req_valid), - .m_axis_tx_req_ready(tx_req_ready), - - /* - * Transmit request status input - */ - .s_axis_tx_req_status_len(tx_req_status_len), - .s_axis_tx_req_status_tag(tx_req_status_tag), - .s_axis_tx_req_status_valid(tx_req_status_valid), - - /* - * Doorbell input - */ - .s_axis_doorbell_queue(s_axis_tx_doorbell_queue), - .s_axis_doorbell_valid(s_axis_tx_doorbell_valid), - - /* - * PTP clock - */ - .ptp_ts_96(ptp_ts_96), - .ptp_ts_step(ptp_ts_step) -); - -axis_fifo #( - .DEPTH(TX_DESC_FIFO_SIZE*DESC_SIZE), - .DATA_WIDTH(AXIS_DESC_DATA_WIDTH), - .KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH), - .LAST_ENABLE(1), - .ID_ENABLE(1), - .ID_WIDTH(DESC_REQ_TAG_WIDTH_INT), - .DEST_ENABLE(0), - .USER_ENABLE(0), - .PIPELINE_OUTPUT(3), - .FRAME_FIFO(0) -) -tx_desc_fifo ( - .clk(clk), - .rst(rst), - - // AXI input - .s_axis_tdata(tx_desc_tdata), - .s_axis_tkeep(tx_desc_tkeep), - .s_axis_tvalid(tx_desc_tvalid), - .s_axis_tready(tx_desc_tready), - .s_axis_tlast(tx_desc_tlast), - .s_axis_tid(tx_desc_tid), - .s_axis_tdest(0), - .s_axis_tuser(tx_desc_tuser), - - // AXI output - .m_axis_tdata(tx_fifo_desc_tdata), - .m_axis_tkeep(tx_fifo_desc_tkeep), - .m_axis_tvalid(tx_fifo_desc_tvalid), - .m_axis_tready(tx_fifo_desc_tready), - .m_axis_tlast(tx_fifo_desc_tlast), - .m_axis_tid(tx_fifo_desc_tid), - .m_axis_tdest(), - .m_axis_tuser(tx_fifo_desc_tuser), - - // Status - .status_overflow(), - .status_bad_frame(), - .status_good_frame() -); - -tx_engine #( - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), - .REQ_TAG_WIDTH(REQ_TAG_WIDTH), - .DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH), - .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), - .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), - .QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH), - .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), - .CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH), - .DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH), - .MAX_TX_SIZE(MAX_TX_SIZE), - .TX_BUFFER_OFFSET(0), - .TX_BUFFER_SIZE(TX_RAM_SIZE), - .TX_BUFFER_STEP_SIZE(SEG_COUNT*SEG_BE_WIDTH), - .DESC_SIZE(DESC_SIZE), - .CPL_SIZE(CPL_SIZE), - .MAX_DESC_REQ(TX_MAX_DESC_REQ), - .AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH), - .AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH), - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE) -) -tx_engine_inst ( - .clk(clk), - .rst(rst), - - /* - * Transmit request input (queue index) - */ - .s_axis_tx_req_queue(tx_req_queue), - .s_axis_tx_req_tag(tx_req_tag), - .s_axis_tx_req_valid(tx_req_valid), - .s_axis_tx_req_ready(tx_req_ready), - - /* - * Transmit request status output - */ - .m_axis_tx_req_status_len(tx_req_status_len), - .m_axis_tx_req_status_tag(tx_req_status_tag), - .m_axis_tx_req_status_valid(tx_req_status_valid), - - /* - * Descriptor request output - */ - .m_axis_desc_req_queue(tx_desc_req_queue), - .m_axis_desc_req_tag(tx_desc_req_tag), - .m_axis_desc_req_valid(tx_desc_req_valid), - .m_axis_desc_req_ready(tx_desc_req_ready), - - /* - * Descriptor request status input - */ - .s_axis_desc_req_status_queue(tx_desc_req_status_queue), - .s_axis_desc_req_status_ptr(tx_desc_req_status_ptr), - .s_axis_desc_req_status_cpl(tx_desc_req_status_cpl), - .s_axis_desc_req_status_tag(tx_desc_req_status_tag), - .s_axis_desc_req_status_empty(tx_desc_req_status_empty), - .s_axis_desc_req_status_error(tx_desc_req_status_error), - .s_axis_desc_req_status_valid(tx_desc_req_status_valid), - - /* - * Descriptor data input - */ - .s_axis_desc_tdata(tx_fifo_desc_tdata), - .s_axis_desc_tkeep(tx_fifo_desc_tkeep), - .s_axis_desc_tvalid(tx_fifo_desc_tvalid), - .s_axis_desc_tready(tx_fifo_desc_tready), - .s_axis_desc_tlast(tx_fifo_desc_tlast), - .s_axis_desc_tid(tx_fifo_desc_tid), - .s_axis_desc_tuser(tx_fifo_desc_tuser), - - /* - * Completion request output - */ - .m_axis_cpl_req_queue(tx_cpl_req_queue), - .m_axis_cpl_req_tag(tx_cpl_req_tag), - .m_axis_cpl_req_data(tx_cpl_req_data), - .m_axis_cpl_req_valid(tx_cpl_req_valid), - .m_axis_cpl_req_ready(tx_cpl_req_ready), - - /* - * Completion request status input - */ - .s_axis_cpl_req_status_tag(tx_cpl_req_status_tag), - .s_axis_cpl_req_status_full(tx_cpl_req_status_full), - .s_axis_cpl_req_status_error(tx_cpl_req_status_error), - .s_axis_cpl_req_status_valid(tx_cpl_req_status_valid), - - /* - * DMA read descriptor output - */ - .m_axis_dma_read_desc_dma_addr(m_axis_dma_read_desc_dma_addr), - .m_axis_dma_read_desc_ram_addr(m_axis_dma_read_desc_ram_addr), - .m_axis_dma_read_desc_len(m_axis_dma_read_desc_len), - .m_axis_dma_read_desc_tag(m_axis_dma_read_desc_tag), - .m_axis_dma_read_desc_valid(m_axis_dma_read_desc_valid), - .m_axis_dma_read_desc_ready(m_axis_dma_read_desc_ready), - - /* - * DMA read descriptor status input - */ - .s_axis_dma_read_desc_status_tag(s_axis_dma_read_desc_status_tag), - .s_axis_dma_read_desc_status_error(s_axis_dma_read_desc_status_error), - .s_axis_dma_read_desc_status_valid(s_axis_dma_read_desc_status_valid), - - /* - * Transmit descriptor output - */ - .m_axis_tx_desc_addr(dma_tx_desc_addr), - .m_axis_tx_desc_len(dma_tx_desc_len), - .m_axis_tx_desc_tag(dma_tx_desc_tag), - .m_axis_tx_desc_user(dma_tx_desc_user), - .m_axis_tx_desc_valid(dma_tx_desc_valid), - .m_axis_tx_desc_ready(dma_tx_desc_ready), - - /* - * Transmit descriptor status input - */ - .s_axis_tx_desc_status_tag(dma_tx_desc_status_tag), - .s_axis_tx_desc_status_error(dma_tx_desc_status_error), - .s_axis_tx_desc_status_valid(dma_tx_desc_status_valid), - - /* - * Transmit checksum command output - */ - .m_axis_tx_csum_cmd_csum_enable(tx_csum_cmd_csum_enable), - .m_axis_tx_csum_cmd_csum_start(tx_csum_cmd_csum_start), - .m_axis_tx_csum_cmd_csum_offset(tx_csum_cmd_csum_offset), - .m_axis_tx_csum_cmd_valid(tx_csum_cmd_valid), - .m_axis_tx_csum_cmd_ready(tx_csum_cmd_ready), - - /* - * Transmit timestamp input - */ - .s_axis_tx_ptp_ts_96(s_axis_tx_ptp_ts_96), - .s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid), - .s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready), - - /* - * Configuration - */ - .enable(1'b1) -); - -axis_fifo #( - .DEPTH(RX_DESC_FIFO_SIZE*DESC_SIZE), - .DATA_WIDTH(AXIS_DESC_DATA_WIDTH), - .KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH), - .LAST_ENABLE(1), - .ID_ENABLE(1), - .ID_WIDTH(DESC_REQ_TAG_WIDTH_INT), - .DEST_ENABLE(0), - .USER_ENABLE(0), - .PIPELINE_OUTPUT(3), - .FRAME_FIFO(0) -) -rx_desc_fifo ( - .clk(clk), - .rst(rst), - - // AXI input - .s_axis_tdata(rx_desc_tdata), - .s_axis_tkeep(rx_desc_tkeep), - .s_axis_tvalid(rx_desc_tvalid), - .s_axis_tready(rx_desc_tready), - .s_axis_tlast(rx_desc_tlast), - .s_axis_tid(rx_desc_tid), - .s_axis_tdest(0), - .s_axis_tuser(rx_desc_tuser), - - // AXI output - .m_axis_tdata(rx_fifo_desc_tdata), - .m_axis_tkeep(rx_fifo_desc_tkeep), - .m_axis_tvalid(rx_fifo_desc_tvalid), - .m_axis_tready(rx_fifo_desc_tready), - .m_axis_tlast(rx_fifo_desc_tlast), - .m_axis_tid(rx_fifo_desc_tid), - .m_axis_tdest(), - .m_axis_tuser(rx_fifo_desc_tuser), - - // Status - .status_overflow(), - .status_bad_frame(), - .status_good_frame() -); - -rx_engine #( - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), - .DMA_LEN_WIDTH(DMA_LEN_WIDTH), - .DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), - .REQ_TAG_WIDTH(REQ_TAG_WIDTH), - .DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH_INT), - .DMA_TAG_WIDTH(DMA_TAG_WIDTH), - .DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH), - .QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH), - .QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH), - .QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH), - .QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH), - .CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), - .DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH), - .MAX_RX_SIZE(MAX_RX_SIZE), - .RX_BUFFER_OFFSET(0), - .RX_BUFFER_SIZE(RX_RAM_SIZE), - .RX_BUFFER_STEP_SIZE(SEG_COUNT*SEG_BE_WIDTH), - .DESC_SIZE(DESC_SIZE), - .CPL_SIZE(CPL_SIZE), - .MAX_DESC_REQ(RX_MAX_DESC_REQ), - .AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH), - .AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH), - .PTP_TS_ENABLE(PTP_TS_ENABLE), - .RX_HASH_ENABLE(RX_HASH_ENABLE), - .RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE) -) -rx_engine_inst ( - .clk(clk), - .rst(rst), - - /* - * Receive request input (queue index) - */ - .s_axis_rx_req_queue(rx_req_queue), - .s_axis_rx_req_tag(rx_req_tag), - .s_axis_rx_req_valid(rx_req_valid), - .s_axis_rx_req_ready(rx_req_ready), - - /* - * Receive request status output - */ - .m_axis_rx_req_status_tag(rx_req_status_tag), - .m_axis_rx_req_status_valid(rx_req_status_valid), - - /* - * Descriptor request output - */ - .m_axis_desc_req_queue(rx_desc_req_queue), - .m_axis_desc_req_tag(rx_desc_req_tag), - .m_axis_desc_req_valid(rx_desc_req_valid), - .m_axis_desc_req_ready(rx_desc_req_ready), - - /* - * Descriptor request status input - */ - .s_axis_desc_req_status_queue(rx_desc_req_status_queue), - .s_axis_desc_req_status_ptr(rx_desc_req_status_ptr), - .s_axis_desc_req_status_cpl(rx_desc_req_status_cpl), - .s_axis_desc_req_status_tag(rx_desc_req_status_tag), - .s_axis_desc_req_status_empty(rx_desc_req_status_empty), - .s_axis_desc_req_status_error(rx_desc_req_status_error), - .s_axis_desc_req_status_valid(rx_desc_req_status_valid), - - /* - * Descriptor data input - */ - .s_axis_desc_tdata(rx_fifo_desc_tdata), - .s_axis_desc_tkeep(rx_fifo_desc_tkeep), - .s_axis_desc_tvalid(rx_fifo_desc_tvalid), - .s_axis_desc_tready(rx_fifo_desc_tready), - .s_axis_desc_tlast(rx_fifo_desc_tlast), - .s_axis_desc_tid(rx_fifo_desc_tid), - .s_axis_desc_tuser(rx_fifo_desc_tuser), - - /* - * Completion request output - */ - .m_axis_cpl_req_queue(rx_cpl_req_queue), - .m_axis_cpl_req_tag(rx_cpl_req_tag), - .m_axis_cpl_req_data(rx_cpl_req_data), - .m_axis_cpl_req_valid(rx_cpl_req_valid), - .m_axis_cpl_req_ready(rx_cpl_req_ready), - - /* - * Completion request status input - */ - .s_axis_cpl_req_status_tag(rx_cpl_req_status_tag), - .s_axis_cpl_req_status_full(rx_cpl_req_status_full), - .s_axis_cpl_req_status_error(rx_cpl_req_status_error), - .s_axis_cpl_req_status_valid(rx_cpl_req_status_valid), - - /* - * DMA write descriptor output - */ - .m_axis_dma_write_desc_dma_addr(m_axis_dma_write_desc_dma_addr), - .m_axis_dma_write_desc_ram_addr(m_axis_dma_write_desc_ram_addr), - .m_axis_dma_write_desc_len(m_axis_dma_write_desc_len), - .m_axis_dma_write_desc_tag(m_axis_dma_write_desc_tag), - .m_axis_dma_write_desc_valid(m_axis_dma_write_desc_valid), - .m_axis_dma_write_desc_ready(m_axis_dma_write_desc_ready), - - /* - * DMA write descriptor status input - */ - .s_axis_dma_write_desc_status_tag(s_axis_dma_write_desc_status_tag), - .s_axis_dma_write_desc_status_error(s_axis_dma_write_desc_status_error), - .s_axis_dma_write_desc_status_valid(s_axis_dma_write_desc_status_valid), - - /* - * Receive descriptor output - */ - .m_axis_rx_desc_addr(dma_rx_desc_addr), - .m_axis_rx_desc_len(dma_rx_desc_len), - .m_axis_rx_desc_tag(dma_rx_desc_tag), - .m_axis_rx_desc_valid(dma_rx_desc_valid), - .m_axis_rx_desc_ready(dma_rx_desc_ready), - - /* - * Receive descriptor status input - */ - .s_axis_rx_desc_status_len(dma_rx_desc_status_len), - .s_axis_rx_desc_status_tag(dma_rx_desc_status_tag), - .s_axis_rx_desc_status_user(dma_rx_desc_status_user), - .s_axis_rx_desc_status_error(dma_rx_desc_status_error), - .s_axis_rx_desc_status_valid(dma_rx_desc_status_valid), - - /* - * Receive timestamp input - */ - .s_axis_rx_ptp_ts_96(s_axis_rx_ptp_ts_96), - .s_axis_rx_ptp_ts_valid(s_axis_rx_ptp_ts_valid), - .s_axis_rx_ptp_ts_ready(s_axis_rx_ptp_ts_ready), - - /* - * Receive hash input - */ - .s_axis_rx_hash(rx_fifo_hash), - .s_axis_rx_hash_type(rx_fifo_hash_type), - .s_axis_rx_hash_valid(rx_fifo_hash_valid), - .s_axis_rx_hash_ready(rx_fifo_hash_ready), - - /* - * Receive checksum input - */ - .s_axis_rx_csum(rx_fifo_csum), - .s_axis_rx_csum_valid(rx_fifo_csum_valid), - .s_axis_rx_csum_ready(rx_fifo_csum_ready), - - /* - * Configuration - */ - .mtu(rx_mtu), - .enable(1'b1) -); - -generate - -if (RX_HASH_ENABLE) begin - - rx_hash #( - .DATA_WIDTH(AXIS_DATA_WIDTH) - ) - rx_hash_inst ( - .clk(clk), - .rst(rst), - .s_axis_tdata(rx_axis_tdata), - .s_axis_tkeep(rx_axis_tkeep), - .s_axis_tvalid(rx_axis_tvalid & rx_axis_tready), - .s_axis_tlast(rx_axis_tlast), - .hash_key(320'h6d5a56da255b0ec24167253d43a38fb0d0ca2bcbae7b30b477cb2da38030f20c6a42b73bbeac01fa), - .m_axis_hash(rx_hash), - .m_axis_hash_type(rx_hash_type), - .m_axis_hash_valid(rx_hash_valid) - ); - - axis_fifo #( - .DEPTH(32), - .DATA_WIDTH(32+4), - .KEEP_ENABLE(0), - .LAST_ENABLE(0), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(0), - .FRAME_FIFO(0) - ) - rx_hash_fifo ( - .clk(clk), - .rst(rst), - - // AXI input - .s_axis_tdata({rx_hash_type, rx_hash}), - .s_axis_tkeep(0), - .s_axis_tvalid(rx_hash_valid), - .s_axis_tready(), - .s_axis_tlast(0), - .s_axis_tid(0), - .s_axis_tdest(0), - .s_axis_tuser(0), - - // AXI output - .m_axis_tdata({rx_fifo_hash_type, rx_fifo_hash}), - .m_axis_tkeep(), - .m_axis_tvalid(rx_fifo_hash_valid), - .m_axis_tready(rx_fifo_hash_ready), - .m_axis_tlast(), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(), - - // Status - .status_overflow(), - .status_bad_frame(), - .status_good_frame() - ); - -end else begin - - assign rx_fifo_hash = 32'd0; - assign rx_fifo_hash_type = 4'd0; - assign rx_fifo_hash_valid = 1'b0; - -end - -if (RX_RSS_ENABLE && RX_HASH_ENABLE) begin - - axis_fifo #( - .DEPTH(AXIS_KEEP_WIDTH*32), - .DATA_WIDTH(AXIS_DATA_WIDTH), - .KEEP_ENABLE(AXIS_KEEP_WIDTH > 1), - .KEEP_WIDTH(AXIS_KEEP_WIDTH), - .LAST_ENABLE(1), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(1), - .USER_WIDTH(1), - .FRAME_FIFO(0) - ) - rx_hash_data_fifo ( - .clk(clk), - .rst(rst), - - // AXI input - .s_axis_tdata(rx_axis_tdata), - .s_axis_tkeep(rx_axis_tkeep), - .s_axis_tvalid(rx_axis_tvalid), - .s_axis_tready(rx_axis_tready), - .s_axis_tlast(rx_axis_tlast), - .s_axis_tid(0), - .s_axis_tdest(0), - .s_axis_tuser(rx_axis_tuser), - - // AXI output - .m_axis_tdata(rx_axis_tdata_int), - .m_axis_tkeep(rx_axis_tkeep_int), - .m_axis_tvalid(rx_axis_tvalid_int), - .m_axis_tready(rx_axis_tready_int), - .m_axis_tlast(rx_axis_tlast_int), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(rx_axis_tuser_int), - - // Status - .status_overflow(), - .status_bad_frame(), - .status_good_frame() - ); - - // Generate RX requests (RSS) - assign rx_req_tag = 0; - - axis_fifo #( - .DEPTH(32), - .DATA_WIDTH(RX_QUEUE_INDEX_WIDTH), - .KEEP_ENABLE(0), - .LAST_ENABLE(0), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(0), - .FRAME_FIFO(0) - ) - rx_req_fifo ( - .clk(clk), - .rst(rst), - - // AXI input - .s_axis_tdata(rx_hash & rss_mask), - .s_axis_tkeep(0), - .s_axis_tvalid(rx_hash_valid), - .s_axis_tready(), - .s_axis_tlast(0), - .s_axis_tid(0), - .s_axis_tdest(0), - .s_axis_tuser(0), - - // AXI output - .m_axis_tdata(rx_req_queue), - .m_axis_tkeep(), - .m_axis_tvalid(rx_req_valid), - .m_axis_tready(rx_req_ready), - .m_axis_tlast(), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(), - - // Status - .status_overflow(), - .status_bad_frame(), - .status_good_frame() - ); - -end else begin - - assign rx_axis_tdata_int = rx_axis_tdata; - assign rx_axis_tkeep_int = rx_axis_tkeep; - assign rx_axis_tvalid_int = rx_axis_tvalid; - assign rx_axis_tready = rx_axis_tready_int; - assign rx_axis_tlast_int = rx_axis_tlast; - assign rx_axis_tuser_int = rx_axis_tuser; - - // Generate RX requests (no RSS) - reg rx_frame_reg = 1'b0; - reg rx_req_valid_reg = 1'b0; - - assign rx_req_queue = 0; - assign rx_req_tag = 0; - assign rx_req_valid = rx_axis_tvalid_int && !rx_frame_reg; - - always @(posedge clk) begin - if (rx_req_ready) begin - rx_req_valid_reg <= 1'b0; - end - - if (rx_axis_tready_int && rx_axis_tvalid_int) begin - if (!rx_frame_reg) begin - rx_req_valid_reg <= 1'b1; - end - rx_frame_reg <= !rx_axis_tlast_int; - end - - if (rst) begin - rx_frame_reg <= 1'b0; - rx_req_valid_reg <= 1'b0; - end - end - -end - -if (RX_CHECKSUM_ENABLE) begin - - rx_checksum #( - .DATA_WIDTH(AXIS_DATA_WIDTH) - ) - rx_checksum_inst ( - .clk(clk), - .rst(rst), - .s_axis_tdata(rx_axis_tdata_int), - .s_axis_tkeep(rx_axis_tkeep_int), - .s_axis_tvalid(rx_axis_tvalid_int & rx_axis_tready_int), - .s_axis_tlast(rx_axis_tlast_int), - .m_axis_csum(rx_csum), - .m_axis_csum_valid(rx_csum_valid) - ); - - axis_fifo #( - .DEPTH(32), - .DATA_WIDTH(16), - .KEEP_ENABLE(0), - .LAST_ENABLE(0), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(0), - .FRAME_FIFO(0) - ) - rx_csum_fifo ( - .clk(clk), - .rst(rst), - - // AXI input - .s_axis_tdata(rx_csum), - .s_axis_tkeep(0), - .s_axis_tvalid(rx_csum_valid), - .s_axis_tready(), - .s_axis_tlast(0), - .s_axis_tid(0), - .s_axis_tdest(0), - .s_axis_tuser(0), - - // AXI output - .m_axis_tdata(rx_fifo_csum), - .m_axis_tkeep(), - .m_axis_tvalid(rx_fifo_csum_valid), - .m_axis_tready(rx_fifo_csum_ready), - .m_axis_tlast(), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(), - - // Status - .status_overflow(), - .status_bad_frame(), - .status_good_frame() - ); - -end else begin - - assign rx_fifo_csum = 16'd0; - assign rx_fifo_csum_valid = 1'b0; - -end - -if (TX_CHECKSUM_ENABLE) begin - - axis_fifo #( - .DEPTH(32), - .DATA_WIDTH(1+8+8), - .KEEP_ENABLE(0), - .LAST_ENABLE(0), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(0), - .FRAME_FIFO(0) - ) - tx_csum_fifo ( - .clk(clk), - .rst(rst), - - // AXI input - .s_axis_tdata({tx_csum_cmd_csum_enable, tx_csum_cmd_csum_start, tx_csum_cmd_csum_offset}), - .s_axis_tkeep(0), - .s_axis_tvalid(tx_csum_cmd_valid), - .s_axis_tready(tx_csum_cmd_ready), - .s_axis_tlast(0), - .s_axis_tid(0), - .s_axis_tdest(0), - .s_axis_tuser(0), - - // AXI output - .m_axis_tdata({tx_fifo_csum_cmd_csum_enable, tx_fifo_csum_cmd_csum_start, tx_fifo_csum_cmd_csum_offset}), - .m_axis_tkeep(), - .m_axis_tvalid(tx_fifo_csum_cmd_valid), - .m_axis_tready(tx_fifo_csum_cmd_ready), - .m_axis_tlast(), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(), - - // Status - .status_overflow(), - .status_bad_frame(), - .status_good_frame() - ); - - tx_checksum #( - .DATA_WIDTH(AXIS_DATA_WIDTH), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(1), - .USER_WIDTH(1), - .USE_INIT_VALUE(0), - .DATA_FIFO_DEPTH(MAX_TX_SIZE), - .CHECKSUM_FIFO_DEPTH(64) - ) - tx_checksum_inst ( - .clk(clk), - .rst(rst), - - /* - * AXI input - */ - .s_axis_tdata(tx_axis_tdata_int), - .s_axis_tkeep(tx_axis_tkeep_int), - .s_axis_tvalid(tx_axis_tvalid_int), - .s_axis_tready(tx_axis_tready_int), - .s_axis_tlast(tx_axis_tlast_int), - .s_axis_tid(0), - .s_axis_tdest(0), - .s_axis_tuser(tx_axis_tuser_int), - - /* - * AXI output - */ - .m_axis_tdata(tx_axis_tdata), - .m_axis_tkeep(tx_axis_tkeep), - .m_axis_tvalid(tx_axis_tvalid), - .m_axis_tready(tx_axis_tready), - .m_axis_tlast(tx_axis_tlast), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(tx_axis_tuser), - - /* - * Control - */ - .s_axis_cmd_csum_enable(tx_fifo_csum_cmd_csum_enable), - .s_axis_cmd_csum_start(tx_fifo_csum_cmd_csum_start), - .s_axis_cmd_csum_offset(tx_fifo_csum_cmd_csum_offset), - .s_axis_cmd_csum_init(16'd0), - .s_axis_cmd_valid(tx_fifo_csum_cmd_valid), - .s_axis_cmd_ready(tx_fifo_csum_cmd_ready) - ); - -end else begin - - assign tx_axis_tdata = tx_axis_tdata_int; - assign tx_axis_tkeep = tx_axis_tkeep_int; - assign tx_axis_tvalid = tx_axis_tvalid_int; - assign tx_axis_tready_int = tx_axis_tready; - assign tx_axis_tlast = tx_axis_tlast_int; - assign tx_axis_tuser = tx_axis_tuser_int; - - assign tx_csum_cmd_ready = 1'b1; - -end - -endgenerate - -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr_int; -wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid_int; -wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready_int; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data_int; -wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid_int; -wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready_int; - -dma_psdpram #( - .SIZE(TX_RAM_SIZE), - .SEG_COUNT(SEG_COUNT), - .SEG_DATA_WIDTH(SEG_DATA_WIDTH), - .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), - .SEG_BE_WIDTH(SEG_BE_WIDTH), - .PIPELINE(RAM_PIPELINE) -) -dma_psdpram_tx_inst ( - .clk(clk), - .rst(rst), - - /* - * Write port - */ - .wr_cmd_be(dma_ram_wr_cmd_be), - .wr_cmd_addr(dma_ram_wr_cmd_addr), - .wr_cmd_data(dma_ram_wr_cmd_data), - .wr_cmd_valid(dma_ram_wr_cmd_valid), - .wr_cmd_ready(dma_ram_wr_cmd_ready), - .wr_done(dma_ram_wr_done), - - /* - * Read port - */ - .rd_cmd_addr(dma_ram_rd_cmd_addr_int), - .rd_cmd_valid(dma_ram_rd_cmd_valid_int), - .rd_cmd_ready(dma_ram_rd_cmd_ready_int), - .rd_resp_data(dma_ram_rd_resp_data_int), - .rd_resp_valid(dma_ram_rd_resp_valid_int), - .rd_resp_ready(dma_ram_rd_resp_ready_int) -); - -dma_client_axis_source #( - .SEG_COUNT(SEG_COUNT), - .SEG_DATA_WIDTH(SEG_DATA_WIDTH), - .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), - .SEG_BE_WIDTH(SEG_BE_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), - .AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1), - .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), - .AXIS_LAST_ENABLE(1), - .AXIS_ID_ENABLE(0), - .AXIS_DEST_ENABLE(0), - .AXIS_USER_ENABLE(1), - .AXIS_USER_WIDTH(1), - .LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), - .TAG_WIDTH(DMA_CLIENT_TAG_WIDTH) -) -dma_client_axis_source_inst ( - .clk(clk), - .rst(rst), - - /* - * DMA read descriptor input - */ - .s_axis_read_desc_ram_addr(dma_tx_desc_addr), - .s_axis_read_desc_len(dma_tx_desc_len), - .s_axis_read_desc_tag(dma_tx_desc_tag), - .s_axis_read_desc_id(0), - .s_axis_read_desc_dest(0), - .s_axis_read_desc_user(dma_tx_desc_user), - .s_axis_read_desc_valid(dma_tx_desc_valid), - .s_axis_read_desc_ready(dma_tx_desc_ready), - - /* - * DMA read descriptor status output - */ - .m_axis_read_desc_status_tag(dma_tx_desc_status_tag), - .m_axis_read_desc_status_error(dma_tx_desc_status_error), - .m_axis_read_desc_status_valid(dma_tx_desc_status_valid), - - /* - * AXI stream read data output - */ - .m_axis_read_data_tdata(tx_axis_tdata_int), - .m_axis_read_data_tkeep(tx_axis_tkeep_int), - .m_axis_read_data_tvalid(tx_axis_tvalid_int), - .m_axis_read_data_tready(tx_axis_tready_int), - .m_axis_read_data_tlast(tx_axis_tlast_int), - .m_axis_read_data_tid(), - .m_axis_read_data_tdest(), - .m_axis_read_data_tuser(tx_axis_tuser_int), - - /* - * RAM interface - */ - .ram_rd_cmd_addr(dma_ram_rd_cmd_addr_int), - .ram_rd_cmd_valid(dma_ram_rd_cmd_valid_int), - .ram_rd_cmd_ready(dma_ram_rd_cmd_ready_int), - .ram_rd_resp_data(dma_ram_rd_resp_data_int), - .ram_rd_resp_valid(dma_ram_rd_resp_valid_int), - .ram_rd_resp_ready(dma_ram_rd_resp_ready_int), - - /* - * Configuration - */ - .enable(1'b1) -); - -wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be_int; -wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr_int; -wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data_int; -wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid_int; -wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready_int; -wire [SEG_COUNT-1:0] dma_ram_wr_done_int; - -dma_psdpram #( - .SIZE(RX_RAM_SIZE), - .SEG_COUNT(SEG_COUNT), - .SEG_DATA_WIDTH(SEG_DATA_WIDTH), - .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), - .SEG_BE_WIDTH(SEG_BE_WIDTH), - .PIPELINE(RAM_PIPELINE) -) -dma_psdpram_rx_inst ( - .clk(clk), - .rst(rst), - - /* - * Write port - */ - .wr_cmd_be(dma_ram_wr_cmd_be_int), - .wr_cmd_addr(dma_ram_wr_cmd_addr_int), - .wr_cmd_data(dma_ram_wr_cmd_data_int), - .wr_cmd_valid(dma_ram_wr_cmd_valid_int), - .wr_cmd_ready(dma_ram_wr_cmd_ready_int), - .wr_done(dma_ram_wr_done_int), - - /* - * Read port - */ - .rd_cmd_addr(dma_ram_rd_cmd_addr), - .rd_cmd_valid(dma_ram_rd_cmd_valid), - .rd_cmd_ready(dma_ram_rd_cmd_ready), - .rd_resp_data(dma_ram_rd_resp_data), - .rd_resp_valid(dma_ram_rd_resp_valid), - .rd_resp_ready(dma_ram_rd_resp_ready) -); - -dma_client_axis_sink #( - .SEG_COUNT(SEG_COUNT), - .SEG_DATA_WIDTH(SEG_DATA_WIDTH), - .SEG_ADDR_WIDTH(SEG_ADDR_WIDTH), - .SEG_BE_WIDTH(SEG_BE_WIDTH), - .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), - .AXIS_DATA_WIDTH(AXIS_DATA_WIDTH), - .AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1), - .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), - .AXIS_LAST_ENABLE(1), - .AXIS_ID_ENABLE(0), - .AXIS_DEST_ENABLE(0), - .AXIS_USER_ENABLE(1), - .AXIS_USER_WIDTH(1), - .LEN_WIDTH(DMA_CLIENT_LEN_WIDTH), - .TAG_WIDTH(DMA_CLIENT_TAG_WIDTH) -) -dma_client_axis_sink_inst ( - .clk(clk), - .rst(rst), - - /* - * DMA write descriptor input - */ - .s_axis_write_desc_ram_addr(dma_rx_desc_addr), - .s_axis_write_desc_len(dma_rx_desc_len), - .s_axis_write_desc_tag(dma_rx_desc_tag), - .s_axis_write_desc_valid(dma_rx_desc_valid), - .s_axis_write_desc_ready(dma_rx_desc_ready), - - /* - * DMA write descriptor status output - */ - .m_axis_write_desc_status_len(dma_rx_desc_status_len), - .m_axis_write_desc_status_tag(dma_rx_desc_status_tag), - .m_axis_write_desc_status_id(), - .m_axis_write_desc_status_dest(), - .m_axis_write_desc_status_user(dma_rx_desc_status_user), - .m_axis_write_desc_status_error(dma_rx_desc_status_error), - .m_axis_write_desc_status_valid(dma_rx_desc_status_valid), - - /* - * AXI stream write data input - */ - .s_axis_write_data_tdata(rx_axis_tdata_int), - .s_axis_write_data_tkeep(rx_axis_tkeep_int), - .s_axis_write_data_tvalid(rx_axis_tvalid_int), - .s_axis_write_data_tready(rx_axis_tready_int), - .s_axis_write_data_tlast(rx_axis_tlast_int), - .s_axis_write_data_tid(0), - .s_axis_write_data_tdest(0), - .s_axis_write_data_tuser(rx_axis_tuser_int), - - /* - * RAM interface - */ - .ram_wr_cmd_be(dma_ram_wr_cmd_be_int), - .ram_wr_cmd_addr(dma_ram_wr_cmd_addr_int), - .ram_wr_cmd_data(dma_ram_wr_cmd_data_int), - .ram_wr_cmd_valid(dma_ram_wr_cmd_valid_int), - .ram_wr_cmd_ready(dma_ram_wr_cmd_ready_int), - .ram_wr_done(dma_ram_wr_done_int), - - /* - * Configuration - */ - .enable(1'b1), - .abort(1'b0) -); - -endmodule - -`resetall diff --git a/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v b/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v index 67fcd1b22..1aab562cf 100644 --- a/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v +++ b/fpga/common/rtl/mqnic_tx_scheduler_block_rr.v @@ -42,6 +42,10 @@ either expressed or implied, of The Regents of the University of California. */ module mqnic_tx_scheduler_block # ( + // Number of ports + parameter PORTS = 1, + // Scheduler index + parameter INDEX = 0, // Width of control register interface address in bits parameter REG_ADDR_WIDTH = 16, // Width of control register interface data in bits @@ -74,6 +78,8 @@ module mqnic_tx_scheduler_block # parameter TDMA_INDEX_WIDTH = 8, // PTP timestamp width parameter PTP_TS_WIDTH = 96, + // AXI stream tdest signal width + parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4, // Max transmit packet size parameter MAX_TX_SIZE = 2048 ) @@ -124,6 +130,7 @@ module mqnic_tx_scheduler_block # */ output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_req_queue, output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_tag, + output wire [AXIS_TX_DEST_WIDTH-1:0] m_axis_tx_req_dest, output wire m_axis_tx_req_valid, input wire m_axis_tx_req_ready, @@ -144,7 +151,12 @@ module mqnic_tx_scheduler_block # * PTP clock */ input wire [PTP_TS_WIDTH-1:0] ptp_ts_96, - input wire ptp_ts_step + input wire ptp_ts_step, + + /* + * Configuration + */ + input wire [LEN_WIDTH-1:0] mtu ); parameter SCHED_COUNT = 1; @@ -218,6 +230,8 @@ always @(posedge clk) begin end end +assign m_axis_tx_req_dest = INDEX << 4; + tx_scheduler_rr #( .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), .AXIL_ADDR_WIDTH(AXIL_SCHED_ADDR_WIDTH), diff --git a/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v b/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v index 0e693bc58..101594efb 100644 --- a/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v +++ b/fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v @@ -42,6 +42,10 @@ either expressed or implied, of The Regents of the University of California. */ module mqnic_tx_scheduler_block # ( + // Number of ports + parameter PORTS = 1, + // Scheduler index + parameter INDEX = 0, // Width of control register interface address in bits parameter REG_ADDR_WIDTH = 16, // Width of control register interface data in bits @@ -74,6 +78,8 @@ module mqnic_tx_scheduler_block # parameter TDMA_INDEX_WIDTH = 8, // PTP timestamp width parameter PTP_TS_WIDTH = 96, + // AXI stream tdest signal width + parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4, // Max transmit packet size parameter MAX_TX_SIZE = 2048 ) @@ -124,6 +130,7 @@ module mqnic_tx_scheduler_block # */ output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_req_queue, output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_tag, + output wire [AXIS_TX_DEST_WIDTH-1:0] m_axis_tx_req_dest, output wire m_axis_tx_req_valid, input wire m_axis_tx_req_ready, @@ -144,7 +151,12 @@ module mqnic_tx_scheduler_block # * PTP clock */ input wire [PTP_TS_WIDTH-1:0] ptp_ts_96, - input wire ptp_ts_step + input wire ptp_ts_step, + + /* + * Configuration + */ + input wire [LEN_WIDTH-1:0] mtu ); parameter SCHED_COUNT = 2; @@ -411,6 +423,8 @@ axil_crossbar_inst ( .m_axil_rready(axil_sched_rready) ); +assign m_axis_tx_req_dest = INDEX << 4; + tx_scheduler_rr #( .AXIL_DATA_WIDTH(AXIL_DATA_WIDTH), .AXIL_ADDR_WIDTH(AXIL_SCHED_ADDR_WIDTH), diff --git a/fpga/common/rtl/rx_engine.v b/fpga/common/rtl/rx_engine.v index 052bd2a8f..59610f502 100644 --- a/fpga/common/rtl/rx_engine.v +++ b/fpga/common/rtl/rx_engine.v @@ -42,6 +42,8 @@ either expressed or implied, of The Regents of the University of California. */ module rx_engine # ( + // Number of ports + parameter PORTS = 1, // DMA RAM address width parameter RAM_ADDR_WIDTH = 16, // DMA address width @@ -92,10 +94,18 @@ module rx_engine # parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8, // Enable PTP timestamping parameter PTP_TS_ENABLE = 1, + // PTP timestamp width + parameter PTP_TS_WIDTH = 96, // Enable RX hashing parameter RX_HASH_ENABLE = 1, // Enable RX checksum offload - parameter RX_CHECKSUM_ENABLE = 1 + parameter RX_CHECKSUM_ENABLE = 1, + // AXI stream tid signal width + parameter AXIS_RX_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1, + // AXI stream tdest signal width + parameter AXIS_RX_DEST_WIDTH = QUEUE_INDEX_WIDTH, + // AXI stream tuser signal width + parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1 ) ( input wire clk, @@ -194,17 +204,12 @@ module rx_engine # */ input wire [DMA_CLIENT_LEN_WIDTH-1:0] s_axis_rx_desc_status_len, input wire [DMA_CLIENT_TAG_WIDTH-1:0] s_axis_rx_desc_status_tag, - input wire s_axis_rx_desc_status_user, + input wire [AXIS_RX_ID_WIDTH-1:0] s_axis_rx_desc_status_id, + input wire [AXIS_RX_DEST_WIDTH-1:0] s_axis_rx_desc_status_dest, + input wire [AXIS_RX_USER_WIDTH-1:0] s_axis_rx_desc_status_user, input wire [3:0] s_axis_rx_desc_status_error, input wire s_axis_rx_desc_status_valid, - /* - * Receive timestamp input - */ - input wire [95:0] s_axis_rx_ptp_ts_96, - input wire s_axis_rx_ptp_ts_valid, - output wire s_axis_rx_ptp_ts_ready, - /* * Receive hash input */ @@ -289,8 +294,6 @@ reg [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_rx_desc_len_reg = {DMA_CLIENT_LEN_WIDTH{1' reg [DMA_CLIENT_TAG_WIDTH-1:0] m_axis_rx_desc_tag_reg = {DMA_CLIENT_TAG_WIDTH{1'b0}}, m_axis_rx_desc_tag_next; reg m_axis_rx_desc_valid_reg = 1'b0, m_axis_rx_desc_valid_next; -reg s_axis_rx_ptp_ts_ready_reg = 1'b0, s_axis_rx_ptp_ts_ready_next; - reg s_axis_rx_hash_ready_reg = 1'b0, s_axis_rx_hash_ready_next; reg s_axis_rx_csum_ready_reg = 1'b0, s_axis_rx_csum_ready_next; @@ -328,9 +331,11 @@ reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_dma_len[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_desc_len[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) +reg [AXIS_RX_ID_WIDTH-1:0] desc_table_id[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CL_RX_BUFFER_SIZE+1-1:0] desc_table_buf_ptr[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) -reg [95:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0]; +reg [PTP_TS_WIDTH-1:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [31:0] desc_table_hash[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) @@ -351,6 +356,8 @@ reg [CL_RX_BUFFER_SIZE+1-1:0] desc_table_start_buf_ptr; reg desc_table_start_en; reg [CL_DESC_TABLE_SIZE-1:0] desc_table_rx_finish_ptr; reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_rx_finish_len; +reg [AXIS_RX_ID_WIDTH-1:0] desc_table_rx_finish_id; +reg [PTP_TS_WIDTH-1:0] desc_table_rx_finish_ptp_ts; reg desc_table_rx_finish_en; reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_dequeue_start_ptr_reg = 0; reg desc_table_dequeue_start_en; @@ -364,9 +371,6 @@ reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_desc_fetched_len; reg desc_table_desc_fetched_en; reg [CL_DESC_TABLE_SIZE-1:0] desc_table_data_written_ptr; reg desc_table_data_written_en; -reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_store_ptp_ts_ptr_reg = 0; -reg [95:0] desc_table_store_ptp_ts; -reg desc_table_store_ptp_ts_en; reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_store_hash_ptr_reg = 0; reg [31:0] desc_table_store_hash; reg [3:0] desc_table_store_hash_type; @@ -415,8 +419,6 @@ assign m_axis_rx_desc_len = m_axis_rx_desc_len_reg; assign m_axis_rx_desc_tag = m_axis_rx_desc_tag_reg; assign m_axis_rx_desc_valid = m_axis_rx_desc_valid_reg; -assign s_axis_rx_ptp_ts_ready = s_axis_rx_ptp_ts_ready_reg; - assign s_axis_rx_hash_ready = s_axis_rx_hash_ready_reg; assign s_axis_rx_csum_ready = s_axis_rx_csum_ready_reg; @@ -466,6 +468,7 @@ initial begin desc_table_cpl_queue[i] = 0; desc_table_dma_len[i] = 0; desc_table_desc_len[i] = 0; + desc_table_id[i] = 0; desc_table_buf_ptr[i] = 0; desc_table_ptp_ts[i] = 0; desc_table_hash[i] = 0; @@ -506,8 +509,6 @@ always @* begin m_axis_rx_desc_tag_next = m_axis_rx_desc_tag_reg; m_axis_rx_desc_valid_next = m_axis_rx_desc_valid_reg && !m_axis_rx_desc_ready; - s_axis_rx_ptp_ts_ready_next = 1'b0; - s_axis_rx_hash_ready_next = 1'b0; s_axis_rx_csum_ready_next = 1'b0; @@ -529,6 +530,8 @@ always @* begin desc_table_start_en = 1'b0; desc_table_rx_finish_ptr = s_axis_rx_desc_status_tag; desc_table_rx_finish_len = s_axis_rx_desc_status_len; + desc_table_rx_finish_id = s_axis_rx_desc_status_id; + desc_table_rx_finish_ptp_ts = s_axis_rx_desc_status_user >> 1; desc_table_rx_finish_en = 1'b0; desc_table_dequeue_start_en = 1'b0; desc_table_dequeue_ptr = s_axis_desc_req_status_tag; @@ -541,8 +544,6 @@ always @* begin desc_table_desc_fetched_en = 1'b0; desc_table_data_written_ptr = s_axis_dma_write_desc_status_tag & DESC_PTR_MASK; desc_table_data_written_en = 1'b0; - desc_table_store_ptp_ts = s_axis_rx_ptp_ts_96; - desc_table_store_ptp_ts_en = 1'b0; desc_table_store_hash = s_axis_rx_hash; desc_table_store_hash_type = s_axis_rx_hash_type; desc_table_store_hash_en = 1'b0; @@ -591,6 +592,9 @@ always @* begin // update entry in descriptor table desc_table_rx_finish_ptr = s_axis_rx_desc_status_tag; desc_table_rx_finish_len = s_axis_rx_desc_status_len; + desc_table_rx_finish_id = s_axis_rx_desc_status_id; + // desc_table_rx_finish_queue = s_axis_rx_desc_status_dest; + desc_table_rx_finish_ptp_ts = s_axis_rx_desc_status_user >> 1; desc_table_rx_finish_en = 1'b1; end @@ -699,23 +703,6 @@ always @* begin desc_table_write_finish_en = 1'b1; end - // store PTP timestamp - if (desc_table_active[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK] && desc_table_store_ptp_ts_ptr_reg != desc_table_start_ptr_reg && PTP_TS_ENABLE) begin - s_axis_rx_ptp_ts_ready_next = 1'b1; - if (desc_table_invalid[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK]) begin - // invalid entry; skip - desc_table_store_ptp_ts_en = 1'b1; - - s_axis_rx_ptp_ts_ready_next = 1'b0; - end else if (s_axis_rx_ptp_ts_ready && s_axis_rx_ptp_ts_valid) begin - // update entry in descriptor table - desc_table_store_ptp_ts = s_axis_rx_ptp_ts_96; - desc_table_store_ptp_ts_en = 1'b1; - - s_axis_rx_ptp_ts_ready_next = 1'b0; - end - end - // store RX hash if (desc_table_active[desc_table_store_hash_ptr_reg & DESC_PTR_MASK] && desc_table_store_hash_ptr_reg != desc_table_start_ptr_reg && RX_HASH_ENABLE) begin s_axis_rx_hash_ready_next = 1'b1; @@ -755,7 +742,6 @@ always @* begin if (desc_table_active[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && desc_table_cpl_enqueue_start_ptr_reg != desc_table_start_ptr_reg && desc_table_cpl_enqueue_start_ptr_reg != desc_table_dequeue_start_ptr_reg && - (desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_ptp_ts_ptr_reg || !PTP_TS_ENABLE) && (desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_hash_ptr_reg || !RX_HASH_ENABLE) && (desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_csum_ptr_reg || !RX_CHECKSUM_ENABLE)) begin if (desc_table_invalid[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK]) begin @@ -798,6 +784,7 @@ always @* begin if (RX_CHECKSUM_ENABLE) begin m_axis_cpl_req_data_next[127:112] = desc_table_csum[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK]; end + m_axis_cpl_req_data_next[176:168] = desc_table_id[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK]; m_axis_cpl_req_valid_next = 1'b1; end end @@ -861,8 +848,6 @@ always @(posedge clk) begin m_axis_rx_desc_tag_reg <= m_axis_rx_desc_tag_next; m_axis_rx_desc_valid_reg <= m_axis_rx_desc_valid_next; - s_axis_rx_ptp_ts_ready_reg <= s_axis_rx_ptp_ts_ready_next; - s_axis_rx_hash_ready_reg <= s_axis_rx_hash_ready_next; s_axis_rx_csum_ready_reg <= s_axis_rx_csum_ready_next; @@ -894,6 +879,8 @@ always @(posedge clk) begin if (desc_table_rx_finish_en) begin desc_table_dma_len[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_len; + desc_table_id[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_id; + desc_table_ptp_ts[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_ptp_ts; desc_table_rx_done[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= 1'b1; end @@ -918,11 +905,6 @@ always @(posedge clk) begin desc_table_data_written[desc_table_data_written_ptr & DESC_PTR_MASK] <= 1'b1; end - if (desc_table_store_ptp_ts_en) begin - desc_table_ptp_ts[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK] <= desc_table_store_ptp_ts; - desc_table_store_ptp_ts_ptr_reg <= desc_table_store_ptp_ts_ptr_reg + 1; - end - if (desc_table_store_hash_en) begin desc_table_hash[desc_table_store_hash_ptr_reg & DESC_PTR_MASK] <= desc_table_store_hash; desc_table_hash_type[desc_table_store_hash_ptr_reg & DESC_PTR_MASK] <= desc_table_store_hash_type; @@ -973,7 +955,6 @@ always @(posedge clk) begin m_axis_cpl_req_valid_reg <= 1'b0; m_axis_dma_write_desc_valid_reg <= 1'b0; m_axis_rx_desc_valid_reg <= 1'b0; - s_axis_rx_ptp_ts_ready_reg <= 1'b0; s_axis_rx_hash_ready_reg <= 1'b0; s_axis_rx_csum_ready_reg <= 1'b0; @@ -994,7 +975,6 @@ always @(posedge clk) begin desc_table_start_ptr_reg <= 0; desc_table_dequeue_start_ptr_reg <= 0; - desc_table_store_ptp_ts_ptr_reg <= 0; desc_table_store_hash_ptr_reg <= 0; desc_table_store_csum_ptr_reg <= 0; desc_table_cpl_enqueue_start_ptr_reg <= 0; diff --git a/fpga/common/rtl/rx_fifo.v b/fpga/common/rtl/rx_fifo.v new file mode 100644 index 000000000..24b0fe402 --- /dev/null +++ b/fpga/common/rtl/rx_fifo.v @@ -0,0 +1,244 @@ +/* + +Copyright 2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * RX FIFO + */ +module rx_fifo # +( + // FIFO depth in words (each FIFO) + // KEEP_WIDTH words per cycle if KEEP_ENABLE set + // Rounded up to nearest power of 2 cycles + parameter FIFO_DEPTH = 4096, + // Number of AXI stream inputs + parameter PORTS = 4, + // Width of input AXI stream interfaces in bits + parameter S_DATA_WIDTH = 8, + // Propagate tkeep signal + parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8), + // tkeep signal width (words per cycle) + parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8), + // Width of output AXI stream interface in bits + parameter M_DATA_WIDTH = 8*PORTS, + // Propagate tkeep signal + parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8), + // tkeep signal width (words per cycle) + parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8), + // Propagate tid signal + parameter ID_ENABLE = 1, + // input tid signal width + parameter S_ID_WIDTH = 1, + // output tid signal width + parameter M_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1, + // Propagate tdest signal + parameter DEST_ENABLE = 0, + // tdest signal width + parameter DEST_WIDTH = 8, + // Propagate tuser signal + parameter USER_ENABLE = 1, + // tuser signal width + parameter USER_WIDTH = 1, + // number of output pipeline registers + parameter PIPELINE_OUTPUT = 2 +) +( + input wire clk, + input wire rst, + + /* + * AXI Stream inputs + */ + input wire [PORTS*S_DATA_WIDTH-1:0] s_axis_tdata, + input wire [PORTS*S_KEEP_WIDTH-1:0] s_axis_tkeep, + input wire [PORTS-1:0] s_axis_tvalid, + output wire [PORTS-1:0] s_axis_tready, + input wire [PORTS-1:0] s_axis_tlast, + input wire [PORTS*S_ID_WIDTH-1:0] s_axis_tid, + input wire [PORTS*DEST_WIDTH-1:0] s_axis_tdest, + input wire [PORTS*USER_WIDTH-1:0] s_axis_tuser, + + /* + * AXI Stream output + */ + output wire [M_DATA_WIDTH-1:0] m_axis_tdata, + output wire [M_KEEP_WIDTH-1:0] m_axis_tkeep, + output wire m_axis_tvalid, + input wire m_axis_tready, + output wire m_axis_tlast, + output wire [M_ID_WIDTH-1:0] m_axis_tid, + output wire [DEST_WIDTH-1:0] m_axis_tdest, + output wire [USER_WIDTH-1:0] m_axis_tuser, + + /* + * Status + */ + output wire [PORTS-1:0] status_overflow, + output wire [PORTS-1:0] status_bad_frame, + output wire [PORTS-1:0] status_good_frame +); + +wire [PORTS*M_DATA_WIDTH-1:0] axis_fifo_tdata; +wire [PORTS*M_KEEP_WIDTH-1:0] axis_fifo_tkeep; +wire [PORTS-1:0] axis_fifo_tvalid; +wire [PORTS-1:0] axis_fifo_tready; +wire [PORTS-1:0] axis_fifo_tlast; +wire [PORTS*S_ID_WIDTH-1:0] axis_fifo_tid; +wire [PORTS*DEST_WIDTH-1:0] axis_fifo_tdest; +wire [PORTS*USER_WIDTH-1:0] axis_fifo_tuser; + +generate + +genvar n; + +for (n = 0; n < PORTS; n = n + 1) begin : fifo + + axis_fifo_adapter #( + .DEPTH(FIFO_DEPTH), + .S_DATA_WIDTH(S_DATA_WIDTH), + .S_KEEP_ENABLE(S_KEEP_ENABLE), + .S_KEEP_WIDTH(S_KEEP_WIDTH), + .M_DATA_WIDTH(M_DATA_WIDTH), + .M_KEEP_ENABLE(M_KEEP_ENABLE), + .M_KEEP_WIDTH(M_KEEP_WIDTH), + .ID_ENABLE(ID_ENABLE), + .ID_WIDTH(S_ID_WIDTH), + .DEST_ENABLE(DEST_ENABLE), + .USER_ENABLE(USER_ENABLE), + .USER_WIDTH(USER_WIDTH), + .PIPELINE_OUTPUT(PIPELINE_OUTPUT), + .FRAME_FIFO(1), + .USER_BAD_FRAME_VALUE(1'b1), + .USER_BAD_FRAME_MASK(1'b1), + .DROP_BAD_FRAME(USER_ENABLE), + .DROP_WHEN_FULL(0) + ) + fifo_inst ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata(s_axis_tdata[n*S_DATA_WIDTH +: S_DATA_WIDTH]), + .s_axis_tkeep(s_axis_tkeep[n*S_KEEP_WIDTH +: S_KEEP_WIDTH]), + .s_axis_tvalid(s_axis_tvalid[n +: 1]), + .s_axis_tready(s_axis_tready[n +: 1]), + .s_axis_tlast(s_axis_tlast[n +: 1]), + .s_axis_tid(s_axis_tid[n*S_ID_WIDTH +: S_ID_WIDTH]), + .s_axis_tdest(s_axis_tdest[n*DEST_WIDTH +: DEST_WIDTH]), + .s_axis_tuser(s_axis_tuser[n*USER_WIDTH +: USER_WIDTH]), + + // AXI output + .m_axis_tdata(axis_fifo_tdata[n*M_DATA_WIDTH +: M_DATA_WIDTH]), + .m_axis_tkeep(axis_fifo_tkeep[n*M_KEEP_WIDTH +: M_KEEP_WIDTH]), + .m_axis_tvalid(axis_fifo_tvalid[n +: 1]), + .m_axis_tready(axis_fifo_tready[n +: 1]), + .m_axis_tlast(axis_fifo_tlast[n +: 1]), + .m_axis_tid(axis_fifo_tid[n*S_ID_WIDTH +: S_ID_WIDTH]), + .m_axis_tdest(axis_fifo_tdest[n*DEST_WIDTH +: DEST_WIDTH]), + .m_axis_tuser(axis_fifo_tuser[n*USER_WIDTH +: USER_WIDTH]), + + // Status + .status_overflow(status_overflow), + .status_bad_frame(status_bad_frame), + .status_good_frame(status_good_frame) + ); + +end + +if (PORTS > 1) begin : mux + + axis_arb_mux #( + .S_COUNT(PORTS), + .DATA_WIDTH(M_DATA_WIDTH), + .KEEP_ENABLE(M_KEEP_ENABLE), + .KEEP_WIDTH(M_KEEP_WIDTH), + .ID_ENABLE(ID_ENABLE), + .S_ID_WIDTH(S_ID_WIDTH), + .M_ID_WIDTH(M_ID_WIDTH), + .DEST_ENABLE(DEST_ENABLE), + .DEST_WIDTH(DEST_WIDTH), + .USER_ENABLE(USER_ENABLE), + .USER_WIDTH(USER_WIDTH), + .LAST_ENABLE(1'b1), + .UPDATE_TID(1), + .ARB_TYPE_ROUND_ROBIN(1'b1), + .ARB_LSB_HIGH_PRIORITY(1'b1) + ) + mux_inst ( + .clk(clk), + .rst(rst), + + // AXI Stream inputs + .s_axis_tdata(axis_fifo_tdata), + .s_axis_tkeep(axis_fifo_tkeep), + .s_axis_tvalid(axis_fifo_tvalid), + .s_axis_tready(axis_fifo_tready), + .s_axis_tlast(axis_fifo_tlast), + .s_axis_tid(axis_fifo_tid), + .s_axis_tdest(axis_fifo_tdest), + .s_axis_tuser(axis_fifo_tuser), + + // AXI Stream output + .m_axis_tdata(m_axis_tdata), + .m_axis_tkeep(m_axis_tkeep), + .m_axis_tvalid(m_axis_tvalid), + .m_axis_tready(m_axis_tready), + .m_axis_tlast(m_axis_tlast), + .m_axis_tid(m_axis_tid), + .m_axis_tdest(m_axis_tdest), + .m_axis_tuser(m_axis_tuser) + ); + +end else begin + + assign m_axis_tdata = axis_fifo_tdata; + assign m_axis_tkeep = axis_fifo_tkeep; + assign m_axis_tvalid = axis_fifo_tvalid; + assign axis_fifo_tready = m_axis_tready; + assign m_axis_tlast = axis_fifo_tlast; + assign m_axis_tid = axis_fifo_tid; + assign m_axis_tdest = axis_fifo_tdest; + assign m_axis_tuser = axis_fifo_tuser; + +end + +endgenerate + +endmodule + +`resetall diff --git a/fpga/common/rtl/tx_engine.v b/fpga/common/rtl/tx_engine.v index 19ab75677..7fd07ffb5 100644 --- a/fpga/common/rtl/tx_engine.v +++ b/fpga/common/rtl/tx_engine.v @@ -42,6 +42,8 @@ either expressed or implied, of The Regents of the University of California. */ module tx_engine # ( + // Number of ports + parameter PORTS = 1, // DMA RAM address width parameter RAM_ADDR_WIDTH = 16, // DMA address width @@ -92,8 +94,18 @@ module tx_engine # parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8, // Enable PTP timestamping parameter PTP_TS_ENABLE = 1, + // PTP timestamp width + parameter PTP_TS_WIDTH = 96, + // PTP tag width + parameter PTP_TAG_WIDTH = 16, // Enable TX checksum offload - parameter TX_CHECKSUM_ENABLE = 1 + parameter TX_CHECKSUM_ENABLE = 1, + // AXI stream tid signal width + parameter AXIS_TX_ID_WIDTH = QUEUE_INDEX_WIDTH, + // AXI stream tdest signal width + parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4, + // AXI stream tuser signal width + parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1 ) ( input wire clk, @@ -104,6 +116,7 @@ module tx_engine # */ input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_req_queue, input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_req_tag, + input wire [AXIS_TX_DEST_WIDTH-1:0] s_axis_tx_req_dest, input wire s_axis_tx_req_valid, output wire s_axis_tx_req_ready, @@ -184,7 +197,9 @@ module tx_engine # output wire [RAM_ADDR_WIDTH-1:0] m_axis_tx_desc_addr, output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_desc_len, output wire [DMA_CLIENT_TAG_WIDTH-1:0] m_axis_tx_desc_tag, - output wire m_axis_tx_desc_user, + output wire [AXIS_TX_ID_WIDTH-1:0] m_axis_tx_desc_id, + output wire [AXIS_TX_DEST_WIDTH-1:0] m_axis_tx_desc_dest, + output wire [AXIS_TX_USER_WIDTH-1:0] m_axis_tx_desc_user, output wire m_axis_tx_desc_valid, input wire m_axis_tx_desc_ready, @@ -207,7 +222,8 @@ module tx_engine # /* * Transmit timestamp input */ - input wire [95:0] s_axis_tx_ptp_ts_96, + input wire [PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts, + input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag, input wire s_axis_tx_ptp_ts_valid, output wire s_axis_tx_ptp_ts_ready, @@ -282,7 +298,9 @@ reg m_axis_dma_read_desc_valid_reg = 1'b0, m_axis_dma_read_desc_valid_next; reg [RAM_ADDR_WIDTH-1:0] m_axis_tx_desc_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, m_axis_tx_desc_addr_next; reg [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_desc_len_reg = {DMA_CLIENT_LEN_WIDTH{1'b0}}, m_axis_tx_desc_len_next; reg [DMA_CLIENT_TAG_WIDTH-1:0] m_axis_tx_desc_tag_reg = {DMA_CLIENT_TAG_WIDTH{1'b0}}, m_axis_tx_desc_tag_next; -reg m_axis_tx_desc_user_reg = 1'b0, m_axis_tx_desc_user_next; +reg [AXIS_TX_ID_WIDTH-1:0] m_axis_tx_desc_id_reg = 0, m_axis_tx_desc_id_next; +reg [AXIS_TX_DEST_WIDTH-1:0] m_axis_tx_desc_dest_reg = 0, m_axis_tx_desc_dest_next; +reg [AXIS_TX_USER_WIDTH-1:0] m_axis_tx_desc_user_reg = 0, m_axis_tx_desc_user_next; reg m_axis_tx_desc_valid_reg = 1'b0, m_axis_tx_desc_valid_next; reg m_axis_tx_csum_cmd_csum_enable_reg = 1'b0, m_axis_tx_csum_cmd_csum_enable_next; @@ -315,7 +333,10 @@ reg [DESC_TABLE_SIZE-1:0] desc_table_active = 0; reg [DESC_TABLE_SIZE-1:0] desc_table_invalid = 0; reg [DESC_TABLE_SIZE-1:0] desc_table_desc_fetched = 0; reg [DESC_TABLE_SIZE-1:0] desc_table_data_fetched = 0; -reg [DESC_TABLE_SIZE-1:0] desc_table_tx_done = 0; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) +reg desc_table_tx_done_a[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) +reg desc_table_tx_done_b[DESC_TABLE_SIZE-1:0]; reg [DESC_TABLE_SIZE-1:0] desc_table_cpl_write_done = 0; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [REQ_TAG_WIDTH-1:0] desc_table_tag[DESC_TABLE_SIZE-1:0]; @@ -326,6 +347,8 @@ reg [QUEUE_PTR_WIDTH-1:0] desc_table_queue_ptr[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) +reg [AXIS_TX_DEST_WIDTH-1:0] desc_table_dest[DESC_TABLE_SIZE-1:0]; +(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [6:0] desc_table_csum_start[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [7:0] desc_table_csum_offset[DESC_TABLE_SIZE-1:0]; @@ -336,7 +359,7 @@ reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_len[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg [CL_TX_BUFFER_SIZE+1-1:0] desc_table_buf_ptr[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) -reg [95:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0]; +reg [PTP_TS_WIDTH-1:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) reg desc_table_read_commit[DESC_TABLE_SIZE-1:0]; (* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *) @@ -347,6 +370,7 @@ reg [DESC_TABLE_DMA_OP_COUNT_WIDTH-1:0] desc_table_read_count_finish[DESC_TABLE_ reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_start_ptr_reg = 0; reg [QUEUE_INDEX_WIDTH-1:0] desc_table_start_queue; reg [REQ_TAG_WIDTH-1:0] desc_table_start_tag; +reg [AXIS_TX_DEST_WIDTH-1:0] desc_table_start_dest; reg desc_table_start_en; reg [CL_DESC_TABLE_SIZE-1:0] desc_table_dequeue_ptr; reg [QUEUE_PTR_WIDTH-1:0] desc_table_dequeue_queue_ptr; @@ -368,8 +392,8 @@ reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_tx_start_ptr_reg = 0; reg desc_table_tx_start_en; reg [CL_DESC_TABLE_SIZE-1:0] desc_table_tx_finish_ptr; reg desc_table_tx_finish_en; -reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_store_ptp_ts_ptr_reg = 0; -reg [95:0] desc_table_store_ptp_ts; +reg [CL_DESC_TABLE_SIZE-1:0] desc_table_store_ptp_ts_ptr; +reg [PTP_TS_WIDTH-1:0] desc_table_store_ptp_ts; reg desc_table_store_ptp_ts_en; reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_cpl_enqueue_start_ptr_reg = 0; reg desc_table_cpl_enqueue_start_en; @@ -410,6 +434,8 @@ assign m_axis_dma_read_desc_valid = m_axis_dma_read_desc_valid_reg; assign m_axis_tx_desc_addr = m_axis_tx_desc_addr_reg; assign m_axis_tx_desc_len = m_axis_tx_desc_len_reg; assign m_axis_tx_desc_tag = m_axis_tx_desc_tag_reg; +assign m_axis_tx_desc_id = m_axis_tx_desc_id_reg; +assign m_axis_tx_desc_dest = m_axis_tx_desc_dest_reg; assign m_axis_tx_desc_user = m_axis_tx_desc_user_reg; assign m_axis_tx_desc_valid = m_axis_tx_desc_valid_reg; @@ -459,10 +485,13 @@ integer i; initial begin for (i = 0; i < DESC_TABLE_SIZE; i = i + 1) begin + desc_table_tx_done_a[i] = 0; + desc_table_tx_done_b[i] = 0; desc_table_tag[i] = 0; desc_table_queue[i] = 0; desc_table_queue_ptr[i] = 0; desc_table_cpl_queue[i] = 0; + desc_table_dest[i] = 0; desc_table_csum_start[i] = 0; desc_table_csum_offset[i] = 0; desc_table_csum_enable[i] = 0; @@ -502,6 +531,8 @@ always @* begin m_axis_tx_desc_addr_next = m_axis_tx_desc_addr_reg; m_axis_tx_desc_len_next = m_axis_tx_desc_len_reg; m_axis_tx_desc_tag_next = m_axis_tx_desc_tag_reg; + m_axis_tx_desc_id_next = m_axis_tx_desc_id_reg; + m_axis_tx_desc_dest_next = m_axis_tx_desc_dest_reg; m_axis_tx_desc_user_next = m_axis_tx_desc_user_reg; m_axis_tx_desc_valid_next = m_axis_tx_desc_valid_reg && !m_axis_tx_desc_ready; @@ -532,6 +563,7 @@ always @* begin desc_table_start_tag = s_axis_tx_req_tag; desc_table_start_queue = s_axis_tx_req_queue; + desc_table_start_dest = 0; desc_table_start_en = 1'b0; desc_table_dequeue_ptr = s_axis_desc_req_status_tag; desc_table_dequeue_queue_ptr = s_axis_desc_req_status_ptr; @@ -558,7 +590,8 @@ always @* begin desc_table_tx_start_en = 1'b0; desc_table_tx_finish_ptr = s_axis_tx_desc_status_tag; desc_table_tx_finish_en = 1'b0; - desc_table_store_ptp_ts = s_axis_tx_ptp_ts_96; + desc_table_store_ptp_ts_ptr = s_axis_tx_ptp_ts_tag; + desc_table_store_ptp_ts = s_axis_tx_ptp_ts; desc_table_store_ptp_ts_en = 1'b0; desc_table_cpl_enqueue_start_en = 1'b0; desc_table_cpl_write_done_ptr = s_axis_cpl_req_status_tag & DESC_PTR_MASK; @@ -580,6 +613,7 @@ always @* begin // store in descriptor table desc_table_start_tag = s_axis_tx_req_tag; desc_table_start_queue = s_axis_tx_req_queue; + desc_table_start_dest = s_axis_tx_req_dest; desc_table_start_en = 1'b1; // initiate descriptor fetch @@ -697,7 +731,7 @@ always @* begin desc_table_read_finish_en = 1'b1; end - // transmit + // transmit start // wait for data fetch completion if (desc_table_active[desc_table_tx_start_ptr_reg & DESC_PTR_MASK] && desc_table_tx_start_ptr_reg != desc_table_start_ptr_reg) begin if (desc_table_invalid[desc_table_tx_start_ptr_reg & DESC_PTR_MASK]) begin @@ -712,7 +746,12 @@ always @* begin m_axis_tx_desc_addr_next = desc_table_buf_ptr[desc_table_tx_start_ptr_reg & DESC_PTR_MASK] & TX_BUFFER_PTR_MASK + TX_BUFFER_OFFSET; m_axis_tx_desc_len_next = desc_table_len[desc_table_tx_start_ptr_reg & DESC_PTR_MASK]; m_axis_tx_desc_tag_next = desc_table_tx_start_ptr_reg & DESC_PTR_MASK; - m_axis_tx_desc_user_next = 1'b0; + m_axis_tx_desc_id_next = desc_table_queue[desc_table_tx_start_ptr_reg & DESC_PTR_MASK]; + m_axis_tx_desc_dest_next = desc_table_dest[desc_table_tx_start_ptr_reg & DESC_PTR_MASK]; + m_axis_tx_desc_user_next = 0; + m_axis_tx_desc_user_next[1+PTP_TAG_WIDTH-1 +: 1] = 1'b1; + m_axis_tx_desc_user_next[1 +: PTP_TAG_WIDTH-1] = desc_table_tx_start_ptr_reg & DESC_PTR_MASK; + m_axis_tx_desc_user_next[0 +: 1] = 1'b0; m_axis_tx_desc_valid_next = 1'b1; // send TX checksum command @@ -725,8 +764,8 @@ always @* begin end end - // transmit done - // wait for transmit completion + // transmit DMA done + // wait for transmit DMA completion; free buffer space if (s_axis_tx_desc_status_valid) begin // update entry in descriptor table desc_table_tx_finish_ptr = s_axis_tx_desc_status_tag; @@ -740,29 +779,21 @@ always @* begin end end - // store PTP timestamp - if (desc_table_active[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK] && desc_table_store_ptp_ts_ptr_reg != desc_table_start_ptr_reg && desc_table_store_ptp_ts_ptr_reg != desc_table_tx_start_ptr_reg && PTP_TS_ENABLE) begin - s_axis_tx_ptp_ts_ready_next = 1'b1; - if (desc_table_invalid[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK]) begin - // invalid entry; skip - desc_table_store_ptp_ts_en = 1'b1; - - s_axis_tx_ptp_ts_ready_next = 1'b0; - end else if (s_axis_tx_ptp_ts_ready && s_axis_tx_ptp_ts_valid) begin - // update entry in descriptor table - desc_table_store_ptp_ts = s_axis_tx_ptp_ts_96; - desc_table_store_ptp_ts_en = 1'b1; - - s_axis_tx_ptp_ts_ready_next = 1'b0; - end + // transmit done + // wait for transmit completion; store PTP timestamp + s_axis_tx_ptp_ts_ready_next = 1'b1; + if (s_axis_tx_ptp_ts_valid && s_axis_tx_ptp_ts_tag[PTP_TAG_WIDTH-1]) begin + desc_table_store_ptp_ts_ptr = s_axis_tx_ptp_ts_tag; + desc_table_store_ptp_ts = s_axis_tx_ptp_ts; + desc_table_store_ptp_ts_en = 1'b1; end // finish transmit; start completion enqueue - if (desc_table_active[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && desc_table_cpl_enqueue_start_ptr_reg != desc_table_start_ptr_reg && desc_table_cpl_enqueue_start_ptr_reg != desc_table_tx_start_ptr_reg && (desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_ptp_ts_ptr_reg || !PTP_TS_ENABLE)) begin + if (desc_table_active[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && desc_table_cpl_enqueue_start_ptr_reg != desc_table_start_ptr_reg && desc_table_cpl_enqueue_start_ptr_reg != desc_table_tx_start_ptr_reg) begin if (desc_table_invalid[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK]) begin // invalid entry; skip desc_table_cpl_enqueue_start_en = 1'b1; - end else if (desc_table_tx_done[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_cpl_req_valid_next) begin + end else if (desc_table_tx_done_a[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] != desc_table_tx_done_b[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_cpl_req_valid_next) begin // update entry in descriptor table desc_table_cpl_enqueue_start_en = 1'b1; @@ -777,6 +808,7 @@ always @* begin //m_axis_cpl_req_data_next[127:64] = desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16; m_axis_cpl_req_data_next[111:64] = desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16; end + m_axis_cpl_req_data_next[176:168] = desc_table_dest[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK]; m_axis_cpl_req_valid_next = 1'b1; end end @@ -846,6 +878,8 @@ always @(posedge clk) begin m_axis_tx_desc_addr_reg <= m_axis_tx_desc_addr_next; m_axis_tx_desc_len_reg <= m_axis_tx_desc_len_next; m_axis_tx_desc_tag_reg <= m_axis_tx_desc_tag_next; + m_axis_tx_desc_id_reg <= m_axis_tx_desc_id_next; + m_axis_tx_desc_dest_reg <= m_axis_tx_desc_dest_next; m_axis_tx_desc_user_reg <= m_axis_tx_desc_user_next; m_axis_tx_desc_valid_reg <= m_axis_tx_desc_valid_next; @@ -878,10 +912,11 @@ always @(posedge clk) begin desc_table_invalid[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0; desc_table_desc_fetched[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0; desc_table_data_fetched[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0; - desc_table_tx_done[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0; + desc_table_tx_done_a[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_tx_done_b[desc_table_start_ptr_reg & DESC_PTR_MASK]; desc_table_cpl_write_done[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0; desc_table_queue[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_queue; desc_table_tag[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_tag; + desc_table_dest[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_dest; desc_table_start_ptr_reg <= desc_table_start_ptr_reg + 1; end @@ -914,13 +949,9 @@ always @(posedge clk) begin desc_table_tx_start_ptr_reg <= desc_table_tx_start_ptr_reg + 1; end - if (desc_table_tx_finish_en) begin - desc_table_tx_done[desc_table_tx_finish_ptr & DESC_PTR_MASK] <= 1'b1; - end - if (desc_table_store_ptp_ts_en) begin - desc_table_ptp_ts[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK] <= desc_table_store_ptp_ts; - desc_table_store_ptp_ts_ptr_reg <= desc_table_store_ptp_ts_ptr_reg + 1; + desc_table_ptp_ts[desc_table_store_ptp_ts_ptr] <= desc_table_store_ptp_ts; + desc_table_tx_done_b[desc_table_store_ptp_ts_ptr] <= !desc_table_tx_done_a[desc_table_store_ptp_ts_ptr]; end if (desc_table_cpl_enqueue_start_en) begin @@ -928,7 +959,7 @@ always @(posedge clk) begin end if (desc_table_cpl_write_done_en) begin - desc_table_cpl_write_done[desc_table_cpl_write_done_ptr & DESC_PTR_MASK] <= 1'b1; + desc_table_cpl_write_done[desc_table_cpl_write_done_ptr] <= 1'b1; end if (desc_table_finish_en) begin @@ -980,11 +1011,9 @@ always @(posedge clk) begin desc_table_invalid <= 0; desc_table_desc_fetched <= 0; desc_table_data_fetched <= 0; - desc_table_tx_done <= 0; desc_table_start_ptr_reg <= 0; desc_table_tx_start_ptr_reg <= 0; - desc_table_store_ptp_ts_ptr_reg <= 0; desc_table_cpl_enqueue_start_ptr_reg <= 0; desc_table_finish_ptr_reg <= 0; end diff --git a/fpga/common/rtl/tx_fifo.v b/fpga/common/rtl/tx_fifo.v new file mode 100644 index 000000000..3e0cdfd52 --- /dev/null +++ b/fpga/common/rtl/tx_fifo.v @@ -0,0 +1,246 @@ +/* + +Copyright 2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * TX FIFO + */ +module tx_fifo # +( + // FIFO depth in words (each FIFO) + // KEEP_WIDTH words per cycle if KEEP_ENABLE set + // Rounded up to nearest power of 2 cycles + parameter FIFO_DEPTH = 4096, + // Number of AXI stream outputs + parameter PORTS = 4, + // Width of input AXI stream interfaces in bits + parameter S_DATA_WIDTH = 8, + // Propagate tkeep signal + parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8), + // tkeep signal width (words per cycle) + parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8), + // Width of output AXI stream interfaces in bits + parameter M_DATA_WIDTH = 8, + // Propagate tkeep signal + parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8), + // tkeep signal width (words per cycle) + parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8), + // Propagate tid signal + parameter ID_ENABLE = 0, + // tid signal width + parameter ID_WIDTH = 8, + // output tdest signal width + parameter M_DEST_WIDTH = 3, + // input tdest signal width + // must be wide enough to uniquely address outputs + parameter S_DEST_WIDTH = M_DEST_WIDTH+$clog2(PORTS), + // Propagate tuser signal + parameter USER_ENABLE = 1, + // tuser signal width + parameter USER_WIDTH = 1, + // number of output pipeline registers + parameter PIPELINE_OUTPUT = 2 +) +( + input wire clk, + input wire rst, + + /* + * AXI Stream input + */ + input wire [S_DATA_WIDTH-1:0] s_axis_tdata, + input wire [S_KEEP_WIDTH-1:0] s_axis_tkeep, + input wire s_axis_tvalid, + output wire s_axis_tready, + input wire s_axis_tlast, + input wire [ID_WIDTH-1:0] s_axis_tid, + input wire [S_DEST_WIDTH-1:0] s_axis_tdest, + input wire [USER_WIDTH-1:0] s_axis_tuser, + + /* + * AXI Stream outputs + */ + output wire [PORTS*M_DATA_WIDTH-1:0] m_axis_tdata, + output wire [PORTS*M_KEEP_WIDTH-1:0] m_axis_tkeep, + output wire [PORTS-1:0] m_axis_tvalid, + input wire [PORTS-1:0] m_axis_tready, + output wire [PORTS-1:0] m_axis_tlast, + output wire [PORTS*ID_WIDTH-1:0] m_axis_tid, + output wire [PORTS*M_DEST_WIDTH-1:0] m_axis_tdest, + output wire [PORTS*USER_WIDTH-1:0] m_axis_tuser, + + /* + * Status + */ + output wire [PORTS-1:0] status_overflow, + output wire [PORTS-1:0] status_bad_frame, + output wire [PORTS-1:0] status_good_frame +); + +wire [PORTS*S_DATA_WIDTH-1:0] axis_fifo_tdata; +wire [PORTS*S_KEEP_WIDTH-1:0] axis_fifo_tkeep; +wire [PORTS-1:0] axis_fifo_tvalid; +wire [PORTS-1:0] axis_fifo_tready; +wire [PORTS-1:0] axis_fifo_tlast; +wire [PORTS*ID_WIDTH-1:0] axis_fifo_tid; +wire [PORTS*M_DEST_WIDTH-1:0] axis_fifo_tdest; +wire [PORTS*USER_WIDTH-1:0] axis_fifo_tuser; + +generate + +genvar n; + +if (PORTS > 1) begin : demux + + axis_demux #( + .M_COUNT(PORTS), + .DATA_WIDTH(S_DATA_WIDTH), + .KEEP_ENABLE(S_KEEP_ENABLE), + .KEEP_WIDTH(S_KEEP_WIDTH), + .ID_ENABLE(ID_ENABLE), + .ID_WIDTH(ID_WIDTH), + .DEST_ENABLE(1), + .S_DEST_WIDTH(S_DEST_WIDTH), + .M_DEST_WIDTH(M_DEST_WIDTH), + .USER_ENABLE(USER_ENABLE), + .USER_WIDTH(USER_WIDTH), + .TDEST_ROUTE(1) + ) + switch_inst ( + .clk(clk), + .rst(rst), + + // AXI Stream input + .s_axis_tdata(s_axis_tdata), + .s_axis_tkeep(s_axis_tkeep), + .s_axis_tvalid(s_axis_tvalid), + .s_axis_tready(s_axis_tready), + .s_axis_tlast(s_axis_tlast), + .s_axis_tid(s_axis_tid), + .s_axis_tdest(s_axis_tdest), + .s_axis_tuser(s_axis_tuser), + + // AXI Stream outputs + .m_axis_tdata(axis_fifo_tdata), + .m_axis_tkeep(axis_fifo_tkeep), + .m_axis_tvalid(axis_fifo_tvalid), + .m_axis_tready(axis_fifo_tready), + .m_axis_tlast(axis_fifo_tlast), + .m_axis_tid(axis_fifo_tid), + .m_axis_tdest(axis_fifo_tdest), + .m_axis_tuser(axis_fifo_tuser), + + // Control + .enable(1), + .drop(0), + .select(0) + ); + +end else begin + + assign axis_fifo_tdata = s_axis_tdata; + assign axis_fifo_tkeep = s_axis_tkeep; + assign axis_fifo_tvalid = s_axis_tvalid; + assign s_axis_tready = axis_fifo_tready; + assign axis_fifo_tlast = s_axis_tlast; + assign axis_fifo_tid = s_axis_tid; + assign axis_fifo_tdest = s_axis_tdest; + assign axis_fifo_tuser = s_axis_tuser; + +end + +for (n = 0; n < PORTS; n = n + 1) begin : fifo + + axis_fifo_adapter #( + .DEPTH(FIFO_DEPTH), + .S_DATA_WIDTH(S_DATA_WIDTH), + .S_KEEP_ENABLE(S_KEEP_ENABLE), + .S_KEEP_WIDTH(S_KEEP_WIDTH), + .M_DATA_WIDTH(M_DATA_WIDTH), + .M_KEEP_ENABLE(M_KEEP_ENABLE), + .M_KEEP_WIDTH(M_KEEP_WIDTH), + .ID_ENABLE(ID_ENABLE), + .ID_WIDTH(ID_WIDTH), + .DEST_ENABLE(1), + .DEST_WIDTH(M_DEST_WIDTH), + .USER_ENABLE(USER_ENABLE), + .USER_WIDTH(USER_WIDTH), + .PIPELINE_OUTPUT(PIPELINE_OUTPUT), + .FRAME_FIFO(1), + .USER_BAD_FRAME_VALUE(1'b1), + .USER_BAD_FRAME_MASK(1'b1), + .DROP_BAD_FRAME(USER_ENABLE), + .DROP_WHEN_FULL(0) + ) + fifo_inst ( + .clk(clk), + .rst(rst), + + // AXI input + .s_axis_tdata(axis_fifo_tdata[n*S_DATA_WIDTH +: S_DATA_WIDTH]), + .s_axis_tkeep(axis_fifo_tkeep[n*S_KEEP_WIDTH +: S_KEEP_WIDTH]), + .s_axis_tvalid(axis_fifo_tvalid[n +: 1]), + .s_axis_tready(axis_fifo_tready[n +: 1]), + .s_axis_tlast(axis_fifo_tlast[n +: 1]), + .s_axis_tid(axis_fifo_tid[n*ID_WIDTH +: ID_WIDTH]), + .s_axis_tdest(axis_fifo_tdest[n*M_DEST_WIDTH +: M_DEST_WIDTH]), + .s_axis_tuser(axis_fifo_tuser[n*USER_WIDTH +: USER_WIDTH]), + + // AXI output + .m_axis_tdata(m_axis_tdata[n*M_DATA_WIDTH +: M_DATA_WIDTH]), + .m_axis_tkeep(m_axis_tkeep[n*M_KEEP_WIDTH +: M_KEEP_WIDTH]), + .m_axis_tvalid(m_axis_tvalid[n +: 1]), + .m_axis_tready(m_axis_tready[n +: 1]), + .m_axis_tlast(m_axis_tlast[n +: 1]), + .m_axis_tid(m_axis_tid[n*ID_WIDTH +: ID_WIDTH]), + .m_axis_tdest(m_axis_tdest[n*M_DEST_WIDTH +: M_DEST_WIDTH]), + .m_axis_tuser(m_axis_tuser[n*USER_WIDTH +: USER_WIDTH]), + + // Status + .status_overflow(status_overflow), + .status_bad_frame(status_bad_frame), + .status_good_frame(status_good_frame) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/fpga/common/rtl/tx_req_mux.v b/fpga/common/rtl/tx_req_mux.v new file mode 100644 index 000000000..736c34dda --- /dev/null +++ b/fpga/common/rtl/tx_req_mux.v @@ -0,0 +1,284 @@ +/* + +Copyright 2021, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transmit request mux + */ +module tx_req_mux # +( + // Number of ports + parameter PORTS = 2, + // Queue index width + parameter QUEUE_INDEX_WIDTH = 4, + // Input request tag field width + parameter S_REQ_TAG_WIDTH = 8, + // Output request tag field width (towards transmit engine) + // Additional bits required for response routing + parameter M_REQ_TAG_WIDTH = S_REQ_TAG_WIDTH+$clog2(PORTS), + // dest width + parameter DEST_WIDTH = 8, + // Length field width + parameter LEN_WIDTH = 20, + // select round robin arbitration + parameter ARB_TYPE_ROUND_ROBIN = 0, + // LSB priority selection + parameter ARB_LSB_HIGH_PRIORITY = 1 +) +( + input wire clk, + input wire rst, + + /* + * Transmit request output (to transmit engine) + */ + output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_req_queue, + output wire [M_REQ_TAG_WIDTH-1:0] m_axis_req_tag, + output wire [DEST_WIDTH-1:0] m_axis_req_dest, + output wire m_axis_req_valid, + input wire m_axis_req_ready, + + /* + * Transmit request status input (from transmit engine) + */ + input wire [LEN_WIDTH-1:0] s_axis_req_status_len, + input wire [M_REQ_TAG_WIDTH-1:0] s_axis_req_status_tag, + input wire s_axis_req_status_empty, + input wire s_axis_req_status_error, + input wire s_axis_req_status_valid, + + /* + * Transmit request input + */ + input wire [PORTS*QUEUE_INDEX_WIDTH-1:0] s_axis_req_queue, + input wire [PORTS*S_REQ_TAG_WIDTH-1:0] s_axis_req_tag, + input wire [PORTS*DEST_WIDTH-1:0] s_axis_req_dest, + input wire [PORTS-1:0] s_axis_req_valid, + output wire [PORTS-1:0] s_axis_req_ready, + + /* + * Transmit request status output + */ + output wire [PORTS*LEN_WIDTH-1:0] m_axis_req_status_len, + output wire [PORTS*S_REQ_TAG_WIDTH-1:0] m_axis_req_status_tag, + output wire [PORTS-1:0] m_axis_req_status_empty, + output wire [PORTS-1:0] m_axis_req_status_error, + output wire [PORTS-1:0] m_axis_req_status_valid +); + +parameter CL_PORTS = $clog2(PORTS); + +// check configuration +initial begin + if (M_REQ_TAG_WIDTH < S_REQ_TAG_WIDTH+$clog2(PORTS)) begin + $error("Error: M_REQ_TAG_WIDTH must be at least $clog2(PORTS) larger than S_REQ_TAG_WIDTH (instance %m)"); + $finish; + end +end + +// request mux +wire [PORTS-1:0] request; +wire [PORTS-1:0] acknowledge; +wire [PORTS-1:0] grant; +wire grant_valid; +wire [CL_PORTS-1:0] grant_encoded; + +// internal datapath +reg [QUEUE_INDEX_WIDTH-1:0] m_axis_req_queue_int; +reg [M_REQ_TAG_WIDTH-1:0] m_axis_req_tag_int; +reg [DEST_WIDTH-1:0] m_axis_req_dest_int; +reg m_axis_req_valid_int; +reg m_axis_req_ready_int_reg = 1'b0; +wire m_axis_req_ready_int_early; + +assign s_axis_req_ready = (m_axis_req_ready_int_reg && grant_valid) << grant_encoded; + +// mux for incoming packet +wire [QUEUE_INDEX_WIDTH-1:0] current_s_desc_queue = s_axis_req_queue[grant_encoded*QUEUE_INDEX_WIDTH +: QUEUE_INDEX_WIDTH]; +wire [S_REQ_TAG_WIDTH-1:0] current_s_desc_tag = s_axis_req_tag[grant_encoded*S_REQ_TAG_WIDTH +: S_REQ_TAG_WIDTH]; +wire [DEST_WIDTH-1:0] current_s_desc_data = s_axis_req_dest[grant_encoded*DEST_WIDTH +: DEST_WIDTH]; +wire current_s_desc_valid = s_axis_req_valid[grant_encoded]; +wire current_s_desc_ready = s_axis_req_ready[grant_encoded]; + +// arbiter instance +arbiter #( + .PORTS(PORTS), + .ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN), + .ARB_BLOCK(1), + .ARB_BLOCK_ACK(1), + .ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY) +) +arb_inst ( + .clk(clk), + .rst(rst), + .request(request), + .acknowledge(acknowledge), + .grant(grant), + .grant_valid(grant_valid), + .grant_encoded(grant_encoded) +); + +assign request = s_axis_req_valid & ~grant; +assign acknowledge = grant & s_axis_req_valid & s_axis_req_ready; + +always @* begin + // pass through selected packet data + m_axis_req_queue_int = current_s_desc_queue; + m_axis_req_tag_int = {grant_encoded, current_s_desc_tag}; + m_axis_req_dest_int = current_s_desc_data; + m_axis_req_valid_int = current_s_desc_valid && m_axis_req_ready_int_reg && grant_valid; +end + +// output datapath logic +reg [QUEUE_INDEX_WIDTH-1:0] m_axis_req_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}; +reg [M_REQ_TAG_WIDTH-1:0] m_axis_req_tag_reg = {M_REQ_TAG_WIDTH{1'b0}}; +reg [DEST_WIDTH-1:0] m_axis_req_dest_reg = {DEST_WIDTH{1'b0}}; +reg m_axis_req_valid_reg = 1'b0, m_axis_req_valid_next; + +reg [QUEUE_INDEX_WIDTH-1:0] temp_m_axis_req_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}}; +reg [M_REQ_TAG_WIDTH-1:0] temp_m_axis_req_tag_reg = {M_REQ_TAG_WIDTH{1'b0}}; +reg [DEST_WIDTH-1:0] temp_m_axis_req_dest_reg = {DEST_WIDTH{1'b0}}; +reg temp_m_axis_req_valid_reg = 1'b0, temp_m_axis_req_valid_next; + +// datapath control +reg store_axis_int_to_output; +reg store_axis_int_to_temp; +reg store_axis_temp_to_output; + +assign m_axis_req_queue = m_axis_req_queue_reg; +assign m_axis_req_tag = m_axis_req_tag_reg; +assign m_axis_req_dest = m_axis_req_dest_reg; +assign m_axis_req_valid = m_axis_req_valid_reg; + +// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input) +assign m_axis_req_ready_int_early = m_axis_req_ready || (!temp_m_axis_req_valid_reg && (!m_axis_req_valid_reg || !m_axis_req_valid_int)); + +always @* begin + // transfer sink ready state to source + m_axis_req_valid_next = m_axis_req_valid_reg; + temp_m_axis_req_valid_next = temp_m_axis_req_valid_reg; + + store_axis_int_to_output = 1'b0; + store_axis_int_to_temp = 1'b0; + store_axis_temp_to_output = 1'b0; + + if (m_axis_req_ready_int_reg) begin + // input is ready + if (m_axis_req_ready || !m_axis_req_valid_reg) begin + // output is ready or currently not valid, transfer data to output + m_axis_req_valid_next = m_axis_req_valid_int; + store_axis_int_to_output = 1'b1; + end else begin + // output is not ready, store input in temp + temp_m_axis_req_valid_next = m_axis_req_valid_int; + store_axis_int_to_temp = 1'b1; + end + end else if (m_axis_req_ready) begin + // input is not ready, but output is ready + m_axis_req_valid_next = temp_m_axis_req_valid_reg; + temp_m_axis_req_valid_next = 1'b0; + store_axis_temp_to_output = 1'b1; + end +end + +always @(posedge clk) begin + if (rst) begin + m_axis_req_valid_reg <= 1'b0; + m_axis_req_ready_int_reg <= 1'b0; + temp_m_axis_req_valid_reg <= 1'b0; + end else begin + m_axis_req_valid_reg <= m_axis_req_valid_next; + m_axis_req_ready_int_reg <= m_axis_req_ready_int_early; + temp_m_axis_req_valid_reg <= temp_m_axis_req_valid_next; + end + + // datapath + if (store_axis_int_to_output) begin + m_axis_req_queue_reg <= m_axis_req_queue_int; + m_axis_req_tag_reg <= m_axis_req_tag_int; + m_axis_req_dest_reg <= m_axis_req_dest_int; + end else if (store_axis_temp_to_output) begin + m_axis_req_queue_reg <= temp_m_axis_req_queue_reg; + m_axis_req_tag_reg <= temp_m_axis_req_tag_reg; + m_axis_req_dest_reg <= temp_m_axis_req_dest_reg; + end + + if (store_axis_int_to_temp) begin + temp_m_axis_req_queue_reg <= m_axis_req_queue_int; + temp_m_axis_req_tag_reg <= m_axis_req_tag_int; + temp_m_axis_req_dest_reg <= m_axis_req_dest_int; + end +end + +// request status demux +reg [LEN_WIDTH-1:0] m_axis_req_status_len_reg = {LEN_WIDTH{1'b0}}, m_axis_req_status_len_next; +reg [S_REQ_TAG_WIDTH-1:0] m_axis_req_status_tag_reg = {S_REQ_TAG_WIDTH{1'b0}}, m_axis_req_status_tag_next; +reg m_axis_req_status_empty_reg = 1'b0, m_axis_req_status_empty_next; +reg m_axis_req_status_error_reg = 1'b0, m_axis_req_status_error_next; +reg [PORTS-1:0] m_axis_req_status_valid_reg = {PORTS{1'b0}}, m_axis_req_status_valid_next; + +assign m_axis_req_status_len = {PORTS{m_axis_req_status_len_reg}}; +assign m_axis_req_status_tag = {PORTS{m_axis_req_status_tag_reg}}; +assign m_axis_req_status_empty = {PORTS{m_axis_req_status_empty_reg}}; +assign m_axis_req_status_error = {PORTS{m_axis_req_status_error_reg}}; +assign m_axis_req_status_valid = m_axis_req_status_valid_reg; + +always @* begin + m_axis_req_status_len_next = s_axis_req_status_len; + m_axis_req_status_tag_next = s_axis_req_status_tag; + m_axis_req_status_empty_next = s_axis_req_status_empty; + m_axis_req_status_error_next = s_axis_req_status_error; + m_axis_req_status_valid_next = s_axis_req_status_valid << (PORTS > 1 ? (s_axis_req_status_tag >> S_REQ_TAG_WIDTH) : 0); +end + +always @(posedge clk) begin + if (rst) begin + m_axis_req_status_valid_reg <= {PORTS{1'b0}}; + end else begin + m_axis_req_status_valid_reg <= m_axis_req_status_valid_next; + end + + m_axis_req_status_len_reg <= m_axis_req_status_len_next; + m_axis_req_status_tag_reg <= m_axis_req_status_tag_next; + m_axis_req_status_empty_reg <= m_axis_req_status_empty_next; + m_axis_req_status_error_reg <= m_axis_req_status_error_next; +end + +endmodule + +`resetall diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile index af1c0400d..434c6c68c 100644 --- a/fpga/common/tb/mqnic_core_axi/Makefile +++ b/fpga/common/tb/mqnic_core_axi/Makefile @@ -41,7 +41,10 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/mqnic_core.v VERILOG_SOURCES += ../../rtl/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/mqnic_port.v +VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v @@ -52,6 +55,9 @@ VERILOG_SOURCES += ../../rtl/desc_op_mux.v VERILOG_SOURCES += ../../rtl/event_mux.v VERILOG_SOURCES += ../../rtl/queue_manager.v VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/tx_fifo.v +VERILOG_SOURCES += ../../rtl/rx_fifo.v +VERILOG_SOURCES += ../../rtl/tx_req_mux.v VERILOG_SOURCES += ../../rtl/tx_engine.v VERILOG_SOURCES += ../../rtl/rx_engine.v VERILOG_SOURCES += ../../rtl/tx_checksum.v @@ -84,7 +90,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi.v diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py index ebb7fe8da..22a44454a 100644 --- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py +++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py @@ -384,8 +384,8 @@ pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl')) @pytest.mark.parametrize(("if_count", "ports_per_if", "axi_data_width", "axis_data_width", "axis_sync_data_width"), [ (1, 1, 128, 64, 64), - (2, 1, 256, 64, 64), - (1, 2, 256, 64, 64), + (2, 1, 128, 64, 64), + (1, 2, 128, 64, 64), (1, 1, 128, 64, 128), ]) def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width, @@ -398,7 +398,10 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width, os.path.join(rtl_dir, f"{dut}.v"), os.path.join(rtl_dir, "mqnic_core.v"), os.path.join(rtl_dir, "mqnic_interface.v"), - os.path.join(rtl_dir, "mqnic_port.v"), + os.path.join(rtl_dir, "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "mqnic_egress.v"), + os.path.join(rtl_dir, "mqnic_ingress.v"), os.path.join(rtl_dir, "mqnic_ptp.v"), os.path.join(rtl_dir, "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "mqnic_ptp_perout.v"), @@ -409,6 +412,9 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width, os.path.join(rtl_dir, "event_mux.v"), os.path.join(rtl_dir, "queue_manager.v"), os.path.join(rtl_dir, "cpl_queue_manager.v"), + os.path.join(rtl_dir, "tx_fifo.v"), + os.path.join(rtl_dir, "rx_fifo.v"), + os.path.join(rtl_dir, "tx_req_mux.v"), os.path.join(rtl_dir, "tx_engine.v"), os.path.join(rtl_dir, "rx_engine.v"), os.path.join(rtl_dir, "tx_checksum.v"), @@ -441,7 +447,9 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width, os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "dma_if_axi.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile index ab7da0a3e..bc840dd6e 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile @@ -42,7 +42,10 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/mqnic_core.v VERILOG_SOURCES += ../../rtl/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/mqnic_port.v +VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v @@ -53,6 +56,9 @@ VERILOG_SOURCES += ../../rtl/desc_op_mux.v VERILOG_SOURCES += ../../rtl/event_mux.v VERILOG_SOURCES += ../../rtl/queue_manager.v VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/tx_fifo.v +VERILOG_SOURCES += ../../rtl/rx_fifo.v +VERILOG_SOURCES += ../../rtl/tx_req_mux.v VERILOG_SOURCES += ../../rtl/tx_engine.v VERILOG_SOURCES += ../../rtl/rx_engine.v VERILOG_SOURCES += ../../rtl/tx_checksum.v @@ -85,7 +91,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py index 3896d9023..76e74c280 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py +++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py @@ -513,7 +513,10 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, os.path.join(rtl_dir, "mqnic_core.v"), os.path.join(rtl_dir, "mqnic_core_pcie.v"), os.path.join(rtl_dir, "mqnic_interface.v"), - os.path.join(rtl_dir, "mqnic_port.v"), + os.path.join(rtl_dir, "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "mqnic_egress.v"), + os.path.join(rtl_dir, "mqnic_ingress.v"), os.path.join(rtl_dir, "mqnic_ptp.v"), os.path.join(rtl_dir, "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "mqnic_ptp_perout.v"), @@ -524,6 +527,9 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, os.path.join(rtl_dir, "event_mux.v"), os.path.join(rtl_dir, "queue_manager.v"), os.path.join(rtl_dir, "cpl_queue_manager.v"), + os.path.join(rtl_dir, "tx_fifo.v"), + os.path.join(rtl_dir, "rx_fifo.v"), + os.path.join(rtl_dir, "tx_req_mux.v"), os.path.join(rtl_dir, "tx_engine.v"), os.path.join(rtl_dir, "rx_engine.v"), os.path.join(rtl_dir, "tx_checksum.v"), @@ -556,7 +562,9 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile index f5088b6e9..f8a331229 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile @@ -42,7 +42,10 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/mqnic_core.v VERILOG_SOURCES += ../../rtl/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/mqnic_port.v +VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v @@ -53,6 +56,9 @@ VERILOG_SOURCES += ../../rtl/desc_op_mux.v VERILOG_SOURCES += ../../rtl/event_mux.v VERILOG_SOURCES += ../../rtl/queue_manager.v VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/tx_fifo.v +VERILOG_SOURCES += ../../rtl/rx_fifo.v +VERILOG_SOURCES += ../../rtl/tx_req_mux.v VERILOG_SOURCES += ../../rtl/tx_engine.v VERILOG_SOURCES += ../../rtl/rx_engine.v VERILOG_SOURCES += ../../rtl/tx_checksum.v @@ -85,7 +91,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 7036fa2ef..294b10ff4 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -588,7 +588,10 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "mqnic_core.v"), os.path.join(rtl_dir, "mqnic_core_pcie.v"), os.path.join(rtl_dir, "mqnic_interface.v"), - os.path.join(rtl_dir, "mqnic_port.v"), + os.path.join(rtl_dir, "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "mqnic_egress.v"), + os.path.join(rtl_dir, "mqnic_ingress.v"), os.path.join(rtl_dir, "mqnic_ptp.v"), os.path.join(rtl_dir, "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "mqnic_ptp_perout.v"), @@ -599,6 +602,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "event_mux.v"), os.path.join(rtl_dir, "queue_manager.v"), os.path.join(rtl_dir, "cpl_queue_manager.v"), + os.path.join(rtl_dir, "tx_fifo.v"), + os.path.join(rtl_dir, "rx_fifo.v"), + os.path.join(rtl_dir, "tx_req_mux.v"), os.path.join(rtl_dir, "tx_engine.v"), os.path.join(rtl_dir, "rx_engine.v"), os.path.join(rtl_dir, "tx_checksum.v"), @@ -631,7 +637,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile index dcd9bb948..96fb6e8d3 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile @@ -42,7 +42,10 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/mqnic_core.v VERILOG_SOURCES += ../../rtl/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/mqnic_port.v +VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v @@ -53,6 +56,9 @@ VERILOG_SOURCES += ../../rtl/desc_op_mux.v VERILOG_SOURCES += ../../rtl/event_mux.v VERILOG_SOURCES += ../../rtl/queue_manager.v VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/tx_fifo.v +VERILOG_SOURCES += ../../rtl/rx_fifo.v +VERILOG_SOURCES += ../../rtl/tx_req_mux.v VERILOG_SOURCES += ../../rtl/tx_engine.v VERILOG_SOURCES += ../../rtl/rx_engine.v VERILOG_SOURCES += ../../rtl/tx_checksum.v @@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py index 687d68cb3..d11ef628d 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py @@ -641,7 +641,10 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "mqnic_core.v"), os.path.join(rtl_dir, "mqnic_core_pcie.v"), os.path.join(rtl_dir, "mqnic_interface.v"), - os.path.join(rtl_dir, "mqnic_port.v"), + os.path.join(rtl_dir, "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "mqnic_egress.v"), + os.path.join(rtl_dir, "mqnic_ingress.v"), os.path.join(rtl_dir, "mqnic_ptp.v"), os.path.join(rtl_dir, "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "mqnic_ptp_perout.v"), @@ -652,6 +655,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "event_mux.v"), os.path.join(rtl_dir, "queue_manager.v"), os.path.join(rtl_dir, "cpl_queue_manager.v"), + os.path.join(rtl_dir, "tx_fifo.v"), + os.path.join(rtl_dir, "rx_fifo.v"), + os.path.join(rtl_dir, "tx_req_mux.v"), os.path.join(rtl_dir, "tx_engine.v"), os.path.join(rtl_dir, "rx_engine.v"), os.path.join(rtl_dir, "tx_checksum.v"), @@ -686,7 +692,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile index 0e887d4a7..0b129fce4 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile @@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -58,7 +64,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile index 7d5675557..e2bb48fcd 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile @@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -60,7 +66,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile index 0ec3ce1c2..ee2cadfef 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py index 0426cb343..33b6738a4 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -523,7 +523,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -534,6 +537,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -567,7 +573,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile index a6e3d2473..70707b10b 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile @@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -75,7 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga_tdma/Makefile index 8a2e3b183..62f43226f 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga_tdma/Makefile @@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -76,7 +82,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile index 3225ed6d6..ca7390682 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py index 0ed277d6f..87f1a1786 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -565,7 +565,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -576,6 +579,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -616,7 +622,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index a6e3d2473..70707b10b 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -75,7 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile index 8a2e3b183..62f43226f 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile @@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -76,7 +82,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile index 3225ed6d6..ca7390682 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index 4ba5f3ef1..d68a60240 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -565,7 +565,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -576,6 +579,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -616,7 +622,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile index 262b8cbac..686cd319c 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile @@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -61,7 +67,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile index d418b9605..381e297e7 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py index 5e76acaa0..15d0ab989 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -523,7 +523,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -534,6 +537,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -567,7 +573,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/AU200/fpga_10g/fpga/Makefile b/fpga/mqnic/AU200/fpga_10g/fpga/Makefile index a8ec68a7c..548913c21 100644 --- a/fpga/mqnic/AU200/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_10g/fpga/Makefile @@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -78,7 +84,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/AU200/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_10g/tb/fpga_core/Makefile index 8b13a90f4..1f5af3000 100644 --- a/fpga/mqnic/AU200/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_10g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py index 9abaf344e..acc3317f6 100644 --- a/fpga/mqnic/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -565,7 +565,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -576,6 +579,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -616,7 +622,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile index cdf83c7b5..a430b3059 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile @@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -61,7 +67,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile index d418b9605..381e297e7 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py index 5e76acaa0..15d0ab989 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -523,7 +523,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -534,6 +537,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -567,7 +573,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/AU250/fpga_10g/fpga/Makefile b/fpga/mqnic/AU250/fpga_10g/fpga/Makefile index 81b5f82fd..0d0e841e9 100644 --- a/fpga/mqnic/AU250/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_10g/fpga/Makefile @@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -78,7 +84,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/AU250/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_10g/tb/fpga_core/Makefile index 8b13a90f4..1f5af3000 100644 --- a/fpga/mqnic/AU250/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_10g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py index 9abaf344e..acc3317f6 100644 --- a/fpga/mqnic/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -565,7 +565,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -576,6 +579,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -616,7 +622,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile index c0cc8d3e8..27dec3bf6 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile @@ -12,7 +12,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -23,6 +26,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -60,7 +66,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile index d418b9605..381e297e7 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py index 2ef45cf78..7b925665a 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -512,7 +512,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -523,6 +526,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -556,7 +562,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/AU280/fpga_10g/fpga/Makefile b/fpga/mqnic/AU280/fpga_10g/fpga/Makefile index 0a5c5a7de..1aeb7a8ec 100644 --- a/fpga/mqnic/AU280/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_10g/fpga/Makefile @@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -77,7 +83,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/AU280/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_10g/tb/fpga_core/Makefile index 8b13a90f4..1f5af3000 100644 --- a/fpga/mqnic/AU280/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_10g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py index 1cb5d46ca..95c444284 100644 --- a/fpga/mqnic/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -554,7 +554,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -565,6 +568,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -605,7 +611,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile index 0a444dbaa..a3b10887d 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile @@ -12,7 +12,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -23,6 +26,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -60,7 +66,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile index a96fb3b3c..83bff77d5 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py index 5f4118777..a1a63f2fa 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -473,7 +473,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -484,6 +487,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -517,7 +523,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/AU50/fpga_10g/fpga/Makefile b/fpga/mqnic/AU50/fpga_10g/fpga/Makefile index 8da693777..aeca0e6f2 100644 --- a/fpga/mqnic/AU50/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_10g/fpga/Makefile @@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -77,7 +83,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/Makefile index 63f7768b5..1cb0a6052 100644 --- a/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py index e0e569915..c382b3278 100644 --- a/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -484,7 +484,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -495,6 +498,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -535,7 +541,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile b/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile index 3fda966be..d9e5fe9e8 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile +++ b/fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile @@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -74,7 +80,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile index cec9de640..12d97d02b 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py index f29c4f577..1ef54cb4b 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py @@ -472,7 +472,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -483,6 +486,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -523,7 +529,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile index df3be6e7e..1cc86f8d7 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile @@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -74,7 +80,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile index 02ae30cbf..784305037 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py index b26199ede..dbf6ff254 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -481,7 +481,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -492,6 +495,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -532,7 +538,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile index df3be6e7e..1cc86f8d7 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile @@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -74,7 +80,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile index 02ae30cbf..784305037 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py index 227177f1a..40079bf44 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -481,7 +481,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -492,6 +495,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -532,7 +538,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile index fbc0e582e..b303faea0 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile @@ -15,7 +15,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -26,6 +29,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -75,7 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile index 96efe6314..b41fa7bc2 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py index b3f8622b8..91f089a9d 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py @@ -487,7 +487,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -498,6 +501,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -538,7 +544,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile b/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile index 8c9e3ac28..6e93fddbb 100644 --- a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile @@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_s10.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -75,8 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v -SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile b/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile index f0a8b5d9f..31bd5296c 100644 --- a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile @@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_s10.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -75,8 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v -SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile index dbc7ec77f..f89fbd063 100644 --- a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_s10.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py index 8966ba439..2779c2bad 100644 --- a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -484,7 +484,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -495,6 +498,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -535,7 +541,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile b/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile index b5de78890..4e8eaa0bc 100644 --- a/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/VCU108/fpga_10g/fpga/Makefile @@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -75,7 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile index b591faf16..4aadcab2b 100644 --- a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py index 9d7158f3b..06342513b 100644 --- a/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -491,7 +491,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -502,6 +505,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -542,7 +548,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile index acd3ca7c7..e1237aa89 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile @@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -58,7 +64,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile index 3a1294dee..6ba72d17d 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py index 90779472a..fdd17f772 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -527,7 +527,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -538,6 +541,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -571,7 +577,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/VCU118/fpga_10g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_10g/fpga/Makefile index 845a62541..186fcb271 100644 --- a/fpga/mqnic/VCU118/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_10g/fpga/Makefile @@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -75,7 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/VCU118/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_10g/tb/fpga_core/Makefile index 6a5cda04d..0c55fd96b 100644 --- a/fpga/mqnic/VCU118/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_10g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py index 64132e501..13b93b5da 100644 --- a/fpga/mqnic/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -569,7 +569,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -580,6 +583,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -620,7 +626,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile index 2d0a55410..508abe57d 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile @@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -58,7 +64,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile index d418b9605..381e297e7 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py index 166fe804d..0b047b924 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -521,7 +521,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -532,6 +535,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -565,7 +571,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile index 7bddf045e..2051e227a 100644 --- a/fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile @@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -75,7 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/VCU1525/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_10g/tb/fpga_core/Makefile index 8b13a90f4..1f5af3000 100644 --- a/fpga/mqnic/VCU1525/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_10g/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py index 98f1b01e5..385cd55a7 100644 --- a/fpga/mqnic/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -563,7 +563,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -574,6 +577,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -614,7 +620,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile index b2fb0e873..94c352eab 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile @@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -75,7 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile index f337fb68b..fea5658a6 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile @@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py index e380b68d9..2aa99926d 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py @@ -475,7 +475,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -486,6 +489,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -526,7 +532,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile index 229f65831..25a687500 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile @@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -59,7 +65,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile index 73649b5f0..c9d58f074 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile @@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -61,7 +67,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile index 5bbba203f..190325199 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile @@ -44,7 +44,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -55,6 +58,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -88,7 +94,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py index e6ff3877b..230087d65 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -526,7 +526,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -537,6 +540,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -570,7 +576,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile index 663a5f2e5..6d8b71b96 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_10g/fpga/Makefile @@ -15,7 +15,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -26,6 +29,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -76,8 +82,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v -SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/fb2CG/fpga_10g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_10g/fpga_tdma/Makefile index 789194bfa..adb090ac5 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_10g/fpga_tdma/Makefile @@ -15,7 +15,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -26,6 +29,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -77,8 +83,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v -SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/Makefile index 686418c4e..0e98559bb 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/Makefile @@ -44,7 +44,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -55,6 +58,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -95,7 +101,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py index 74ff6f265..70195d374 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_10g/tb/fpga_core/test_fpga_core.py @@ -568,7 +568,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -579,6 +582,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -619,7 +625,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile index 663a5f2e5..6d8b71b96 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile @@ -15,7 +15,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -26,6 +29,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -76,8 +82,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v -SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile index 789194bfa..adb090ac5 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile @@ -15,7 +15,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v SYN_FILES += rtl/common/mqnic_interface.v -SYN_FILES += rtl/common/mqnic_port.v +SYN_FILES += rtl/common/mqnic_interface_tx.v +SYN_FILES += rtl/common/mqnic_interface_rx.v +SYN_FILES += rtl/common/mqnic_egress.v +SYN_FILES += rtl/common/mqnic_ingress.v SYN_FILES += rtl/common/mqnic_ptp.v SYN_FILES += rtl/common/mqnic_ptp_clock.v SYN_FILES += rtl/common/mqnic_ptp_perout.v @@ -26,6 +29,9 @@ SYN_FILES += rtl/common/desc_op_mux.v SYN_FILES += rtl/common/event_mux.v SYN_FILES += rtl/common/queue_manager.v SYN_FILES += rtl/common/cpl_queue_manager.v +SYN_FILES += rtl/common/tx_fifo.v +SYN_FILES += rtl/common/rx_fifo.v +SYN_FILES += rtl/common/tx_req_mux.v SYN_FILES += rtl/common/tx_engine.v SYN_FILES += rtl/common/rx_engine.v SYN_FILES += rtl/common/tx_checksum.v @@ -77,8 +83,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v SYN_FILES += lib/axis/rtl/axis_arb_mux.v SYN_FILES += lib/axis/rtl/axis_async_fifo.v SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v -SYN_FILES += lib/axis/rtl/axis_arb_mux.v +SYN_FILES += lib/axis/rtl/axis_demux.v SYN_FILES += lib/axis/rtl/axis_fifo.v +SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v SYN_FILES += lib/axis/rtl/axis_register.v SYN_FILES += lib/axis/rtl/sync_reset.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile index 686418c4e..0e98559bb 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile @@ -44,7 +44,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v -VERILOG_SOURCES += ../../rtl/common/mqnic_port.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v +VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v +VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v @@ -55,6 +58,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v VERILOG_SOURCES += ../../rtl/common/event_mux.v VERILOG_SOURCES += ../../rtl/common/queue_manager.v VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v +VERILOG_SOURCES += ../../rtl/common/tx_fifo.v +VERILOG_SOURCES += ../../rtl/common/rx_fifo.v +VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v VERILOG_SOURCES += ../../rtl/common/tx_engine.v VERILOG_SOURCES += ../../rtl/common/rx_engine.v VERILOG_SOURCES += ../../rtl/common/tx_checksum.v @@ -95,7 +101,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v +VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py index b0850720f..42a5305a5 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -568,7 +568,10 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), - os.path.join(rtl_dir, "common", "mqnic_port.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), + os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), + os.path.join(rtl_dir, "common", "mqnic_egress.v"), + os.path.join(rtl_dir, "common", "mqnic_ingress.v"), os.path.join(rtl_dir, "common", "mqnic_ptp.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"), os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"), @@ -579,6 +582,9 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "event_mux.v"), os.path.join(rtl_dir, "common", "queue_manager.v"), os.path.join(rtl_dir, "common", "cpl_queue_manager.v"), + os.path.join(rtl_dir, "common", "tx_fifo.v"), + os.path.join(rtl_dir, "common", "rx_fifo.v"), + os.path.join(rtl_dir, "common", "tx_req_mux.v"), os.path.join(rtl_dir, "common", "tx_engine.v"), os.path.join(rtl_dir, "common", "rx_engine.v"), os.path.join(rtl_dir, "common", "tx_checksum.v"), @@ -619,7 +625,9 @@ def test_fpga_core(request): os.path.join(axis_rtl_dir, "axis_arb_mux.v"), os.path.join(axis_rtl_dir, "axis_async_fifo.v"), os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), + os.path.join(axis_rtl_dir, "axis_demux.v"), os.path.join(axis_rtl_dir, "axis_fifo.v"), + os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"), os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"), os.path.join(axis_rtl_dir, "axis_register.v"), os.path.join(pcie_rtl_dir, "pcie_axil_master.v"), diff --git a/modules/mqnic/mqnic_hw.h b/modules/mqnic/mqnic_hw.h index 69ddf89ff..6973cdad8 100644 --- a/modules/mqnic/mqnic_hw.h +++ b/modules/mqnic/mqnic_hw.h @@ -323,7 +323,7 @@ struct mqnic_cpl { __le16 rx_csum; __le32 rx_hash; __u8 rx_hash_type; - __u8 rsvd1; + __u8 port; __u8 rsvd2; __u8 rsvd3; __le32 rsvd4;