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Initial implementation of shared interface datapath

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This commit is contained in:
Alex Forencich 2021-12-31 14:33:31 -08:00
parent ce21774f06
commit 335a5e890b
112 changed files with 4956 additions and 3010 deletions
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82
fpga/app/template/rtl/mqnic_app_block.v
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@ -105,8 +105,12 @@ module mqnic_app_block #
parameter AXIS_SYNC_RX_USER_WIDTH = AXIS_RX_USER_WIDTH,
// Ethernet interface configuration (interface)
parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH,
parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF),
parameter AXIS_IF_KEEP_WIDTH = AXIS_IF_DATA_WIDTH/8,
parameter AXIS_IF_TX_ID_WIDTH = 12,
parameter AXIS_IF_RX_ID_WIDTH = PORTS_PER_IF > 1 ? $clog2(PORTS_PER_IF) : 1,
parameter AXIS_IF_TX_DEST_WIDTH = $clog2(PORTS_PER_IF)+4,
parameter AXIS_IF_RX_DEST_WIDTH = 8,
parameter AXIS_IF_TX_USER_WIDTH = AXIS_SYNC_TX_USER_WIDTH,
parameter AXIS_IF_RX_USER_WIDTH = AXIS_SYNC_RX_USER_WIDTH,
@ -375,43 +379,51 @@ module mqnic_app_block #
/*
* Ethernet (internal at interface module)
*/
input wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] s_axis_if_tx_tdata,
input wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] s_axis_if_tx_tkeep,
input wire [PORT_COUNT-1:0] s_axis_if_tx_tvalid,
output wire [PORT_COUNT-1:0] s_axis_if_tx_tready,
input wire [PORT_COUNT-1:0] s_axis_if_tx_tlast,
input wire [PORT_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] s_axis_if_tx_tuser,
input wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] s_axis_if_tx_tdata,
input wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] s_axis_if_tx_tkeep,
input wire [IF_COUNT-1:0] s_axis_if_tx_tvalid,
output wire [IF_COUNT-1:0] s_axis_if_tx_tready,
input wire [IF_COUNT-1:0] s_axis_if_tx_tlast,
input wire [IF_COUNT*AXIS_IF_TX_ID_WIDTH-1:0] s_axis_if_tx_tid,
input wire [IF_COUNT*AXIS_IF_TX_DEST_WIDTH-1:0] s_axis_if_tx_tdest,
input wire [IF_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] s_axis_if_tx_tuser,
output wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] m_axis_if_tx_tdata,
output wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] m_axis_if_tx_tkeep,
output wire [PORT_COUNT-1:0] m_axis_if_tx_tvalid,
input wire [PORT_COUNT-1:0] m_axis_if_tx_tready,
output wire [PORT_COUNT-1:0] m_axis_if_tx_tlast,
output wire [PORT_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] m_axis_if_tx_tuser,
output wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] m_axis_if_tx_tdata,
output wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] m_axis_if_tx_tkeep,
output wire [IF_COUNT-1:0] m_axis_if_tx_tvalid,
input wire [IF_COUNT-1:0] m_axis_if_tx_tready,
output wire [IF_COUNT-1:0] m_axis_if_tx_tlast,
output wire [IF_COUNT*AXIS_IF_TX_ID_WIDTH-1:0] m_axis_if_tx_tid,
output wire [IF_COUNT*AXIS_IF_TX_DEST_WIDTH-1:0] m_axis_if_tx_tdest,
output wire [IF_COUNT*AXIS_IF_TX_USER_WIDTH-1:0] m_axis_if_tx_tuser,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_if_tx_ptp_ts,
input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_if_tx_ptp_ts_tag,
input wire [PORT_COUNT-1:0] s_axis_if_tx_ptp_ts_valid,
output wire [PORT_COUNT-1:0] s_axis_if_tx_ptp_ts_ready,
input wire [IF_COUNT*PTP_TS_WIDTH-1:0] s_axis_if_tx_ptp_ts,
input wire [IF_COUNT*PTP_TAG_WIDTH-1:0] s_axis_if_tx_ptp_ts_tag,
input wire [IF_COUNT-1:0] s_axis_if_tx_ptp_ts_valid,
output wire [IF_COUNT-1:0] s_axis_if_tx_ptp_ts_ready,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] m_axis_if_tx_ptp_ts,
output wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] m_axis_if_tx_ptp_ts_tag,
output wire [PORT_COUNT-1:0] m_axis_if_tx_ptp_ts_valid,
input wire [PORT_COUNT-1:0] m_axis_if_tx_ptp_ts_ready,
output wire [IF_COUNT*PTP_TS_WIDTH-1:0] m_axis_if_tx_ptp_ts,
output wire [IF_COUNT*PTP_TAG_WIDTH-1:0] m_axis_if_tx_ptp_ts_tag,
output wire [IF_COUNT-1:0] m_axis_if_tx_ptp_ts_valid,
input wire [IF_COUNT-1:0] m_axis_if_tx_ptp_ts_ready,
input wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] s_axis_if_rx_tdata,
input wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] s_axis_if_rx_tkeep,
input wire [PORT_COUNT-1:0] s_axis_if_rx_tvalid,
output wire [PORT_COUNT-1:0] s_axis_if_rx_tready,
input wire [PORT_COUNT-1:0] s_axis_if_rx_tlast,
input wire [PORT_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] s_axis_if_rx_tuser,
input wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] s_axis_if_rx_tdata,
input wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] s_axis_if_rx_tkeep,
input wire [IF_COUNT-1:0] s_axis_if_rx_tvalid,
output wire [IF_COUNT-1:0] s_axis_if_rx_tready,
input wire [IF_COUNT-1:0] s_axis_if_rx_tlast,
input wire [IF_COUNT*AXIS_IF_RX_ID_WIDTH-1:0] s_axis_if_rx_tid,
input wire [IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0] s_axis_if_rx_tdest,
input wire [IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] s_axis_if_rx_tuser,
output wire [PORT_COUNT*AXIS_IF_DATA_WIDTH-1:0] m_axis_if_rx_tdata,
output wire [PORT_COUNT*AXIS_IF_KEEP_WIDTH-1:0] m_axis_if_rx_tkeep,
output wire [PORT_COUNT-1:0] m_axis_if_rx_tvalid,
input wire [PORT_COUNT-1:0] m_axis_if_rx_tready,
output wire [PORT_COUNT-1:0] m_axis_if_rx_tlast,
output wire [PORT_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] m_axis_if_rx_tuser,
output wire [IF_COUNT*AXIS_IF_DATA_WIDTH-1:0] m_axis_if_rx_tdata,
output wire [IF_COUNT*AXIS_IF_KEEP_WIDTH-1:0] m_axis_if_rx_tkeep,
output wire [IF_COUNT-1:0] m_axis_if_rx_tvalid,
input wire [IF_COUNT-1:0] m_axis_if_rx_tready,
output wire [IF_COUNT-1:0] m_axis_if_rx_tlast,
output wire [IF_COUNT*AXIS_IF_RX_ID_WIDTH-1:0] m_axis_if_rx_tid,
output wire [IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0] m_axis_if_rx_tdest,
output wire [IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] m_axis_if_rx_tuser,
/*
* Statistics increment output
@ -523,6 +535,8 @@ assign m_axis_if_tx_tkeep = s_axis_if_tx_tkeep;
assign m_axis_if_tx_tvalid = s_axis_if_tx_tvalid;
assign s_axis_if_tx_tready = m_axis_if_tx_tready;
assign m_axis_if_tx_tlast = s_axis_if_tx_tlast;
assign m_axis_if_tx_tid = s_axis_if_tx_tid;
assign m_axis_if_tx_tdest = s_axis_if_tx_tdest;
assign m_axis_if_tx_tuser = s_axis_if_tx_tuser;
assign m_axis_if_tx_ptp_ts = s_axis_if_tx_ptp_ts;
@ -535,6 +549,8 @@ assign m_axis_if_rx_tkeep = s_axis_if_rx_tkeep;
assign m_axis_if_rx_tvalid = s_axis_if_rx_tvalid;
assign s_axis_if_rx_tready = m_axis_if_rx_tready;
assign m_axis_if_rx_tlast = s_axis_if_rx_tlast;
assign m_axis_if_rx_tid = s_axis_if_rx_tid;
assign m_axis_if_rx_tdest = s_axis_if_rx_tdest;
assign m_axis_if_rx_tuser = s_axis_if_rx_tuser;
/*

10
fpga/app/template/tb/mqnic_core_pcie_us/Makefile
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@ -42,7 +42,10 @@ VERILOG_SOURCES += ../../rtl/common/$(DUT).v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -53,6 +56,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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@ -594,7 +594,10 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -605,6 +608,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -639,7 +645,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

883
fpga/common/rtl/mqnic_core.v
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File diff suppressed because it is too large Load Diff

6
fpga/common/rtl/mqnic_core_axi.v
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@ -38,7 +38,7 @@ either expressed or implied, of The Regents of the University of California.
`default_nettype none
/*
* FPGA core logic
* mqnic core logic - AXI DMA wrapper
*/
module mqnic_core_axi #
(
@ -158,6 +158,7 @@ module mqnic_core_axi #
parameter AXIS_DATA_WIDTH = 64,
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH,
parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF),
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_RX_USE_READY = 0,
@ -368,7 +369,7 @@ parameter RAM_SEG_COUNT = 2;
parameter RAM_SEG_DATA_WIDTH = AXI_DATA_WIDTH*2/RAM_SEG_COUNT;
parameter RAM_SEG_ADDR_WIDTH = 12;
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8;
parameter IF_RAM_SEL_WIDTH = PORTS_PER_IF > 1 ? $clog2(PORTS_PER_IF) : 1;
parameter IF_RAM_SEL_WIDTH = 1;
parameter RAM_SEL_WIDTH = $clog2(IF_COUNT+(APP_ENABLE && APP_DMA_ENABLE ? 1 : 0))+IF_RAM_SEL_WIDTH+1;
parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH);
@ -651,6 +652,7 @@ mqnic_core #(
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
.AXIS_IF_DATA_WIDTH(AXIS_IF_DATA_WIDTH),
.AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH),
.AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH),
.AXIS_RX_USE_READY(AXIS_RX_USE_READY),

6
fpga/common/rtl/mqnic_core_pcie.v
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@ -38,7 +38,7 @@ either expressed or implied, of The Regents of the University of California.
`default_nettype none
/*
* FPGA core logic
* mqnic core logic - Generic PCIe DMA wrapper
*/
module mqnic_core_pcie #
(
@ -166,6 +166,7 @@ module mqnic_core_pcie #
parameter AXIS_DATA_WIDTH = 512,
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH,
parameter AXIS_IF_DATA_WIDTH = AXIS_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF),
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_RX_USE_READY = 0,
@ -380,7 +381,7 @@ parameter RAM_SEG_COUNT = TLP_SEG_COUNT*2;
parameter RAM_SEG_DATA_WIDTH = TLP_SEG_COUNT*TLP_SEG_DATA_WIDTH*2/RAM_SEG_COUNT;
parameter RAM_SEG_ADDR_WIDTH = 12;
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8;
parameter IF_RAM_SEL_WIDTH = PORTS_PER_IF > 1 ? $clog2(PORTS_PER_IF) : 1;
parameter IF_RAM_SEL_WIDTH = 1;
parameter RAM_SEL_WIDTH = $clog2(IF_COUNT+(APP_ENABLE && APP_DMA_ENABLE ? 1 : 0))+IF_RAM_SEL_WIDTH+1;
parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH);
@ -1407,6 +1408,7 @@ mqnic_core #(
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
.AXIS_IF_DATA_WIDTH(AXIS_IF_DATA_WIDTH),
.AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH),
.AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH),
.AXIS_RX_USE_READY(AXIS_RX_USE_READY),

2
fpga/common/rtl/mqnic_core_pcie_s10.v
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@ -163,6 +163,7 @@ module mqnic_core_pcie_s10 #
parameter AXIS_ETH_DATA_WIDTH = 512,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_IF_DATA_WIDTH = AXIS_ETH_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF),
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_RX_USE_READY = 0,
@ -687,6 +688,7 @@ mqnic_core_pcie #(
.AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.AXIS_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH),
.AXIS_IF_DATA_WIDTH(AXIS_ETH_IF_DATA_WIDTH),
.AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
.AXIS_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
.AXIS_RX_USE_READY(AXIS_ETH_RX_USE_READY),

4
fpga/common/rtl/mqnic_core_pcie_us.v
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@ -38,7 +38,7 @@ either expressed or implied, of The Regents of the University of California.
`default_nettype none
/*
* FPGA core logic
* mqnic core logic - Xilinx UltraScale/UltraScale+ wrapper
*/
module mqnic_core_pcie_us #
(
@ -164,6 +164,7 @@ module mqnic_core_pcie_us #
parameter AXIS_ETH_DATA_WIDTH = 512,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_IF_DATA_WIDTH = AXIS_ETH_SYNC_DATA_WIDTH*2**$clog2(PORTS_PER_IF),
parameter AXIS_ETH_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_RX_USE_READY = 0,
@ -777,6 +778,7 @@ mqnic_core_pcie #(
.AXIS_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.AXIS_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH),
.AXIS_IF_DATA_WIDTH(AXIS_ETH_IF_DATA_WIDTH),
.AXIS_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
.AXIS_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
.AXIS_RX_USE_READY(AXIS_ETH_RX_USE_READY),

218
fpga/common/rtl/mqnic_egress.v Normal file
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@ -0,0 +1,218 @@
/*
Copyright 2021, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* NIC egress processing
*/
module mqnic_egress #
(
// Enable TX checksum offload
parameter TX_CHECKSUM_ENABLE = 1,
// Width of AXI stream interfaces in bits
parameter AXIS_DATA_WIDTH = 256,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
// AXI stream tid signal width
parameter AXIS_ID_WIDTH = 8,
// AXI stream tdest signal width
parameter AXIS_DEST_WIDTH = 8,
// AXI stream tuser signal width
parameter AXIS_USER_WIDTH = 1,
// Max transmit packet size
parameter MAX_TX_SIZE = 2048
)
(
input wire clk,
input wire rst,
/*
* Transmit data input
*/
input wire [AXIS_DATA_WIDTH-1:0] s_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [AXIS_ID_WIDTH-1:0] s_axis_tid,
input wire [AXIS_DEST_WIDTH-1:0] s_axis_tdest,
input wire [AXIS_USER_WIDTH-1:0] s_axis_tuser,
/*
* Transmit data output
*/
output wire [AXIS_DATA_WIDTH-1:0] m_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [AXIS_ID_WIDTH-1:0] m_axis_tid,
output wire [AXIS_DEST_WIDTH-1:0] m_axis_tdest,
output wire [AXIS_USER_WIDTH-1:0] m_axis_tuser,
/*
* Transmit checksum command
*/
input wire tx_csum_cmd_csum_enable,
input wire [7:0] tx_csum_cmd_csum_start,
input wire [7:0] tx_csum_cmd_csum_offset,
input wire tx_csum_cmd_valid,
output wire tx_csum_cmd_ready
);
generate
if (TX_CHECKSUM_ENABLE) begin
wire tx_csum_cmd_csum_enable_int;
wire [7:0] tx_csum_cmd_csum_start_int;
wire [7:0] tx_csum_cmd_csum_offset_int;
wire tx_csum_cmd_valid_int;
wire tx_csum_cmd_ready_int;
axis_fifo #(
.DEPTH(32),
.DATA_WIDTH(1+8+8),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
tx_csum_cmd_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata({tx_csum_cmd_csum_enable, tx_csum_cmd_csum_start, tx_csum_cmd_csum_offset}),
.s_axis_tkeep(0),
.s_axis_tvalid(tx_csum_cmd_valid),
.s_axis_tready(tx_csum_cmd_ready),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_axis_tdata({tx_csum_cmd_csum_enable_int, tx_csum_cmd_csum_start_int, tx_csum_cmd_csum_offset_int}),
.m_axis_tkeep(),
.m_axis_tvalid(tx_csum_cmd_valid_int),
.m_axis_tready(tx_csum_cmd_ready_int),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
tx_checksum #(
.DATA_WIDTH(AXIS_DATA_WIDTH),
.ID_ENABLE(1),
.ID_WIDTH(AXIS_ID_WIDTH),
.DEST_ENABLE(1),
.DEST_WIDTH(AXIS_DEST_WIDTH),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_USER_WIDTH),
.USE_INIT_VALUE(0),
.DATA_FIFO_DEPTH(MAX_TX_SIZE),
.CHECKSUM_FIFO_DEPTH(64)
)
tx_checksum_inst (
.clk(clk),
.rst(rst),
/*
* AXI input
*/
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
/*
* AXI output
*/
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
/*
* Control
*/
.s_axis_cmd_csum_enable(tx_csum_cmd_csum_enable_int),
.s_axis_cmd_csum_start(tx_csum_cmd_csum_start_int),
.s_axis_cmd_csum_offset(tx_csum_cmd_csum_offset_int),
.s_axis_cmd_csum_init(16'd0),
.s_axis_cmd_valid(tx_csum_cmd_valid_int),
.s_axis_cmd_ready(tx_csum_cmd_ready_int)
);
end else begin
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = s_axis_tkeep;
assign m_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = m_axis_tready;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tid = s_axis_tid;
assign m_axis_tdest = s_axis_tdest;
assign m_axis_tuser = s_axis_tuser;
assign tx_csum_cmd_ready = 1'b1;
end
endgenerate
endmodule
`resetall

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fpga/common/rtl/mqnic_ingress.v Normal file
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/*
Copyright 2021, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* NIC ingress processing
*/
module mqnic_ingress #
(
// Request tag field width
parameter REQ_TAG_WIDTH = 8,
// Receive queue index width
parameter RX_QUEUE_INDEX_WIDTH = 8,
// Enable RX RSS
parameter RX_RSS_ENABLE = 1,
// Enable RX hashing
parameter RX_HASH_ENABLE = 1,
// Enable RX checksum offload
parameter RX_CHECKSUM_ENABLE = 1,
// Width of AXI stream interfaces in bits
parameter AXIS_DATA_WIDTH = 256,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
// AXI stream tid signal width
parameter AXIS_ID_WIDTH = 8,
// AXI stream tdest signal width
parameter AXIS_DEST_WIDTH = 8,
// AXI stream tuser signal width
parameter AXIS_USER_WIDTH = 1,
// Max receive packet size
parameter MAX_RX_SIZE = 2048
)
(
input wire clk,
input wire rst,
/*
* Receive data input
*/
input wire [AXIS_DATA_WIDTH-1:0] s_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [AXIS_ID_WIDTH-1:0] s_axis_tid,
input wire [AXIS_DEST_WIDTH-1:0] s_axis_tdest,
input wire [AXIS_USER_WIDTH-1:0] s_axis_tuser,
/*
* Receive data output
*/
output wire [AXIS_DATA_WIDTH-1:0] m_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [AXIS_ID_WIDTH-1:0] m_axis_tid,
output wire [AXIS_DEST_WIDTH-1:0] m_axis_tdest,
output wire [AXIS_USER_WIDTH-1:0] m_axis_tuser,
/*
* RX command output
*/
output wire [RX_QUEUE_INDEX_WIDTH-1:0] rx_req_queue,
output wire [REQ_TAG_WIDTH-1:0] rx_req_tag,
output wire rx_req_valid,
input wire rx_req_ready,
/*
* RX hash output
*/
output wire [31:0] rx_hash,
output wire [3:0] rx_hash_type,
output wire rx_hash_valid,
input wire rx_hash_ready,
/*
* RX checksum output
*/
output wire [15:0] rx_csum,
output wire rx_csum_valid,
input wire rx_csum_ready,
/*
* Configuration
*/
input wire [31:0] rss_mask
);
generate
wire [31:0] rx_hash_int;
wire [3:0] rx_hash_type_int;
wire rx_hash_valid_int;
if (RX_HASH_ENABLE) begin
rx_hash #(
.DATA_WIDTH(AXIS_DATA_WIDTH)
)
rx_hash_inst (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid & s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.hash_key(320'h6d5a56da255b0ec24167253d43a38fb0d0ca2bcbae7b30b477cb2da38030f20c6a42b73bbeac01fa),
.m_axis_hash(rx_hash_int),
.m_axis_hash_type(rx_hash_type_int),
.m_axis_hash_valid(rx_hash_valid_int)
);
axis_fifo #(
.DEPTH(32),
.DATA_WIDTH(32+4),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
rx_hash_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata({rx_hash_type_int, rx_hash_int}),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_hash_valid_int),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_axis_tdata({rx_hash_type, rx_hash}),
.m_axis_tkeep(),
.m_axis_tvalid(rx_hash_valid),
.m_axis_tready(rx_hash_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
end else begin
assign rx_hash = 32'd0;
assign rx_hash_type = 4'd0;
assign rx_hash_valid = 1'b0;
end
if (RX_RSS_ENABLE && RX_HASH_ENABLE) begin
axis_fifo #(
.DEPTH(AXIS_KEEP_WIDTH*32),
.DATA_WIDTH(AXIS_DATA_WIDTH),
.KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.KEEP_WIDTH(AXIS_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(1),
.ID_WIDTH(AXIS_ID_WIDTH),
.DEST_ENABLE(1),
.DEST_WIDTH(AXIS_DEST_WIDTH),
.USER_ENABLE(1),
.USER_WIDTH(AXIS_USER_WIDTH),
.FRAME_FIFO(0)
)
rx_hash_data_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
// Generate RX requests (RSS)
assign rx_req_tag = 0;
axis_fifo #(
.DEPTH(32),
.DATA_WIDTH(RX_QUEUE_INDEX_WIDTH),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
rx_req_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_hash_int & rss_mask),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_hash_valid_int),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_axis_tdata(rx_req_queue),
.m_axis_tkeep(),
.m_axis_tvalid(rx_req_valid),
.m_axis_tready(rx_req_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
end else begin
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = s_axis_tkeep;
assign m_axis_tvalid = s_axis_tvalid;
assign s_axis_tready = m_axis_tready;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tid = s_axis_tid;
assign m_axis_tdest = s_axis_tdest;
assign m_axis_tuser = s_axis_tuser;
// Generate RX requests (no RSS)
reg rx_frame_reg = 1'b0;
reg rx_req_valid_reg = 1'b0;
assign rx_req_queue = 0;
assign rx_req_tag = 0;
assign rx_req_valid = s_axis_tvalid && !rx_frame_reg;
always @(posedge clk) begin
if (rx_req_ready) begin
rx_req_valid_reg <= 1'b0;
end
if (s_axis_tready && s_axis_tvalid) begin
if (!rx_frame_reg) begin
rx_req_valid_reg <= 1'b1;
end
rx_frame_reg <= !s_axis_tlast;
end
if (rst) begin
rx_frame_reg <= 1'b0;
rx_req_valid_reg <= 1'b0;
end
end
end
if (RX_CHECKSUM_ENABLE) begin
wire [15:0] rx_csum_int;
wire rx_csum_valid_int;
rx_checksum #(
.DATA_WIDTH(AXIS_DATA_WIDTH)
)
rx_checksum_inst (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid & s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.m_axis_csum(rx_csum_int),
.m_axis_csum_valid(rx_csum_valid_int)
);
axis_fifo #(
.DEPTH(32),
.DATA_WIDTH(16),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.FRAME_FIFO(0)
)
rx_csum_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_csum_int),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_csum_valid_int),
.s_axis_tready(),
.s_axis_tlast(0),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(0),
// AXI output
.m_axis_tdata(rx_csum),
.m_axis_tkeep(),
.m_axis_tvalid(rx_csum_valid),
.m_axis_tready(rx_csum_ready),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
end else begin
assign rx_csum = 16'd0;
assign rx_csum_valid = 1'b0;
end
endgenerate
endmodule
`resetall

1383
fpga/common/rtl/mqnic_interface.v
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fpga/common/rtl/mqnic_interface_rx.v Normal file
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/*
Copyright 2021, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* NIC Interface RX path
*/
module mqnic_interface_rx #
(
// Number of ports
parameter PORTS = 1,
// DMA address width
parameter DMA_ADDR_WIDTH = 64,
// DMA length field width
parameter DMA_LEN_WIDTH = 16,
// DMA tag field width
parameter DMA_TAG_WIDTH = 8,
// Descriptor request tag field width
parameter DESC_REQ_TAG_WIDTH = 8,
// Queue request tag field width
parameter QUEUE_REQ_TAG_WIDTH = 8,
// Queue operation tag field width
parameter QUEUE_OP_TAG_WIDTH = 8,
// Receive queue index width
parameter RX_QUEUE_INDEX_WIDTH = 8,
// Max queue index width
parameter QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
// Receive completion queue index width
parameter RX_CPL_QUEUE_INDEX_WIDTH = 8,
// Max completion queue index width
parameter CPL_QUEUE_INDEX_WIDTH = RX_CPL_QUEUE_INDEX_WIDTH,
// Receive descriptor table size (number of in-flight operations)
parameter RX_DESC_TABLE_SIZE = 16,
// Width of descriptor table field for tracking outstanding DMA operations
parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4,
// Max number of in-flight descriptor requests (transmit)
parameter RX_MAX_DESC_REQ = 16,
// Receive descriptor FIFO size
parameter RX_DESC_FIFO_SIZE = RX_MAX_DESC_REQ*8,
// Queue element pointer width
parameter QUEUE_PTR_WIDTH = 16,
// Queue log size field width
parameter LOG_QUEUE_SIZE_WIDTH = 4,
// Log desc block size field width
parameter LOG_BLOCK_SIZE_WIDTH = 2,
// Enable PTP timestamping
parameter PTP_TS_ENABLE = 1,
// PTP timestamp width
parameter PTP_TS_WIDTH = 96,
// PTP tag width
parameter PTP_TAG_WIDTH = 16,
// Enable RX RSS
parameter RX_RSS_ENABLE = 1,
// Enable RX hashing
parameter RX_HASH_ENABLE = 1,
// Enable RX checksum offload
parameter RX_CHECKSUM_ENABLE = 1,
// DMA RAM segment count
parameter SEG_COUNT = 2,
// DMA RAM segment data width
parameter SEG_DATA_WIDTH = 64,
// DMA RAM segment address width
parameter SEG_ADDR_WIDTH = 8,
// DMA RAM segment byte enable width
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
// DMA RAM address width
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),
// DMA RAM pipeline stages
parameter RAM_PIPELINE = 2,
// Width of AXI stream interfaces in bits
parameter AXIS_DATA_WIDTH = 256,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
// AXI stream tid signal width
parameter AXIS_RX_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1,
// AXI stream tdest signal width
parameter AXIS_RX_DEST_WIDTH = RX_QUEUE_INDEX_WIDTH,
// AXI stream tuser signal width
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
// Max receive packet size
parameter MAX_RX_SIZE = 2048,
// DMA RX RAM size
parameter RX_RAM_SIZE = 8*MAX_RX_SIZE,
// Descriptor size (in bytes)
parameter DESC_SIZE = 16,
// Descriptor size (in bytes)
parameter CPL_SIZE = 32,
// Width of AXI stream descriptor interfaces in bits
parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8,
// AXI stream descriptor tkeep signal width (words per cycle)
parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8
)
(
input wire clk,
input wire rst,
/*
* Descriptor request output
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue,
output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag,
output wire m_axis_desc_req_valid,
input wire m_axis_desc_req_ready,
/*
* Descriptor request status input
*/
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
input wire s_axis_desc_req_status_empty,
input wire s_axis_desc_req_status_error,
input wire s_axis_desc_req_status_valid,
/*
* Descriptor data input
*/
input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata,
input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
input wire s_axis_desc_tvalid,
output wire s_axis_desc_tready,
input wire s_axis_desc_tlast,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_tid,
input wire s_axis_desc_tuser,
/*
* Completion request output
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
output wire m_axis_cpl_req_valid,
input wire m_axis_cpl_req_ready,
/*
* Completion request status input
*/
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag,
input wire s_axis_cpl_req_status_full,
input wire s_axis_cpl_req_status_error,
input wire s_axis_cpl_req_status_valid,
/*
* DMA write descriptor output (data)
*/
output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_write_desc_dma_addr,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_write_desc_ram_addr,
output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_write_desc_len,
output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_write_desc_tag,
output wire m_axis_dma_write_desc_valid,
input wire m_axis_dma_write_desc_ready,
/*
* DMA write descriptor status input (data)
*/
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_write_desc_status_tag,
input wire [3:0] s_axis_dma_write_desc_status_error,
input wire s_axis_dma_write_desc_status_valid,
/*
* RAM interface (data)
*/
input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr,
input wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid,
output wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready,
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data,
output wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid,
input wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready,
/*
* Receive data input
*/
input wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata,
input wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep,
input wire rx_axis_tvalid,
output wire rx_axis_tready,
input wire rx_axis_tlast,
input wire [AXIS_RX_ID_WIDTH-1:0] rx_axis_tid,
input wire [AXIS_RX_DEST_WIDTH-1:0] rx_axis_tdest,
input wire [AXIS_RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* PTP clock
*/
input wire [95:0] ptp_ts_96,
input wire ptp_ts_step,
/*
* Configuration
*/
input wire [DMA_CLIENT_LEN_WIDTH-1:0] mtu,
input wire [31:0] rss_mask
);
parameter DMA_CLIENT_TAG_WIDTH = $clog2(RX_DESC_TABLE_SIZE);
parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH;
parameter REQ_TAG_WIDTH = $clog2(RX_DESC_TABLE_SIZE);
wire [AXIS_DESC_DATA_WIDTH-1:0] rx_fifo_desc_tdata;
wire [AXIS_DESC_KEEP_WIDTH-1:0] rx_fifo_desc_tkeep;
wire rx_fifo_desc_tvalid;
wire rx_fifo_desc_tready;
wire rx_fifo_desc_tlast;
wire [DESC_REQ_TAG_WIDTH-1:0] rx_fifo_desc_tid;
wire rx_fifo_desc_tuser;
axis_fifo #(
.DEPTH(RX_DESC_FIFO_SIZE*DESC_SIZE),
.DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
.KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(1),
.ID_WIDTH(DESC_REQ_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.PIPELINE_OUTPUT(3),
.FRAME_FIFO(0)
)
rx_desc_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_desc_tdata),
.s_axis_tkeep(s_axis_desc_tkeep),
.s_axis_tvalid(s_axis_desc_tvalid),
.s_axis_tready(s_axis_desc_tready),
.s_axis_tlast(s_axis_desc_tlast),
.s_axis_tid(s_axis_desc_tid),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_desc_tuser),
// AXI output
.m_axis_tdata(rx_fifo_desc_tdata),
.m_axis_tkeep(rx_fifo_desc_tkeep),
.m_axis_tvalid(rx_fifo_desc_tvalid),
.m_axis_tready(rx_fifo_desc_tready),
.m_axis_tlast(rx_fifo_desc_tlast),
.m_axis_tid(rx_fifo_desc_tid),
.m_axis_tdest(),
.m_axis_tuser(rx_fifo_desc_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
wire [RX_QUEUE_INDEX_WIDTH-1:0] rx_req_queue;
wire [REQ_TAG_WIDTH-1:0] rx_req_tag;
wire rx_req_valid;
wire rx_req_ready;
wire [31:0] rx_hash;
wire [3:0] rx_hash_type;
wire rx_hash_valid;
wire rx_hash_ready;
wire [15:0] rx_csum;
wire rx_csum_valid;
wire rx_csum_ready;
wire [RAM_ADDR_WIDTH-1:0] dma_rx_desc_addr;
wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_len;
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_tag;
wire dma_rx_desc_valid;
wire dma_rx_desc_ready;
wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_rx_desc_status_len;
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_rx_desc_status_tag;
wire [AXIS_RX_ID_WIDTH-1:0] dma_rx_desc_status_id;
wire [AXIS_RX_DEST_WIDTH-1:0] dma_rx_desc_status_dest;
wire [AXIS_RX_USER_WIDTH-1:0] dma_rx_desc_status_user;
wire [3:0] dma_rx_desc_status_error;
wire dma_rx_desc_status_valid;
rx_engine #(
.PORTS(PORTS),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH),
.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH),
.MAX_RX_SIZE(MAX_RX_SIZE),
.RX_BUFFER_OFFSET(0),
.RX_BUFFER_SIZE(RX_RAM_SIZE),
.RX_BUFFER_STEP_SIZE(SEG_COUNT*SEG_BE_WIDTH),
.DESC_SIZE(DESC_SIZE),
.CPL_SIZE(CPL_SIZE),
.MAX_DESC_REQ(RX_MAX_DESC_REQ),
.AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
.AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.AXIS_RX_ID_WIDTH(AXIS_RX_ID_WIDTH),
.AXIS_RX_DEST_WIDTH(AXIS_RX_DEST_WIDTH),
.AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH)
)
rx_engine_inst (
.clk(clk),
.rst(rst),
/*
* Receive request input (queue index)
*/
.s_axis_rx_req_queue(rx_req_queue),
.s_axis_rx_req_tag(rx_req_tag),
.s_axis_rx_req_valid(rx_req_valid),
.s_axis_rx_req_ready(rx_req_ready),
/*
* Receive request status output
*/
.m_axis_rx_req_status_tag(),
.m_axis_rx_req_status_len(),
.m_axis_rx_req_status_valid(),
/*
* Descriptor request output
*/
.m_axis_desc_req_queue(m_axis_desc_req_queue),
.m_axis_desc_req_tag(m_axis_desc_req_tag),
.m_axis_desc_req_valid(m_axis_desc_req_valid),
.m_axis_desc_req_ready(m_axis_desc_req_ready),
/*
* Descriptor request status input
*/
.s_axis_desc_req_status_queue(s_axis_desc_req_status_queue),
.s_axis_desc_req_status_ptr(s_axis_desc_req_status_ptr),
.s_axis_desc_req_status_cpl(s_axis_desc_req_status_cpl),
.s_axis_desc_req_status_tag(s_axis_desc_req_status_tag),
.s_axis_desc_req_status_empty(s_axis_desc_req_status_empty),
.s_axis_desc_req_status_error(s_axis_desc_req_status_error),
.s_axis_desc_req_status_valid(s_axis_desc_req_status_valid),
/*
* Descriptor data input
*/
.s_axis_desc_tdata(rx_fifo_desc_tdata),
.s_axis_desc_tkeep(rx_fifo_desc_tkeep),
.s_axis_desc_tvalid(rx_fifo_desc_tvalid),
.s_axis_desc_tready(rx_fifo_desc_tready),
.s_axis_desc_tlast(rx_fifo_desc_tlast),
.s_axis_desc_tid(rx_fifo_desc_tid),
.s_axis_desc_tuser(rx_fifo_desc_tuser),
/*
* Completion request output
*/
.m_axis_cpl_req_queue(m_axis_cpl_req_queue),
.m_axis_cpl_req_tag(m_axis_cpl_req_tag),
.m_axis_cpl_req_data(m_axis_cpl_req_data),
.m_axis_cpl_req_valid(m_axis_cpl_req_valid),
.m_axis_cpl_req_ready(m_axis_cpl_req_ready),
/*
* Completion request status input
*/
.s_axis_cpl_req_status_tag(s_axis_cpl_req_status_tag),
.s_axis_cpl_req_status_full(s_axis_cpl_req_status_full),
.s_axis_cpl_req_status_error(s_axis_cpl_req_status_error),
.s_axis_cpl_req_status_valid(s_axis_cpl_req_status_valid),
/*
* DMA write descriptor output
*/
.m_axis_dma_write_desc_dma_addr(m_axis_dma_write_desc_dma_addr),
.m_axis_dma_write_desc_ram_addr(m_axis_dma_write_desc_ram_addr),
.m_axis_dma_write_desc_len(m_axis_dma_write_desc_len),
.m_axis_dma_write_desc_tag(m_axis_dma_write_desc_tag),
.m_axis_dma_write_desc_valid(m_axis_dma_write_desc_valid),
.m_axis_dma_write_desc_ready(m_axis_dma_write_desc_ready),
/*
* DMA write descriptor status input
*/
.s_axis_dma_write_desc_status_tag(s_axis_dma_write_desc_status_tag),
.s_axis_dma_write_desc_status_error(s_axis_dma_write_desc_status_error),
.s_axis_dma_write_desc_status_valid(s_axis_dma_write_desc_status_valid),
/*
* Receive descriptor output
*/
.m_axis_rx_desc_addr(dma_rx_desc_addr),
.m_axis_rx_desc_len(dma_rx_desc_len),
.m_axis_rx_desc_tag(dma_rx_desc_tag),
.m_axis_rx_desc_valid(dma_rx_desc_valid),
.m_axis_rx_desc_ready(dma_rx_desc_ready),
/*
* Receive descriptor status input
*/
.s_axis_rx_desc_status_len(dma_rx_desc_status_len),
.s_axis_rx_desc_status_tag(dma_rx_desc_status_tag),
.s_axis_rx_desc_status_id(dma_rx_desc_status_id),
.s_axis_rx_desc_status_dest(dma_rx_desc_status_dest),
.s_axis_rx_desc_status_user(dma_rx_desc_status_user),
.s_axis_rx_desc_status_error(dma_rx_desc_status_error),
.s_axis_rx_desc_status_valid(dma_rx_desc_status_valid),
/*
* Receive hash input
*/
.s_axis_rx_hash(rx_hash),
.s_axis_rx_hash_type(rx_hash_type),
.s_axis_rx_hash_valid(rx_hash_valid),
.s_axis_rx_hash_ready(rx_hash_ready),
/*
* Receive checksum input
*/
.s_axis_rx_csum(rx_csum),
.s_axis_rx_csum_valid(rx_csum_valid),
.s_axis_rx_csum_ready(rx_csum_ready),
/*
* Configuration
*/
.mtu(mtu),
.enable(1'b1)
);
wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be_int;
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr_int;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data_int;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid_int;
wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready_int;
wire [SEG_COUNT-1:0] dma_ram_wr_done_int;
dma_psdpram #(
.SIZE(RX_RAM_SIZE),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.PIPELINE(RAM_PIPELINE)
)
dma_psdpram_rx_inst (
.clk(clk),
.rst(rst),
/*
* Write port
*/
.wr_cmd_be(dma_ram_wr_cmd_be_int),
.wr_cmd_addr(dma_ram_wr_cmd_addr_int),
.wr_cmd_data(dma_ram_wr_cmd_data_int),
.wr_cmd_valid(dma_ram_wr_cmd_valid_int),
.wr_cmd_ready(dma_ram_wr_cmd_ready_int),
.wr_done(dma_ram_wr_done_int),
/*
* Read port
*/
.rd_cmd_addr(dma_ram_rd_cmd_addr),
.rd_cmd_valid(dma_ram_rd_cmd_valid),
.rd_cmd_ready(dma_ram_rd_cmd_ready),
.rd_resp_data(dma_ram_rd_resp_data),
.rd_resp_valid(dma_ram_rd_resp_valid),
.rd_resp_ready(dma_ram_rd_resp_ready)
);
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata_int;
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep_int;
wire rx_axis_tvalid_int;
wire rx_axis_tready_int;
wire rx_axis_tlast_int;
wire [AXIS_RX_ID_WIDTH-1:0] rx_axis_tid_int;
wire [AXIS_RX_DEST_WIDTH-1:0] rx_axis_tdest_int;
wire [AXIS_RX_USER_WIDTH-1:0] rx_axis_tuser_int;
mqnic_ingress #(
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_ID_WIDTH(AXIS_RX_ID_WIDTH),
.AXIS_DEST_WIDTH(AXIS_RX_DEST_WIDTH),
.AXIS_USER_WIDTH(AXIS_RX_USER_WIDTH),
.MAX_RX_SIZE(MAX_RX_SIZE)
)
ingress_inst (
.clk(clk),
.rst(rst),
/*
* Receive data input
*/
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tid(rx_axis_tid),
.s_axis_tdest(rx_axis_tdest),
.s_axis_tuser(rx_axis_tuser),
/*
* Receive data output
*/
.m_axis_tdata(rx_axis_tdata_int),
.m_axis_tkeep(rx_axis_tkeep_int),
.m_axis_tvalid(rx_axis_tvalid_int),
.m_axis_tready(rx_axis_tready_int),
.m_axis_tlast(rx_axis_tlast_int),
.m_axis_tid(rx_axis_tid_int),
.m_axis_tdest(rx_axis_tdest_int),
.m_axis_tuser(rx_axis_tuser_int),
/*
* RX command output
*/
.rx_req_queue(rx_req_queue),
.rx_req_tag(rx_req_tag),
.rx_req_valid(rx_req_valid),
.rx_req_ready(rx_req_ready),
/*
* RX hash output
*/
.rx_hash(rx_hash),
.rx_hash_type(rx_hash_type),
.rx_hash_valid(rx_hash_valid),
.rx_hash_ready(rx_hash_ready),
/*
* RX checksum output
*/
.rx_csum(rx_csum),
.rx_csum_valid(rx_csum_valid),
.rx_csum_ready(rx_csum_ready),
/*
* Configuration
*/
.rss_mask(rss_mask)
);
dma_client_axis_sink #(
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_LAST_ENABLE(1),
.AXIS_ID_ENABLE(1),
.AXIS_ID_WIDTH(AXIS_RX_ID_WIDTH),
.AXIS_DEST_ENABLE(1),
.AXIS_DEST_WIDTH(AXIS_RX_DEST_WIDTH),
.AXIS_USER_ENABLE(1),
.AXIS_USER_WIDTH(AXIS_RX_USER_WIDTH),
.LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
.TAG_WIDTH(DMA_CLIENT_TAG_WIDTH)
)
dma_client_axis_sink_inst (
.clk(clk),
.rst(rst),
/*
* DMA write descriptor input
*/
.s_axis_write_desc_ram_addr(dma_rx_desc_addr),
.s_axis_write_desc_len(dma_rx_desc_len),
.s_axis_write_desc_tag(dma_rx_desc_tag),
.s_axis_write_desc_valid(dma_rx_desc_valid),
.s_axis_write_desc_ready(dma_rx_desc_ready),
/*
* DMA write descriptor status output
*/
.m_axis_write_desc_status_len(dma_rx_desc_status_len),
.m_axis_write_desc_status_tag(dma_rx_desc_status_tag),
.m_axis_write_desc_status_id(dma_rx_desc_status_id),
.m_axis_write_desc_status_dest(dma_rx_desc_status_dest),
.m_axis_write_desc_status_user(dma_rx_desc_status_user),
.m_axis_write_desc_status_error(dma_rx_desc_status_error),
.m_axis_write_desc_status_valid(dma_rx_desc_status_valid),
/*
* AXI stream write data input
*/
.s_axis_write_data_tdata(rx_axis_tdata_int),
.s_axis_write_data_tkeep(rx_axis_tkeep_int),
.s_axis_write_data_tvalid(rx_axis_tvalid_int),
.s_axis_write_data_tready(rx_axis_tready_int),
.s_axis_write_data_tlast(rx_axis_tlast_int),
.s_axis_write_data_tid(rx_axis_tid_int),
.s_axis_write_data_tdest(rx_axis_tdest_int),
.s_axis_write_data_tuser(rx_axis_tuser_int),
/*
* RAM interface
*/
.ram_wr_cmd_be(dma_ram_wr_cmd_be_int),
.ram_wr_cmd_addr(dma_ram_wr_cmd_addr_int),
.ram_wr_cmd_data(dma_ram_wr_cmd_data_int),
.ram_wr_cmd_valid(dma_ram_wr_cmd_valid_int),
.ram_wr_cmd_ready(dma_ram_wr_cmd_ready_int),
.ram_wr_done(dma_ram_wr_done_int),
/*
* Configuration
*/
.enable(1'b1),
.abort(1'b0)
);
endmodule
`resetall

659
fpga/common/rtl/mqnic_interface_tx.v Normal file
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@ -0,0 +1,659 @@
/*
Copyright 2021, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* NIC Interface TX path
*/
module mqnic_interface_tx #
(
// Number of ports
parameter PORTS = 1,
// DMA address width
parameter DMA_ADDR_WIDTH = 64,
// DMA length field width
parameter DMA_LEN_WIDTH = 16,
// DMA tag field width
parameter DMA_TAG_WIDTH = 8,
// Transmit request tag field width
parameter REQ_TAG_WIDTH = 8,
// Descriptor request tag field width
parameter DESC_REQ_TAG_WIDTH = 8,
// Queue request tag field width
parameter QUEUE_REQ_TAG_WIDTH = 8,
// Queue operation tag field width
parameter QUEUE_OP_TAG_WIDTH = 8,
// Transmit queue index width
parameter TX_QUEUE_INDEX_WIDTH = 8,
// Max queue index width
parameter QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
// Transmit completion queue index width
parameter TX_CPL_QUEUE_INDEX_WIDTH = 8,
// Max completion queue index width
parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH,
// Transmit descriptor table size (number of in-flight operations)
parameter TX_DESC_TABLE_SIZE = 16,
// Width of descriptor table field for tracking outstanding DMA operations
parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4,
// Max number of in-flight descriptor requests (transmit)
parameter TX_MAX_DESC_REQ = 16,
// Transmit descriptor FIFO size
parameter TX_DESC_FIFO_SIZE = TX_MAX_DESC_REQ*8,
// Scheduler operation table size
parameter TX_SCHEDULER_OP_TABLE_SIZE = 32,
// Scheduler pipeline setting
parameter TX_SCHEDULER_PIPELINE = 3,
// Scheduler TDMA index width
parameter TDMA_INDEX_WIDTH = 8,
// Interrupt number width
parameter INT_WIDTH = 8,
// Queue element pointer width
parameter QUEUE_PTR_WIDTH = 16,
// Queue log size field width
parameter LOG_QUEUE_SIZE_WIDTH = 4,
// Log desc block size field width
parameter LOG_BLOCK_SIZE_WIDTH = 2,
// Enable PTP timestamping
parameter PTP_TS_ENABLE = 1,
// PTP timestamp width
parameter PTP_TS_WIDTH = 96,
// PTP tag width
parameter PTP_TAG_WIDTH = 16,
// Enable TX checksum offload
parameter TX_CHECKSUM_ENABLE = 1,
// DMA RAM segment count
parameter SEG_COUNT = 2,
// DMA RAM segment data width
parameter SEG_DATA_WIDTH = 64,
// DMA RAM segment address width
parameter SEG_ADDR_WIDTH = 8,
// DMA RAM segment byte enable width
parameter SEG_BE_WIDTH = SEG_DATA_WIDTH/8,
// DMA RAM address width
parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH),
// DMA RAM pipeline stages
parameter RAM_PIPELINE = 2,
// Width of AXI stream interfaces in bits
parameter AXIS_DATA_WIDTH = 256,
// AXI stream tkeep signal width (words per cycle)
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
// AXI stream tid signal width
parameter AXIS_TX_ID_WIDTH = TX_QUEUE_INDEX_WIDTH,
// AXI stream tdest signal width
parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4,
// AXI stream tuser signal width
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
// Max transmit packet size
parameter MAX_TX_SIZE = 2048,
// DMA TX RAM size
parameter TX_RAM_SIZE = 8*MAX_TX_SIZE,
// Descriptor size (in bytes)
parameter DESC_SIZE = 16,
// Descriptor size (in bytes)
parameter CPL_SIZE = 32,
// Width of AXI stream descriptor interfaces in bits
parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8,
// AXI stream descriptor tkeep signal width (words per cycle)
parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8
)
(
input wire clk,
input wire rst,
/*
* Transmit request input (queue index)
*/
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_req_queue,
input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_req_tag,
input wire [AXIS_TX_DEST_WIDTH-1:0] s_axis_tx_req_dest,
input wire s_axis_tx_req_valid,
output wire s_axis_tx_req_ready,
/*
* Transmit request status output
*/
output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_req_status_len,
output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_status_tag,
output wire m_axis_tx_req_status_valid,
/*
* Descriptor request output
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_desc_req_queue,
output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_desc_req_tag,
output wire m_axis_desc_req_valid,
input wire m_axis_desc_req_ready,
/*
* Descriptor request status input
*/
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_queue,
input wire [QUEUE_PTR_WIDTH-1:0] s_axis_desc_req_status_ptr,
input wire [CPL_QUEUE_INDEX_WIDTH-1:0] s_axis_desc_req_status_cpl,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_req_status_tag,
input wire s_axis_desc_req_status_empty,
input wire s_axis_desc_req_status_error,
input wire s_axis_desc_req_status_valid,
/*
* Descriptor data input
*/
input wire [AXIS_DESC_DATA_WIDTH-1:0] s_axis_desc_tdata,
input wire [AXIS_DESC_KEEP_WIDTH-1:0] s_axis_desc_tkeep,
input wire s_axis_desc_tvalid,
output wire s_axis_desc_tready,
input wire s_axis_desc_tlast,
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_desc_tid,
input wire s_axis_desc_tuser,
/*
* Completion request output
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_cpl_req_queue,
output wire [DESC_REQ_TAG_WIDTH-1:0] m_axis_cpl_req_tag,
output wire [CPL_SIZE*8-1:0] m_axis_cpl_req_data,
output wire m_axis_cpl_req_valid,
input wire m_axis_cpl_req_ready,
/*
* Completion request status input
*/
input wire [DESC_REQ_TAG_WIDTH-1:0] s_axis_cpl_req_status_tag,
input wire s_axis_cpl_req_status_full,
input wire s_axis_cpl_req_status_error,
input wire s_axis_cpl_req_status_valid,
/*
* DMA read descriptor output (data)
*/
output wire [DMA_ADDR_WIDTH-1:0] m_axis_dma_read_desc_dma_addr,
output wire [RAM_ADDR_WIDTH-1:0] m_axis_dma_read_desc_ram_addr,
output wire [DMA_LEN_WIDTH-1:0] m_axis_dma_read_desc_len,
output wire [DMA_TAG_WIDTH-1:0] m_axis_dma_read_desc_tag,
output wire m_axis_dma_read_desc_valid,
input wire m_axis_dma_read_desc_ready,
/*
* DMA read descriptor status input (data)
*/
input wire [DMA_TAG_WIDTH-1:0] s_axis_dma_read_desc_status_tag,
input wire [3:0] s_axis_dma_read_desc_status_error,
input wire s_axis_dma_read_desc_status_valid,
/*
* RAM interface (data)
*/
input wire [SEG_COUNT*SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be,
input wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr,
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data,
input wire [SEG_COUNT-1:0] dma_ram_wr_cmd_valid,
output wire [SEG_COUNT-1:0] dma_ram_wr_cmd_ready,
output wire [SEG_COUNT-1:0] dma_ram_wr_done,
/*
* Transmit data output
*/
output wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata,
output wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep,
output wire tx_axis_tvalid,
input wire tx_axis_tready,
output wire tx_axis_tlast,
output wire [AXIS_TX_ID_WIDTH-1:0] tx_axis_tid,
output wire [AXIS_TX_DEST_WIDTH-1:0] tx_axis_tdest,
output wire [AXIS_TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* Transmit timestamp input
*/
input wire [PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts,
input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire s_axis_tx_ptp_ts_valid,
output wire s_axis_tx_ptp_ts_ready,
/*
* PTP clock
*/
input wire [95:0] ptp_ts_96,
input wire ptp_ts_step,
/*
* Configuration
*/
input wire [DMA_CLIENT_LEN_WIDTH-1:0] mtu
);
parameter DMA_CLIENT_TAG_WIDTH = $clog2(TX_DESC_TABLE_SIZE);
parameter DMA_CLIENT_LEN_WIDTH = DMA_LEN_WIDTH;
wire [AXIS_DESC_DATA_WIDTH-1:0] tx_fifo_desc_tdata;
wire [AXIS_DESC_KEEP_WIDTH-1:0] tx_fifo_desc_tkeep;
wire tx_fifo_desc_tvalid;
wire tx_fifo_desc_tready;
wire tx_fifo_desc_tlast;
wire [DESC_REQ_TAG_WIDTH-1:0] tx_fifo_desc_tid;
wire tx_fifo_desc_tuser;
axis_fifo #(
.DEPTH(TX_DESC_FIFO_SIZE*DESC_SIZE),
.DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
.KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
.LAST_ENABLE(1),
.ID_ENABLE(1),
.ID_WIDTH(DESC_REQ_TAG_WIDTH),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.PIPELINE_OUTPUT(3),
.FRAME_FIFO(0)
)
tx_desc_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_desc_tdata),
.s_axis_tkeep(s_axis_desc_tkeep),
.s_axis_tvalid(s_axis_desc_tvalid),
.s_axis_tready(s_axis_desc_tready),
.s_axis_tlast(s_axis_desc_tlast),
.s_axis_tid(s_axis_desc_tid),
.s_axis_tdest(0),
.s_axis_tuser(s_axis_desc_tuser),
// AXI output
.m_axis_tdata(tx_fifo_desc_tdata),
.m_axis_tkeep(tx_fifo_desc_tkeep),
.m_axis_tvalid(tx_fifo_desc_tvalid),
.m_axis_tready(tx_fifo_desc_tready),
.m_axis_tlast(tx_fifo_desc_tlast),
.m_axis_tid(tx_fifo_desc_tid),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_desc_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
wire tx_csum_cmd_csum_enable;
wire [7:0] tx_csum_cmd_csum_start;
wire [7:0] tx_csum_cmd_csum_offset;
wire tx_csum_cmd_valid;
wire tx_csum_cmd_ready;
wire [RAM_ADDR_WIDTH-1:0] dma_tx_desc_addr;
wire [DMA_CLIENT_LEN_WIDTH-1:0] dma_tx_desc_len;
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_tx_desc_tag;
wire [AXIS_TX_ID_WIDTH-1:0] dma_tx_desc_id;
wire [AXIS_TX_DEST_WIDTH-1:0] dma_tx_desc_dest;
wire [AXIS_TX_USER_WIDTH-1:0] dma_tx_desc_user;
wire dma_tx_desc_valid;
wire dma_tx_desc_ready;
wire [DMA_CLIENT_TAG_WIDTH-1:0] dma_tx_desc_status_tag;
wire [3:0] dma_tx_desc_status_error;
wire dma_tx_desc_status_valid;
tx_engine #(
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_CLIENT_LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
.REQ_TAG_WIDTH(REQ_TAG_WIDTH),
.DESC_REQ_TAG_WIDTH(DESC_REQ_TAG_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.DMA_CLIENT_TAG_WIDTH(DMA_CLIENT_TAG_WIDTH),
.QUEUE_REQ_TAG_WIDTH(QUEUE_REQ_TAG_WIDTH),
.QUEUE_OP_TAG_WIDTH(QUEUE_OP_TAG_WIDTH),
.QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.QUEUE_PTR_WIDTH(QUEUE_PTR_WIDTH),
.CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.DESC_TABLE_DMA_OP_COUNT_WIDTH(DESC_TABLE_DMA_OP_COUNT_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.TX_BUFFER_OFFSET(0),
.TX_BUFFER_SIZE(TX_RAM_SIZE),
.TX_BUFFER_STEP_SIZE(SEG_COUNT*SEG_BE_WIDTH),
.DESC_SIZE(DESC_SIZE),
.CPL_SIZE(CPL_SIZE),
.MAX_DESC_REQ(TX_MAX_DESC_REQ),
.AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH),
.AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.AXIS_TX_ID_WIDTH(AXIS_TX_ID_WIDTH),
.AXIS_TX_DEST_WIDTH(AXIS_TX_DEST_WIDTH),
.AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH)
)
tx_engine_inst (
.clk(clk),
.rst(rst),
/*
* Transmit request input (queue index)
*/
.s_axis_tx_req_queue(s_axis_tx_req_queue),
.s_axis_tx_req_tag(s_axis_tx_req_tag),
.s_axis_tx_req_dest(s_axis_tx_req_dest),
.s_axis_tx_req_valid(s_axis_tx_req_valid),
.s_axis_tx_req_ready(s_axis_tx_req_ready),
/*
* Transmit request status output
*/
.m_axis_tx_req_status_len(m_axis_tx_req_status_len),
.m_axis_tx_req_status_tag(m_axis_tx_req_status_tag),
.m_axis_tx_req_status_valid(m_axis_tx_req_status_valid),
/*
* Descriptor request output
*/
.m_axis_desc_req_queue(m_axis_desc_req_queue),
.m_axis_desc_req_tag(m_axis_desc_req_tag),
.m_axis_desc_req_valid(m_axis_desc_req_valid),
.m_axis_desc_req_ready(m_axis_desc_req_ready),
/*
* Descriptor request status input
*/
.s_axis_desc_req_status_queue(s_axis_desc_req_status_queue),
.s_axis_desc_req_status_ptr(s_axis_desc_req_status_ptr),
.s_axis_desc_req_status_cpl(s_axis_desc_req_status_cpl),
.s_axis_desc_req_status_tag(s_axis_desc_req_status_tag),
.s_axis_desc_req_status_empty(s_axis_desc_req_status_empty),
.s_axis_desc_req_status_error(s_axis_desc_req_status_error),
.s_axis_desc_req_status_valid(s_axis_desc_req_status_valid),
/*
* Descriptor data input
*/
.s_axis_desc_tdata(tx_fifo_desc_tdata),
.s_axis_desc_tkeep(tx_fifo_desc_tkeep),
.s_axis_desc_tvalid(tx_fifo_desc_tvalid),
.s_axis_desc_tready(tx_fifo_desc_tready),
.s_axis_desc_tlast(tx_fifo_desc_tlast),
.s_axis_desc_tid(tx_fifo_desc_tid),
.s_axis_desc_tuser(tx_fifo_desc_tuser),
/*
* Completion request output
*/
.m_axis_cpl_req_queue(m_axis_cpl_req_queue),
.m_axis_cpl_req_tag(m_axis_cpl_req_tag),
.m_axis_cpl_req_data(m_axis_cpl_req_data),
.m_axis_cpl_req_valid(m_axis_cpl_req_valid),
.m_axis_cpl_req_ready(m_axis_cpl_req_ready),
/*
* Completion request status input
*/
.s_axis_cpl_req_status_tag(s_axis_cpl_req_status_tag),
.s_axis_cpl_req_status_full(s_axis_cpl_req_status_full),
.s_axis_cpl_req_status_error(s_axis_cpl_req_status_error),
.s_axis_cpl_req_status_valid(s_axis_cpl_req_status_valid),
/*
* DMA read descriptor output
*/
.m_axis_dma_read_desc_dma_addr(m_axis_dma_read_desc_dma_addr),
.m_axis_dma_read_desc_ram_addr(m_axis_dma_read_desc_ram_addr),
.m_axis_dma_read_desc_len(m_axis_dma_read_desc_len),
.m_axis_dma_read_desc_tag(m_axis_dma_read_desc_tag),
.m_axis_dma_read_desc_valid(m_axis_dma_read_desc_valid),
.m_axis_dma_read_desc_ready(m_axis_dma_read_desc_ready),
/*
* DMA read descriptor status input
*/
.s_axis_dma_read_desc_status_tag(s_axis_dma_read_desc_status_tag),
.s_axis_dma_read_desc_status_error(s_axis_dma_read_desc_status_error),
.s_axis_dma_read_desc_status_valid(s_axis_dma_read_desc_status_valid),
/*
* Transmit descriptor output
*/
.m_axis_tx_desc_addr(dma_tx_desc_addr),
.m_axis_tx_desc_len(dma_tx_desc_len),
.m_axis_tx_desc_tag(dma_tx_desc_tag),
.m_axis_tx_desc_id(dma_tx_desc_id),
.m_axis_tx_desc_dest(dma_tx_desc_dest),
.m_axis_tx_desc_user(dma_tx_desc_user),
.m_axis_tx_desc_valid(dma_tx_desc_valid),
.m_axis_tx_desc_ready(dma_tx_desc_ready),
/*
* Transmit descriptor status input
*/
.s_axis_tx_desc_status_tag(dma_tx_desc_status_tag),
.s_axis_tx_desc_status_error(dma_tx_desc_status_error),
.s_axis_tx_desc_status_valid(dma_tx_desc_status_valid),
/*
* Transmit checksum command output
*/
.m_axis_tx_csum_cmd_csum_enable(tx_csum_cmd_csum_enable),
.m_axis_tx_csum_cmd_csum_start(tx_csum_cmd_csum_start),
.m_axis_tx_csum_cmd_csum_offset(tx_csum_cmd_csum_offset),
.m_axis_tx_csum_cmd_valid(tx_csum_cmd_valid),
.m_axis_tx_csum_cmd_ready(tx_csum_cmd_ready),
/*
* Transmit timestamp input
*/
.s_axis_tx_ptp_ts(s_axis_tx_ptp_ts),
.s_axis_tx_ptp_ts_tag(s_axis_tx_ptp_ts_tag),
.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready),
/*
* Configuration
*/
.enable(1'b1)
);
wire [SEG_COUNT*SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr_int;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_valid_int;
wire [SEG_COUNT-1:0] dma_ram_rd_cmd_ready_int;
wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data_int;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_valid_int;
wire [SEG_COUNT-1:0] dma_ram_rd_resp_ready_int;
dma_psdpram #(
.SIZE(TX_RAM_SIZE),
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.PIPELINE(RAM_PIPELINE)
)
dma_psdpram_tx_inst (
.clk(clk),
.rst(rst),
/*
* Write port
*/
.wr_cmd_be(dma_ram_wr_cmd_be),
.wr_cmd_addr(dma_ram_wr_cmd_addr),
.wr_cmd_data(dma_ram_wr_cmd_data),
.wr_cmd_valid(dma_ram_wr_cmd_valid),
.wr_cmd_ready(dma_ram_wr_cmd_ready),
.wr_done(dma_ram_wr_done),
/*
* Read port
*/
.rd_cmd_addr(dma_ram_rd_cmd_addr_int),
.rd_cmd_valid(dma_ram_rd_cmd_valid_int),
.rd_cmd_ready(dma_ram_rd_cmd_ready_int),
.rd_resp_data(dma_ram_rd_resp_data_int),
.rd_resp_valid(dma_ram_rd_resp_valid_int),
.rd_resp_ready(dma_ram_rd_resp_ready_int)
);
wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata_int;
wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep_int;
wire tx_axis_tvalid_int;
wire tx_axis_tready_int;
wire tx_axis_tlast_int;
wire [AXIS_TX_ID_WIDTH-1:0] tx_axis_tid_int;
wire [AXIS_TX_DEST_WIDTH-1:0] tx_axis_tdest_int;
wire [AXIS_TX_USER_WIDTH-1:0] tx_axis_tuser_int;
dma_client_axis_source #(
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_ADDR_WIDTH(SEG_ADDR_WIDTH),
.SEG_BE_WIDTH(SEG_BE_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_LAST_ENABLE(1),
.AXIS_ID_ENABLE(1),
.AXIS_ID_WIDTH(AXIS_TX_ID_WIDTH),
.AXIS_DEST_ENABLE(1),
.AXIS_DEST_WIDTH(AXIS_TX_DEST_WIDTH),
.AXIS_USER_ENABLE(1),
.AXIS_USER_WIDTH(AXIS_TX_USER_WIDTH),
.LEN_WIDTH(DMA_CLIENT_LEN_WIDTH),
.TAG_WIDTH(DMA_CLIENT_TAG_WIDTH)
)
dma_client_axis_source_inst (
.clk(clk),
.rst(rst),
/*
* DMA read descriptor input
*/
.s_axis_read_desc_ram_addr(dma_tx_desc_addr),
.s_axis_read_desc_len(dma_tx_desc_len),
.s_axis_read_desc_tag(dma_tx_desc_tag),
.s_axis_read_desc_id(dma_tx_desc_id),
.s_axis_read_desc_dest(dma_tx_desc_dest),
.s_axis_read_desc_user(dma_tx_desc_user),
.s_axis_read_desc_valid(dma_tx_desc_valid),
.s_axis_read_desc_ready(dma_tx_desc_ready),
/*
* DMA read descriptor status output
*/
.m_axis_read_desc_status_tag(dma_tx_desc_status_tag),
.m_axis_read_desc_status_error(dma_tx_desc_status_error),
.m_axis_read_desc_status_valid(dma_tx_desc_status_valid),
/*
* AXI stream read data output
*/
.m_axis_read_data_tdata(tx_axis_tdata_int),
.m_axis_read_data_tkeep(tx_axis_tkeep_int),
.m_axis_read_data_tvalid(tx_axis_tvalid_int),
.m_axis_read_data_tready(tx_axis_tready_int),
.m_axis_read_data_tlast(tx_axis_tlast_int),
.m_axis_read_data_tid(tx_axis_tid_int),
.m_axis_read_data_tdest(tx_axis_tdest_int),
.m_axis_read_data_tuser(tx_axis_tuser_int),
/*
* RAM interface
*/
.ram_rd_cmd_addr(dma_ram_rd_cmd_addr_int),
.ram_rd_cmd_valid(dma_ram_rd_cmd_valid_int),
.ram_rd_cmd_ready(dma_ram_rd_cmd_ready_int),
.ram_rd_resp_data(dma_ram_rd_resp_data_int),
.ram_rd_resp_valid(dma_ram_rd_resp_valid_int),
.ram_rd_resp_ready(dma_ram_rd_resp_ready_int),
/*
* Configuration
*/
.enable(1'b1)
);
mqnic_egress #(
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_ID_WIDTH(AXIS_TX_ID_WIDTH),
.AXIS_DEST_WIDTH(AXIS_TX_DEST_WIDTH),
.AXIS_USER_WIDTH(AXIS_TX_USER_WIDTH),
.MAX_TX_SIZE(MAX_TX_SIZE)
)
egress_inst (
.clk(clk),
.rst(rst),
/*
* Transmit data input
*/
.s_axis_tdata(tx_axis_tdata_int),
.s_axis_tkeep(tx_axis_tkeep_int),
.s_axis_tvalid(tx_axis_tvalid_int),
.s_axis_tready(tx_axis_tready_int),
.s_axis_tlast(tx_axis_tlast_int),
.s_axis_tid(tx_axis_tid_int),
.s_axis_tdest(tx_axis_tdest_int),
.s_axis_tuser(tx_axis_tuser_int),
/*
* Transmit data output
*/
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tid(tx_axis_tid),
.m_axis_tdest(tx_axis_tdest),
.m_axis_tuser(tx_axis_tuser),
/*
* Transmit checksum command
*/
.tx_csum_cmd_csum_enable(tx_csum_cmd_csum_enable),
.tx_csum_cmd_csum_start(tx_csum_cmd_csum_start),
.tx_csum_cmd_csum_offset(tx_csum_cmd_csum_offset),
.tx_csum_cmd_valid(tx_csum_cmd_valid),
.tx_csum_cmd_ready(tx_csum_cmd_ready)
);
endmodule
`resetall

1738
fpga/common/rtl/mqnic_port.v
View File

File diff suppressed because it is too large Load Diff

16
fpga/common/rtl/mqnic_tx_scheduler_block_rr.v
View File

@ -42,6 +42,10 @@ either expressed or implied, of The Regents of the University of California.
*/
module mqnic_tx_scheduler_block #
(
// Number of ports
parameter PORTS = 1,
// Scheduler index
parameter INDEX = 0,
// Width of control register interface address in bits
parameter REG_ADDR_WIDTH = 16,
// Width of control register interface data in bits
@ -74,6 +78,8 @@ module mqnic_tx_scheduler_block #
parameter TDMA_INDEX_WIDTH = 8,
// PTP timestamp width
parameter PTP_TS_WIDTH = 96,
// AXI stream tdest signal width
parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4,
// Max transmit packet size
parameter MAX_TX_SIZE = 2048
)
@ -124,6 +130,7 @@ module mqnic_tx_scheduler_block #
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_req_queue,
output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_tag,
output wire [AXIS_TX_DEST_WIDTH-1:0] m_axis_tx_req_dest,
output wire m_axis_tx_req_valid,
input wire m_axis_tx_req_ready,
@ -144,7 +151,12 @@ module mqnic_tx_scheduler_block #
* PTP clock
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
input wire ptp_ts_step
input wire ptp_ts_step,
/*
* Configuration
*/
input wire [LEN_WIDTH-1:0] mtu
);
parameter SCHED_COUNT = 1;
@ -218,6 +230,8 @@ always @(posedge clk) begin
end
end
assign m_axis_tx_req_dest = INDEX << 4;
tx_scheduler_rr #(
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_SCHED_ADDR_WIDTH),

16
fpga/common/rtl/mqnic_tx_scheduler_block_rr_tdma.v
View File

@ -42,6 +42,10 @@ either expressed or implied, of The Regents of the University of California.
*/
module mqnic_tx_scheduler_block #
(
// Number of ports
parameter PORTS = 1,
// Scheduler index
parameter INDEX = 0,
// Width of control register interface address in bits
parameter REG_ADDR_WIDTH = 16,
// Width of control register interface data in bits
@ -74,6 +78,8 @@ module mqnic_tx_scheduler_block #
parameter TDMA_INDEX_WIDTH = 8,
// PTP timestamp width
parameter PTP_TS_WIDTH = 96,
// AXI stream tdest signal width
parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4,
// Max transmit packet size
parameter MAX_TX_SIZE = 2048
)
@ -124,6 +130,7 @@ module mqnic_tx_scheduler_block #
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_tx_req_queue,
output wire [REQ_TAG_WIDTH-1:0] m_axis_tx_req_tag,
output wire [AXIS_TX_DEST_WIDTH-1:0] m_axis_tx_req_dest,
output wire m_axis_tx_req_valid,
input wire m_axis_tx_req_ready,
@ -144,7 +151,12 @@ module mqnic_tx_scheduler_block #
* PTP clock
*/
input wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
input wire ptp_ts_step
input wire ptp_ts_step,
/*
* Configuration
*/
input wire [LEN_WIDTH-1:0] mtu
);
parameter SCHED_COUNT = 2;
@ -411,6 +423,8 @@ axil_crossbar_inst (
.m_axil_rready(axil_sched_rready)
);
assign m_axis_tx_req_dest = INDEX << 4;
tx_scheduler_rr #(
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
.AXIL_ADDR_WIDTH(AXIL_SCHED_ADDR_WIDTH),

76
fpga/common/rtl/rx_engine.v
View File

@ -42,6 +42,8 @@ either expressed or implied, of The Regents of the University of California.
*/
module rx_engine #
(
// Number of ports
parameter PORTS = 1,
// DMA RAM address width
parameter RAM_ADDR_WIDTH = 16,
// DMA address width
@ -92,10 +94,18 @@ module rx_engine #
parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8,
// Enable PTP timestamping
parameter PTP_TS_ENABLE = 1,
// PTP timestamp width
parameter PTP_TS_WIDTH = 96,
// Enable RX hashing
parameter RX_HASH_ENABLE = 1,
// Enable RX checksum offload
parameter RX_CHECKSUM_ENABLE = 1
parameter RX_CHECKSUM_ENABLE = 1,
// AXI stream tid signal width
parameter AXIS_RX_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1,
// AXI stream tdest signal width
parameter AXIS_RX_DEST_WIDTH = QUEUE_INDEX_WIDTH,
// AXI stream tuser signal width
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1
)
(
input wire clk,
@ -194,17 +204,12 @@ module rx_engine #
*/
input wire [DMA_CLIENT_LEN_WIDTH-1:0] s_axis_rx_desc_status_len,
input wire [DMA_CLIENT_TAG_WIDTH-1:0] s_axis_rx_desc_status_tag,
input wire s_axis_rx_desc_status_user,
input wire [AXIS_RX_ID_WIDTH-1:0] s_axis_rx_desc_status_id,
input wire [AXIS_RX_DEST_WIDTH-1:0] s_axis_rx_desc_status_dest,
input wire [AXIS_RX_USER_WIDTH-1:0] s_axis_rx_desc_status_user,
input wire [3:0] s_axis_rx_desc_status_error,
input wire s_axis_rx_desc_status_valid,
/*
* Receive timestamp input
*/
input wire [95:0] s_axis_rx_ptp_ts_96,
input wire s_axis_rx_ptp_ts_valid,
output wire s_axis_rx_ptp_ts_ready,
/*
* Receive hash input
*/
@ -289,8 +294,6 @@ reg [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_rx_desc_len_reg = {DMA_CLIENT_LEN_WIDTH{1'
reg [DMA_CLIENT_TAG_WIDTH-1:0] m_axis_rx_desc_tag_reg = {DMA_CLIENT_TAG_WIDTH{1'b0}}, m_axis_rx_desc_tag_next;
reg m_axis_rx_desc_valid_reg = 1'b0, m_axis_rx_desc_valid_next;
reg s_axis_rx_ptp_ts_ready_reg = 1'b0, s_axis_rx_ptp_ts_ready_next;
reg s_axis_rx_hash_ready_reg = 1'b0, s_axis_rx_hash_ready_next;
reg s_axis_rx_csum_ready_reg = 1'b0, s_axis_rx_csum_ready_next;
@ -328,9 +331,11 @@ reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_dma_len[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_desc_len[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [AXIS_RX_ID_WIDTH-1:0] desc_table_id[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [CL_RX_BUFFER_SIZE+1-1:0] desc_table_buf_ptr[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [95:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0];
reg [PTP_TS_WIDTH-1:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [31:0] desc_table_hash[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
@ -351,6 +356,8 @@ reg [CL_RX_BUFFER_SIZE+1-1:0] desc_table_start_buf_ptr;
reg desc_table_start_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_rx_finish_ptr;
reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_rx_finish_len;
reg [AXIS_RX_ID_WIDTH-1:0] desc_table_rx_finish_id;
reg [PTP_TS_WIDTH-1:0] desc_table_rx_finish_ptp_ts;
reg desc_table_rx_finish_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_dequeue_start_ptr_reg = 0;
reg desc_table_dequeue_start_en;
@ -364,9 +371,6 @@ reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_desc_fetched_len;
reg desc_table_desc_fetched_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_data_written_ptr;
reg desc_table_data_written_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_store_ptp_ts_ptr_reg = 0;
reg [95:0] desc_table_store_ptp_ts;
reg desc_table_store_ptp_ts_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_store_hash_ptr_reg = 0;
reg [31:0] desc_table_store_hash;
reg [3:0] desc_table_store_hash_type;
@ -415,8 +419,6 @@ assign m_axis_rx_desc_len = m_axis_rx_desc_len_reg;
assign m_axis_rx_desc_tag = m_axis_rx_desc_tag_reg;
assign m_axis_rx_desc_valid = m_axis_rx_desc_valid_reg;
assign s_axis_rx_ptp_ts_ready = s_axis_rx_ptp_ts_ready_reg;
assign s_axis_rx_hash_ready = s_axis_rx_hash_ready_reg;
assign s_axis_rx_csum_ready = s_axis_rx_csum_ready_reg;
@ -466,6 +468,7 @@ initial begin
desc_table_cpl_queue[i] = 0;
desc_table_dma_len[i] = 0;
desc_table_desc_len[i] = 0;
desc_table_id[i] = 0;
desc_table_buf_ptr[i] = 0;
desc_table_ptp_ts[i] = 0;
desc_table_hash[i] = 0;
@ -506,8 +509,6 @@ always @* begin
m_axis_rx_desc_tag_next = m_axis_rx_desc_tag_reg;
m_axis_rx_desc_valid_next = m_axis_rx_desc_valid_reg && !m_axis_rx_desc_ready;
s_axis_rx_ptp_ts_ready_next = 1'b0;
s_axis_rx_hash_ready_next = 1'b0;
s_axis_rx_csum_ready_next = 1'b0;
@ -529,6 +530,8 @@ always @* begin
desc_table_start_en = 1'b0;
desc_table_rx_finish_ptr = s_axis_rx_desc_status_tag;
desc_table_rx_finish_len = s_axis_rx_desc_status_len;
desc_table_rx_finish_id = s_axis_rx_desc_status_id;
desc_table_rx_finish_ptp_ts = s_axis_rx_desc_status_user >> 1;
desc_table_rx_finish_en = 1'b0;
desc_table_dequeue_start_en = 1'b0;
desc_table_dequeue_ptr = s_axis_desc_req_status_tag;
@ -541,8 +544,6 @@ always @* begin
desc_table_desc_fetched_en = 1'b0;
desc_table_data_written_ptr = s_axis_dma_write_desc_status_tag & DESC_PTR_MASK;
desc_table_data_written_en = 1'b0;
desc_table_store_ptp_ts = s_axis_rx_ptp_ts_96;
desc_table_store_ptp_ts_en = 1'b0;
desc_table_store_hash = s_axis_rx_hash;
desc_table_store_hash_type = s_axis_rx_hash_type;
desc_table_store_hash_en = 1'b0;
@ -591,6 +592,9 @@ always @* begin
// update entry in descriptor table
desc_table_rx_finish_ptr = s_axis_rx_desc_status_tag;
desc_table_rx_finish_len = s_axis_rx_desc_status_len;
desc_table_rx_finish_id = s_axis_rx_desc_status_id;
// desc_table_rx_finish_queue = s_axis_rx_desc_status_dest;
desc_table_rx_finish_ptp_ts = s_axis_rx_desc_status_user >> 1;
desc_table_rx_finish_en = 1'b1;
end
@ -699,23 +703,6 @@ always @* begin
desc_table_write_finish_en = 1'b1;
end
// store PTP timestamp
if (desc_table_active[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK] && desc_table_store_ptp_ts_ptr_reg != desc_table_start_ptr_reg && PTP_TS_ENABLE) begin
s_axis_rx_ptp_ts_ready_next = 1'b1;
if (desc_table_invalid[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK]) begin
// invalid entry; skip
desc_table_store_ptp_ts_en = 1'b1;
s_axis_rx_ptp_ts_ready_next = 1'b0;
end else if (s_axis_rx_ptp_ts_ready && s_axis_rx_ptp_ts_valid) begin
// update entry in descriptor table
desc_table_store_ptp_ts = s_axis_rx_ptp_ts_96;
desc_table_store_ptp_ts_en = 1'b1;
s_axis_rx_ptp_ts_ready_next = 1'b0;
end
end
// store RX hash
if (desc_table_active[desc_table_store_hash_ptr_reg & DESC_PTR_MASK] && desc_table_store_hash_ptr_reg != desc_table_start_ptr_reg && RX_HASH_ENABLE) begin
s_axis_rx_hash_ready_next = 1'b1;
@ -755,7 +742,6 @@ always @* begin
if (desc_table_active[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] &&
desc_table_cpl_enqueue_start_ptr_reg != desc_table_start_ptr_reg &&
desc_table_cpl_enqueue_start_ptr_reg != desc_table_dequeue_start_ptr_reg &&
(desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_ptp_ts_ptr_reg || !PTP_TS_ENABLE) &&
(desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_hash_ptr_reg || !RX_HASH_ENABLE) &&
(desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_csum_ptr_reg || !RX_CHECKSUM_ENABLE)) begin
if (desc_table_invalid[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK]) begin
@ -798,6 +784,7 @@ always @* begin
if (RX_CHECKSUM_ENABLE) begin
m_axis_cpl_req_data_next[127:112] = desc_table_csum[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
end
m_axis_cpl_req_data_next[176:168] = desc_table_id[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_valid_next = 1'b1;
end
end
@ -861,8 +848,6 @@ always @(posedge clk) begin
m_axis_rx_desc_tag_reg <= m_axis_rx_desc_tag_next;
m_axis_rx_desc_valid_reg <= m_axis_rx_desc_valid_next;
s_axis_rx_ptp_ts_ready_reg <= s_axis_rx_ptp_ts_ready_next;
s_axis_rx_hash_ready_reg <= s_axis_rx_hash_ready_next;
s_axis_rx_csum_ready_reg <= s_axis_rx_csum_ready_next;
@ -894,6 +879,8 @@ always @(posedge clk) begin
if (desc_table_rx_finish_en) begin
desc_table_dma_len[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_len;
desc_table_id[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_id;
desc_table_ptp_ts[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= desc_table_rx_finish_ptp_ts;
desc_table_rx_done[desc_table_rx_finish_ptr & DESC_PTR_MASK] <= 1'b1;
end
@ -918,11 +905,6 @@ always @(posedge clk) begin
desc_table_data_written[desc_table_data_written_ptr & DESC_PTR_MASK] <= 1'b1;
end
if (desc_table_store_ptp_ts_en) begin
desc_table_ptp_ts[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK] <= desc_table_store_ptp_ts;
desc_table_store_ptp_ts_ptr_reg <= desc_table_store_ptp_ts_ptr_reg + 1;
end
if (desc_table_store_hash_en) begin
desc_table_hash[desc_table_store_hash_ptr_reg & DESC_PTR_MASK] <= desc_table_store_hash;
desc_table_hash_type[desc_table_store_hash_ptr_reg & DESC_PTR_MASK] <= desc_table_store_hash_type;
@ -973,7 +955,6 @@ always @(posedge clk) begin
m_axis_cpl_req_valid_reg <= 1'b0;
m_axis_dma_write_desc_valid_reg <= 1'b0;
m_axis_rx_desc_valid_reg <= 1'b0;
s_axis_rx_ptp_ts_ready_reg <= 1'b0;
s_axis_rx_hash_ready_reg <= 1'b0;
s_axis_rx_csum_ready_reg <= 1'b0;
@ -994,7 +975,6 @@ always @(posedge clk) begin
desc_table_start_ptr_reg <= 0;
desc_table_dequeue_start_ptr_reg <= 0;
desc_table_store_ptp_ts_ptr_reg <= 0;
desc_table_store_hash_ptr_reg <= 0;
desc_table_store_csum_ptr_reg <= 0;
desc_table_cpl_enqueue_start_ptr_reg <= 0;

244
fpga/common/rtl/rx_fifo.v Normal file
View File

@ -0,0 +1,244 @@
/*
Copyright 2021, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* RX FIFO
*/
module rx_fifo #
(
// FIFO depth in words (each FIFO)
// KEEP_WIDTH words per cycle if KEEP_ENABLE set
// Rounded up to nearest power of 2 cycles
parameter FIFO_DEPTH = 4096,
// Number of AXI stream inputs
parameter PORTS = 4,
// Width of input AXI stream interfaces in bits
parameter S_DATA_WIDTH = 8,
// Propagate tkeep signal
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
// Width of output AXI stream interface in bits
parameter M_DATA_WIDTH = 8*PORTS,
// Propagate tkeep signal
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 1,
// input tid signal width
parameter S_ID_WIDTH = 1,
// output tid signal width
parameter M_ID_WIDTH = PORTS > 1 ? $clog2(PORTS) : 1,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// number of output pipeline registers
parameter PIPELINE_OUTPUT = 2
)
(
input wire clk,
input wire rst,
/*
* AXI Stream inputs
*/
input wire [PORTS*S_DATA_WIDTH-1:0] s_axis_tdata,
input wire [PORTS*S_KEEP_WIDTH-1:0] s_axis_tkeep,
input wire [PORTS-1:0] s_axis_tvalid,
output wire [PORTS-1:0] s_axis_tready,
input wire [PORTS-1:0] s_axis_tlast,
input wire [PORTS*S_ID_WIDTH-1:0] s_axis_tid,
input wire [PORTS*DEST_WIDTH-1:0] s_axis_tdest,
input wire [PORTS*USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI Stream output
*/
output wire [M_DATA_WIDTH-1:0] m_axis_tdata,
output wire [M_KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [M_ID_WIDTH-1:0] m_axis_tid,
output wire [DEST_WIDTH-1:0] m_axis_tdest,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Status
*/
output wire [PORTS-1:0] status_overflow,
output wire [PORTS-1:0] status_bad_frame,
output wire [PORTS-1:0] status_good_frame
);
wire [PORTS*M_DATA_WIDTH-1:0] axis_fifo_tdata;
wire [PORTS*M_KEEP_WIDTH-1:0] axis_fifo_tkeep;
wire [PORTS-1:0] axis_fifo_tvalid;
wire [PORTS-1:0] axis_fifo_tready;
wire [PORTS-1:0] axis_fifo_tlast;
wire [PORTS*S_ID_WIDTH-1:0] axis_fifo_tid;
wire [PORTS*DEST_WIDTH-1:0] axis_fifo_tdest;
wire [PORTS*USER_WIDTH-1:0] axis_fifo_tuser;
generate
genvar n;
for (n = 0; n < PORTS; n = n + 1) begin : fifo
axis_fifo_adapter #(
.DEPTH(FIFO_DEPTH),
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(S_ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(USER_ENABLE),
.DROP_WHEN_FULL(0)
)
fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata[n*S_DATA_WIDTH +: S_DATA_WIDTH]),
.s_axis_tkeep(s_axis_tkeep[n*S_KEEP_WIDTH +: S_KEEP_WIDTH]),
.s_axis_tvalid(s_axis_tvalid[n +: 1]),
.s_axis_tready(s_axis_tready[n +: 1]),
.s_axis_tlast(s_axis_tlast[n +: 1]),
.s_axis_tid(s_axis_tid[n*S_ID_WIDTH +: S_ID_WIDTH]),
.s_axis_tdest(s_axis_tdest[n*DEST_WIDTH +: DEST_WIDTH]),
.s_axis_tuser(s_axis_tuser[n*USER_WIDTH +: USER_WIDTH]),
// AXI output
.m_axis_tdata(axis_fifo_tdata[n*M_DATA_WIDTH +: M_DATA_WIDTH]),
.m_axis_tkeep(axis_fifo_tkeep[n*M_KEEP_WIDTH +: M_KEEP_WIDTH]),
.m_axis_tvalid(axis_fifo_tvalid[n +: 1]),
.m_axis_tready(axis_fifo_tready[n +: 1]),
.m_axis_tlast(axis_fifo_tlast[n +: 1]),
.m_axis_tid(axis_fifo_tid[n*S_ID_WIDTH +: S_ID_WIDTH]),
.m_axis_tdest(axis_fifo_tdest[n*DEST_WIDTH +: DEST_WIDTH]),
.m_axis_tuser(axis_fifo_tuser[n*USER_WIDTH +: USER_WIDTH]),
// Status
.status_overflow(status_overflow),
.status_bad_frame(status_bad_frame),
.status_good_frame(status_good_frame)
);
end
if (PORTS > 1) begin : mux
axis_arb_mux #(
.S_COUNT(PORTS),
.DATA_WIDTH(M_DATA_WIDTH),
.KEEP_ENABLE(M_KEEP_ENABLE),
.KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.S_ID_WIDTH(S_ID_WIDTH),
.M_ID_WIDTH(M_ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.LAST_ENABLE(1'b1),
.UPDATE_TID(1),
.ARB_TYPE_ROUND_ROBIN(1'b1),
.ARB_LSB_HIGH_PRIORITY(1'b1)
)
mux_inst (
.clk(clk),
.rst(rst),
// AXI Stream inputs
.s_axis_tdata(axis_fifo_tdata),
.s_axis_tkeep(axis_fifo_tkeep),
.s_axis_tvalid(axis_fifo_tvalid),
.s_axis_tready(axis_fifo_tready),
.s_axis_tlast(axis_fifo_tlast),
.s_axis_tid(axis_fifo_tid),
.s_axis_tdest(axis_fifo_tdest),
.s_axis_tuser(axis_fifo_tuser),
// AXI Stream output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
end else begin
assign m_axis_tdata = axis_fifo_tdata;
assign m_axis_tkeep = axis_fifo_tkeep;
assign m_axis_tvalid = axis_fifo_tvalid;
assign axis_fifo_tready = m_axis_tready;
assign m_axis_tlast = axis_fifo_tlast;
assign m_axis_tid = axis_fifo_tid;
assign m_axis_tdest = axis_fifo_tdest;
assign m_axis_tuser = axis_fifo_tuser;
end
endgenerate
endmodule
`resetall

109
fpga/common/rtl/tx_engine.v
View File

@ -42,6 +42,8 @@ either expressed or implied, of The Regents of the University of California.
*/
module tx_engine #
(
// Number of ports
parameter PORTS = 1,
// DMA RAM address width
parameter RAM_ADDR_WIDTH = 16,
// DMA address width
@ -92,8 +94,18 @@ module tx_engine #
parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8,
// Enable PTP timestamping
parameter PTP_TS_ENABLE = 1,
// PTP timestamp width
parameter PTP_TS_WIDTH = 96,
// PTP tag width
parameter PTP_TAG_WIDTH = 16,
// Enable TX checksum offload
parameter TX_CHECKSUM_ENABLE = 1
parameter TX_CHECKSUM_ENABLE = 1,
// AXI stream tid signal width
parameter AXIS_TX_ID_WIDTH = QUEUE_INDEX_WIDTH,
// AXI stream tdest signal width
parameter AXIS_TX_DEST_WIDTH = $clog2(PORTS)+4,
// AXI stream tuser signal width
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1
)
(
input wire clk,
@ -104,6 +116,7 @@ module tx_engine #
*/
input wire [QUEUE_INDEX_WIDTH-1:0] s_axis_tx_req_queue,
input wire [REQ_TAG_WIDTH-1:0] s_axis_tx_req_tag,
input wire [AXIS_TX_DEST_WIDTH-1:0] s_axis_tx_req_dest,
input wire s_axis_tx_req_valid,
output wire s_axis_tx_req_ready,
@ -184,7 +197,9 @@ module tx_engine #
output wire [RAM_ADDR_WIDTH-1:0] m_axis_tx_desc_addr,
output wire [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_desc_len,
output wire [DMA_CLIENT_TAG_WIDTH-1:0] m_axis_tx_desc_tag,
output wire m_axis_tx_desc_user,
output wire [AXIS_TX_ID_WIDTH-1:0] m_axis_tx_desc_id,
output wire [AXIS_TX_DEST_WIDTH-1:0] m_axis_tx_desc_dest,
output wire [AXIS_TX_USER_WIDTH-1:0] m_axis_tx_desc_user,
output wire m_axis_tx_desc_valid,
input wire m_axis_tx_desc_ready,
@ -207,7 +222,8 @@ module tx_engine #
/*
* Transmit timestamp input
*/
input wire [95:0] s_axis_tx_ptp_ts_96,
input wire [PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts,
input wire [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire s_axis_tx_ptp_ts_valid,
output wire s_axis_tx_ptp_ts_ready,
@ -282,7 +298,9 @@ reg m_axis_dma_read_desc_valid_reg = 1'b0, m_axis_dma_read_desc_valid_next;
reg [RAM_ADDR_WIDTH-1:0] m_axis_tx_desc_addr_reg = {RAM_ADDR_WIDTH{1'b0}}, m_axis_tx_desc_addr_next;
reg [DMA_CLIENT_LEN_WIDTH-1:0] m_axis_tx_desc_len_reg = {DMA_CLIENT_LEN_WIDTH{1'b0}}, m_axis_tx_desc_len_next;
reg [DMA_CLIENT_TAG_WIDTH-1:0] m_axis_tx_desc_tag_reg = {DMA_CLIENT_TAG_WIDTH{1'b0}}, m_axis_tx_desc_tag_next;
reg m_axis_tx_desc_user_reg = 1'b0, m_axis_tx_desc_user_next;
reg [AXIS_TX_ID_WIDTH-1:0] m_axis_tx_desc_id_reg = 0, m_axis_tx_desc_id_next;
reg [AXIS_TX_DEST_WIDTH-1:0] m_axis_tx_desc_dest_reg = 0, m_axis_tx_desc_dest_next;
reg [AXIS_TX_USER_WIDTH-1:0] m_axis_tx_desc_user_reg = 0, m_axis_tx_desc_user_next;
reg m_axis_tx_desc_valid_reg = 1'b0, m_axis_tx_desc_valid_next;
reg m_axis_tx_csum_cmd_csum_enable_reg = 1'b0, m_axis_tx_csum_cmd_csum_enable_next;
@ -315,7 +333,10 @@ reg [DESC_TABLE_SIZE-1:0] desc_table_active = 0;
reg [DESC_TABLE_SIZE-1:0] desc_table_invalid = 0;
reg [DESC_TABLE_SIZE-1:0] desc_table_desc_fetched = 0;
reg [DESC_TABLE_SIZE-1:0] desc_table_data_fetched = 0;
reg [DESC_TABLE_SIZE-1:0] desc_table_tx_done = 0;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg desc_table_tx_done_a[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg desc_table_tx_done_b[DESC_TABLE_SIZE-1:0];
reg [DESC_TABLE_SIZE-1:0] desc_table_cpl_write_done = 0;
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [REQ_TAG_WIDTH-1:0] desc_table_tag[DESC_TABLE_SIZE-1:0];
@ -326,6 +347,8 @@ reg [QUEUE_PTR_WIDTH-1:0] desc_table_queue_ptr[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [CPL_QUEUE_INDEX_WIDTH-1:0] desc_table_cpl_queue[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [AXIS_TX_DEST_WIDTH-1:0] desc_table_dest[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [6:0] desc_table_csum_start[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [7:0] desc_table_csum_offset[DESC_TABLE_SIZE-1:0];
@ -336,7 +359,7 @@ reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_len[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [CL_TX_BUFFER_SIZE+1-1:0] desc_table_buf_ptr[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg [95:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0];
reg [PTP_TS_WIDTH-1:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
reg desc_table_read_commit[DESC_TABLE_SIZE-1:0];
(* ram_style = "distributed", ramstyle = "no_rw_check, mlab" *)
@ -347,6 +370,7 @@ reg [DESC_TABLE_DMA_OP_COUNT_WIDTH-1:0] desc_table_read_count_finish[DESC_TABLE_
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_start_ptr_reg = 0;
reg [QUEUE_INDEX_WIDTH-1:0] desc_table_start_queue;
reg [REQ_TAG_WIDTH-1:0] desc_table_start_tag;
reg [AXIS_TX_DEST_WIDTH-1:0] desc_table_start_dest;
reg desc_table_start_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_dequeue_ptr;
reg [QUEUE_PTR_WIDTH-1:0] desc_table_dequeue_queue_ptr;
@ -368,8 +392,8 @@ reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_tx_start_ptr_reg = 0;
reg desc_table_tx_start_en;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_tx_finish_ptr;
reg desc_table_tx_finish_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_store_ptp_ts_ptr_reg = 0;
reg [95:0] desc_table_store_ptp_ts;
reg [CL_DESC_TABLE_SIZE-1:0] desc_table_store_ptp_ts_ptr;
reg [PTP_TS_WIDTH-1:0] desc_table_store_ptp_ts;
reg desc_table_store_ptp_ts_en;
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_cpl_enqueue_start_ptr_reg = 0;
reg desc_table_cpl_enqueue_start_en;
@ -410,6 +434,8 @@ assign m_axis_dma_read_desc_valid = m_axis_dma_read_desc_valid_reg;
assign m_axis_tx_desc_addr = m_axis_tx_desc_addr_reg;
assign m_axis_tx_desc_len = m_axis_tx_desc_len_reg;
assign m_axis_tx_desc_tag = m_axis_tx_desc_tag_reg;
assign m_axis_tx_desc_id = m_axis_tx_desc_id_reg;
assign m_axis_tx_desc_dest = m_axis_tx_desc_dest_reg;
assign m_axis_tx_desc_user = m_axis_tx_desc_user_reg;
assign m_axis_tx_desc_valid = m_axis_tx_desc_valid_reg;
@ -459,10 +485,13 @@ integer i;
initial begin
for (i = 0; i < DESC_TABLE_SIZE; i = i + 1) begin
desc_table_tx_done_a[i] = 0;
desc_table_tx_done_b[i] = 0;
desc_table_tag[i] = 0;
desc_table_queue[i] = 0;
desc_table_queue_ptr[i] = 0;
desc_table_cpl_queue[i] = 0;
desc_table_dest[i] = 0;
desc_table_csum_start[i] = 0;
desc_table_csum_offset[i] = 0;
desc_table_csum_enable[i] = 0;
@ -502,6 +531,8 @@ always @* begin
m_axis_tx_desc_addr_next = m_axis_tx_desc_addr_reg;
m_axis_tx_desc_len_next = m_axis_tx_desc_len_reg;
m_axis_tx_desc_tag_next = m_axis_tx_desc_tag_reg;
m_axis_tx_desc_id_next = m_axis_tx_desc_id_reg;
m_axis_tx_desc_dest_next = m_axis_tx_desc_dest_reg;
m_axis_tx_desc_user_next = m_axis_tx_desc_user_reg;
m_axis_tx_desc_valid_next = m_axis_tx_desc_valid_reg && !m_axis_tx_desc_ready;
@ -532,6 +563,7 @@ always @* begin
desc_table_start_tag = s_axis_tx_req_tag;
desc_table_start_queue = s_axis_tx_req_queue;
desc_table_start_dest = 0;
desc_table_start_en = 1'b0;
desc_table_dequeue_ptr = s_axis_desc_req_status_tag;
desc_table_dequeue_queue_ptr = s_axis_desc_req_status_ptr;
@ -558,7 +590,8 @@ always @* begin
desc_table_tx_start_en = 1'b0;
desc_table_tx_finish_ptr = s_axis_tx_desc_status_tag;
desc_table_tx_finish_en = 1'b0;
desc_table_store_ptp_ts = s_axis_tx_ptp_ts_96;
desc_table_store_ptp_ts_ptr = s_axis_tx_ptp_ts_tag;
desc_table_store_ptp_ts = s_axis_tx_ptp_ts;
desc_table_store_ptp_ts_en = 1'b0;
desc_table_cpl_enqueue_start_en = 1'b0;
desc_table_cpl_write_done_ptr = s_axis_cpl_req_status_tag & DESC_PTR_MASK;
@ -580,6 +613,7 @@ always @* begin
// store in descriptor table
desc_table_start_tag = s_axis_tx_req_tag;
desc_table_start_queue = s_axis_tx_req_queue;
desc_table_start_dest = s_axis_tx_req_dest;
desc_table_start_en = 1'b1;
// initiate descriptor fetch
@ -697,7 +731,7 @@ always @* begin
desc_table_read_finish_en = 1'b1;
end
// transmit
// transmit start
// wait for data fetch completion
if (desc_table_active[desc_table_tx_start_ptr_reg & DESC_PTR_MASK] && desc_table_tx_start_ptr_reg != desc_table_start_ptr_reg) begin
if (desc_table_invalid[desc_table_tx_start_ptr_reg & DESC_PTR_MASK]) begin
@ -712,7 +746,12 @@ always @* begin
m_axis_tx_desc_addr_next = desc_table_buf_ptr[desc_table_tx_start_ptr_reg & DESC_PTR_MASK] & TX_BUFFER_PTR_MASK + TX_BUFFER_OFFSET;
m_axis_tx_desc_len_next = desc_table_len[desc_table_tx_start_ptr_reg & DESC_PTR_MASK];
m_axis_tx_desc_tag_next = desc_table_tx_start_ptr_reg & DESC_PTR_MASK;
m_axis_tx_desc_user_next = 1'b0;
m_axis_tx_desc_id_next = desc_table_queue[desc_table_tx_start_ptr_reg & DESC_PTR_MASK];
m_axis_tx_desc_dest_next = desc_table_dest[desc_table_tx_start_ptr_reg & DESC_PTR_MASK];
m_axis_tx_desc_user_next = 0;
m_axis_tx_desc_user_next[1+PTP_TAG_WIDTH-1 +: 1] = 1'b1;
m_axis_tx_desc_user_next[1 +: PTP_TAG_WIDTH-1] = desc_table_tx_start_ptr_reg & DESC_PTR_MASK;
m_axis_tx_desc_user_next[0 +: 1] = 1'b0;
m_axis_tx_desc_valid_next = 1'b1;
// send TX checksum command
@ -725,8 +764,8 @@ always @* begin
end
end
// transmit done
// wait for transmit completion
// transmit DMA done
// wait for transmit DMA completion; free buffer space
if (s_axis_tx_desc_status_valid) begin
// update entry in descriptor table
desc_table_tx_finish_ptr = s_axis_tx_desc_status_tag;
@ -740,29 +779,21 @@ always @* begin
end
end
// store PTP timestamp
if (desc_table_active[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK] && desc_table_store_ptp_ts_ptr_reg != desc_table_start_ptr_reg && desc_table_store_ptp_ts_ptr_reg != desc_table_tx_start_ptr_reg && PTP_TS_ENABLE) begin
s_axis_tx_ptp_ts_ready_next = 1'b1;
if (desc_table_invalid[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK]) begin
// invalid entry; skip
desc_table_store_ptp_ts_en = 1'b1;
s_axis_tx_ptp_ts_ready_next = 1'b0;
end else if (s_axis_tx_ptp_ts_ready && s_axis_tx_ptp_ts_valid) begin
// update entry in descriptor table
desc_table_store_ptp_ts = s_axis_tx_ptp_ts_96;
desc_table_store_ptp_ts_en = 1'b1;
s_axis_tx_ptp_ts_ready_next = 1'b0;
end
// transmit done
// wait for transmit completion; store PTP timestamp
s_axis_tx_ptp_ts_ready_next = 1'b1;
if (s_axis_tx_ptp_ts_valid && s_axis_tx_ptp_ts_tag[PTP_TAG_WIDTH-1]) begin
desc_table_store_ptp_ts_ptr = s_axis_tx_ptp_ts_tag;
desc_table_store_ptp_ts = s_axis_tx_ptp_ts;
desc_table_store_ptp_ts_en = 1'b1;
end
// finish transmit; start completion enqueue
if (desc_table_active[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && desc_table_cpl_enqueue_start_ptr_reg != desc_table_start_ptr_reg && desc_table_cpl_enqueue_start_ptr_reg != desc_table_tx_start_ptr_reg && (desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_ptp_ts_ptr_reg || !PTP_TS_ENABLE)) begin
if (desc_table_active[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && desc_table_cpl_enqueue_start_ptr_reg != desc_table_start_ptr_reg && desc_table_cpl_enqueue_start_ptr_reg != desc_table_tx_start_ptr_reg) begin
if (desc_table_invalid[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK]) begin
// invalid entry; skip
desc_table_cpl_enqueue_start_en = 1'b1;
end else if (desc_table_tx_done[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_cpl_req_valid_next) begin
end else if (desc_table_tx_done_a[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] != desc_table_tx_done_b[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && !m_axis_cpl_req_valid_next) begin
// update entry in descriptor table
desc_table_cpl_enqueue_start_en = 1'b1;
@ -777,6 +808,7 @@ always @* begin
//m_axis_cpl_req_data_next[127:64] = desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
m_axis_cpl_req_data_next[111:64] = desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
end
m_axis_cpl_req_data_next[176:168] = desc_table_dest[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
m_axis_cpl_req_valid_next = 1'b1;
end
end
@ -846,6 +878,8 @@ always @(posedge clk) begin
m_axis_tx_desc_addr_reg <= m_axis_tx_desc_addr_next;
m_axis_tx_desc_len_reg <= m_axis_tx_desc_len_next;
m_axis_tx_desc_tag_reg <= m_axis_tx_desc_tag_next;
m_axis_tx_desc_id_reg <= m_axis_tx_desc_id_next;
m_axis_tx_desc_dest_reg <= m_axis_tx_desc_dest_next;
m_axis_tx_desc_user_reg <= m_axis_tx_desc_user_next;
m_axis_tx_desc_valid_reg <= m_axis_tx_desc_valid_next;
@ -878,10 +912,11 @@ always @(posedge clk) begin
desc_table_invalid[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
desc_table_desc_fetched[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
desc_table_data_fetched[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
desc_table_tx_done[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
desc_table_tx_done_a[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_tx_done_b[desc_table_start_ptr_reg & DESC_PTR_MASK];
desc_table_cpl_write_done[desc_table_start_ptr_reg & DESC_PTR_MASK] <= 1'b0;
desc_table_queue[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_queue;
desc_table_tag[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_tag;
desc_table_dest[desc_table_start_ptr_reg & DESC_PTR_MASK] <= desc_table_start_dest;
desc_table_start_ptr_reg <= desc_table_start_ptr_reg + 1;
end
@ -914,13 +949,9 @@ always @(posedge clk) begin
desc_table_tx_start_ptr_reg <= desc_table_tx_start_ptr_reg + 1;
end
if (desc_table_tx_finish_en) begin
desc_table_tx_done[desc_table_tx_finish_ptr & DESC_PTR_MASK] <= 1'b1;
end
if (desc_table_store_ptp_ts_en) begin
desc_table_ptp_ts[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK] <= desc_table_store_ptp_ts;
desc_table_store_ptp_ts_ptr_reg <= desc_table_store_ptp_ts_ptr_reg + 1;
desc_table_ptp_ts[desc_table_store_ptp_ts_ptr] <= desc_table_store_ptp_ts;
desc_table_tx_done_b[desc_table_store_ptp_ts_ptr] <= !desc_table_tx_done_a[desc_table_store_ptp_ts_ptr];
end
if (desc_table_cpl_enqueue_start_en) begin
@ -928,7 +959,7 @@ always @(posedge clk) begin
end
if (desc_table_cpl_write_done_en) begin
desc_table_cpl_write_done[desc_table_cpl_write_done_ptr & DESC_PTR_MASK] <= 1'b1;
desc_table_cpl_write_done[desc_table_cpl_write_done_ptr] <= 1'b1;
end
if (desc_table_finish_en) begin
@ -980,11 +1011,9 @@ always @(posedge clk) begin
desc_table_invalid <= 0;
desc_table_desc_fetched <= 0;
desc_table_data_fetched <= 0;
desc_table_tx_done <= 0;
desc_table_start_ptr_reg <= 0;
desc_table_tx_start_ptr_reg <= 0;
desc_table_store_ptp_ts_ptr_reg <= 0;
desc_table_cpl_enqueue_start_ptr_reg <= 0;
desc_table_finish_ptr_reg <= 0;
end

246
fpga/common/rtl/tx_fifo.v Normal file
View File

@ -0,0 +1,246 @@
/*
Copyright 2021, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* TX FIFO
*/
module tx_fifo #
(
// FIFO depth in words (each FIFO)
// KEEP_WIDTH words per cycle if KEEP_ENABLE set
// Rounded up to nearest power of 2 cycles
parameter FIFO_DEPTH = 4096,
// Number of AXI stream outputs
parameter PORTS = 4,
// Width of input AXI stream interfaces in bits
parameter S_DATA_WIDTH = 8,
// Propagate tkeep signal
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
// Width of output AXI stream interfaces in bits
parameter M_DATA_WIDTH = 8,
// Propagate tkeep signal
parameter M_KEEP_ENABLE = (M_DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter M_KEEP_WIDTH = (M_DATA_WIDTH/8),
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// output tdest signal width
parameter M_DEST_WIDTH = 3,
// input tdest signal width
// must be wide enough to uniquely address outputs
parameter S_DEST_WIDTH = M_DEST_WIDTH+$clog2(PORTS),
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1,
// number of output pipeline registers
parameter PIPELINE_OUTPUT = 2
)
(
input wire clk,
input wire rst,
/*
* AXI Stream input
*/
input wire [S_DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [ID_WIDTH-1:0] s_axis_tid,
input wire [S_DEST_WIDTH-1:0] s_axis_tdest,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI Stream outputs
*/
output wire [PORTS*M_DATA_WIDTH-1:0] m_axis_tdata,
output wire [PORTS*M_KEEP_WIDTH-1:0] m_axis_tkeep,
output wire [PORTS-1:0] m_axis_tvalid,
input wire [PORTS-1:0] m_axis_tready,
output wire [PORTS-1:0] m_axis_tlast,
output wire [PORTS*ID_WIDTH-1:0] m_axis_tid,
output wire [PORTS*M_DEST_WIDTH-1:0] m_axis_tdest,
output wire [PORTS*USER_WIDTH-1:0] m_axis_tuser,
/*
* Status
*/
output wire [PORTS-1:0] status_overflow,
output wire [PORTS-1:0] status_bad_frame,
output wire [PORTS-1:0] status_good_frame
);
wire [PORTS*S_DATA_WIDTH-1:0] axis_fifo_tdata;
wire [PORTS*S_KEEP_WIDTH-1:0] axis_fifo_tkeep;
wire [PORTS-1:0] axis_fifo_tvalid;
wire [PORTS-1:0] axis_fifo_tready;
wire [PORTS-1:0] axis_fifo_tlast;
wire [PORTS*ID_WIDTH-1:0] axis_fifo_tid;
wire [PORTS*M_DEST_WIDTH-1:0] axis_fifo_tdest;
wire [PORTS*USER_WIDTH-1:0] axis_fifo_tuser;
generate
genvar n;
if (PORTS > 1) begin : demux
axis_demux #(
.M_COUNT(PORTS),
.DATA_WIDTH(S_DATA_WIDTH),
.KEEP_ENABLE(S_KEEP_ENABLE),
.KEEP_WIDTH(S_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(1),
.S_DEST_WIDTH(S_DEST_WIDTH),
.M_DEST_WIDTH(M_DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.TDEST_ROUTE(1)
)
switch_inst (
.clk(clk),
.rst(rst),
// AXI Stream input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI Stream outputs
.m_axis_tdata(axis_fifo_tdata),
.m_axis_tkeep(axis_fifo_tkeep),
.m_axis_tvalid(axis_fifo_tvalid),
.m_axis_tready(axis_fifo_tready),
.m_axis_tlast(axis_fifo_tlast),
.m_axis_tid(axis_fifo_tid),
.m_axis_tdest(axis_fifo_tdest),
.m_axis_tuser(axis_fifo_tuser),
// Control
.enable(1),
.drop(0),
.select(0)
);
end else begin
assign axis_fifo_tdata = s_axis_tdata;
assign axis_fifo_tkeep = s_axis_tkeep;
assign axis_fifo_tvalid = s_axis_tvalid;
assign s_axis_tready = axis_fifo_tready;
assign axis_fifo_tlast = s_axis_tlast;
assign axis_fifo_tid = s_axis_tid;
assign axis_fifo_tdest = s_axis_tdest;
assign axis_fifo_tuser = s_axis_tuser;
end
for (n = 0; n < PORTS; n = n + 1) begin : fifo
axis_fifo_adapter #(
.DEPTH(FIFO_DEPTH),
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(1),
.DEST_WIDTH(M_DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(1),
.USER_BAD_FRAME_VALUE(1'b1),
.USER_BAD_FRAME_MASK(1'b1),
.DROP_BAD_FRAME(USER_ENABLE),
.DROP_WHEN_FULL(0)
)
fifo_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(axis_fifo_tdata[n*S_DATA_WIDTH +: S_DATA_WIDTH]),
.s_axis_tkeep(axis_fifo_tkeep[n*S_KEEP_WIDTH +: S_KEEP_WIDTH]),
.s_axis_tvalid(axis_fifo_tvalid[n +: 1]),
.s_axis_tready(axis_fifo_tready[n +: 1]),
.s_axis_tlast(axis_fifo_tlast[n +: 1]),
.s_axis_tid(axis_fifo_tid[n*ID_WIDTH +: ID_WIDTH]),
.s_axis_tdest(axis_fifo_tdest[n*M_DEST_WIDTH +: M_DEST_WIDTH]),
.s_axis_tuser(axis_fifo_tuser[n*USER_WIDTH +: USER_WIDTH]),
// AXI output
.m_axis_tdata(m_axis_tdata[n*M_DATA_WIDTH +: M_DATA_WIDTH]),
.m_axis_tkeep(m_axis_tkeep[n*M_KEEP_WIDTH +: M_KEEP_WIDTH]),
.m_axis_tvalid(m_axis_tvalid[n +: 1]),
.m_axis_tready(m_axis_tready[n +: 1]),
.m_axis_tlast(m_axis_tlast[n +: 1]),
.m_axis_tid(m_axis_tid[n*ID_WIDTH +: ID_WIDTH]),
.m_axis_tdest(m_axis_tdest[n*M_DEST_WIDTH +: M_DEST_WIDTH]),
.m_axis_tuser(m_axis_tuser[n*USER_WIDTH +: USER_WIDTH]),
// Status
.status_overflow(status_overflow),
.status_bad_frame(status_bad_frame),
.status_good_frame(status_good_frame)
);
end
endgenerate
endmodule
`resetall

284
fpga/common/rtl/tx_req_mux.v Normal file
View File

@ -0,0 +1,284 @@
/*
Copyright 2021, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Transmit request mux
*/
module tx_req_mux #
(
// Number of ports
parameter PORTS = 2,
// Queue index width
parameter QUEUE_INDEX_WIDTH = 4,
// Input request tag field width
parameter S_REQ_TAG_WIDTH = 8,
// Output request tag field width (towards transmit engine)
// Additional bits required for response routing
parameter M_REQ_TAG_WIDTH = S_REQ_TAG_WIDTH+$clog2(PORTS),
// dest width
parameter DEST_WIDTH = 8,
// Length field width
parameter LEN_WIDTH = 20,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// LSB priority selection
parameter ARB_LSB_HIGH_PRIORITY = 1
)
(
input wire clk,
input wire rst,
/*
* Transmit request output (to transmit engine)
*/
output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_req_queue,
output wire [M_REQ_TAG_WIDTH-1:0] m_axis_req_tag,
output wire [DEST_WIDTH-1:0] m_axis_req_dest,
output wire m_axis_req_valid,
input wire m_axis_req_ready,
/*
* Transmit request status input (from transmit engine)
*/
input wire [LEN_WIDTH-1:0] s_axis_req_status_len,
input wire [M_REQ_TAG_WIDTH-1:0] s_axis_req_status_tag,
input wire s_axis_req_status_empty,
input wire s_axis_req_status_error,
input wire s_axis_req_status_valid,
/*
* Transmit request input
*/
input wire [PORTS*QUEUE_INDEX_WIDTH-1:0] s_axis_req_queue,
input wire [PORTS*S_REQ_TAG_WIDTH-1:0] s_axis_req_tag,
input wire [PORTS*DEST_WIDTH-1:0] s_axis_req_dest,
input wire [PORTS-1:0] s_axis_req_valid,
output wire [PORTS-1:0] s_axis_req_ready,
/*
* Transmit request status output
*/
output wire [PORTS*LEN_WIDTH-1:0] m_axis_req_status_len,
output wire [PORTS*S_REQ_TAG_WIDTH-1:0] m_axis_req_status_tag,
output wire [PORTS-1:0] m_axis_req_status_empty,
output wire [PORTS-1:0] m_axis_req_status_error,
output wire [PORTS-1:0] m_axis_req_status_valid
);
parameter CL_PORTS = $clog2(PORTS);
// check configuration
initial begin
if (M_REQ_TAG_WIDTH < S_REQ_TAG_WIDTH+$clog2(PORTS)) begin
$error("Error: M_REQ_TAG_WIDTH must be at least $clog2(PORTS) larger than S_REQ_TAG_WIDTH (instance %m)");
$finish;
end
end
// request mux
wire [PORTS-1:0] request;
wire [PORTS-1:0] acknowledge;
wire [PORTS-1:0] grant;
wire grant_valid;
wire [CL_PORTS-1:0] grant_encoded;
// internal datapath
reg [QUEUE_INDEX_WIDTH-1:0] m_axis_req_queue_int;
reg [M_REQ_TAG_WIDTH-1:0] m_axis_req_tag_int;
reg [DEST_WIDTH-1:0] m_axis_req_dest_int;
reg m_axis_req_valid_int;
reg m_axis_req_ready_int_reg = 1'b0;
wire m_axis_req_ready_int_early;
assign s_axis_req_ready = (m_axis_req_ready_int_reg && grant_valid) << grant_encoded;
// mux for incoming packet
wire [QUEUE_INDEX_WIDTH-1:0] current_s_desc_queue = s_axis_req_queue[grant_encoded*QUEUE_INDEX_WIDTH +: QUEUE_INDEX_WIDTH];
wire [S_REQ_TAG_WIDTH-1:0] current_s_desc_tag = s_axis_req_tag[grant_encoded*S_REQ_TAG_WIDTH +: S_REQ_TAG_WIDTH];
wire [DEST_WIDTH-1:0] current_s_desc_data = s_axis_req_dest[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
wire current_s_desc_valid = s_axis_req_valid[grant_encoded];
wire current_s_desc_ready = s_axis_req_ready[grant_encoded];
// arbiter instance
arbiter #(
.PORTS(PORTS),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(1),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
assign request = s_axis_req_valid & ~grant;
assign acknowledge = grant & s_axis_req_valid & s_axis_req_ready;
always @* begin
// pass through selected packet data
m_axis_req_queue_int = current_s_desc_queue;
m_axis_req_tag_int = {grant_encoded, current_s_desc_tag};
m_axis_req_dest_int = current_s_desc_data;
m_axis_req_valid_int = current_s_desc_valid && m_axis_req_ready_int_reg && grant_valid;
end
// output datapath logic
reg [QUEUE_INDEX_WIDTH-1:0] m_axis_req_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}};
reg [M_REQ_TAG_WIDTH-1:0] m_axis_req_tag_reg = {M_REQ_TAG_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_axis_req_dest_reg = {DEST_WIDTH{1'b0}};
reg m_axis_req_valid_reg = 1'b0, m_axis_req_valid_next;
reg [QUEUE_INDEX_WIDTH-1:0] temp_m_axis_req_queue_reg = {QUEUE_INDEX_WIDTH{1'b0}};
reg [M_REQ_TAG_WIDTH-1:0] temp_m_axis_req_tag_reg = {M_REQ_TAG_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_axis_req_dest_reg = {DEST_WIDTH{1'b0}};
reg temp_m_axis_req_valid_reg = 1'b0, temp_m_axis_req_valid_next;
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_axis_req_queue = m_axis_req_queue_reg;
assign m_axis_req_tag = m_axis_req_tag_reg;
assign m_axis_req_dest = m_axis_req_dest_reg;
assign m_axis_req_valid = m_axis_req_valid_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_axis_req_ready_int_early = m_axis_req_ready || (!temp_m_axis_req_valid_reg && (!m_axis_req_valid_reg || !m_axis_req_valid_int));
always @* begin
// transfer sink ready state to source
m_axis_req_valid_next = m_axis_req_valid_reg;
temp_m_axis_req_valid_next = temp_m_axis_req_valid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_axis_req_ready_int_reg) begin
// input is ready
if (m_axis_req_ready || !m_axis_req_valid_reg) begin
// output is ready or currently not valid, transfer data to output
m_axis_req_valid_next = m_axis_req_valid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_axis_req_valid_next = m_axis_req_valid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_axis_req_ready) begin
// input is not ready, but output is ready
m_axis_req_valid_next = temp_m_axis_req_valid_reg;
temp_m_axis_req_valid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_axis_req_valid_reg <= 1'b0;
m_axis_req_ready_int_reg <= 1'b0;
temp_m_axis_req_valid_reg <= 1'b0;
end else begin
m_axis_req_valid_reg <= m_axis_req_valid_next;
m_axis_req_ready_int_reg <= m_axis_req_ready_int_early;
temp_m_axis_req_valid_reg <= temp_m_axis_req_valid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_axis_req_queue_reg <= m_axis_req_queue_int;
m_axis_req_tag_reg <= m_axis_req_tag_int;
m_axis_req_dest_reg <= m_axis_req_dest_int;
end else if (store_axis_temp_to_output) begin
m_axis_req_queue_reg <= temp_m_axis_req_queue_reg;
m_axis_req_tag_reg <= temp_m_axis_req_tag_reg;
m_axis_req_dest_reg <= temp_m_axis_req_dest_reg;
end
if (store_axis_int_to_temp) begin
temp_m_axis_req_queue_reg <= m_axis_req_queue_int;
temp_m_axis_req_tag_reg <= m_axis_req_tag_int;
temp_m_axis_req_dest_reg <= m_axis_req_dest_int;
end
end
// request status demux
reg [LEN_WIDTH-1:0] m_axis_req_status_len_reg = {LEN_WIDTH{1'b0}}, m_axis_req_status_len_next;
reg [S_REQ_TAG_WIDTH-1:0] m_axis_req_status_tag_reg = {S_REQ_TAG_WIDTH{1'b0}}, m_axis_req_status_tag_next;
reg m_axis_req_status_empty_reg = 1'b0, m_axis_req_status_empty_next;
reg m_axis_req_status_error_reg = 1'b0, m_axis_req_status_error_next;
reg [PORTS-1:0] m_axis_req_status_valid_reg = {PORTS{1'b0}}, m_axis_req_status_valid_next;
assign m_axis_req_status_len = {PORTS{m_axis_req_status_len_reg}};
assign m_axis_req_status_tag = {PORTS{m_axis_req_status_tag_reg}};
assign m_axis_req_status_empty = {PORTS{m_axis_req_status_empty_reg}};
assign m_axis_req_status_error = {PORTS{m_axis_req_status_error_reg}};
assign m_axis_req_status_valid = m_axis_req_status_valid_reg;
always @* begin
m_axis_req_status_len_next = s_axis_req_status_len;
m_axis_req_status_tag_next = s_axis_req_status_tag;
m_axis_req_status_empty_next = s_axis_req_status_empty;
m_axis_req_status_error_next = s_axis_req_status_error;
m_axis_req_status_valid_next = s_axis_req_status_valid << (PORTS > 1 ? (s_axis_req_status_tag >> S_REQ_TAG_WIDTH) : 0);
end
always @(posedge clk) begin
if (rst) begin
m_axis_req_status_valid_reg <= {PORTS{1'b0}};
end else begin
m_axis_req_status_valid_reg <= m_axis_req_status_valid_next;
end
m_axis_req_status_len_reg <= m_axis_req_status_len_next;
m_axis_req_status_tag_reg <= m_axis_req_status_tag_next;
m_axis_req_status_empty_reg <= m_axis_req_status_empty_next;
m_axis_req_status_error_reg <= m_axis_req_status_error_next;
end
endmodule
`resetall

10
fpga/common/tb/mqnic_core_axi/Makefile
View File

@ -41,7 +41,10 @@ MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/mqnic_core.v
VERILOG_SOURCES += ../../rtl/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/mqnic_port.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v
@ -52,6 +55,9 @@ VERILOG_SOURCES += ../../rtl/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/event_mux.v
VERILOG_SOURCES += ../../rtl/queue_manager.v
VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/tx_fifo.v
VERILOG_SOURCES += ../../rtl/rx_fifo.v
VERILOG_SOURCES += ../../rtl/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/tx_engine.v
VERILOG_SOURCES += ../../rtl/rx_engine.v
VERILOG_SOURCES += ../../rtl/tx_checksum.v
@ -84,7 +90,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi.v

14
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -384,8 +384,8 @@ pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
@pytest.mark.parametrize(("if_count", "ports_per_if", "axi_data_width",
"axis_data_width", "axis_sync_data_width"), [
(1, 1, 128, 64, 64),
(2, 1, 256, 64, 64),
(1, 2, 256, 64, 64),
(2, 1, 128, 64, 64),
(1, 2, 128, 64, 64),
(1, 1, 128, 64, 128),
])
def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
@ -398,7 +398,10 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
os.path.join(rtl_dir, f"{dut}.v"),
os.path.join(rtl_dir, "mqnic_core.v"),
os.path.join(rtl_dir, "mqnic_interface.v"),
os.path.join(rtl_dir, "mqnic_port.v"),
os.path.join(rtl_dir, "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "mqnic_egress.v"),
os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "mqnic_ptp_perout.v"),
@ -409,6 +412,9 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
os.path.join(rtl_dir, "event_mux.v"),
os.path.join(rtl_dir, "queue_manager.v"),
os.path.join(rtl_dir, "cpl_queue_manager.v"),
os.path.join(rtl_dir, "tx_fifo.v"),
os.path.join(rtl_dir, "rx_fifo.v"),
os.path.join(rtl_dir, "tx_req_mux.v"),
os.path.join(rtl_dir, "tx_engine.v"),
os.path.join(rtl_dir, "rx_engine.v"),
os.path.join(rtl_dir, "tx_checksum.v"),
@ -441,7 +447,9 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width,
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "dma_if_axi.v"),

10
fpga/common/tb/mqnic_core_pcie_s10/Makefile
View File

@ -42,7 +42,10 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/mqnic_core.v
VERILOG_SOURCES += ../../rtl/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/mqnic_port.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v
@ -53,6 +56,9 @@ VERILOG_SOURCES += ../../rtl/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/event_mux.v
VERILOG_SOURCES += ../../rtl/queue_manager.v
VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/tx_fifo.v
VERILOG_SOURCES += ../../rtl/rx_fifo.v
VERILOG_SOURCES += ../../rtl/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/tx_engine.v
VERILOG_SOURCES += ../../rtl/rx_engine.v
VERILOG_SOURCES += ../../rtl/tx_checksum.v
@ -85,7 +91,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -513,7 +513,10 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
os.path.join(rtl_dir, "mqnic_core.v"),
os.path.join(rtl_dir, "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "mqnic_interface.v"),
os.path.join(rtl_dir, "mqnic_port.v"),
os.path.join(rtl_dir, "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "mqnic_egress.v"),
os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "mqnic_ptp_perout.v"),
@ -524,6 +527,9 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
os.path.join(rtl_dir, "event_mux.v"),
os.path.join(rtl_dir, "queue_manager.v"),
os.path.join(rtl_dir, "cpl_queue_manager.v"),
os.path.join(rtl_dir, "tx_fifo.v"),
os.path.join(rtl_dir, "rx_fifo.v"),
os.path.join(rtl_dir, "tx_req_mux.v"),
os.path.join(rtl_dir, "tx_engine.v"),
os.path.join(rtl_dir, "rx_engine.v"),
os.path.join(rtl_dir, "tx_checksum.v"),
@ -556,7 +562,9 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width,
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/common/tb/mqnic_core_pcie_us/Makefile
View File

@ -42,7 +42,10 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/mqnic_core.v
VERILOG_SOURCES += ../../rtl/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/mqnic_port.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v
@ -53,6 +56,9 @@ VERILOG_SOURCES += ../../rtl/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/event_mux.v
VERILOG_SOURCES += ../../rtl/queue_manager.v
VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/tx_fifo.v
VERILOG_SOURCES += ../../rtl/rx_fifo.v
VERILOG_SOURCES += ../../rtl/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/tx_engine.v
VERILOG_SOURCES += ../../rtl/rx_engine.v
VERILOG_SOURCES += ../../rtl/tx_checksum.v
@ -85,7 +91,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -588,7 +588,10 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "mqnic_core.v"),
os.path.join(rtl_dir, "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "mqnic_interface.v"),
os.path.join(rtl_dir, "mqnic_port.v"),
os.path.join(rtl_dir, "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "mqnic_egress.v"),
os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "mqnic_ptp_perout.v"),
@ -599,6 +602,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "event_mux.v"),
os.path.join(rtl_dir, "queue_manager.v"),
os.path.join(rtl_dir, "cpl_queue_manager.v"),
os.path.join(rtl_dir, "tx_fifo.v"),
os.path.join(rtl_dir, "rx_fifo.v"),
os.path.join(rtl_dir, "tx_req_mux.v"),
os.path.join(rtl_dir, "tx_engine.v"),
os.path.join(rtl_dir, "rx_engine.v"),
os.path.join(rtl_dir, "tx_checksum.v"),
@ -631,7 +637,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile
View File

@ -42,7 +42,10 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/mqnic_core.v
VERILOG_SOURCES += ../../rtl/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/mqnic_port.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v
@ -53,6 +56,9 @@ VERILOG_SOURCES += ../../rtl/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/event_mux.v
VERILOG_SOURCES += ../../rtl/queue_manager.v
VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/tx_fifo.v
VERILOG_SOURCES += ../../rtl/rx_fifo.v
VERILOG_SOURCES += ../../rtl/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/tx_engine.v
VERILOG_SOURCES += ../../rtl/rx_engine.v
VERILOG_SOURCES += ../../rtl/tx_checksum.v
@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -641,7 +641,10 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "mqnic_core.v"),
os.path.join(rtl_dir, "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "mqnic_interface.v"),
os.path.join(rtl_dir, "mqnic_port.v"),
os.path.join(rtl_dir, "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "mqnic_egress.v"),
os.path.join(rtl_dir, "mqnic_ingress.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "mqnic_ptp_perout.v"),
@ -652,6 +655,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "event_mux.v"),
os.path.join(rtl_dir, "queue_manager.v"),
os.path.join(rtl_dir, "cpl_queue_manager.v"),
os.path.join(rtl_dir, "tx_fifo.v"),
os.path.join(rtl_dir, "rx_fifo.v"),
os.path.join(rtl_dir, "tx_req_mux.v"),
os.path.join(rtl_dir, "tx_engine.v"),
os.path.join(rtl_dir, "rx_engine.v"),
os.path.join(rtl_dir, "tx_checksum.v"),
@ -686,7 +692,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile
View File

@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -58,7 +64,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile
View File

@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -60,7 +66,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -523,7 +523,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -534,6 +537,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -567,7 +573,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga/Makefile
View File

@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -75,7 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/fpga_tdma/Makefile
View File

@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -76,7 +82,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -565,7 +565,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -576,6 +579,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -616,7 +622,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile
View File

@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -75,7 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile
View File

@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -76,7 +82,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -565,7 +565,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -576,6 +579,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -616,7 +622,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/AU200/fpga_100g/fpga/Makefile
View File

@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -61,7 +67,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -523,7 +523,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -534,6 +537,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -567,7 +573,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/AU200/fpga_10g/fpga/Makefile
View File

@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -78,7 +84,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/AU200/fpga_10g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/AU200/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -565,7 +565,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -576,6 +579,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -616,7 +622,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/AU250/fpga_100g/fpga/Makefile
View File

@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -61,7 +67,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -523,7 +523,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -534,6 +537,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -567,7 +573,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/AU250/fpga_10g/fpga/Makefile
View File

@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -78,7 +84,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/AU250/fpga_10g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/AU250/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -565,7 +565,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -576,6 +579,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -616,7 +622,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/AU280/fpga_100g/fpga/Makefile
View File

@ -12,7 +12,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -23,6 +26,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -60,7 +66,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -512,7 +512,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -523,6 +526,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -556,7 +562,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/AU280/fpga_10g/fpga/Makefile
View File

@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -77,7 +83,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/AU280/fpga_10g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/AU280/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -554,7 +554,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -565,6 +568,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -605,7 +611,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/AU50/fpga_100g/fpga/Makefile
View File

@ -12,7 +12,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -23,6 +26,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -60,7 +66,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -473,7 +473,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -484,6 +487,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -517,7 +523,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/AU50/fpga_10g/fpga/Makefile
View File

@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -77,7 +83,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/AU50/fpga_10g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/AU50/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -484,7 +484,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -495,6 +498,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -535,7 +541,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/ExaNIC_X10/fpga/fpga/Makefile
View File

@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -74,7 +80,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -472,7 +472,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -483,6 +486,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -523,7 +529,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/ExaNIC_X25/fpga_10g/fpga/Makefile
View File

@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -74,7 +80,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/ExaNIC_X25/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -481,7 +481,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -492,6 +495,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -532,7 +538,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/ExaNIC_X25/fpga_25g/fpga/Makefile
View File

@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -74,7 +80,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/ExaNIC_X25/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -481,7 +481,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -492,6 +495,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -532,7 +538,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/NetFPGA_SUME/fpga/fpga/Makefile
View File

@ -15,7 +15,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -26,6 +29,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -75,7 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -487,7 +487,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -498,6 +501,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -538,7 +544,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

11
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile
View File

@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_s10.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -75,8 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

11
fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile
View File

@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_s10.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -75,8 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_s10.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -484,7 +484,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -495,6 +498,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -535,7 +541,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/VCU108/fpga_10g/fpga/Makefile
View File

@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -75,7 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/VCU108/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -491,7 +491,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -502,6 +505,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -542,7 +548,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/VCU118/fpga_100g/fpga/Makefile
View File

@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -58,7 +64,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -527,7 +527,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -538,6 +541,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -571,7 +577,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/VCU118/fpga_10g/fpga/Makefile
View File

@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -75,7 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/VCU118/fpga_10g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -569,7 +569,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -580,6 +583,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -620,7 +626,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile
View File

@ -13,7 +13,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -24,6 +27,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -58,7 +64,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -87,7 +93,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -521,7 +521,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -532,6 +535,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -565,7 +571,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/VCU1525/fpga_10g/fpga/Makefile
View File

@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -75,7 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/VCU1525/fpga_10g/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/VCU1525/fpga_10g/tb/fpga_core/test_fpga_core.py
View File

@ -563,7 +563,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -574,6 +577,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -614,7 +620,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile
View File

@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -75,7 +81,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

10
fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile
View File

@ -43,7 +43,10 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/common/mqnic_port.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v
VERILOG_SOURCES += ../../rtl/common/mqnic_egress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ingress.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/common/mqnic_ptp_perout.v
@ -54,6 +57,9 @@ VERILOG_SOURCES += ../../rtl/common/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/common/event_mux.v
VERILOG_SOURCES += ../../rtl/common/queue_manager.v
VERILOG_SOURCES += ../../rtl/common/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/common/tx_fifo.v
VERILOG_SOURCES += ../../rtl/common/rx_fifo.v
VERILOG_SOURCES += ../../rtl/common/tx_req_mux.v
VERILOG_SOURCES += ../../rtl/common/tx_engine.v
VERILOG_SOURCES += ../../rtl/common/rx_engine.v
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
@ -94,7 +100,9 @@ VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_demux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v

10
fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
View File

@ -475,7 +475,10 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
os.path.join(rtl_dir, "common", "mqnic_core.v"),
os.path.join(rtl_dir, "common", "mqnic_interface.v"),
os.path.join(rtl_dir, "common", "mqnic_port.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"),
os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),
os.path.join(rtl_dir, "common", "mqnic_egress.v"),
os.path.join(rtl_dir, "common", "mqnic_ingress.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "common", "mqnic_ptp_perout.v"),
@ -486,6 +489,9 @@ def test_fpga_core(request):
os.path.join(rtl_dir, "common", "event_mux.v"),
os.path.join(rtl_dir, "common", "queue_manager.v"),
os.path.join(rtl_dir, "common", "cpl_queue_manager.v"),
os.path.join(rtl_dir, "common", "tx_fifo.v"),
os.path.join(rtl_dir, "common", "rx_fifo.v"),
os.path.join(rtl_dir, "common", "tx_req_mux.v"),
os.path.join(rtl_dir, "common", "tx_engine.v"),
os.path.join(rtl_dir, "common", "rx_engine.v"),
os.path.join(rtl_dir, "common", "tx_checksum.v"),
@ -526,7 +532,9 @@ def test_fpga_core(request):
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_demux.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),

10
fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile
View File

@ -14,7 +14,10 @@ SYN_FILES += rtl/common/mqnic_core_pcie_us.v
SYN_FILES += rtl/common/mqnic_core_pcie.v
SYN_FILES += rtl/common/mqnic_core.v
SYN_FILES += rtl/common/mqnic_interface.v
SYN_FILES += rtl/common/mqnic_port.v
SYN_FILES += rtl/common/mqnic_interface_tx.v
SYN_FILES += rtl/common/mqnic_interface_rx.v
SYN_FILES += rtl/common/mqnic_egress.v
SYN_FILES += rtl/common/mqnic_ingress.v
SYN_FILES += rtl/common/mqnic_ptp.v
SYN_FILES += rtl/common/mqnic_ptp_clock.v
SYN_FILES += rtl/common/mqnic_ptp_perout.v
@ -25,6 +28,9 @@ SYN_FILES += rtl/common/desc_op_mux.v
SYN_FILES += rtl/common/event_mux.v
SYN_FILES += rtl/common/queue_manager.v
SYN_FILES += rtl/common/cpl_queue_manager.v
SYN_FILES += rtl/common/tx_fifo.v
SYN_FILES += rtl/common/rx_fifo.v
SYN_FILES += rtl/common/tx_req_mux.v
SYN_FILES += rtl/common/tx_engine.v
SYN_FILES += rtl/common/rx_engine.v
SYN_FILES += rtl/common/tx_checksum.v
@ -59,7 +65,9 @@ SYN_FILES += lib/axis/rtl/axis_adapter.v
SYN_FILES += lib/axis/rtl/axis_arb_mux.v
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_demux.v
SYN_FILES += lib/axis/rtl/axis_fifo.v
SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
SYN_FILES += lib/axis/rtl/axis_register.v
SYN_FILES += lib/axis/rtl/sync_reset.v

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