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merged changes in pcie

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This commit is contained in:
Alex Forencich 2022-08-15 23:47:49 -07:00
commit 338457cd75
4 changed files with 14 additions and 13 deletions
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3
fpga/lib/pcie/rtl/pcie_ptile_fc_counter.v
View File

@ -31,7 +31,8 @@ THE SOFTWARE.
/*
* P-Tile PCIe flow control counter
*/
module ptile_tx_fc_counter #(
module pcie_ptile_fc_counter #
(
parameter WIDTH = 16,
parameter INDEX = 0
)

12
fpga/lib/pcie/rtl/pcie_ptile_if_tx.v
View File

@ -364,7 +364,7 @@ pcie_tlp_fifo_mux_inst (
.fifo_watermark()
);
ptile_tx_fc_counter #(
pcie_ptile_fc_counter #(
.WIDTH(12),
.INDEX(0)
)
@ -377,7 +377,7 @@ fc_counter_ph (
.fc_av(tx_fc_ph_av)
);
ptile_tx_fc_counter #(
pcie_ptile_fc_counter #(
.WIDTH(12),
.INDEX(1)
)
@ -390,7 +390,7 @@ fc_counter_nph (
.fc_av(tx_fc_nph_av)
);
ptile_tx_fc_counter #(
pcie_ptile_fc_counter #(
.WIDTH(12),
.INDEX(2)
)
@ -403,7 +403,7 @@ fc_counter_cplh (
.fc_av(tx_fc_cplh_av)
);
ptile_tx_fc_counter #(
pcie_ptile_fc_counter #(
.WIDTH(16),
.INDEX(4)
)
@ -416,7 +416,7 @@ fc_counter_pd (
.fc_av(tx_fc_pd_av)
);
ptile_tx_fc_counter #(
pcie_ptile_fc_counter #(
.WIDTH(16),
.INDEX(5)
)
@ -429,7 +429,7 @@ fc_counter_npd (
.fc_av(tx_fc_npd_av)
);
ptile_tx_fc_counter #(
pcie_ptile_fc_counter #(
.WIDTH(16),
.INDEX(6)
)

6
fpga/lib/pcie/rtl/pcie_tlp_fifo_mux.v
View File

@ -347,13 +347,13 @@ always @* begin
// compute mux settings
for (port = 0; port < PORTS; port = port + 1) begin
port_seg_valid[port] = {2{fifo_ctrl_tlp_valid[port]}} >> fifo_ctrl_seg_offset[port];
port_seg_valid[port] = pause[port] ? 0 : {2{fifo_ctrl_tlp_valid[port]}} >> fifo_ctrl_seg_offset[port];
port_seg_eop[port] = {2{fifo_ctrl_tlp_eop[port]}} >> fifo_ctrl_seg_offset[port];
end
for (seg = 0; seg < OUT_TLP_SEG_COUNT; seg = seg + 1) begin
// select port
if (!frame_cyc && !abort) begin
if (!frame_cyc) begin
if (ARB_TYPE_ROUND_ROBIN) begin
// round robin arb - start checking after previously-selected port
if (ARB_LSB_HIGH_PRIORITY) begin
@ -383,7 +383,7 @@ always @* begin
port_cyc = cur_port;
seg_offset_cyc = port_seg_offset_cyc[cur_port];
seg_count_cyc = port_seg_count_cyc[cur_port];
if (port_seg_valid[cur_port][0] && !pause[cur_port]) begin
if (port_seg_valid[cur_port][0]) begin
// set frame
frame_cyc = 1;
sel_tlp_seq_valid_cyc[OUT_TLP_SEG_COUNT*cur_port+seg] = 1'b1;

6
fpga/lib/pcie/rtl/pcie_tlp_mux.v
View File

@ -241,13 +241,13 @@ always @* begin
// compute mux settings
for (port = 0; port < PORTS; port = port + 1) begin
port_seg_valid[port] = {2{in_tlp_valid_full[port]}} >> port_seg_offset_reg[port];
port_seg_valid[port] = pause[port] ? 0 : {2{in_tlp_valid_full[port]}} >> port_seg_offset_reg[port];
port_seg_eop[port] = {2{in_tlp_eop_full[port]}} >> port_seg_offset_reg[port];
end
for (seg = 0; seg < TLP_SEG_COUNT; seg = seg + 1) begin
// select port
if (!frame_cyc && !abort) begin
if (!frame_cyc) begin
if (ARB_TYPE_ROUND_ROBIN) begin
// round robin arb - start checking after previously-selected port
if (ARB_LSB_HIGH_PRIORITY) begin
@ -276,7 +276,7 @@ always @* begin
// select port
port_cyc = cur_port;
seg_offset_cyc = port_seg_offset_next[cur_port];
if (port_seg_valid[cur_port][0] && !pause[cur_port]) begin
if (port_seg_valid[cur_port][0]) begin
// set frame
frame_cyc = 1;
sel_tlp_seq_valid_cyc[TLP_SEG_COUNT*cur_port+seg] = 1'b1;