From 34150323dfbe40e940673f61a3c15fc4c35430c9 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 20 Aug 2021 18:15:06 -0700 Subject: [PATCH] Remove obsolete packet table size parameters --- fpga/common/rtl/mqnic_interface.v | 16 +++++----------- fpga/common/rtl/mqnic_port.v | 14 +++++--------- .../mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v | 9 ++------- fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v | 9 ++------- fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v | 9 ++------- fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v | 9 ++------- fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v | 9 ++------- .../ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v | 9 ++------- fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v | 9 ++------- fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v | 9 ++------- fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v | 9 ++------- 29 files changed, 64 insertions(+), 209 deletions(-) diff --git a/fpga/common/rtl/mqnic_interface.v b/fpga/common/rtl/mqnic_interface.v index 4fc9363af..526ad5fe3 100644 --- a/fpga/common/rtl/mqnic_interface.v +++ b/fpga/common/rtl/mqnic_interface.v @@ -80,12 +80,8 @@ module mqnic_interface # parameter RX_CPL_QUEUE_PIPELINE = 3, // Transmit descriptor table size (number of in-flight operations) parameter TX_DESC_TABLE_SIZE = 16, - // Transmit packet table size (number of in-progress packets) - parameter TX_PKT_TABLE_SIZE = 8, // Receive descriptor table size (number of in-flight operations) parameter RX_DESC_TABLE_SIZE = 16, - // Receive packet table size (number of in-progress packets) - parameter RX_PKT_TABLE_SIZE = 8, // Max number of in-flight descriptor requests (transmit) parameter TX_MAX_DESC_REQ = 16, // Max number of in-flight descriptor requests (transmit) @@ -147,9 +143,9 @@ module mqnic_interface # // Max receive packet size parameter MAX_RX_SIZE = 2048, // DMA TX RAM size - parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE, + parameter TX_RAM_SIZE = 8*MAX_TX_SIZE, // DMA RX RAM size - parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE + parameter RX_RAM_SIZE = 8*MAX_RX_SIZE ) ( input wire clk, @@ -2055,9 +2051,7 @@ generate .RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH), .CPL_QUEUE_INDEX_WIDTH(CPL_QUEUE_INDEX_WIDTH), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .DESC_TABLE_DMA_OP_COUNT_WIDTH(((2**LOG_BLOCK_SIZE_WIDTH)-1)+1), .TX_MAX_DESC_REQ(TX_MAX_DESC_REQ), .TX_DESC_FIFO_SIZE(TX_MAX_DESC_REQ*(2**((2**LOG_BLOCK_SIZE_WIDTH)-1))), @@ -2087,12 +2081,12 @@ generate .AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH), .MAX_TX_SIZE(MAX_TX_SIZE), .MAX_RX_SIZE(MAX_RX_SIZE), + .TX_RAM_SIZE(TX_RAM_SIZE), + .RX_RAM_SIZE(RX_RAM_SIZE), .DESC_SIZE(DESC_SIZE), .CPL_SIZE(CPL_SIZE), .AXIS_DESC_DATA_WIDTH(AXIS_DESC_DATA_WIDTH), - .AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH), - .TX_RAM_SIZE(TX_RAM_SIZE), - .RX_RAM_SIZE(RX_RAM_SIZE) + .AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH) ) port_inst ( .clk(clk), diff --git a/fpga/common/rtl/mqnic_port.v b/fpga/common/rtl/mqnic_port.v index 71152080c..285f150f7 100644 --- a/fpga/common/rtl/mqnic_port.v +++ b/fpga/common/rtl/mqnic_port.v @@ -68,12 +68,8 @@ module mqnic_port # parameter CPL_QUEUE_INDEX_WIDTH = TX_CPL_QUEUE_INDEX_WIDTH > RX_CPL_QUEUE_INDEX_WIDTH ? TX_CPL_QUEUE_INDEX_WIDTH : RX_CPL_QUEUE_INDEX_WIDTH, // Transmit descriptor table size (number of in-flight operations) parameter TX_DESC_TABLE_SIZE = 16, - // Transmit packet table size (number of in-progress packets) - parameter TX_PKT_TABLE_SIZE = 8, // Receive descriptor table size (number of in-flight operations) parameter RX_DESC_TABLE_SIZE = 16, - // Receive packet table size (number of in-progress packets) - parameter RX_PKT_TABLE_SIZE = 8, // Width of descriptor table field for tracking outstanding DMA operations parameter DESC_TABLE_DMA_OP_COUNT_WIDTH = 4, // Max number of in-flight descriptor requests (transmit) @@ -132,6 +128,10 @@ module mqnic_port # parameter MAX_TX_SIZE = 2048, // Max receive packet size parameter MAX_RX_SIZE = 2048, + // DMA TX RAM size + parameter TX_RAM_SIZE = 8*MAX_TX_SIZE, + // DMA RX RAM size + parameter RX_RAM_SIZE = 8*MAX_RX_SIZE, // Descriptor size (in bytes) parameter DESC_SIZE = 16, // Descriptor size (in bytes) @@ -139,11 +139,7 @@ module mqnic_port # // Width of AXI stream descriptor interfaces in bits parameter AXIS_DESC_DATA_WIDTH = DESC_SIZE*8, // AXI stream descriptor tkeep signal width (words per cycle) - parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8, - // DMA TX RAM size - parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE, - // DMA RX RAM size - parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE + parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8 ) ( input wire clk, diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v index 6106ed268..ba20a540e 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v @@ -277,9 +277,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -302,6 +300,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 131072; parameter MAX_TX_SIZE = 16384; parameter MAX_RX_SIZE = 16384; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -329,9 +329,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2350,9 +2347,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index fabcfffc9..a74bc9a6d 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -315,9 +315,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -345,6 +343,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -372,9 +372,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2439,9 +2436,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 0eb1cbc99..7aa647712 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -315,9 +315,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -345,6 +343,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -372,9 +372,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2440,9 +2437,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v index 9af3ebade..14cac639d 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v @@ -294,9 +294,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -322,6 +320,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 131072; parameter MAX_TX_SIZE = 16384; parameter MAX_RX_SIZE = 16384; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -349,9 +349,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2361,9 +2358,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v index 315467182..fe5e8c078 100644 --- a/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v @@ -332,9 +332,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -362,6 +360,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -389,9 +389,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2447,9 +2444,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v index fa763952e..f1dd9ff0a 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v @@ -294,9 +294,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -322,6 +320,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 131072; parameter MAX_TX_SIZE = 16384; parameter MAX_RX_SIZE = 16384; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -349,9 +349,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2361,9 +2358,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v index 0250ea874..76f270db5 100644 --- a/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v @@ -332,9 +332,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -362,6 +360,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -389,9 +389,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2447,9 +2444,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v index 85497385f..ab562a602 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v @@ -266,9 +266,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -294,6 +292,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 131072; parameter MAX_TX_SIZE = 16384; parameter MAX_RX_SIZE = 16384; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -321,9 +321,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2272,9 +2269,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v index d8098b641..6b27b1602 100644 --- a/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v @@ -304,9 +304,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -334,6 +332,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -361,9 +361,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2358,9 +2355,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v index e6567eeca..485687028 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v @@ -248,9 +248,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -276,6 +274,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 131072; parameter MAX_TX_SIZE = 16384; parameter MAX_RX_SIZE = 16384; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -303,9 +303,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2171,9 +2168,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v index d00820016..8fa8417e2 100644 --- a/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v @@ -266,9 +266,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -296,6 +294,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -323,9 +323,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2241,9 +2238,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v index 57f4cdf56..13d182c91 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -247,9 +247,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -277,6 +275,8 @@ parameter TX_FIFO_DEPTH = 16384; parameter RX_FIFO_DEPTH = 16384; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -304,9 +304,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 4; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2260,9 +2257,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v index 3ed92e35a..0b14ab634 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v @@ -249,9 +249,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -279,6 +277,8 @@ parameter TX_FIFO_DEPTH = 16384; parameter RX_FIFO_DEPTH = 16384; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -306,9 +306,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 4; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2260,9 +2257,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v index 485e08509..dbe1c7e60 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v @@ -248,9 +248,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -278,6 +276,8 @@ parameter TX_FIFO_DEPTH = 16384; parameter RX_FIFO_DEPTH = 16384; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -305,9 +305,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 4; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2188,9 +2185,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v index 01d2c3b98..d0a67d26f 100644 --- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v @@ -266,9 +266,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -296,6 +294,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -323,9 +323,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2369,9 +2366,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v index 461afa7ea..9c722b53d 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v @@ -280,9 +280,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -308,6 +306,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 131072; parameter MAX_TX_SIZE = 16384; parameter MAX_RX_SIZE = 16384; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -335,9 +335,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2430,9 +2427,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v index 9a036711a..12501ab1d 100644 --- a/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v @@ -318,9 +318,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -348,6 +346,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -375,9 +375,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2516,9 +2513,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v index 7190cc9b3..5720adfa8 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v @@ -269,9 +269,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -297,6 +295,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 131072; parameter MAX_TX_SIZE = 16384; parameter MAX_RX_SIZE = 16384; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -324,9 +324,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2289,9 +2286,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v index 96d07f87d..ae2dea039 100644 --- a/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v @@ -307,9 +307,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -337,6 +335,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -364,9 +364,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2375,9 +2372,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v index 29c18978a..109f51201 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v @@ -220,9 +220,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -250,6 +248,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -277,9 +277,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2040,9 +2037,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v index 7a2149ea4..34301c2cc 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v @@ -284,9 +284,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -309,6 +307,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 131072; parameter MAX_TX_SIZE = 16384; parameter MAX_RX_SIZE = 16384; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -336,9 +336,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2480,9 +2477,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v index c08a0ef0e..776387309 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v @@ -322,9 +322,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -352,6 +350,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -379,9 +379,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2569,9 +2566,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v index 4f9ece67c..ceb55ec43 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v @@ -322,9 +322,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "RR"; @@ -352,6 +350,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -379,9 +379,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2569,9 +2566,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index 661cd384a..3e05e61d5 100644 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -315,9 +315,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "TDMA_RR"; @@ -345,6 +343,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -372,9 +372,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2439,9 +2436,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v index 8241625b2..37aaeafb6 100644 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -247,9 +247,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "TDMA_RR"; @@ -277,6 +275,8 @@ parameter TX_FIFO_DEPTH = 16384; parameter RX_FIFO_DEPTH = 16384; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -304,9 +304,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 4; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2260,9 +2257,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v index 58e03d63f..6e2528d1e 100644 --- a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v @@ -266,9 +266,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "TDMA_RR"; @@ -296,6 +294,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -323,9 +323,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2369,9 +2366,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE), diff --git a/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v index 8e586d5f9..02d478274 100644 --- a/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v @@ -318,9 +318,7 @@ parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE; // TX and RX engine parameters (port) parameter TX_DESC_TABLE_SIZE = 32; -parameter TX_PKT_TABLE_SIZE = 8; parameter RX_DESC_TABLE_SIZE = 32; -parameter RX_PKT_TABLE_SIZE = 8; // Scheduler parameters (port) parameter TX_SCHEDULER = "TDMA_RR"; @@ -348,6 +346,8 @@ parameter TX_FIFO_DEPTH = 32768; parameter RX_FIFO_DEPTH = 32768; parameter MAX_TX_SIZE = 2048; parameter MAX_RX_SIZE = 2048; +parameter TX_RAM_SIZE = 8*MAX_TX_SIZE; +parameter RX_RAM_SIZE = 8*MAX_RX_SIZE; // AXI lite interface parameters parameter AXIL_DATA_WIDTH = 32; @@ -375,9 +375,6 @@ parameter RAM_SEL_WIDTH = $clog2(IF_COUNT)+IF_RAM_SEL_WIDTH+1; parameter RAM_ADDR_WIDTH = SEG_ADDR_WIDTH+$clog2(SEG_COUNT)+$clog2(SEG_BE_WIDTH); parameter RAM_PIPELINE = 2; -parameter TX_RAM_SIZE = TX_PKT_TABLE_SIZE*MAX_TX_SIZE; -parameter RX_RAM_SIZE = RX_PKT_TABLE_SIZE*MAX_RX_SIZE; - // parameter sizing helpers function [31:0] w_32(input [31:0] val); w_32 = val; @@ -2516,9 +2513,7 @@ generate .TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE), .RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE), .TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE), - .TX_PKT_TABLE_SIZE(TX_PKT_TABLE_SIZE), .RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE), - .RX_PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE), .TX_SCHEDULER(TX_SCHEDULER), .TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE), .TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),