From 344fcd45fcf7d52e4d7926fcc012f9e805047472 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 24 Jun 2023 01:25:25 -0700 Subject: [PATCH] fpga/mqnic: Testbench parameter clean-up Signed-off-by: Alex Forencich --- fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py | 2 -- fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile | 1 - .../DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py | 1 - .../DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py | 2 -- 4 files changed, 6 deletions(-) diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py index 7f42ae79b..14081dbac 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -758,8 +758,6 @@ def test_fpga_core(request): parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 parameters['PTP_USE_SAMPLE_CLOCK'] = 1 - parameters['PTP_SEPARATE_TX_CLOCK'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1 diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile index 66c1acdb4..a671d97b2 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile @@ -191,7 +191,6 @@ export PARAM_TDMA_INDEX_WIDTH := 6 export PARAM_PTP_TS_ENABLE := 1 export PARAM_TX_CPL_FIFO_DEPTH := 32 export PARAM_TX_CHECKSUM_ENABLE := 1 -export PARAM_RX_RSS_ENABLE := 1 export PARAM_RX_HASH_ENABLE := 1 export PARAM_RX_CHECKSUM_ENABLE := 1 export PARAM_TX_FIFO_DEPTH := 32768 diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py index 0c8f80ab0..bb064bc46 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -734,7 +734,6 @@ def test_fpga_core(request): parameters['PTP_TS_ENABLE'] = 1 parameters['TX_CPL_FIFO_DEPTH'] = 32 parameters['TX_CHECKSUM_ENABLE'] = 1 - parameters['RX_RSS_ENABLE'] = 1 parameters['RX_HASH_ENABLE'] = 1 parameters['RX_CHECKSUM_ENABLE'] = 1 parameters['TX_FIFO_DEPTH'] = 32768 diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py index 1380e450f..10093e780 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -756,8 +756,6 @@ def test_fpga_core(request): parameters['PTP_CLOCK_PIPELINE'] = 0 parameters['PTP_CLOCK_CDC_PIPELINE'] = 0 parameters['PTP_USE_SAMPLE_CLOCK'] = 1 - parameters['PTP_SEPARATE_TX_CLOCK'] = 0 - parameters['PTP_SEPARATE_RX_CLOCK'] = 0 parameters['PTP_PORT_CDC_PIPELINE'] = 0 parameters['PTP_PEROUT_ENABLE'] = 1 parameters['PTP_PEROUT_COUNT'] = 1