diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl index 04512c1e1..2a6de4893 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl @@ -209,17 +209,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -264,6 +253,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl index 0491ecfa0..8744d335a 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl index b28ad5626..26c92f8a9 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl index da7278275..8d213db18 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl @@ -209,17 +209,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -264,6 +253,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl index e2d9fcc13..52dcd663b 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl @@ -209,17 +209,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -264,6 +253,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl index 12f9b9cc1..067d09ba1 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl index 0c28ba4af..030221035 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl index 2e5b3f295..a7b7b5a1b 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl index 91e17d681..94e461334 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl @@ -209,17 +209,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -264,6 +253,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl index 3941dde81..824d894a9 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl @@ -209,17 +209,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -264,6 +253,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl index 8d9adec01..4c0200e26 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl index 6c44b2dde..5657a3ea0 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl index d4d102e75..b6f6ce226 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl @@ -209,17 +209,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -264,6 +253,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl index b1bb8d57d..aeedb4c4b 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl @@ -209,17 +209,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -264,6 +253,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl index c80b11807..d0adc4892 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl index 6a25357d3..ae15a936e 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl index c228d7218..1fdc87e21 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl @@ -214,17 +214,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4c_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -269,6 +258,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl index c94fb6fd9..9770a5219 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl @@ -214,17 +214,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4c_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -269,6 +258,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl index a1399dccc..5ad0deb95 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl @@ -227,17 +227,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4c_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -282,6 +271,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl index e3952ea88..f91760f52 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl @@ -227,17 +227,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4c_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -282,6 +271,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl index 93fba0834..9a5411b99 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl @@ -197,17 +197,6 @@ dict set params STAT_ID_WIDTH "12" # PCIe IP core settings set pcie [get_ips pcie4c_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -252,6 +241,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl index 834723d92..2ea1a08ec 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl @@ -197,17 +197,6 @@ dict set params STAT_ID_WIDTH "12" # PCIe IP core settings set pcie [get_ips pcie4c_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -252,6 +241,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl index d76d66a75..108fbc17a 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl @@ -210,17 +210,6 @@ dict set params STAT_ID_WIDTH "12" # PCIe IP core settings set pcie [get_ips pcie4c_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -265,6 +254,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl index 498f57898..4896ee3e4 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl @@ -210,17 +210,6 @@ dict set params STAT_ID_WIDTH "12" # PCIe IP core settings set pcie [get_ips pcie4c_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -265,6 +254,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl index 03d7698ab..e9cee4a1e 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl @@ -212,19 +212,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie3_ultrascale_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.pf0_class_code_base [format "%02x" [expr ($pcie_class_code >> 16) & 0xff]] $pcie -set_property CONFIG.pf0_class_code_sub [format "%02x" [expr ($pcie_class_code >> 8) & 0xff]] $pcie -set_property CONFIG.pf0_class_code_interface [format "%02x" [expr $pcie_class_code & 0xff]] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -269,6 +256,30 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.pf0_class_code_base" [format "%02x" [expr ($pcie_class_code >> 16) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_sub" [format "%02x" [expr ($pcie_class_code >> 8) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_interface" [format "%02x" [expr $pcie_class_code & 0xff]] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl index 1aa0fbb6c..b233780ea 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl @@ -212,19 +212,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie3_ultrascale_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.pf0_class_code_base [format "%02x" [expr ($pcie_class_code >> 16) & 0xff]] $pcie -set_property CONFIG.pf0_class_code_sub [format "%02x" [expr ($pcie_class_code >> 8) & 0xff]] $pcie -set_property CONFIG.pf0_class_code_interface [format "%02x" [expr $pcie_class_code & 0xff]] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -269,6 +256,30 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.pf0_class_code_base" [format "%02x" [expr ($pcie_class_code >> 16) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_sub" [format "%02x" [expr ($pcie_class_code >> 8) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_interface" [format "%02x" [expr $pcie_class_code & 0xff]] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl index 752230505..e7f73f466 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl +++ b/fpga/mqnic/NetFPGA_SUME/fpga/fpga/config.tcl @@ -190,17 +190,6 @@ dict set params STAT_ID_WIDTH "10" # PCIe IP core settings set pcie [get_ips pcie3_7x_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -245,6 +234,30 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.pf0_class_code_base" [format "%02x" [expr ($pcie_class_code >> 16) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_sub" [format "%02x" [expr ($pcie_class_code >> 8) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_interface" [format "%02x" [expr $pcie_class_code & 0xff]] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl b/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl index 0fbc7258a..93dfd1ca3 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K35_S/fpga/fpga/config.tcl @@ -190,17 +190,6 @@ dict set params STAT_ID_WIDTH "10" # PCIe IP core settings set pcie [get_ips pcie3_ultrascale_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -245,6 +234,30 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.pf0_class_code_base" [format "%02x" [expr ($pcie_class_code >> 16) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_sub" [format "%02x" [expr ($pcie_class_code >> 8) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_interface" [format "%02x" [expr $pcie_class_code & 0xff]] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl index 75e20ad68..3e06f22c3 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl index 3c963d67b..48bf5822c 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl index facb426f9..c5392b070 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl @@ -203,17 +203,6 @@ dict set params STAT_ID_WIDTH "12" # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -258,6 +247,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl index f846fe75d..b907a4d01 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl @@ -203,17 +203,6 @@ dict set params STAT_ID_WIDTH "12" # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -258,6 +247,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl index 9e92eb736..5e4212c15 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie3_ultrascale_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,30 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.pf0_class_code_base" [format "%02x" [expr ($pcie_class_code >> 16) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_sub" [format "%02x" [expr ($pcie_class_code >> 8) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_interface" [format "%02x" [expr $pcie_class_code & 0xff]] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl index 12715fe48..1150b2d98 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie3_ultrascale_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,30 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.pf0_class_code_base" [format "%02x" [expr ($pcie_class_code >> 16) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_sub" [format "%02x" [expr ($pcie_class_code >> 8) & 0xff]] +dict set pcie_config "CONFIG.pf0_class_code_interface" [format "%02x" [expr $pcie_class_code & 0xff]] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl index 6266e2c9d..d804d6a17 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl @@ -209,17 +209,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -264,6 +253,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl index 8e0a5c429..f8f27e92f 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl index acc8330f1..45dec12d5 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl index e2c460080..3a9369dce 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl @@ -209,17 +209,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -264,6 +253,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl index 3f436a8c3..d3f986bef 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl index 8e8f7b768..5a6f9594a 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl index 86d1a5969..b488c1cc2 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl @@ -209,17 +209,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -264,6 +253,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl index a21411961..76dd76504 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl index 3867fdc8c..580395ef6 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl index d69530e63..a998acf94 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl @@ -212,17 +212,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -267,6 +256,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl index dddae149d..e16984458 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl @@ -209,17 +209,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -264,6 +253,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl index 8c06793c5..c3f3c05aa 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl @@ -209,17 +209,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -264,6 +253,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl index 8b50c9337..668e25b8c 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl @@ -209,17 +209,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -264,6 +253,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl index 23c1a10df..31321d2f7 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl @@ -209,17 +209,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -264,6 +253,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl index e4667cc35..0b9fa2ec9 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl index ee44106fe..f021f1130 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create] diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl index f5d9541a5..cf4b9b82c 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl @@ -222,17 +222,6 @@ if {[dict get $params DDR_ENABLE]} { # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] -# PCIe IDs -set_property CONFIG.vendor_id [format "%04x" $pcie_vendor_id] $pcie -set_property CONFIG.PF0_DEVICE_ID [format "%04x" $pcie_device_id] $pcie -set_property CONFIG.PF0_CLASS_CODE [format "%06x" $pcie_class_code] $pcie -set_property CONFIG.PF0_REVISION_ID [format "%02x" $pcie_revision_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_VENDOR_ID [format "%04x" $pcie_subsystem_vendor_id] $pcie -set_property CONFIG.PF0_SUBSYSTEM_ID [format "%04x" $pcie_subsystem_device_id] $pcie - -# PCIe IP core configuration -set_property CONFIG.PF0_MSIX_CAP_TABLE_SIZE [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] $pcie - # Internal interface settings dict set params AXIS_PCIE_DATA_WIDTH [regexp -all -inline -- {[0-9]+} [get_property CONFIG.axisten_if_width $pcie]] dict set params AXIS_PCIE_KEEP_WIDTH [expr [dict get $params AXIS_PCIE_DATA_WIDTH]/32] @@ -277,6 +266,29 @@ configure_bar $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH] # Application BAR (BAR 2) configure_bar $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0] +# PCIe IP core configuration +set pcie_config [dict create] + +# PCIe IDs +dict set pcie_config "CONFIG.vendor_id" [format "%04x" $pcie_vendor_id] +dict set pcie_config "CONFIG.PF0_DEVICE_ID" [format "%04x" $pcie_device_id] +dict set pcie_config "CONFIG.PF0_CLASS_CODE" [format "%06x" $pcie_class_code] +dict set pcie_config "CONFIG.PF0_REVISION_ID" [format "%02x" $pcie_revision_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_VENDOR_ID" [format "%04x" $pcie_subsystem_vendor_id] +dict set pcie_config "CONFIG.PF0_SUBSYSTEM_ID" [format "%04x" $pcie_subsystem_device_id] + +# MSI-X +dict set pcie_config "CONFIG.pf0_msi_enabled" {false} +dict set pcie_config "CONFIG.pf0_msix_enabled" {true} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_SIZE" [format "%03x" [expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]] +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_TABLE_OFFSET" {00010000} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_BIR" {BAR_1:0} +dict set pcie_config "CONFIG.PF0_MSIX_CAP_PBA_OFFSET" {00018000} +dict set pcie_config "CONFIG.MSI_X_OPTIONS" {MSI-X_External} + +set_property -dict $pcie_config $pcie + # Transceiver configuration set xcvr_config [dict create]