diff --git a/example/VCU118/fpga_1g/fpga.xdc b/example/VCU118/fpga_1g/fpga.xdc index 3b1fd2272..a7aa10bb1 100644 --- a/example/VCU118/fpga_1g/fpga.xdc +++ b/example/VCU118/fpga_1g/fpga.xdc @@ -131,22 +131,22 @@ set_false_path -from [get_ports {phy_int_n phy_mdio}] set_input_delay 0 [get_ports {phy_int_n phy_mdio}] # QSFP28 Interfaces -#set_property -dict {LOC Y2 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC Y1 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC V6 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC W4 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC W3 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC V2 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC V1 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC P7 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC P6 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC U4 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC U3 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC M7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -#set_property -dict {LOC M6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC Y2 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC Y1 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC V7 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC V6 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC W4 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC W3 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC V2 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC V1 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC M7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +#set_property -dict {LOC M6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 #set_property -dict {LOC W9 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U38.4 #set_property -dict {LOC W8 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U38.5 #set_property -dict {LOC U9 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U57.28 @@ -167,22 +167,22 @@ set_input_delay 0 [get_ports {phy_int_n phy_mdio}] #set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] #set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] -#set_property -dict {LOC T2 } [get_ports qsfp2_rx1_p] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC T1 } [get_ports qsfp2_rx1_n] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC R4 } [get_ports qsfp2_rx2_p] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC R3 } [get_ports qsfp2_rx2_n] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC K7 } [get_ports qsfp2_tx2_p] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC K6 } [get_ports qsfp2_tx2_n] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC P2 } [get_ports qsfp2_rx3_p] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC P1 } [get_ports qsfp2_rx3_n] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC J5 } [get_ports qsfp2_tx3_p] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC J4 } [get_ports qsfp2_tx3_n] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -#set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC T2 } [get_ports {qsfp2_rx_p[0]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC T1 } [get_ports {qsfp2_rx_n[0]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC L5 } [get_ports {qsfp2_tx_p[0]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC L4 } [get_ports {qsfp2_tx_n[0]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC R4 } [get_ports {qsfp2_rx_p[1]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC R3 } [get_ports {qsfp2_rx_n[1]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC K7 } [get_ports {qsfp2_tx_p[1]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC K6 } [get_ports {qsfp2_tx_n[1]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC P2 } [get_ports {qsfp2_rx_p[2]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC P1 } [get_ports {qsfp2_rx_n[2]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC J5 } [get_ports {qsfp2_tx_p[2]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC J4 } [get_ports {qsfp2_tx_n[2]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC M2 } [get_ports {qsfp2_rx_p[3]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC M1 } [get_ports {qsfp2_rx_n[3]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC H7 } [get_ports {qsfp2_tx_p[3]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +#set_property -dict {LOC H6 } [get_ports {qsfp2_tx_n[3]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 #set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13 #set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14 #set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35 diff --git a/example/VCU118/fpga_25g/fpga.xdc b/example/VCU118/fpga_25g/fpga.xdc index c2fda604f..df08d8be8 100644 --- a/example/VCU118/fpga_25g/fpga.xdc +++ b/example/VCU118/fpga_25g/fpga.xdc @@ -131,22 +131,22 @@ set_false_path -from [get_ports {phy_int_n phy_mdio}] set_input_delay 0 [get_ports {phy_int_n phy_mdio}] # QSFP28 Interfaces -set_property -dict {LOC Y2 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC Y1 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V6 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC W4 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC W3 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V2 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V1 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC P7 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC P6 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC U4 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC U3 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC Y2 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC Y1 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V7 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V6 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC W4 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC W3 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V2 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V1 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 set_property -dict {LOC W9 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U38.4 set_property -dict {LOC W8 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U38.5 #set_property -dict {LOC U9 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U57.28 @@ -167,22 +167,22 @@ set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}] set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] -set_property -dict {LOC T2 } [get_ports qsfp2_rx1_p] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC T1 } [get_ports qsfp2_rx1_n] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R4 } [get_ports qsfp2_rx2_p] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R3 } [get_ports qsfp2_rx2_n] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC K7 } [get_ports qsfp2_tx2_p] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC K6 } [get_ports qsfp2_tx2_n] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC P2 } [get_ports qsfp2_rx3_p] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC P1 } [get_ports qsfp2_rx3_n] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC J5 } [get_ports qsfp2_tx3_p] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC J4 } [get_ports qsfp2_tx3_n] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC T2 } [get_ports {qsfp2_rx_p[0]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC T1 } [get_ports {qsfp2_rx_n[0]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC L5 } [get_ports {qsfp2_tx_p[0]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC L4 } [get_ports {qsfp2_tx_n[0]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC R4 } [get_ports {qsfp2_rx_p[1]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC R3 } [get_ports {qsfp2_rx_n[1]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC K7 } [get_ports {qsfp2_tx_p[1]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC K6 } [get_ports {qsfp2_tx_n[1]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC P2 } [get_ports {qsfp2_rx_p[2]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC P1 } [get_ports {qsfp2_rx_n[2]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC J5 } [get_ports {qsfp2_tx_p[2]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC J4 } [get_ports {qsfp2_tx_n[2]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC M2 } [get_ports {qsfp2_rx_p[3]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC M1 } [get_ports {qsfp2_rx_n[3]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H7 } [get_ports {qsfp2_tx_p[3]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H6 } [get_ports {qsfp2_tx_n[3]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 #set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13 #set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14 #set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35 diff --git a/example/VCU118/fpga_25g/fpga/Makefile b/example/VCU118/fpga_25g/fpga/Makefile index 81d9f3750..91326ee2d 100644 --- a/example/VCU118/fpga_25g/fpga/Makefile +++ b/example/VCU118/fpga_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/mdio_master.v diff --git a/example/VCU118/fpga_25g/fpga_10g/Makefile b/example/VCU118/fpga_25g/fpga_10g/Makefile index 81d9f3750..91326ee2d 100644 --- a/example/VCU118/fpga_25g/fpga_10g/Makefile +++ b/example/VCU118/fpga_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/mdio_master.v diff --git a/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/VCU118/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/VCU118/fpga_25g/rtl/fpga.v b/example/VCU118/fpga_25g/rtl/fpga.v index 30b580ab2..5f091a973 100644 --- a/example/VCU118/fpga_25g/rtl/fpga.v +++ b/example/VCU118/fpga_25g/rtl/fpga.v @@ -60,22 +60,10 @@ module fpga ( /* * Ethernet: QSFP28 */ - output wire qsfp1_tx1_p, - output wire qsfp1_tx1_n, - input wire qsfp1_rx1_p, - input wire qsfp1_rx1_n, - output wire qsfp1_tx2_p, - output wire qsfp1_tx2_n, - input wire qsfp1_rx2_p, - input wire qsfp1_rx2_n, - output wire qsfp1_tx3_p, - output wire qsfp1_tx3_n, - input wire qsfp1_rx3_p, - input wire qsfp1_rx3_n, - output wire qsfp1_tx4_p, - output wire qsfp1_tx4_n, - input wire qsfp1_rx4_p, - input wire qsfp1_rx4_n, + output wire [3:0] qsfp1_tx_p, + output wire [3:0] qsfp1_tx_n, + input wire [3:0] qsfp1_rx_p, + input wire [3:0] qsfp1_rx_n, input wire qsfp1_mgt_refclk_0_p, input wire qsfp1_mgt_refclk_0_n, // input wire qsfp1_mgt_refclk_1_p, @@ -88,22 +76,10 @@ module fpga ( input wire qsfp1_intl, output wire qsfp1_lpmode, - output wire qsfp2_tx1_p, - output wire qsfp2_tx1_n, - input wire qsfp2_rx1_p, - input wire qsfp2_rx1_n, - output wire qsfp2_tx2_p, - output wire qsfp2_tx2_n, - input wire qsfp2_rx2_p, - input wire qsfp2_rx2_n, - output wire qsfp2_tx3_p, - output wire qsfp2_tx3_n, - input wire qsfp2_rx3_p, - input wire qsfp2_rx3_n, - output wire qsfp2_tx4_p, - output wire qsfp2_tx4_n, - input wire qsfp2_rx4_p, - input wire qsfp2_rx4_n, + output wire [3:0] qsfp2_tx_p, + output wire [3:0] qsfp2_tx_n, + input wire [3:0] qsfp2_rx_p, + input wire [3:0] qsfp2_rx_n, // input wire qsfp2_mgt_refclk_0_p, // input wire qsfp2_mgt_refclk_0_n, // input wire qsfp2_mgt_refclk_1_p, @@ -343,218 +319,109 @@ wire qsfp1_rx_block_lock_2; wire qsfp1_rx_block_lock_3; wire qsfp1_rx_block_lock_4; -wire qsfp1_mgt_refclk_0; +wire qsfp1_mgt_refclk; IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_0_inst ( .I (qsfp1_mgt_refclk_0_p), .IB (qsfp1_mgt_refclk_0_n), .CEB (1'b0), - .O (qsfp1_mgt_refclk_0), + .O (qsfp1_mgt_refclk), .ODIV2 () ); -wire qsfp1_qpll0lock; -wire qsfp1_qpll0outclk; -wire qsfp1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out - .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_0), - .xcvr_qpll0lock_out(qsfp1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk), + /* + * PLL + */ + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp1_tx_p), + .xcvr_txn(qsfp1_tx_n), + .xcvr_rxp(qsfp1_rx_p), + .xcvr_rxn(qsfp1_rx_n), - // Serial data - .xcvr_txp(qsfp1_tx1_p), - .xcvr_txn(qsfp1_tx1_n), - .xcvr_rxp(qsfp1_rx1_p), - .xcvr_rxn(qsfp1_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp1_tx_clk_1_int), + .phy_1_tx_rst(qsfp1_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp1_txd_1_int), + .phy_1_xgmii_txc(qsfp1_txc_1_int), + .phy_1_rx_clk(qsfp1_rx_clk_1_int), + .phy_1_rx_rst(qsfp1_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp1_rxd_1_int), + .phy_1_xgmii_rxc(qsfp1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_1_int), - .phy_tx_rst(qsfp1_tx_rst_1_int), - .phy_xgmii_txd(qsfp1_txd_1_int), - .phy_xgmii_txc(qsfp1_txc_1_int), - .phy_rx_clk(qsfp1_rx_clk_1_int), - .phy_rx_rst(qsfp1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp1_rxd_1_int), - .phy_xgmii_rxc(qsfp1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp1_tx_clk_2_int), + .phy_2_tx_rst(qsfp1_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp1_txd_2_int), + .phy_2_xgmii_txc(qsfp1_txc_2_int), + .phy_2_rx_clk(qsfp1_rx_clk_2_int), + .phy_2_rx_rst(qsfp1_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp1_rxd_2_int), + .phy_2_xgmii_rxc(qsfp1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp1_tx_clk_3_int), + .phy_3_tx_rst(qsfp1_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp1_txd_3_int), + .phy_3_xgmii_txc(qsfp1_txc_3_int), + .phy_3_rx_clk(qsfp1_rx_clk_3_int), + .phy_3_rx_rst(qsfp1_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp1_rxd_3_int), + .phy_3_xgmii_rxc(qsfp1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx2_p), - .xcvr_txn(qsfp1_tx2_n), - .xcvr_rxp(qsfp1_rx2_p), - .xcvr_rxn(qsfp1_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_2_int), - .phy_tx_rst(qsfp1_tx_rst_2_int), - .phy_xgmii_txd(qsfp1_txd_2_int), - .phy_xgmii_txc(qsfp1_txc_2_int), - .phy_rx_clk(qsfp1_rx_clk_2_int), - .phy_rx_rst(qsfp1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp1_rxd_2_int), - .phy_xgmii_rxc(qsfp1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx3_p), - .xcvr_txn(qsfp1_tx3_n), - .xcvr_rxp(qsfp1_rx3_p), - .xcvr_rxn(qsfp1_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_3_int), - .phy_tx_rst(qsfp1_tx_rst_3_int), - .phy_xgmii_txd(qsfp1_txd_3_int), - .phy_xgmii_txc(qsfp1_txc_3_int), - .phy_rx_clk(qsfp1_rx_clk_3_int), - .phy_rx_rst(qsfp1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp1_rxd_3_int), - .phy_xgmii_rxc(qsfp1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx4_p), - .xcvr_txn(qsfp1_tx4_n), - .xcvr_rxp(qsfp1_rx4_p), - .xcvr_rxn(qsfp1_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_4_int), - .phy_tx_rst(qsfp1_tx_rst_4_int), - .phy_xgmii_txd(qsfp1_txd_4_int), - .phy_xgmii_txc(qsfp1_txc_4_int), - .phy_rx_clk(qsfp1_rx_clk_4_int), - .phy_rx_rst(qsfp1_rx_rst_4_int), - .phy_xgmii_rxd(qsfp1_rxd_4_int), - .phy_xgmii_rxc(qsfp1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp1_tx_clk_4_int), + .phy_4_tx_rst(qsfp1_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp1_txd_4_int), + .phy_4_xgmii_txc(qsfp1_txc_4_int), + .phy_4_rx_clk(qsfp1_rx_clk_4_int), + .phy_4_rx_rst(qsfp1_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp1_rxd_4_int), + .phy_4_xgmii_rxc(qsfp1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP2 @@ -600,208 +467,99 @@ wire qsfp2_rx_block_lock_2; wire qsfp2_rx_block_lock_3; wire qsfp2_rx_block_lock_4; -wire qsfp2_qpll0lock; -wire qsfp2_qpll0outclk; -wire qsfp2_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp2_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out - .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_0), - .xcvr_qpll0lock_out(qsfp2_qpll0lock), - .xcvr_qpll0outclk_out(qsfp2_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp2_qpll0outrefclk), + /* + * PLL + */ + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp2_tx_p), + .xcvr_txn(qsfp2_tx_n), + .xcvr_rxp(qsfp2_rx_p), + .xcvr_rxn(qsfp2_rx_n), - // Serial data - .xcvr_txp(qsfp2_tx1_p), - .xcvr_txn(qsfp2_tx1_n), - .xcvr_rxp(qsfp2_rx1_p), - .xcvr_rxn(qsfp2_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp2_tx_clk_1_int), + .phy_1_tx_rst(qsfp2_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp2_txd_1_int), + .phy_1_xgmii_txc(qsfp2_txc_1_int), + .phy_1_rx_clk(qsfp2_rx_clk_1_int), + .phy_1_rx_rst(qsfp2_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp2_rxd_1_int), + .phy_1_xgmii_rxc(qsfp2_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp2_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_1_int), - .phy_tx_rst(qsfp2_tx_rst_1_int), - .phy_xgmii_txd(qsfp2_txd_1_int), - .phy_xgmii_txc(qsfp2_txc_1_int), - .phy_rx_clk(qsfp2_rx_clk_1_int), - .phy_rx_rst(qsfp2_rx_rst_1_int), - .phy_xgmii_rxd(qsfp2_rxd_1_int), - .phy_xgmii_rxc(qsfp2_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp2_tx_clk_2_int), + .phy_2_tx_rst(qsfp2_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp2_txd_2_int), + .phy_2_xgmii_txc(qsfp2_txc_2_int), + .phy_2_rx_clk(qsfp2_rx_clk_2_int), + .phy_2_rx_rst(qsfp2_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp2_rxd_2_int), + .phy_2_xgmii_rxc(qsfp2_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp2_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp2_tx_clk_3_int), + .phy_3_tx_rst(qsfp2_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp2_txd_3_int), + .phy_3_xgmii_txc(qsfp2_txc_3_int), + .phy_3_rx_clk(qsfp2_rx_clk_3_int), + .phy_3_rx_rst(qsfp2_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp2_rxd_3_int), + .phy_3_xgmii_rxc(qsfp2_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp2_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx2_p), - .xcvr_txn(qsfp2_tx2_n), - .xcvr_rxp(qsfp2_rx2_p), - .xcvr_rxn(qsfp2_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_2_int), - .phy_tx_rst(qsfp2_tx_rst_2_int), - .phy_xgmii_txd(qsfp2_txd_2_int), - .phy_xgmii_txc(qsfp2_txc_2_int), - .phy_rx_clk(qsfp2_rx_clk_2_int), - .phy_rx_rst(qsfp2_rx_rst_2_int), - .phy_xgmii_rxd(qsfp2_rxd_2_int), - .phy_xgmii_rxc(qsfp2_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx3_p), - .xcvr_txn(qsfp2_tx3_n), - .xcvr_rxp(qsfp2_rx3_p), - .xcvr_rxn(qsfp2_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_3_int), - .phy_tx_rst(qsfp2_tx_rst_3_int), - .phy_xgmii_txd(qsfp2_txd_3_int), - .phy_xgmii_txc(qsfp2_txc_3_int), - .phy_rx_clk(qsfp2_rx_clk_3_int), - .phy_rx_rst(qsfp2_rx_rst_3_int), - .phy_xgmii_rxd(qsfp2_rxd_3_int), - .phy_xgmii_rxc(qsfp2_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx4_p), - .xcvr_txn(qsfp2_tx4_n), - .xcvr_rxp(qsfp2_rx4_p), - .xcvr_rxn(qsfp2_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_4_int), - .phy_tx_rst(qsfp2_tx_rst_4_int), - .phy_xgmii_txd(qsfp2_txd_4_int), - .phy_xgmii_txc(qsfp2_txc_4_int), - .phy_rx_clk(qsfp2_rx_clk_4_int), - .phy_rx_rst(qsfp2_rx_rst_4_int), - .phy_xgmii_rxd(qsfp2_rxd_4_int), - .phy_xgmii_rxc(qsfp2_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp2_tx_clk_4_int), + .phy_4_tx_rst(qsfp2_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp2_txd_4_int), + .phy_4_xgmii_txc(qsfp2_txc_4_int), + .phy_4_rx_clk(qsfp2_rx_clk_4_int), + .phy_4_rx_rst(qsfp2_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp2_rxd_4_int), + .phy_4_xgmii_rxc(qsfp2_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp2_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // SGMII interface to PHY diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc index fb3596a51..8d5fb3f8f 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc @@ -131,22 +131,22 @@ set_false_path -from [get_ports {phy_int_n phy_mdio}] set_input_delay 0 [get_ports {phy_int_n phy_mdio}] # QSFP28 Interfaces -set_property -dict {LOC Y2 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC Y1 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V6 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC W4 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC W3 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V2 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V1 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC P7 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC P6 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC U4 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC U3 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC Y2 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC Y1 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V7 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V6 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC W4 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC W3 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC T7 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC T6 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V2 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC V1 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC P7 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC P6 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC U4 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC U3 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M7 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 +set_property -dict {LOC M6 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 set_property -dict {LOC W9 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U38.4 set_property -dict {LOC W8 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U38.5 #set_property -dict {LOC U9 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U57.28 @@ -167,22 +167,22 @@ set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}] set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] -set_property -dict {LOC T2 } [get_ports qsfp2_rx1_p] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC T1 } [get_ports qsfp2_rx1_n] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R4 } [get_ports qsfp2_rx2_p] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R3 } [get_ports qsfp2_rx2_n] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC K7 } [get_ports qsfp2_tx2_p] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC K6 } [get_ports qsfp2_tx2_n] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC P2 } [get_ports qsfp2_rx3_p] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC P1 } [get_ports qsfp2_rx3_n] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC J5 } [get_ports qsfp2_tx3_p] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC J4 } [get_ports qsfp2_tx3_n] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC T2 } [get_ports {qsfp2_rx_p[0]}] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC T1 } [get_ports {qsfp2_rx_n[0]}] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC L5 } [get_ports {qsfp2_tx_p[0]}] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC L4 } [get_ports {qsfp2_tx_n[0]}] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC R4 } [get_ports {qsfp2_rx_p[1]}] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC R3 } [get_ports {qsfp2_rx_n[1]}] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC K7 } [get_ports {qsfp2_tx_p[1]}] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC K6 } [get_ports {qsfp2_tx_n[1]}] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC P2 } [get_ports {qsfp2_rx_p[2]}] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC P1 } [get_ports {qsfp2_rx_n[2]}] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC J5 } [get_ports {qsfp2_tx_p[2]}] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC J4 } [get_ports {qsfp2_tx_n[2]}] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC M2 } [get_ports {qsfp2_rx_p[3]}] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC M1 } [get_ports {qsfp2_rx_n[3]}] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H7 } [get_ports {qsfp2_tx_p[3]}] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 +set_property -dict {LOC H6 } [get_ports {qsfp2_tx_n[3]}] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 #set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13 #set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14 #set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35 diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/Makefile b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/Makefile index 42996a88f..1f4bdd60d 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/Makefile +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/mdio_master.v diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile index 42996a88f..1f4bdd60d 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/mdio_master.v diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v index 7e8b9d95e..fbfa089b2 100644 --- a/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v +++ b/example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v @@ -60,22 +60,10 @@ module fpga ( /* * Ethernet: QSFP28 */ - output wire qsfp1_tx1_p, - output wire qsfp1_tx1_n, - input wire qsfp1_rx1_p, - input wire qsfp1_rx1_n, - output wire qsfp1_tx2_p, - output wire qsfp1_tx2_n, - input wire qsfp1_rx2_p, - input wire qsfp1_rx2_n, - output wire qsfp1_tx3_p, - output wire qsfp1_tx3_n, - input wire qsfp1_rx3_p, - input wire qsfp1_rx3_n, - output wire qsfp1_tx4_p, - output wire qsfp1_tx4_n, - input wire qsfp1_rx4_p, - input wire qsfp1_rx4_n, + output wire [3:0] qsfp1_tx_p, + output wire [3:0] qsfp1_tx_n, + input wire [3:0] qsfp1_rx_p, + input wire [3:0] qsfp1_rx_n, input wire qsfp1_mgt_refclk_0_p, input wire qsfp1_mgt_refclk_0_n, // input wire qsfp1_mgt_refclk_1_p, @@ -88,22 +76,10 @@ module fpga ( input wire qsfp1_intl, output wire qsfp1_lpmode, - output wire qsfp2_tx1_p, - output wire qsfp2_tx1_n, - input wire qsfp2_rx1_p, - input wire qsfp2_rx1_n, - output wire qsfp2_tx2_p, - output wire qsfp2_tx2_n, - input wire qsfp2_rx2_p, - input wire qsfp2_rx2_n, - output wire qsfp2_tx3_p, - output wire qsfp2_tx3_n, - input wire qsfp2_rx3_p, - input wire qsfp2_rx3_n, - output wire qsfp2_tx4_p, - output wire qsfp2_tx4_n, - input wire qsfp2_rx4_p, - input wire qsfp2_rx4_n, + output wire [3:0] qsfp2_tx_p, + output wire [3:0] qsfp2_tx_n, + input wire [3:0] qsfp2_rx_p, + input wire [3:0] qsfp2_rx_n, // input wire qsfp2_mgt_refclk_0_p, // input wire qsfp2_mgt_refclk_0_n, // input wire qsfp2_mgt_refclk_1_p, @@ -535,208 +511,99 @@ OBUFDS obufds_fmc_refclk_inst ( .OB(fmcp_hspc_sync_c2m_n) ); -wire qsfp1_qpll0lock; -wire qsfp1_qpll0outclk; -wire qsfp1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(qsfp1_gtpowergood), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp1_mgt_refclk), - .xcvr_qpll0lock_out(qsfp1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp1_tx_p), + .xcvr_txn(qsfp1_tx_n), + .xcvr_rxp(qsfp1_rx_p), + .xcvr_rxn(qsfp1_rx_n), - // Serial data - .xcvr_txp(qsfp1_tx1_p), - .xcvr_txn(qsfp1_tx1_n), - .xcvr_rxp(qsfp1_rx1_p), - .xcvr_rxn(qsfp1_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp1_tx_clk_1_int), + .phy_1_tx_rst(qsfp1_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp1_txd_1_int), + .phy_1_xgmii_txc(qsfp1_txc_1_int), + .phy_1_rx_clk(qsfp1_rx_clk_1_int), + .phy_1_rx_rst(qsfp1_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp1_rxd_1_int), + .phy_1_xgmii_rxc(qsfp1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_1_int), - .phy_tx_rst(qsfp1_tx_rst_1_int), - .phy_xgmii_txd(qsfp1_txd_1_int), - .phy_xgmii_txc(qsfp1_txc_1_int), - .phy_rx_clk(qsfp1_rx_clk_1_int), - .phy_rx_rst(qsfp1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp1_rxd_1_int), - .phy_xgmii_rxc(qsfp1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp1_tx_clk_2_int), + .phy_2_tx_rst(qsfp1_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp1_txd_2_int), + .phy_2_xgmii_txc(qsfp1_txc_2_int), + .phy_2_rx_clk(qsfp1_rx_clk_2_int), + .phy_2_rx_rst(qsfp1_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp1_rxd_2_int), + .phy_2_xgmii_rxc(qsfp1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp1_tx_clk_3_int), + .phy_3_tx_rst(qsfp1_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp1_txd_3_int), + .phy_3_xgmii_txc(qsfp1_txc_3_int), + .phy_3_rx_clk(qsfp1_rx_clk_3_int), + .phy_3_rx_rst(qsfp1_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp1_rxd_3_int), + .phy_3_xgmii_rxc(qsfp1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx2_p), - .xcvr_txn(qsfp1_tx2_n), - .xcvr_rxp(qsfp1_rx2_p), - .xcvr_rxn(qsfp1_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_2_int), - .phy_tx_rst(qsfp1_tx_rst_2_int), - .phy_xgmii_txd(qsfp1_txd_2_int), - .phy_xgmii_txc(qsfp1_txc_2_int), - .phy_rx_clk(qsfp1_rx_clk_2_int), - .phy_rx_rst(qsfp1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp1_rxd_2_int), - .phy_xgmii_rxc(qsfp1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx3_p), - .xcvr_txn(qsfp1_tx3_n), - .xcvr_rxp(qsfp1_rx3_p), - .xcvr_rxn(qsfp1_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_3_int), - .phy_tx_rst(qsfp1_tx_rst_3_int), - .phy_xgmii_txd(qsfp1_txd_3_int), - .phy_xgmii_txc(qsfp1_txc_3_int), - .phy_rx_clk(qsfp1_rx_clk_3_int), - .phy_rx_rst(qsfp1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp1_rxd_3_int), - .phy_xgmii_rxc(qsfp1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx4_p), - .xcvr_txn(qsfp1_tx4_n), - .xcvr_rxp(qsfp1_rx4_p), - .xcvr_rxn(qsfp1_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_4_int), - .phy_tx_rst(qsfp1_tx_rst_4_int), - .phy_xgmii_txd(qsfp1_txd_4_int), - .phy_xgmii_txc(qsfp1_txc_4_int), - .phy_rx_clk(qsfp1_rx_clk_4_int), - .phy_rx_rst(qsfp1_rx_rst_4_int), - .phy_xgmii_rxd(qsfp1_rxd_4_int), - .phy_xgmii_rxc(qsfp1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp1_tx_clk_4_int), + .phy_4_tx_rst(qsfp1_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp1_txd_4_int), + .phy_4_xgmii_txc(qsfp1_txc_4_int), + .phy_4_rx_clk(qsfp1_rx_clk_4_int), + .phy_4_rx_rst(qsfp1_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp1_rxd_4_int), + .phy_4_xgmii_rxc(qsfp1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP2 @@ -782,208 +649,99 @@ wire qsfp2_rx_block_lock_2; wire qsfp2_rx_block_lock_3; wire qsfp2_rx_block_lock_4; -wire qsfp2_qpll0lock; -wire qsfp2_qpll0outclk; -wire qsfp2_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +qsfp2_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp1_mgt_refclk), - .xcvr_qpll0lock_out(qsfp2_qpll0lock), - .xcvr_qpll0outclk_out(qsfp2_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp2_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp2_tx_p), + .xcvr_txn(qsfp2_tx_n), + .xcvr_rxp(qsfp2_rx_p), + .xcvr_rxn(qsfp2_rx_n), - // Serial data - .xcvr_txp(qsfp2_tx1_p), - .xcvr_txn(qsfp2_tx1_n), - .xcvr_rxp(qsfp2_rx1_p), - .xcvr_rxn(qsfp2_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp2_tx_clk_1_int), + .phy_1_tx_rst(qsfp2_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp2_txd_1_int), + .phy_1_xgmii_txc(qsfp2_txc_1_int), + .phy_1_rx_clk(qsfp2_rx_clk_1_int), + .phy_1_rx_rst(qsfp2_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp2_rxd_1_int), + .phy_1_xgmii_rxc(qsfp2_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp2_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_1_int), - .phy_tx_rst(qsfp2_tx_rst_1_int), - .phy_xgmii_txd(qsfp2_txd_1_int), - .phy_xgmii_txc(qsfp2_txc_1_int), - .phy_rx_clk(qsfp2_rx_clk_1_int), - .phy_rx_rst(qsfp2_rx_rst_1_int), - .phy_xgmii_rxd(qsfp2_rxd_1_int), - .phy_xgmii_rxc(qsfp2_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp2_tx_clk_2_int), + .phy_2_tx_rst(qsfp2_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp2_txd_2_int), + .phy_2_xgmii_txc(qsfp2_txc_2_int), + .phy_2_rx_clk(qsfp2_rx_clk_2_int), + .phy_2_rx_rst(qsfp2_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp2_rxd_2_int), + .phy_2_xgmii_rxc(qsfp2_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp2_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp2_tx_clk_3_int), + .phy_3_tx_rst(qsfp2_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp2_txd_3_int), + .phy_3_xgmii_txc(qsfp2_txc_3_int), + .phy_3_rx_clk(qsfp2_rx_clk_3_int), + .phy_3_rx_rst(qsfp2_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp2_rxd_3_int), + .phy_3_xgmii_rxc(qsfp2_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp2_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx2_p), - .xcvr_txn(qsfp2_tx2_n), - .xcvr_rxp(qsfp2_rx2_p), - .xcvr_rxn(qsfp2_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_2_int), - .phy_tx_rst(qsfp2_tx_rst_2_int), - .phy_xgmii_txd(qsfp2_txd_2_int), - .phy_xgmii_txc(qsfp2_txc_2_int), - .phy_rx_clk(qsfp2_rx_clk_2_int), - .phy_rx_rst(qsfp2_rx_rst_2_int), - .phy_xgmii_rxd(qsfp2_rxd_2_int), - .phy_xgmii_rxc(qsfp2_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx3_p), - .xcvr_txn(qsfp2_tx3_n), - .xcvr_rxp(qsfp2_rx3_p), - .xcvr_rxn(qsfp2_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_3_int), - .phy_tx_rst(qsfp2_tx_rst_3_int), - .phy_xgmii_txd(qsfp2_txd_3_int), - .phy_xgmii_txc(qsfp2_txc_3_int), - .phy_rx_clk(qsfp2_rx_clk_3_int), - .phy_rx_rst(qsfp2_rx_rst_3_int), - .phy_xgmii_rxd(qsfp2_rxd_3_int), - .phy_xgmii_rxc(qsfp2_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0), - .TX_SERDES_PIPELINE(2), - .RX_SERDES_PIPELINE(2), - .COUNT_125US(125000/2.56) -) -qsfp2_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx4_p), - .xcvr_txn(qsfp2_tx4_n), - .xcvr_rxp(qsfp2_rx4_p), - .xcvr_rxn(qsfp2_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_4_int), - .phy_tx_rst(qsfp2_tx_rst_4_int), - .phy_xgmii_txd(qsfp2_txd_4_int), - .phy_xgmii_txc(qsfp2_txc_4_int), - .phy_rx_clk(qsfp2_rx_clk_4_int), - .phy_rx_rst(qsfp2_rx_rst_4_int), - .phy_xgmii_rxd(qsfp2_rxd_4_int), - .phy_xgmii_rxc(qsfp2_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp2_tx_clk_4_int), + .phy_4_tx_rst(qsfp2_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp2_txd_4_int), + .phy_4_xgmii_txc(qsfp2_txc_4_int), + .phy_4_rx_clk(qsfp2_rx_clk_4_int), + .phy_4_rx_rst(qsfp2_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp2_rxd_4_int), + .phy_4_xgmii_rxc(qsfp2_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp2_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP1 @@ -1039,196 +797,99 @@ IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp1_mgt_refclk_inst ( .ODIV2 () ); -wire fmcp_qsfp1_qpll0lock; -wire fmcp_qsfp1_qpll0outclk; -wire fmcp_qsfp1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmcp_qsfp1_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmcp_qsfp1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmcp_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmcp_qsfp1_mgt_refclk), - .xcvr_qpll0lock_out(fmcp_qsfp1_qpll0lock), - .xcvr_qpll0outclk_out(fmcp_qsfp1_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmcp_qsfp1_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmcp_qsfp1_tx_p), + .xcvr_txn(fmcp_qsfp1_tx_n), + .xcvr_rxp(fmcp_qsfp1_rx_p), + .xcvr_rxn(fmcp_qsfp1_rx_n), - // Serial data - .xcvr_txp(fmcp_qsfp1_tx_p[0]), - .xcvr_txn(fmcp_qsfp1_tx_n[0]), - .xcvr_rxp(fmcp_qsfp1_rx_p[0]), - .xcvr_rxn(fmcp_qsfp1_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmcp_qsfp1_tx_clk_1_int), + .phy_1_tx_rst(fmcp_qsfp1_tx_rst_1_int), + .phy_1_xgmii_txd(fmcp_qsfp1_txd_1_int), + .phy_1_xgmii_txc(fmcp_qsfp1_txc_1_int), + .phy_1_rx_clk(fmcp_qsfp1_rx_clk_1_int), + .phy_1_rx_rst(fmcp_qsfp1_rx_rst_1_int), + .phy_1_xgmii_rxd(fmcp_qsfp1_rxd_1_int), + .phy_1_xgmii_rxc(fmcp_qsfp1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmcp_qsfp1_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmcp_qsfp1_tx_clk_1_int), - .phy_tx_rst(fmcp_qsfp1_tx_rst_1_int), - .phy_xgmii_txd(fmcp_qsfp1_txd_1_int), - .phy_xgmii_txc(fmcp_qsfp1_txc_1_int), - .phy_rx_clk(fmcp_qsfp1_rx_clk_1_int), - .phy_rx_rst(fmcp_qsfp1_rx_rst_1_int), - .phy_xgmii_rxd(fmcp_qsfp1_rxd_1_int), - .phy_xgmii_rxc(fmcp_qsfp1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmcp_qsfp1_tx_clk_2_int), + .phy_2_tx_rst(fmcp_qsfp1_tx_rst_2_int), + .phy_2_xgmii_txd(fmcp_qsfp1_txd_2_int), + .phy_2_xgmii_txc(fmcp_qsfp1_txc_2_int), + .phy_2_rx_clk(fmcp_qsfp1_rx_clk_2_int), + .phy_2_rx_rst(fmcp_qsfp1_rx_rst_2_int), + .phy_2_xgmii_rxd(fmcp_qsfp1_rxd_2_int), + .phy_2_xgmii_rxc(fmcp_qsfp1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmcp_qsfp1_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), + .phy_3_tx_clk(fmcp_qsfp1_tx_clk_3_int), + .phy_3_tx_rst(fmcp_qsfp1_tx_rst_3_int), + .phy_3_xgmii_txd(fmcp_qsfp1_txd_3_int), + .phy_3_xgmii_txc(fmcp_qsfp1_txc_3_int), + .phy_3_rx_clk(fmcp_qsfp1_rx_clk_3_int), + .phy_3_rx_rst(fmcp_qsfp1_rx_rst_3_int), + .phy_3_xgmii_rxd(fmcp_qsfp1_rxd_3_int), + .phy_3_xgmii_rxc(fmcp_qsfp1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmcp_qsfp1_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp1_tx_p[1]), - .xcvr_txn(fmcp_qsfp1_tx_n[1]), - .xcvr_rxp(fmcp_qsfp1_rx_p[1]), - .xcvr_rxn(fmcp_qsfp1_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp1_tx_clk_2_int), - .phy_tx_rst(fmcp_qsfp1_tx_rst_2_int), - .phy_xgmii_txd(fmcp_qsfp1_txd_2_int), - .phy_xgmii_txc(fmcp_qsfp1_txc_2_int), - .phy_rx_clk(fmcp_qsfp1_rx_clk_2_int), - .phy_rx_rst(fmcp_qsfp1_rx_rst_2_int), - .phy_xgmii_rxd(fmcp_qsfp1_rxd_2_int), - .phy_xgmii_rxc(fmcp_qsfp1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp1_tx_p[2]), - .xcvr_txn(fmcp_qsfp1_tx_n[2]), - .xcvr_rxp(fmcp_qsfp1_rx_p[2]), - .xcvr_rxn(fmcp_qsfp1_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp1_tx_clk_3_int), - .phy_tx_rst(fmcp_qsfp1_tx_rst_3_int), - .phy_xgmii_txd(fmcp_qsfp1_txd_3_int), - .phy_xgmii_txc(fmcp_qsfp1_txc_3_int), - .phy_rx_clk(fmcp_qsfp1_rx_clk_3_int), - .phy_rx_rst(fmcp_qsfp1_rx_rst_3_int), - .phy_xgmii_rxd(fmcp_qsfp1_rxd_3_int), - .phy_xgmii_rxc(fmcp_qsfp1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp1_tx_p[3]), - .xcvr_txn(fmcp_qsfp1_tx_n[3]), - .xcvr_rxp(fmcp_qsfp1_rx_p[3]), - .xcvr_rxn(fmcp_qsfp1_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp1_tx_clk_4_int), - .phy_tx_rst(fmcp_qsfp1_tx_rst_4_int), - .phy_xgmii_txd(fmcp_qsfp1_txd_4_int), - .phy_xgmii_txc(fmcp_qsfp1_txc_4_int), - .phy_rx_clk(fmcp_qsfp1_rx_clk_4_int), - .phy_rx_rst(fmcp_qsfp1_rx_rst_4_int), - .phy_xgmii_rxd(fmcp_qsfp1_rxd_4_int), - .phy_xgmii_rxc(fmcp_qsfp1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmcp_qsfp1_tx_clk_4_int), + .phy_4_tx_rst(fmcp_qsfp1_tx_rst_4_int), + .phy_4_xgmii_txd(fmcp_qsfp1_txd_4_int), + .phy_4_xgmii_txc(fmcp_qsfp1_txc_4_int), + .phy_4_rx_clk(fmcp_qsfp1_rx_clk_4_int), + .phy_4_rx_rst(fmcp_qsfp1_rx_rst_4_int), + .phy_4_xgmii_rxd(fmcp_qsfp1_rxd_4_int), + .phy_4_xgmii_rxc(fmcp_qsfp1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmcp_qsfp1_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP2 @@ -1284,196 +945,99 @@ IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp2_mgt_refclk_inst ( .ODIV2 () ); -wire fmcp_qsfp2_qpll0lock; -wire fmcp_qsfp2_qpll0outclk; -wire fmcp_qsfp2_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmcp_qsfp2_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmcp_qsfp2_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmcp_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmcp_qsfp2_mgt_refclk), - .xcvr_qpll0lock_out(fmcp_qsfp2_qpll0lock), - .xcvr_qpll0outclk_out(fmcp_qsfp2_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmcp_qsfp2_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmcp_qsfp2_tx_p), + .xcvr_txn(fmcp_qsfp2_tx_n), + .xcvr_rxp(fmcp_qsfp2_rx_p), + .xcvr_rxn(fmcp_qsfp2_rx_n), - // Serial data - .xcvr_txp(fmcp_qsfp2_tx_p[0]), - .xcvr_txn(fmcp_qsfp2_tx_n[0]), - .xcvr_rxp(fmcp_qsfp2_rx_p[0]), - .xcvr_rxn(fmcp_qsfp2_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmcp_qsfp2_tx_clk_1_int), + .phy_1_tx_rst(fmcp_qsfp2_tx_rst_1_int), + .phy_1_xgmii_txd(fmcp_qsfp2_txd_1_int), + .phy_1_xgmii_txc(fmcp_qsfp2_txc_1_int), + .phy_1_rx_clk(fmcp_qsfp2_rx_clk_1_int), + .phy_1_rx_rst(fmcp_qsfp2_rx_rst_1_int), + .phy_1_xgmii_rxd(fmcp_qsfp2_rxd_1_int), + .phy_1_xgmii_rxc(fmcp_qsfp2_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmcp_qsfp2_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmcp_qsfp2_tx_clk_1_int), - .phy_tx_rst(fmcp_qsfp2_tx_rst_1_int), - .phy_xgmii_txd(fmcp_qsfp2_txd_1_int), - .phy_xgmii_txc(fmcp_qsfp2_txc_1_int), - .phy_rx_clk(fmcp_qsfp2_rx_clk_1_int), - .phy_rx_rst(fmcp_qsfp2_rx_rst_1_int), - .phy_xgmii_rxd(fmcp_qsfp2_rxd_1_int), - .phy_xgmii_rxc(fmcp_qsfp2_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmcp_qsfp2_tx_clk_2_int), + .phy_2_tx_rst(fmcp_qsfp2_tx_rst_2_int), + .phy_2_xgmii_txd(fmcp_qsfp2_txd_2_int), + .phy_2_xgmii_txc(fmcp_qsfp2_txc_2_int), + .phy_2_rx_clk(fmcp_qsfp2_rx_clk_2_int), + .phy_2_rx_rst(fmcp_qsfp2_rx_rst_2_int), + .phy_2_xgmii_rxd(fmcp_qsfp2_rxd_2_int), + .phy_2_xgmii_rxc(fmcp_qsfp2_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmcp_qsfp2_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp2_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), + .phy_3_tx_clk(fmcp_qsfp2_tx_clk_3_int), + .phy_3_tx_rst(fmcp_qsfp2_tx_rst_3_int), + .phy_3_xgmii_txd(fmcp_qsfp2_txd_3_int), + .phy_3_xgmii_txc(fmcp_qsfp2_txc_3_int), + .phy_3_rx_clk(fmcp_qsfp2_rx_clk_3_int), + .phy_3_rx_rst(fmcp_qsfp2_rx_rst_3_int), + .phy_3_xgmii_rxd(fmcp_qsfp2_rxd_3_int), + .phy_3_xgmii_rxc(fmcp_qsfp2_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmcp_qsfp2_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp2_tx_p[1]), - .xcvr_txn(fmcp_qsfp2_tx_n[1]), - .xcvr_rxp(fmcp_qsfp2_rx_p[1]), - .xcvr_rxn(fmcp_qsfp2_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp2_tx_clk_2_int), - .phy_tx_rst(fmcp_qsfp2_tx_rst_2_int), - .phy_xgmii_txd(fmcp_qsfp2_txd_2_int), - .phy_xgmii_txc(fmcp_qsfp2_txc_2_int), - .phy_rx_clk(fmcp_qsfp2_rx_clk_2_int), - .phy_rx_rst(fmcp_qsfp2_rx_rst_2_int), - .phy_xgmii_rxd(fmcp_qsfp2_rxd_2_int), - .phy_xgmii_rxc(fmcp_qsfp2_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp2_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp2_tx_p[2]), - .xcvr_txn(fmcp_qsfp2_tx_n[2]), - .xcvr_rxp(fmcp_qsfp2_rx_p[2]), - .xcvr_rxn(fmcp_qsfp2_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp2_tx_clk_3_int), - .phy_tx_rst(fmcp_qsfp2_tx_rst_3_int), - .phy_xgmii_txd(fmcp_qsfp2_txd_3_int), - .phy_xgmii_txc(fmcp_qsfp2_txc_3_int), - .phy_rx_clk(fmcp_qsfp2_rx_clk_3_int), - .phy_rx_rst(fmcp_qsfp2_rx_rst_3_int), - .phy_xgmii_rxd(fmcp_qsfp2_rxd_3_int), - .phy_xgmii_rxc(fmcp_qsfp2_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp2_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp2_tx_p[3]), - .xcvr_txn(fmcp_qsfp2_tx_n[3]), - .xcvr_rxp(fmcp_qsfp2_rx_p[3]), - .xcvr_rxn(fmcp_qsfp2_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp2_tx_clk_4_int), - .phy_tx_rst(fmcp_qsfp2_tx_rst_4_int), - .phy_xgmii_txd(fmcp_qsfp2_txd_4_int), - .phy_xgmii_txc(fmcp_qsfp2_txc_4_int), - .phy_rx_clk(fmcp_qsfp2_rx_clk_4_int), - .phy_rx_rst(fmcp_qsfp2_rx_rst_4_int), - .phy_xgmii_rxd(fmcp_qsfp2_rxd_4_int), - .phy_xgmii_rxc(fmcp_qsfp2_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp2_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmcp_qsfp2_tx_clk_4_int), + .phy_4_tx_rst(fmcp_qsfp2_tx_rst_4_int), + .phy_4_xgmii_txd(fmcp_qsfp2_txd_4_int), + .phy_4_xgmii_txc(fmcp_qsfp2_txc_4_int), + .phy_4_rx_clk(fmcp_qsfp2_rx_clk_4_int), + .phy_4_rx_rst(fmcp_qsfp2_rx_rst_4_int), + .phy_4_xgmii_rxd(fmcp_qsfp2_rxd_4_int), + .phy_4_xgmii_rxc(fmcp_qsfp2_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmcp_qsfp2_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP3 @@ -1529,196 +1093,99 @@ IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp3_mgt_refclk_inst ( .ODIV2 () ); -wire fmcp_qsfp3_qpll0lock; -wire fmcp_qsfp3_qpll0outclk; -wire fmcp_qsfp3_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmcp_qsfp3_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmcp_qsfp3_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmcp_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmcp_qsfp3_mgt_refclk), - .xcvr_qpll0lock_out(fmcp_qsfp3_qpll0lock), - .xcvr_qpll0outclk_out(fmcp_qsfp3_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmcp_qsfp3_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmcp_qsfp3_tx_p), + .xcvr_txn(fmcp_qsfp3_tx_n), + .xcvr_rxp(fmcp_qsfp3_rx_p), + .xcvr_rxn(fmcp_qsfp3_rx_n), - // Serial data - .xcvr_txp(fmcp_qsfp3_tx_p[0]), - .xcvr_txn(fmcp_qsfp3_tx_n[0]), - .xcvr_rxp(fmcp_qsfp3_rx_p[0]), - .xcvr_rxn(fmcp_qsfp3_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmcp_qsfp3_tx_clk_1_int), + .phy_1_tx_rst(fmcp_qsfp3_tx_rst_1_int), + .phy_1_xgmii_txd(fmcp_qsfp3_txd_1_int), + .phy_1_xgmii_txc(fmcp_qsfp3_txc_1_int), + .phy_1_rx_clk(fmcp_qsfp3_rx_clk_1_int), + .phy_1_rx_rst(fmcp_qsfp3_rx_rst_1_int), + .phy_1_xgmii_rxd(fmcp_qsfp3_rxd_1_int), + .phy_1_xgmii_rxc(fmcp_qsfp3_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmcp_qsfp3_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmcp_qsfp3_tx_clk_1_int), - .phy_tx_rst(fmcp_qsfp3_tx_rst_1_int), - .phy_xgmii_txd(fmcp_qsfp3_txd_1_int), - .phy_xgmii_txc(fmcp_qsfp3_txc_1_int), - .phy_rx_clk(fmcp_qsfp3_rx_clk_1_int), - .phy_rx_rst(fmcp_qsfp3_rx_rst_1_int), - .phy_xgmii_rxd(fmcp_qsfp3_rxd_1_int), - .phy_xgmii_rxc(fmcp_qsfp3_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmcp_qsfp3_tx_clk_2_int), + .phy_2_tx_rst(fmcp_qsfp3_tx_rst_2_int), + .phy_2_xgmii_txd(fmcp_qsfp3_txd_2_int), + .phy_2_xgmii_txc(fmcp_qsfp3_txc_2_int), + .phy_2_rx_clk(fmcp_qsfp3_rx_clk_2_int), + .phy_2_rx_rst(fmcp_qsfp3_rx_rst_2_int), + .phy_2_xgmii_rxd(fmcp_qsfp3_rxd_2_int), + .phy_2_xgmii_rxc(fmcp_qsfp3_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmcp_qsfp3_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp3_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), + .phy_3_tx_clk(fmcp_qsfp3_tx_clk_3_int), + .phy_3_tx_rst(fmcp_qsfp3_tx_rst_3_int), + .phy_3_xgmii_txd(fmcp_qsfp3_txd_3_int), + .phy_3_xgmii_txc(fmcp_qsfp3_txc_3_int), + .phy_3_rx_clk(fmcp_qsfp3_rx_clk_3_int), + .phy_3_rx_rst(fmcp_qsfp3_rx_rst_3_int), + .phy_3_xgmii_rxd(fmcp_qsfp3_rxd_3_int), + .phy_3_xgmii_rxc(fmcp_qsfp3_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmcp_qsfp3_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp3_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp3_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp3_tx_p[1]), - .xcvr_txn(fmcp_qsfp3_tx_n[1]), - .xcvr_rxp(fmcp_qsfp3_rx_p[1]), - .xcvr_rxn(fmcp_qsfp3_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp3_tx_clk_2_int), - .phy_tx_rst(fmcp_qsfp3_tx_rst_2_int), - .phy_xgmii_txd(fmcp_qsfp3_txd_2_int), - .phy_xgmii_txc(fmcp_qsfp3_txc_2_int), - .phy_rx_clk(fmcp_qsfp3_rx_clk_2_int), - .phy_rx_rst(fmcp_qsfp3_rx_rst_2_int), - .phy_xgmii_rxd(fmcp_qsfp3_rxd_2_int), - .phy_xgmii_rxc(fmcp_qsfp3_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp3_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp3_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp3_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp3_tx_p[2]), - .xcvr_txn(fmcp_qsfp3_tx_n[2]), - .xcvr_rxp(fmcp_qsfp3_rx_p[2]), - .xcvr_rxn(fmcp_qsfp3_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp3_tx_clk_3_int), - .phy_tx_rst(fmcp_qsfp3_tx_rst_3_int), - .phy_xgmii_txd(fmcp_qsfp3_txd_3_int), - .phy_xgmii_txc(fmcp_qsfp3_txc_3_int), - .phy_rx_clk(fmcp_qsfp3_rx_clk_3_int), - .phy_rx_rst(fmcp_qsfp3_rx_rst_3_int), - .phy_xgmii_rxd(fmcp_qsfp3_rxd_3_int), - .phy_xgmii_rxc(fmcp_qsfp3_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp3_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp3_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp3_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp3_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp3_tx_p[3]), - .xcvr_txn(fmcp_qsfp3_tx_n[3]), - .xcvr_rxp(fmcp_qsfp3_rx_p[3]), - .xcvr_rxn(fmcp_qsfp3_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp3_tx_clk_4_int), - .phy_tx_rst(fmcp_qsfp3_tx_rst_4_int), - .phy_xgmii_txd(fmcp_qsfp3_txd_4_int), - .phy_xgmii_txc(fmcp_qsfp3_txc_4_int), - .phy_rx_clk(fmcp_qsfp3_rx_clk_4_int), - .phy_rx_rst(fmcp_qsfp3_rx_rst_4_int), - .phy_xgmii_rxd(fmcp_qsfp3_rxd_4_int), - .phy_xgmii_rxc(fmcp_qsfp3_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp3_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmcp_qsfp3_tx_clk_4_int), + .phy_4_tx_rst(fmcp_qsfp3_tx_rst_4_int), + .phy_4_xgmii_txd(fmcp_qsfp3_txd_4_int), + .phy_4_xgmii_txc(fmcp_qsfp3_txc_4_int), + .phy_4_rx_clk(fmcp_qsfp3_rx_clk_4_int), + .phy_4_rx_rst(fmcp_qsfp3_rx_rst_4_int), + .phy_4_xgmii_rxd(fmcp_qsfp3_rxd_4_int), + .phy_4_xgmii_rxc(fmcp_qsfp3_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmcp_qsfp3_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP4 @@ -1774,196 +1241,99 @@ IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp4_mgt_refclk_inst ( .ODIV2 () ); -wire fmcp_qsfp4_qpll0lock; -wire fmcp_qsfp4_qpll0outclk; -wire fmcp_qsfp4_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmcp_qsfp4_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmcp_qsfp4_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmcp_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmcp_qsfp4_mgt_refclk), - .xcvr_qpll0lock_out(fmcp_qsfp4_qpll0lock), - .xcvr_qpll0outclk_out(fmcp_qsfp4_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmcp_qsfp4_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmcp_qsfp4_tx_p), + .xcvr_txn(fmcp_qsfp4_tx_n), + .xcvr_rxp(fmcp_qsfp4_rx_p), + .xcvr_rxn(fmcp_qsfp4_rx_n), - // Serial data - .xcvr_txp(fmcp_qsfp4_tx_p[0]), - .xcvr_txn(fmcp_qsfp4_tx_n[0]), - .xcvr_rxp(fmcp_qsfp4_rx_p[0]), - .xcvr_rxn(fmcp_qsfp4_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmcp_qsfp4_tx_clk_1_int), + .phy_1_tx_rst(fmcp_qsfp4_tx_rst_1_int), + .phy_1_xgmii_txd(fmcp_qsfp4_txd_1_int), + .phy_1_xgmii_txc(fmcp_qsfp4_txc_1_int), + .phy_1_rx_clk(fmcp_qsfp4_rx_clk_1_int), + .phy_1_rx_rst(fmcp_qsfp4_rx_rst_1_int), + .phy_1_xgmii_rxd(fmcp_qsfp4_rxd_1_int), + .phy_1_xgmii_rxc(fmcp_qsfp4_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmcp_qsfp4_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmcp_qsfp4_tx_clk_1_int), - .phy_tx_rst(fmcp_qsfp4_tx_rst_1_int), - .phy_xgmii_txd(fmcp_qsfp4_txd_1_int), - .phy_xgmii_txc(fmcp_qsfp4_txc_1_int), - .phy_rx_clk(fmcp_qsfp4_rx_clk_1_int), - .phy_rx_rst(fmcp_qsfp4_rx_rst_1_int), - .phy_xgmii_rxd(fmcp_qsfp4_rxd_1_int), - .phy_xgmii_rxc(fmcp_qsfp4_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmcp_qsfp4_tx_clk_2_int), + .phy_2_tx_rst(fmcp_qsfp4_tx_rst_2_int), + .phy_2_xgmii_txd(fmcp_qsfp4_txd_2_int), + .phy_2_xgmii_txc(fmcp_qsfp4_txc_2_int), + .phy_2_rx_clk(fmcp_qsfp4_rx_clk_2_int), + .phy_2_rx_rst(fmcp_qsfp4_rx_rst_2_int), + .phy_2_xgmii_rxd(fmcp_qsfp4_rxd_2_int), + .phy_2_xgmii_rxc(fmcp_qsfp4_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmcp_qsfp4_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp4_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), + .phy_3_tx_clk(fmcp_qsfp4_tx_clk_3_int), + .phy_3_tx_rst(fmcp_qsfp4_tx_rst_3_int), + .phy_3_xgmii_txd(fmcp_qsfp4_txd_3_int), + .phy_3_xgmii_txc(fmcp_qsfp4_txc_3_int), + .phy_3_rx_clk(fmcp_qsfp4_rx_clk_3_int), + .phy_3_rx_rst(fmcp_qsfp4_rx_rst_3_int), + .phy_3_xgmii_rxd(fmcp_qsfp4_rxd_3_int), + .phy_3_xgmii_rxc(fmcp_qsfp4_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmcp_qsfp4_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp4_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp4_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp4_tx_p[1]), - .xcvr_txn(fmcp_qsfp4_tx_n[1]), - .xcvr_rxp(fmcp_qsfp4_rx_p[1]), - .xcvr_rxn(fmcp_qsfp4_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp4_tx_clk_2_int), - .phy_tx_rst(fmcp_qsfp4_tx_rst_2_int), - .phy_xgmii_txd(fmcp_qsfp4_txd_2_int), - .phy_xgmii_txc(fmcp_qsfp4_txc_2_int), - .phy_rx_clk(fmcp_qsfp4_rx_clk_2_int), - .phy_rx_rst(fmcp_qsfp4_rx_rst_2_int), - .phy_xgmii_rxd(fmcp_qsfp4_rxd_2_int), - .phy_xgmii_rxc(fmcp_qsfp4_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp4_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp4_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp4_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp4_tx_p[2]), - .xcvr_txn(fmcp_qsfp4_tx_n[2]), - .xcvr_rxp(fmcp_qsfp4_rx_p[2]), - .xcvr_rxn(fmcp_qsfp4_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp4_tx_clk_3_int), - .phy_tx_rst(fmcp_qsfp4_tx_rst_3_int), - .phy_xgmii_txd(fmcp_qsfp4_txd_3_int), - .phy_xgmii_txc(fmcp_qsfp4_txc_3_int), - .phy_rx_clk(fmcp_qsfp4_rx_clk_3_int), - .phy_rx_rst(fmcp_qsfp4_rx_rst_3_int), - .phy_xgmii_rxd(fmcp_qsfp4_rxd_3_int), - .phy_xgmii_rxc(fmcp_qsfp4_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp4_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp4_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp4_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp4_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp4_tx_p[3]), - .xcvr_txn(fmcp_qsfp4_tx_n[3]), - .xcvr_rxp(fmcp_qsfp4_rx_p[3]), - .xcvr_rxn(fmcp_qsfp4_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp4_tx_clk_4_int), - .phy_tx_rst(fmcp_qsfp4_tx_rst_4_int), - .phy_xgmii_txd(fmcp_qsfp4_txd_4_int), - .phy_xgmii_txc(fmcp_qsfp4_txc_4_int), - .phy_rx_clk(fmcp_qsfp4_rx_clk_4_int), - .phy_rx_rst(fmcp_qsfp4_rx_rst_4_int), - .phy_xgmii_rxd(fmcp_qsfp4_rxd_4_int), - .phy_xgmii_rxc(fmcp_qsfp4_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp4_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmcp_qsfp4_tx_clk_4_int), + .phy_4_tx_rst(fmcp_qsfp4_tx_rst_4_int), + .phy_4_xgmii_txd(fmcp_qsfp4_txd_4_int), + .phy_4_xgmii_txc(fmcp_qsfp4_txc_4_int), + .phy_4_rx_clk(fmcp_qsfp4_rx_clk_4_int), + .phy_4_rx_rst(fmcp_qsfp4_rx_rst_4_int), + .phy_4_xgmii_rxd(fmcp_qsfp4_rxd_4_int), + .phy_4_xgmii_rxc(fmcp_qsfp4_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmcp_qsfp4_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP5 @@ -2019,196 +1389,99 @@ IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp5_mgt_refclk_inst ( .ODIV2 () ); -wire fmcp_qsfp5_qpll0lock; -wire fmcp_qsfp5_qpll0outclk; -wire fmcp_qsfp5_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmcp_qsfp5_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmcp_qsfp5_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmcp_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmcp_qsfp5_mgt_refclk), - .xcvr_qpll0lock_out(fmcp_qsfp5_qpll0lock), - .xcvr_qpll0outclk_out(fmcp_qsfp5_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmcp_qsfp5_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmcp_qsfp5_tx_p), + .xcvr_txn(fmcp_qsfp5_tx_n), + .xcvr_rxp(fmcp_qsfp5_rx_p), + .xcvr_rxn(fmcp_qsfp5_rx_n), - // Serial data - .xcvr_txp(fmcp_qsfp5_tx_p[0]), - .xcvr_txn(fmcp_qsfp5_tx_n[0]), - .xcvr_rxp(fmcp_qsfp5_rx_p[0]), - .xcvr_rxn(fmcp_qsfp5_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmcp_qsfp5_tx_clk_1_int), + .phy_1_tx_rst(fmcp_qsfp5_tx_rst_1_int), + .phy_1_xgmii_txd(fmcp_qsfp5_txd_1_int), + .phy_1_xgmii_txc(fmcp_qsfp5_txc_1_int), + .phy_1_rx_clk(fmcp_qsfp5_rx_clk_1_int), + .phy_1_rx_rst(fmcp_qsfp5_rx_rst_1_int), + .phy_1_xgmii_rxd(fmcp_qsfp5_rxd_1_int), + .phy_1_xgmii_rxc(fmcp_qsfp5_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmcp_qsfp5_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmcp_qsfp5_tx_clk_1_int), - .phy_tx_rst(fmcp_qsfp5_tx_rst_1_int), - .phy_xgmii_txd(fmcp_qsfp5_txd_1_int), - .phy_xgmii_txc(fmcp_qsfp5_txc_1_int), - .phy_rx_clk(fmcp_qsfp5_rx_clk_1_int), - .phy_rx_rst(fmcp_qsfp5_rx_rst_1_int), - .phy_xgmii_rxd(fmcp_qsfp5_rxd_1_int), - .phy_xgmii_rxc(fmcp_qsfp5_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmcp_qsfp5_tx_clk_2_int), + .phy_2_tx_rst(fmcp_qsfp5_tx_rst_2_int), + .phy_2_xgmii_txd(fmcp_qsfp5_txd_2_int), + .phy_2_xgmii_txc(fmcp_qsfp5_txc_2_int), + .phy_2_rx_clk(fmcp_qsfp5_rx_clk_2_int), + .phy_2_rx_rst(fmcp_qsfp5_rx_rst_2_int), + .phy_2_xgmii_rxd(fmcp_qsfp5_rxd_2_int), + .phy_2_xgmii_rxc(fmcp_qsfp5_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmcp_qsfp5_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp5_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), + .phy_3_tx_clk(fmcp_qsfp5_tx_clk_3_int), + .phy_3_tx_rst(fmcp_qsfp5_tx_rst_3_int), + .phy_3_xgmii_txd(fmcp_qsfp5_txd_3_int), + .phy_3_xgmii_txc(fmcp_qsfp5_txc_3_int), + .phy_3_rx_clk(fmcp_qsfp5_rx_clk_3_int), + .phy_3_rx_rst(fmcp_qsfp5_rx_rst_3_int), + .phy_3_xgmii_rxd(fmcp_qsfp5_rxd_3_int), + .phy_3_xgmii_rxc(fmcp_qsfp5_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmcp_qsfp5_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp5_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp5_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp5_tx_p[1]), - .xcvr_txn(fmcp_qsfp5_tx_n[1]), - .xcvr_rxp(fmcp_qsfp5_rx_p[1]), - .xcvr_rxn(fmcp_qsfp5_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp5_tx_clk_2_int), - .phy_tx_rst(fmcp_qsfp5_tx_rst_2_int), - .phy_xgmii_txd(fmcp_qsfp5_txd_2_int), - .phy_xgmii_txc(fmcp_qsfp5_txc_2_int), - .phy_rx_clk(fmcp_qsfp5_rx_clk_2_int), - .phy_rx_rst(fmcp_qsfp5_rx_rst_2_int), - .phy_xgmii_rxd(fmcp_qsfp5_rxd_2_int), - .phy_xgmii_rxc(fmcp_qsfp5_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp5_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp5_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp5_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp5_tx_p[2]), - .xcvr_txn(fmcp_qsfp5_tx_n[2]), - .xcvr_rxp(fmcp_qsfp5_rx_p[2]), - .xcvr_rxn(fmcp_qsfp5_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp5_tx_clk_3_int), - .phy_tx_rst(fmcp_qsfp5_tx_rst_3_int), - .phy_xgmii_txd(fmcp_qsfp5_txd_3_int), - .phy_xgmii_txc(fmcp_qsfp5_txc_3_int), - .phy_rx_clk(fmcp_qsfp5_rx_clk_3_int), - .phy_rx_rst(fmcp_qsfp5_rx_rst_3_int), - .phy_xgmii_rxd(fmcp_qsfp5_rxd_3_int), - .phy_xgmii_rxc(fmcp_qsfp5_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp5_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp5_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp5_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp5_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp5_tx_p[3]), - .xcvr_txn(fmcp_qsfp5_tx_n[3]), - .xcvr_rxp(fmcp_qsfp5_rx_p[3]), - .xcvr_rxn(fmcp_qsfp5_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp5_tx_clk_4_int), - .phy_tx_rst(fmcp_qsfp5_tx_rst_4_int), - .phy_xgmii_txd(fmcp_qsfp5_txd_4_int), - .phy_xgmii_txc(fmcp_qsfp5_txc_4_int), - .phy_rx_clk(fmcp_qsfp5_rx_clk_4_int), - .phy_rx_rst(fmcp_qsfp5_rx_rst_4_int), - .phy_xgmii_rxd(fmcp_qsfp5_rxd_4_int), - .phy_xgmii_rxc(fmcp_qsfp5_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp5_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmcp_qsfp5_tx_clk_4_int), + .phy_4_tx_rst(fmcp_qsfp5_tx_rst_4_int), + .phy_4_xgmii_txd(fmcp_qsfp5_txd_4_int), + .phy_4_xgmii_txc(fmcp_qsfp5_txc_4_int), + .phy_4_rx_clk(fmcp_qsfp5_rx_clk_4_int), + .phy_4_rx_rst(fmcp_qsfp5_rx_rst_4_int), + .phy_4_xgmii_rxd(fmcp_qsfp5_rxd_4_int), + .phy_4_xgmii_rxc(fmcp_qsfp5_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmcp_qsfp5_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // FMC QSFP6 @@ -2264,196 +1537,99 @@ IBUFDS_GTE4 ibufds_gte4_fmcp_qsfp6_mgt_refclk_inst ( .ODIV2 () ); -wire fmcp_qsfp6_qpll0lock; -wire fmcp_qsfp6_qpll0outclk; -wire fmcp_qsfp6_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -fmcp_qsfp6_phy_1_inst ( +eth_xcvr_phy_quad_wrapper +fmcp_qsfp6_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(fmcp_qsfp_reset), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(fmcp_qsfp6_mgt_refclk), - .xcvr_qpll0lock_out(fmcp_qsfp6_qpll0lock), - .xcvr_qpll0outclk_out(fmcp_qsfp6_qpll0outclk), - .xcvr_qpll0outrefclk_out(fmcp_qsfp6_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(fmcp_qsfp6_tx_p), + .xcvr_txn(fmcp_qsfp6_tx_n), + .xcvr_rxp(fmcp_qsfp6_rx_p), + .xcvr_rxn(fmcp_qsfp6_rx_n), - // Serial data - .xcvr_txp(fmcp_qsfp6_tx_p[0]), - .xcvr_txn(fmcp_qsfp6_tx_n[0]), - .xcvr_rxp(fmcp_qsfp6_rx_p[0]), - .xcvr_rxn(fmcp_qsfp6_rx_n[0]), + /* + * PHY connections + */ + .phy_1_tx_clk(fmcp_qsfp6_tx_clk_1_int), + .phy_1_tx_rst(fmcp_qsfp6_tx_rst_1_int), + .phy_1_xgmii_txd(fmcp_qsfp6_txd_1_int), + .phy_1_xgmii_txc(fmcp_qsfp6_txc_1_int), + .phy_1_rx_clk(fmcp_qsfp6_rx_clk_1_int), + .phy_1_rx_rst(fmcp_qsfp6_rx_rst_1_int), + .phy_1_xgmii_rxd(fmcp_qsfp6_rxd_1_int), + .phy_1_xgmii_rxc(fmcp_qsfp6_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(fmcp_qsfp6_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(fmcp_qsfp6_tx_clk_1_int), - .phy_tx_rst(fmcp_qsfp6_tx_rst_1_int), - .phy_xgmii_txd(fmcp_qsfp6_txd_1_int), - .phy_xgmii_txc(fmcp_qsfp6_txc_1_int), - .phy_rx_clk(fmcp_qsfp6_rx_clk_1_int), - .phy_rx_rst(fmcp_qsfp6_rx_rst_1_int), - .phy_xgmii_rxd(fmcp_qsfp6_rxd_1_int), - .phy_xgmii_rxc(fmcp_qsfp6_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(fmcp_qsfp6_tx_clk_2_int), + .phy_2_tx_rst(fmcp_qsfp6_tx_rst_2_int), + .phy_2_xgmii_txd(fmcp_qsfp6_txd_2_int), + .phy_2_xgmii_txc(fmcp_qsfp6_txc_2_int), + .phy_2_rx_clk(fmcp_qsfp6_rx_clk_2_int), + .phy_2_rx_rst(fmcp_qsfp6_rx_rst_2_int), + .phy_2_xgmii_rxd(fmcp_qsfp6_rxd_2_int), + .phy_2_xgmii_rxc(fmcp_qsfp6_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(fmcp_qsfp6_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp6_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), + .phy_3_tx_clk(fmcp_qsfp6_tx_clk_3_int), + .phy_3_tx_rst(fmcp_qsfp6_tx_rst_3_int), + .phy_3_xgmii_txd(fmcp_qsfp6_txd_3_int), + .phy_3_xgmii_txc(fmcp_qsfp6_txc_3_int), + .phy_3_rx_clk(fmcp_qsfp6_rx_clk_3_int), + .phy_3_rx_rst(fmcp_qsfp6_rx_rst_3_int), + .phy_3_xgmii_rxd(fmcp_qsfp6_rxd_3_int), + .phy_3_xgmii_rxc(fmcp_qsfp6_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(fmcp_qsfp6_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp6_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp6_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp6_tx_p[1]), - .xcvr_txn(fmcp_qsfp6_tx_n[1]), - .xcvr_rxp(fmcp_qsfp6_rx_p[1]), - .xcvr_rxn(fmcp_qsfp6_rx_n[1]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp6_tx_clk_2_int), - .phy_tx_rst(fmcp_qsfp6_tx_rst_2_int), - .phy_xgmii_txd(fmcp_qsfp6_txd_2_int), - .phy_xgmii_txc(fmcp_qsfp6_txc_2_int), - .phy_rx_clk(fmcp_qsfp6_rx_clk_2_int), - .phy_rx_rst(fmcp_qsfp6_rx_rst_2_int), - .phy_xgmii_rxd(fmcp_qsfp6_rxd_2_int), - .phy_xgmii_rxc(fmcp_qsfp6_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp6_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp6_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp6_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp6_tx_p[2]), - .xcvr_txn(fmcp_qsfp6_tx_n[2]), - .xcvr_rxp(fmcp_qsfp6_rx_p[2]), - .xcvr_rxn(fmcp_qsfp6_rx_n[2]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp6_tx_clk_3_int), - .phy_tx_rst(fmcp_qsfp6_tx_rst_3_int), - .phy_xgmii_txd(fmcp_qsfp6_txd_3_int), - .phy_xgmii_txc(fmcp_qsfp6_txc_3_int), - .phy_rx_clk(fmcp_qsfp6_rx_clk_3_int), - .phy_rx_rst(fmcp_qsfp6_rx_rst_3_int), - .phy_xgmii_rxd(fmcp_qsfp6_rxd_3_int), - .phy_xgmii_rxc(fmcp_qsfp6_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -fmcp_qsfp6_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(fmcp_qsfp_reset), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(fmcp_qsfp6_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(fmcp_qsfp6_qpll0outclk), - .xcvr_qpll0refclk_in(fmcp_qsfp6_qpll0outrefclk), - - // Serial data - .xcvr_txp(fmcp_qsfp6_tx_p[3]), - .xcvr_txn(fmcp_qsfp6_tx_n[3]), - .xcvr_rxp(fmcp_qsfp6_rx_p[3]), - .xcvr_rxn(fmcp_qsfp6_rx_n[3]), - - // PHY connections - .phy_tx_clk(fmcp_qsfp6_tx_clk_4_int), - .phy_tx_rst(fmcp_qsfp6_tx_rst_4_int), - .phy_xgmii_txd(fmcp_qsfp6_txd_4_int), - .phy_xgmii_txc(fmcp_qsfp6_txc_4_int), - .phy_rx_clk(fmcp_qsfp6_rx_clk_4_int), - .phy_rx_rst(fmcp_qsfp6_rx_rst_4_int), - .phy_xgmii_rxd(fmcp_qsfp6_rxd_4_int), - .phy_xgmii_rxc(fmcp_qsfp6_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(fmcp_qsfp6_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(fmcp_qsfp6_tx_clk_4_int), + .phy_4_tx_rst(fmcp_qsfp6_tx_rst_4_int), + .phy_4_xgmii_txd(fmcp_qsfp6_txd_4_int), + .phy_4_xgmii_txc(fmcp_qsfp6_txc_4_int), + .phy_4_rx_clk(fmcp_qsfp6_rx_clk_4_int), + .phy_4_rx_rst(fmcp_qsfp6_rx_rst_4_int), + .phy_4_xgmii_rxd(fmcp_qsfp6_rxd_4_int), + .phy_4_xgmii_rxc(fmcp_qsfp6_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(fmcp_qsfp6_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // SGMII interface to PHY