mirror of
https://github.com/corundum/corundum.git
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Add example design for Alveo U55C and Alveo U55N/Varium C1100
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
fe5f6aa3f5
commit
3535e53746
@ -8,6 +8,8 @@ The design by default listens to UDP port 1234 at IP address 192.168.1.128 and w
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* FPGA
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* AU50: xcu50-fsvh2104-2-e
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* AU55C: xcu55c-fsvh2892-2L-e
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* AU55N/C1100: xcu55n-fsvh2892-2L-e
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* AU200: xcu200-fsgd2104-2-e
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* AU250: xcu250-fsgd2104-2-e
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* AU280: xcu280-fsvh2892-2L-e
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114
example/Alveo/fpga_25g/fpga_AU55C/Makefile
Normal file
114
example/Alveo/fpga_25g/fpga_AU55C/Makefile
Normal file
@ -0,0 +1,114 @@
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# FPGA settings
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FPGA_PART = xcu55c-fsvh2892-2L-e
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FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga_au55.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
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SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
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SYN_FILES += lib/eth/rtl/lfsr.v
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SYN_FILES += lib/eth/rtl/eth_axis_rx.v
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SYN_FILES += lib/eth/rtl/eth_axis_tx.v
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SYN_FILES += lib/eth/rtl/udp_complete_64.v
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SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
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SYN_FILES += lib/eth/rtl/udp_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_complete_64.v
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SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
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SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
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# XDC files
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XDC_FILES = fpga_au55.xdc
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XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
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XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
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XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
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# IP
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IP_TCL_FILES += ip/eth_xcvr_gt.tcl
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# Configuration
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CONFIG_TCL_FILES = ./config.tcl
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include ../common/vivado.mk
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program: $(FPGA_TOP).bit
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echo "open_hw" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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%.mcs %.prm: %.bit
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echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
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echo "exit" >> generate_mcs.tcl
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vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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COUNT=$$((COUNT-1)); \
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for x in .mcs .prm; \
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do cp $*$$x rev/$*_rev$$COUNT$$x; \
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echo "Output: rev/$*_rev$$COUNT$$x"; done;
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flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
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echo "open_hw" > flash.tcl
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echo "connect_hw_server" >> flash.tcl
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echo "open_hw_target" >> flash.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
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echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
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echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
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echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
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echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
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echo "program_hw_devices [current_hw_device]" >> flash.tcl
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echo "refresh_hw_device [current_hw_device]" >> flash.tcl
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echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
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echo "boot_hw_device [current_hw_device]" >> flash.tcl
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echo "exit" >> flash.tcl
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vivado -nojournal -nolog -mode batch -source flash.tcl
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50
example/Alveo/fpga_25g/fpga_AU55C/config.tcl
Normal file
50
example/Alveo/fpga_25g/fpga_AU55C/config.tcl
Normal file
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# Copyright (c) 2023 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# Transceiver configuration
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set eth_xcvr_freerun_freq {125}
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set eth_xcvr_line_rate {25.78125}
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set eth_xcvr_sec_line_rate {0}
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set eth_xcvr_refclk_freq {161.1328125}
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set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
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set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
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set eth_xcvr_rx_eq_mode {DFE}
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set xcvr_config [dict create]
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dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate
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dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
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dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
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dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate
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dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
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dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
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dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode
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if {$eth_xcvr_sec_line_rate != 0} {
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dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
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dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
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dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
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dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
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} else {
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dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
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}
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dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq
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set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full]
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set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel]
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114
example/Alveo/fpga_25g/fpga_AU55C_10g/Makefile
Normal file
114
example/Alveo/fpga_25g/fpga_AU55C_10g/Makefile
Normal file
@ -0,0 +1,114 @@
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# FPGA settings
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FPGA_PART = xcu55c-fsvh2892-2L-e
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FPGA_TOP = fpga
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FPGA_ARCH = virtexuplus
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# Files for synthesis
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SYN_FILES = rtl/fpga_au55.v
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SYN_FILES += rtl/fpga_core.v
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SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
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SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
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SYN_FILES += rtl/sync_signal.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
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SYN_FILES += lib/eth/rtl/eth_mac_10g.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
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SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
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SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
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SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
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SYN_FILES += lib/eth/rtl/lfsr.v
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SYN_FILES += lib/eth/rtl/eth_axis_rx.v
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SYN_FILES += lib/eth/rtl/eth_axis_tx.v
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SYN_FILES += lib/eth/rtl/udp_complete_64.v
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SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
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SYN_FILES += lib/eth/rtl/udp_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
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SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_complete_64.v
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SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
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SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
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SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
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# XDC files
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XDC_FILES = fpga_au55.xdc
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XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
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XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
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XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
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# IP
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IP_TCL_FILES += ip/eth_xcvr_gt.tcl
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# Configuration
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CONFIG_TCL_FILES = ./config.tcl
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include ../common/vivado.mk
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program: $(FPGA_TOP).bit
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echo "open_hw" > program.tcl
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echo "connect_hw_server" >> program.tcl
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echo "open_hw_target" >> program.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
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echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
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echo "program_hw_devices [current_hw_device]" >> program.tcl
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echo "exit" >> program.tcl
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vivado -nojournal -nolog -mode batch -source program.tcl
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%.mcs %.prm: %.bit
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echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
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echo "exit" >> generate_mcs.tcl
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vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$*_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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COUNT=$$((COUNT-1)); \
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for x in .mcs .prm; \
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do cp $*$$x rev/$*_rev$$COUNT$$x; \
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echo "Output: rev/$*_rev$$COUNT$$x"; done;
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flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
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echo "open_hw" > flash.tcl
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echo "connect_hw_server" >> flash.tcl
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echo "open_hw_target" >> flash.tcl
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echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
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echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
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echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
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echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
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echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
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echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
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echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
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echo "program_hw_devices [current_hw_device]" >> flash.tcl
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echo "refresh_hw_device [current_hw_device]" >> flash.tcl
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echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
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echo "boot_hw_device [current_hw_device]" >> flash.tcl
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echo "exit" >> flash.tcl
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vivado -nojournal -nolog -mode batch -source flash.tcl
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50
example/Alveo/fpga_25g/fpga_AU55C_10g/config.tcl
Normal file
50
example/Alveo/fpga_25g/fpga_AU55C_10g/config.tcl
Normal file
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# Copyright (c) 2023 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
|
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
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#
|
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# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
# THE SOFTWARE.
|
||||
|
||||
# Transceiver configuration
|
||||
set eth_xcvr_freerun_freq {125}
|
||||
set eth_xcvr_line_rate {10.3125}
|
||||
set eth_xcvr_sec_line_rate {0}
|
||||
set eth_xcvr_refclk_freq {161.1328125}
|
||||
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
|
||||
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
|
||||
set eth_xcvr_rx_eq_mode {DFE}
|
||||
|
||||
set xcvr_config [dict create]
|
||||
|
||||
dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate
|
||||
dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
|
||||
dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate
|
||||
dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
|
||||
dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode
|
||||
if {$eth_xcvr_sec_line_rate != 0} {
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
} else {
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq
|
||||
|
||||
set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full]
|
||||
set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel]
|
||||
114
example/Alveo/fpga_25g/fpga_AU55N/Makefile
Normal file
114
example/Alveo/fpga_25g/fpga_AU55N/Makefile
Normal file
@ -0,0 +1,114 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu55n-fsvh2892-2L-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga_au55.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
|
||||
SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/eth_axis_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_axis_tx.v
|
||||
SYN_FILES += lib/eth/rtl/udp_complete_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_complete_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_arb_mux.v
|
||||
SYN_FILES += lib/eth/rtl/arp.v
|
||||
SYN_FILES += lib/eth/rtl/arp_cache.v
|
||||
SYN_FILES += lib/eth/rtl/arp_eth_rx.v
|
||||
SYN_FILES += lib/eth/rtl/arp_eth_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_arb_mux.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga_au55.xdc
|
||||
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
|
||||
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES += ip/eth_xcvr_gt.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
%.mcs %.prm: %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
|
||||
echo "open_hw" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
50
example/Alveo/fpga_25g/fpga_AU55N/config.tcl
Normal file
50
example/Alveo/fpga_25g/fpga_AU55N/config.tcl
Normal file
@ -0,0 +1,50 @@
|
||||
# Copyright (c) 2023 Alex Forencich
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
# of this software and associated documentation files (the "Software"), to deal
|
||||
# in the Software without restriction, including without limitation the rights
|
||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
# THE SOFTWARE.
|
||||
|
||||
# Transceiver configuration
|
||||
set eth_xcvr_freerun_freq {125}
|
||||
set eth_xcvr_line_rate {25.78125}
|
||||
set eth_xcvr_sec_line_rate {0}
|
||||
set eth_xcvr_refclk_freq {161.1328125}
|
||||
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
|
||||
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
|
||||
set eth_xcvr_rx_eq_mode {DFE}
|
||||
|
||||
set xcvr_config [dict create]
|
||||
|
||||
dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate
|
||||
dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
|
||||
dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate
|
||||
dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
|
||||
dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode
|
||||
if {$eth_xcvr_sec_line_rate != 0} {
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
} else {
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq
|
||||
|
||||
set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full]
|
||||
set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel]
|
||||
114
example/Alveo/fpga_25g/fpga_AU55N_10g/Makefile
Normal file
114
example/Alveo/fpga_25g/fpga_AU55N_10g/Makefile
Normal file
@ -0,0 +1,114 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu55n-fsvh2892-2L-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga_au55.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
|
||||
SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/eth_axis_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_axis_tx.v
|
||||
SYN_FILES += lib/eth/rtl/udp_complete_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_complete_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_arb_mux.v
|
||||
SYN_FILES += lib/eth/rtl/arp.v
|
||||
SYN_FILES += lib/eth/rtl/arp_cache.v
|
||||
SYN_FILES += lib/eth/rtl/arp_eth_rx.v
|
||||
SYN_FILES += lib/eth/rtl/arp_eth_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_arb_mux.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga_au55.xdc
|
||||
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
|
||||
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES += ip/eth_xcvr_gt.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
%.mcs %.prm: %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in .mcs .prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
|
||||
echo "open_hw" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
50
example/Alveo/fpga_25g/fpga_AU55N_10g/config.tcl
Normal file
50
example/Alveo/fpga_25g/fpga_AU55N_10g/config.tcl
Normal file
@ -0,0 +1,50 @@
|
||||
# Copyright (c) 2023 Alex Forencich
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
# of this software and associated documentation files (the "Software"), to deal
|
||||
# in the Software without restriction, including without limitation the rights
|
||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
# THE SOFTWARE.
|
||||
|
||||
# Transceiver configuration
|
||||
set eth_xcvr_freerun_freq {125}
|
||||
set eth_xcvr_line_rate {10.3125}
|
||||
set eth_xcvr_sec_line_rate {0}
|
||||
set eth_xcvr_refclk_freq {161.1328125}
|
||||
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
|
||||
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
|
||||
set eth_xcvr_rx_eq_mode {DFE}
|
||||
|
||||
set xcvr_config [dict create]
|
||||
|
||||
dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate
|
||||
dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
|
||||
dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate
|
||||
dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
|
||||
dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode
|
||||
if {$eth_xcvr_sec_line_rate != 0} {
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
} else {
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq
|
||||
|
||||
set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full]
|
||||
set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel]
|
||||
236
example/Alveo/fpga_25g/fpga_au55.xdc
Normal file
236
example/Alveo/fpga_25g/fpga_au55.xdc
Normal file
@ -0,0 +1,236 @@
|
||||
# XDC constraints for the Xilinx Alveo U55C/Alveo U55N/Varium C1100 board
|
||||
# U55C part: xcu55c-fsvh2892-2L-e
|
||||
# U55N/C1100 part: xcu55n-fsvh2892-2L-e
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
|
||||
#set_operating_conditions -design_power_budget 63
|
||||
|
||||
# System clocks
|
||||
# 100 MHz
|
||||
#set_property -dict {LOC BK10 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p]
|
||||
#set_property -dict {LOC BL10 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n]
|
||||
#create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p]
|
||||
|
||||
# 100 MHz
|
||||
#set_property -dict {LOC BK43 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p]
|
||||
#set_property -dict {LOC BK44 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n]
|
||||
#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p]
|
||||
|
||||
# 100 MHz
|
||||
#set_property -dict {LOC F24 IOSTANDARD LVDS} [get_ports clk_100mhz_2_p]
|
||||
#set_property -dict {LOC F23 IOSTANDARD LVDS} [get_ports clk_100mhz_2_n]
|
||||
#create_clock -period 10 -name clk_100mhz_2 [get_ports clk_100mhz_2_p]
|
||||
|
||||
# Reset button
|
||||
set_property -dict {LOC BG45 IOSTANDARD LVCMOS18} [get_ports reset]
|
||||
|
||||
set_false_path -from [get_ports {reset}]
|
||||
set_input_delay 0 [get_ports {reset}]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC BL13 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_act[0]}]
|
||||
set_property -dict {LOC BK11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_stat_g[0]}]
|
||||
set_property -dict {LOC BJ11 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_stat_y[0]}]
|
||||
set_property -dict {LOC BK14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_act[1]}]
|
||||
set_property -dict {LOC BK15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_stat_g[1]}]
|
||||
set_property -dict {LOC BL12 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {qsfp_led_stat_y[1]}]
|
||||
|
||||
set_false_path -to [get_ports {qsfp_led_act[*] qsfp_led_stat_g[*] qsfp_led_stat_y[*]}]
|
||||
set_output_delay 0 [get_ports {qsfp_led_act[*] qsfp_led_stat_g[*] qsfp_led_stat_y[*]}]
|
||||
|
||||
# UART
|
||||
set_property -dict {LOC BJ41 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[0]}]
|
||||
set_property -dict {LOC BK41 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[0]}]
|
||||
set_property -dict {LOC BN47 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[1]}]
|
||||
set_property -dict {LOC BP47 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[1]}]
|
||||
set_property -dict {LOC BL45 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {uart_txd[2]}]
|
||||
set_property -dict {LOC BL46 IOSTANDARD LVCMOS18} [get_ports {uart_rxd[2]}]
|
||||
|
||||
#set_false_path -to [get_ports {uart_txd[*]}]
|
||||
#set_output_delay 0 [get_ports {uart_txd[*]}]
|
||||
#set_false_path -from [get_ports {uart_rxd[*]}]
|
||||
#set_input_delay 0 [get_ports {uart_rxd[*]}]
|
||||
|
||||
# BMC
|
||||
#set_property -dict {LOC BE46 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[0]}]
|
||||
#set_property -dict {LOC BH46 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[1]}]
|
||||
#set_property -dict {LOC BF45 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[2]}]
|
||||
#set_property -dict {LOC BF46 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[3]}]
|
||||
#set_property -dict {LOC BH42 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports {msp_uart_txd}]
|
||||
#set_property -dict {LOC BJ42 IOSTANDARD LVCMOS18} [get_ports {msp_uart_rxd}]
|
||||
|
||||
#set_false_path -to [get_ports {msp_uart_txd}]
|
||||
#set_output_delay 0 [get_ports {msp_uart_txd}]
|
||||
#set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
#set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}]
|
||||
|
||||
# HBM overtemp
|
||||
set_property -dict {LOC BE45 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip]
|
||||
|
||||
set_false_path -to [get_ports {hbm_cattrip}]
|
||||
set_output_delay 0 [get_ports {hbm_cattrip}]
|
||||
|
||||
# SI5394 (SI5394B-A10605-GM)
|
||||
# I2C address 0x68
|
||||
# IN0: 161.1328125 MHz from qsfp_recclk
|
||||
# OUT0: 161.1328125 MHz to qsfp0_mgt_refclk
|
||||
# OUT1: 161.1328125 MHz to qsfp1_mgt_refclk
|
||||
# OUT3: 100 MHz to clk_100mhz_0, clk_100mhz_1, pcie_refclk_2, pcie_refclk_3
|
||||
#set_property -dict {LOC BM8 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports si5394_rst_b]
|
||||
#set_property -dict {LOC BM9 IOSTANDARD LVCMOS18 PULLUP true} [get_ports si5394_int_b]
|
||||
#set_property -dict {LOC BN10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports si5394_lol_b]
|
||||
#set_property -dict {LOC BM10 IOSTANDARD LVCMOS18 PULLUP true} [get_ports si5394_los_b]
|
||||
#set_property -dict {LOC BN14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports si5394_sda]
|
||||
#set_property -dict {LOC BM14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8 PULLUP true} [get_ports si5394_scl]
|
||||
|
||||
#set_false_path -to [get_ports {si5394_rst_b}]
|
||||
#set_output_delay 0 [get_ports {si5394_rst_b}]
|
||||
#set_false_path -from [get_ports {si5394_int_b si5394_lol_b si5394_los_b}]
|
||||
#set_input_delay 0 [get_ports {si5394_int_b si5394_lol_b si5394_los_b}]
|
||||
|
||||
#set_false_path -to [get_ports {si5394_i2c_sda si5394_i2c_scl}]
|
||||
#set_output_delay 0 [get_ports {si5394_i2c_sda si5394_i2c_scl}]
|
||||
#set_false_path -from [get_ports {si5394_i2c_sda si5394_i2c_scl}]
|
||||
#set_input_delay 0 [get_ports {si5394_i2c_sda si5394_i2c_scl}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC AD51} [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_130 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AD52} [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_130 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AD46} [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_130 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AD47} [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_130 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AC53} [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_130 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AC54} [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_130 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AC44} [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_130 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AC45} [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_130 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AC49} [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_130 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AC50} [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_130 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AB46} [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_130 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AB47} [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_130 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AB51} [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_130 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AB52} [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_130 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AA48} [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_130 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AA49} [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_130 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AD42} [get_ports qsfp0_mgt_refclk_p] ;# MGTREFCLK0P_130 from SI5394 OUT0
|
||||
set_property -dict {LOC AD43} [get_ports qsfp0_mgt_refclk_n] ;# MGTREFCLK0N_130 from SI5394 OUT0
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (SI5394 OUT0)
|
||||
create_clock -period 6.206 -name qsfp0_mgt_refclk [get_ports qsfp0_mgt_refclk_p]
|
||||
|
||||
set_property -dict {LOC AA53} [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AA54} [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AA44} [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AA45} [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_131 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC Y51 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC Y52 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC Y46 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC Y47 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_131 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC W53 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC W54 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC W48 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC W49 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_131 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC V51 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC V52 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC W44 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC W45 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_131 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7
|
||||
set_property -dict {LOC AB42} [get_ports qsfp1_mgt_refclk_p] ;# MGTREFCLK0P_131 from SI5394 OUT1
|
||||
set_property -dict {LOC AB43} [get_ports qsfp1_mgt_refclk_n] ;# MGTREFCLK0N_131 from SI5394 OUT1
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (SI5394 OUT1)
|
||||
create_clock -period 6.206 -name qsfp1_mgt_refclk [get_ports qsfp1_mgt_refclk_p]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AL11} [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AL10} [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN6 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN5 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN11} [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN10} [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AP9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AP8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AP4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AP3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR11} [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR10} [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU11} [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU10} [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW6 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW5 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AV9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AV8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW11} [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW10} [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC BA6 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA5 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA11} [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA10} [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB9 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB8 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB4 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB3 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC11} [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC10} [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AL15} [get_ports pcie_refclk_0_p] ;# MGTREFCLK0P_227 (for x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AL14} [get_ports pcie_refclk_0_n] ;# MGTREFCLK0N_227 (for x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AK13} [get_ports pcie_refclk_2_p] ;# MGTREFCLK1P_227 (for async x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AK12} [get_ports pcie_refclk_2_n] ;# MGTREFCLK1N_227 (for async x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AR15} [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_225 (for x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AR14} [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_225 (for x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AP13} [get_ports pcie_refclk_3_p] ;# MGTREFCLK1P_225 (for async x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AP12} [get_ports pcie_refclk_3_n] ;# MGTREFCLK1N_225 (for async x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC BF41 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_3 [get_ports pcie_refclk_3_p]
|
||||
|
||||
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
474
example/Alveo/fpga_25g/rtl/fpga_au55.v
Normal file
474
example/Alveo/fpga_25g/rtl/fpga_au55.v
Normal file
@ -0,0 +1,474 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2021 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* FPGA top-level module
|
||||
*/
|
||||
module fpga #
|
||||
(
|
||||
parameter QSFP_CNT = 2,
|
||||
parameter UART_CNT = 3
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Reset: Push button, active low
|
||||
*/
|
||||
input wire reset,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
output wire [QSFP_CNT-1:0] qsfp_led_act,
|
||||
output wire [QSFP_CNT-1:0] qsfp_led_stat_g,
|
||||
output wire [QSFP_CNT-1:0] qsfp_led_stat_y,
|
||||
output wire hbm_cattrip,
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
output wire [UART_CNT-1:0] uart_txd,
|
||||
input wire [UART_CNT-1:0] uart_rxd,
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
output wire [3:0] qsfp0_tx_p,
|
||||
output wire [3:0] qsfp0_tx_n,
|
||||
input wire [3:0] qsfp0_rx_p,
|
||||
input wire [3:0] qsfp0_rx_n,
|
||||
input wire qsfp0_mgt_refclk_p,
|
||||
input wire qsfp0_mgt_refclk_n,
|
||||
|
||||
output wire [3:0] qsfp1_tx_p,
|
||||
output wire [3:0] qsfp1_tx_n,
|
||||
input wire [3:0] qsfp1_rx_p,
|
||||
input wire [3:0] qsfp1_rx_n,
|
||||
input wire qsfp1_mgt_refclk_p,
|
||||
input wire qsfp1_mgt_refclk_n
|
||||
);
|
||||
|
||||
// Clock and reset
|
||||
|
||||
wire clk_161mhz_ref_int;
|
||||
|
||||
// Internal 125 MHz clock
|
||||
wire clk_125mhz_mmcm_out;
|
||||
wire clk_125mhz_int;
|
||||
wire rst_125mhz_int;
|
||||
|
||||
// Internal 156.25 MHz clock
|
||||
wire clk_156mhz_int;
|
||||
wire rst_156mhz_int;
|
||||
|
||||
wire mmcm_rst = 1'b0;
|
||||
wire mmcm_locked;
|
||||
wire mmcm_clkfb;
|
||||
|
||||
// MMCM instance
|
||||
// 161.13 MHz in, 125 MHz out
|
||||
// PFD range: 10 MHz to 500 MHz
|
||||
// VCO range: 800 MHz to 1600 MHz
|
||||
// M = 64, D = 11 sets Fvco = 937.5 MHz (in range)
|
||||
// Divide by 7.5 to get output frequency of 125 MHz
|
||||
MMCME4_BASE #(
|
||||
.BANDWIDTH("OPTIMIZED"),
|
||||
.CLKOUT0_DIVIDE_F(7.5),
|
||||
.CLKOUT0_DUTY_CYCLE(0.5),
|
||||
.CLKOUT0_PHASE(0),
|
||||
.CLKOUT1_DIVIDE(1),
|
||||
.CLKOUT1_DUTY_CYCLE(0.5),
|
||||
.CLKOUT1_PHASE(0),
|
||||
.CLKOUT2_DIVIDE(1),
|
||||
.CLKOUT2_DUTY_CYCLE(0.5),
|
||||
.CLKOUT2_PHASE(0),
|
||||
.CLKOUT3_DIVIDE(1),
|
||||
.CLKOUT3_DUTY_CYCLE(0.5),
|
||||
.CLKOUT3_PHASE(0),
|
||||
.CLKOUT4_DIVIDE(1),
|
||||
.CLKOUT4_DUTY_CYCLE(0.5),
|
||||
.CLKOUT4_PHASE(0),
|
||||
.CLKOUT5_DIVIDE(1),
|
||||
.CLKOUT5_DUTY_CYCLE(0.5),
|
||||
.CLKOUT5_PHASE(0),
|
||||
.CLKOUT6_DIVIDE(1),
|
||||
.CLKOUT6_DUTY_CYCLE(0.5),
|
||||
.CLKOUT6_PHASE(0),
|
||||
.CLKFBOUT_MULT_F(64),
|
||||
.CLKFBOUT_PHASE(0),
|
||||
.DIVCLK_DIVIDE(11),
|
||||
.REF_JITTER1(0.010),
|
||||
.CLKIN1_PERIOD(6.206),
|
||||
.STARTUP_WAIT("FALSE"),
|
||||
.CLKOUT4_CASCADE("FALSE")
|
||||
)
|
||||
clk_mmcm_inst (
|
||||
.CLKIN1(clk_161mhz_ref_int),
|
||||
.CLKFBIN(mmcm_clkfb),
|
||||
.RST(mmcm_rst),
|
||||
.PWRDWN(1'b0),
|
||||
.CLKOUT0(clk_125mhz_mmcm_out),
|
||||
.CLKOUT0B(),
|
||||
.CLKOUT1(),
|
||||
.CLKOUT1B(),
|
||||
.CLKOUT2(),
|
||||
.CLKOUT2B(),
|
||||
.CLKOUT3(),
|
||||
.CLKOUT3B(),
|
||||
.CLKOUT4(),
|
||||
.CLKOUT5(),
|
||||
.CLKOUT6(),
|
||||
.CLKFBOUT(mmcm_clkfb),
|
||||
.CLKFBOUTB(),
|
||||
.LOCKED(mmcm_locked)
|
||||
);
|
||||
|
||||
BUFG
|
||||
clk_125mhz_bufg_inst (
|
||||
.I(clk_125mhz_mmcm_out),
|
||||
.O(clk_125mhz_int)
|
||||
);
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
sync_reset_125mhz_inst (
|
||||
.clk(clk_125mhz_int),
|
||||
.rst(~mmcm_locked),
|
||||
.out(rst_125mhz_int)
|
||||
);
|
||||
|
||||
// GPIO
|
||||
assign hbm_cattrip = 1'b0;
|
||||
|
||||
// XGMII 10G PHY
|
||||
localparam CH_CNT = QSFP_CNT*4;
|
||||
|
||||
wire [CH_CNT-1:0] eth_tx_clk;
|
||||
wire [CH_CNT-1:0] eth_tx_rst;
|
||||
wire [CH_CNT*64-1:0] eth_txd;
|
||||
wire [CH_CNT*8-1:0] eth_txc;
|
||||
wire [CH_CNT-1:0] eth_rx_clk;
|
||||
wire [CH_CNT-1:0] eth_rx_rst;
|
||||
wire [CH_CNT*64-1:0] eth_rxd;
|
||||
wire [CH_CNT*8-1:0] eth_rxc;
|
||||
|
||||
assign clk_156mhz_int = eth_tx_clk[0];
|
||||
assign rst_156mhz_int = eth_tx_rst[0];
|
||||
|
||||
// QSFP0
|
||||
wire qsfp0_rx_block_lock_1;
|
||||
wire qsfp0_rx_block_lock_2;
|
||||
wire qsfp0_rx_block_lock_3;
|
||||
wire qsfp0_rx_block_lock_4;
|
||||
|
||||
wire qsfp0_gtpowergood;
|
||||
|
||||
wire qsfp0_mgt_refclk;
|
||||
wire qsfp0_mgt_refclk_int;
|
||||
wire qsfp0_mgt_refclk_bufg;
|
||||
|
||||
assign clk_161mhz_ref_int = qsfp0_mgt_refclk_bufg;
|
||||
|
||||
IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_inst (
|
||||
.I (qsfp0_mgt_refclk_p),
|
||||
.IB (qsfp0_mgt_refclk_n),
|
||||
.CEB (1'b0),
|
||||
.O (qsfp0_mgt_refclk),
|
||||
.ODIV2 (qsfp0_mgt_refclk_int)
|
||||
);
|
||||
|
||||
BUFG_GT bufg_gt_refclk_inst (
|
||||
.CE (qsfp0_gtpowergood),
|
||||
.CEMASK (1'b1),
|
||||
.CLR (1'b0),
|
||||
.CLRMASK (1'b1),
|
||||
.DIV (3'd0),
|
||||
.I (qsfp0_mgt_refclk_int),
|
||||
.O (qsfp0_mgt_refclk_bufg)
|
||||
);
|
||||
|
||||
eth_xcvr_phy_quad_wrapper #(
|
||||
.TX_SERDES_PIPELINE(2),
|
||||
.RX_SERDES_PIPELINE(2),
|
||||
.COUNT_125US(125000/2.56)
|
||||
)
|
||||
qsfp0_phy_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz_int),
|
||||
.xcvr_ctrl_rst(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(qsfp0_gtpowergood),
|
||||
|
||||
/*
|
||||
* PLL
|
||||
*/
|
||||
.xcvr_gtrefclk00_in(qsfp0_mgt_refclk),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(qsfp0_tx_p),
|
||||
.xcvr_txn(qsfp0_tx_n),
|
||||
.xcvr_rxp(qsfp0_rx_p),
|
||||
.xcvr_rxn(qsfp0_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
*/
|
||||
.phy_1_tx_clk(eth_tx_clk[0*4+0 +: 1]),
|
||||
.phy_1_tx_rst(eth_tx_rst[0*4+0 +: 1]),
|
||||
.phy_1_xgmii_txd(eth_txd[(0*4+0)*64 +: 64]),
|
||||
.phy_1_xgmii_txc(eth_txc[(0*4+0)*8 +: 8]),
|
||||
.phy_1_rx_clk(eth_rx_clk[0*4+0 +: 1]),
|
||||
.phy_1_rx_rst(eth_rx_rst[0*4+0 +: 1]),
|
||||
.phy_1_xgmii_rxd(eth_rxd[(0*4+0)*64 +: 64]),
|
||||
.phy_1_xgmii_rxc(eth_rxc[(0*4+0)*8 +: 8]),
|
||||
.phy_1_tx_bad_block(),
|
||||
.phy_1_rx_error_count(),
|
||||
.phy_1_rx_bad_block(),
|
||||
.phy_1_rx_sequence_error(),
|
||||
.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
|
||||
.phy_1_rx_status(),
|
||||
.phy_1_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_1_cfg_rx_prbs31_enable(1'b0),
|
||||
|
||||
.phy_2_tx_clk(eth_tx_clk[0*4+1 +: 1]),
|
||||
.phy_2_tx_rst(eth_tx_rst[0*4+1 +: 1]),
|
||||
.phy_2_xgmii_txd(eth_txd[(0*4+1)*64 +: 64]),
|
||||
.phy_2_xgmii_txc(eth_txc[(0*4+1)*8 +: 8]),
|
||||
.phy_2_rx_clk(eth_rx_clk[0*4+1 +: 1]),
|
||||
.phy_2_rx_rst(eth_rx_rst[0*4+1 +: 1]),
|
||||
.phy_2_xgmii_rxd(eth_rxd[(0*4+1)*64 +: 64]),
|
||||
.phy_2_xgmii_rxc(eth_rxc[(0*4+1)*8 +: 8]),
|
||||
.phy_2_tx_bad_block(),
|
||||
.phy_2_rx_error_count(),
|
||||
.phy_2_rx_bad_block(),
|
||||
.phy_2_rx_sequence_error(),
|
||||
.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
|
||||
.phy_2_rx_status(),
|
||||
.phy_2_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_2_cfg_rx_prbs31_enable(1'b0),
|
||||
|
||||
.phy_3_tx_clk(eth_tx_clk[0*4+2 +: 1]),
|
||||
.phy_3_tx_rst(eth_tx_rst[0*4+2 +: 1]),
|
||||
.phy_3_xgmii_txd(eth_txd[(0*4+2)*64 +: 64]),
|
||||
.phy_3_xgmii_txc(eth_txc[(0*4+2)*8 +: 8]),
|
||||
.phy_3_rx_clk(eth_rx_clk[0*4+2 +: 1]),
|
||||
.phy_3_rx_rst(eth_rx_rst[0*4+2 +: 1]),
|
||||
.phy_3_xgmii_rxd(eth_rxd[(0*4+2)*64 +: 64]),
|
||||
.phy_3_xgmii_rxc(eth_rxc[(0*4+2)*8 +: 8]),
|
||||
.phy_3_tx_bad_block(),
|
||||
.phy_3_rx_error_count(),
|
||||
.phy_3_rx_bad_block(),
|
||||
.phy_3_rx_sequence_error(),
|
||||
.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
|
||||
.phy_3_rx_status(),
|
||||
.phy_3_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_3_cfg_rx_prbs31_enable(1'b0),
|
||||
|
||||
.phy_4_tx_clk(eth_tx_clk[0*4+3 +: 1]),
|
||||
.phy_4_tx_rst(eth_tx_rst[0*4+3 +: 1]),
|
||||
.phy_4_xgmii_txd(eth_txd[(0*4+3)*64 +: 64]),
|
||||
.phy_4_xgmii_txc(eth_txc[(0*4+3)*8 +: 8]),
|
||||
.phy_4_rx_clk(eth_rx_clk[0*4+3 +: 1]),
|
||||
.phy_4_rx_rst(eth_rx_rst[0*4+3 +: 1]),
|
||||
.phy_4_xgmii_rxd(eth_rxd[(0*4+3)*64 +: 64]),
|
||||
.phy_4_xgmii_rxc(eth_rxc[(0*4+3)*8 +: 8]),
|
||||
.phy_4_tx_bad_block(),
|
||||
.phy_4_rx_error_count(),
|
||||
.phy_4_rx_bad_block(),
|
||||
.phy_4_rx_sequence_error(),
|
||||
.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
|
||||
.phy_4_rx_status(),
|
||||
.phy_4_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_4_cfg_rx_prbs31_enable(1'b0)
|
||||
);
|
||||
|
||||
// QSFP1
|
||||
wire qsfp1_rx_block_lock_1;
|
||||
wire qsfp1_rx_block_lock_2;
|
||||
wire qsfp1_rx_block_lock_3;
|
||||
wire qsfp1_rx_block_lock_4;
|
||||
|
||||
wire qsfp1_mgt_refclk;
|
||||
|
||||
IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_inst (
|
||||
.I (qsfp1_mgt_refclk_p),
|
||||
.IB (qsfp1_mgt_refclk_n),
|
||||
.CEB (1'b0),
|
||||
.O (qsfp1_mgt_refclk),
|
||||
.ODIV2 ()
|
||||
);
|
||||
|
||||
eth_xcvr_phy_quad_wrapper #(
|
||||
.TX_SERDES_PIPELINE(2),
|
||||
.RX_SERDES_PIPELINE(2),
|
||||
.COUNT_125US(125000/2.56)
|
||||
)
|
||||
qsfp1_phy_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz_int),
|
||||
.xcvr_ctrl_rst(rst_125mhz_int),
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(),
|
||||
|
||||
/*
|
||||
* PLL
|
||||
*/
|
||||
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk),
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(qsfp1_tx_p),
|
||||
.xcvr_txn(qsfp1_tx_n),
|
||||
.xcvr_rxp(qsfp1_rx_p),
|
||||
.xcvr_rxn(qsfp1_rx_n),
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
*/
|
||||
.phy_1_tx_clk(eth_tx_clk[1*4+0 +: 1]),
|
||||
.phy_1_tx_rst(eth_tx_rst[1*4+0 +: 1]),
|
||||
.phy_1_xgmii_txd(eth_txd[(1*4+0)*64 +: 64]),
|
||||
.phy_1_xgmii_txc(eth_txc[(1*4+0)*8 +: 8]),
|
||||
.phy_1_rx_clk(eth_rx_clk[1*4+0 +: 1]),
|
||||
.phy_1_rx_rst(eth_rx_rst[1*4+0 +: 1]),
|
||||
.phy_1_xgmii_rxd(eth_rxd[(1*4+0)*64 +: 64]),
|
||||
.phy_1_xgmii_rxc(eth_rxc[(1*4+0)*8 +: 8]),
|
||||
.phy_1_tx_bad_block(),
|
||||
.phy_1_rx_error_count(),
|
||||
.phy_1_rx_bad_block(),
|
||||
.phy_1_rx_sequence_error(),
|
||||
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
|
||||
.phy_1_rx_status(),
|
||||
.phy_1_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_1_cfg_rx_prbs31_enable(1'b0),
|
||||
|
||||
.phy_2_tx_clk(eth_tx_clk[1*4+1 +: 1]),
|
||||
.phy_2_tx_rst(eth_tx_rst[1*4+1 +: 1]),
|
||||
.phy_2_xgmii_txd(eth_txd[(1*4+1)*64 +: 64]),
|
||||
.phy_2_xgmii_txc(eth_txc[(1*4+1)*8 +: 8]),
|
||||
.phy_2_rx_clk(eth_rx_clk[1*4+1 +: 1]),
|
||||
.phy_2_rx_rst(eth_rx_rst[1*4+1 +: 1]),
|
||||
.phy_2_xgmii_rxd(eth_rxd[(1*4+1)*64 +: 64]),
|
||||
.phy_2_xgmii_rxc(eth_rxc[(1*4+1)*8 +: 8]),
|
||||
.phy_2_tx_bad_block(),
|
||||
.phy_2_rx_error_count(),
|
||||
.phy_2_rx_bad_block(),
|
||||
.phy_2_rx_sequence_error(),
|
||||
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
|
||||
.phy_2_rx_status(),
|
||||
.phy_2_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_2_cfg_rx_prbs31_enable(1'b0),
|
||||
|
||||
.phy_3_tx_clk(eth_tx_clk[1*4+2 +: 1]),
|
||||
.phy_3_tx_rst(eth_tx_rst[1*4+2 +: 1]),
|
||||
.phy_3_xgmii_txd(eth_txd[(1*4+2)*64 +: 64]),
|
||||
.phy_3_xgmii_txc(eth_txc[(1*4+2)*8 +: 8]),
|
||||
.phy_3_rx_clk(eth_rx_clk[1*4+2 +: 1]),
|
||||
.phy_3_rx_rst(eth_rx_rst[1*4+2 +: 1]),
|
||||
.phy_3_xgmii_rxd(eth_rxd[(1*4+2)*64 +: 64]),
|
||||
.phy_3_xgmii_rxc(eth_rxc[(1*4+2)*8 +: 8]),
|
||||
.phy_3_tx_bad_block(),
|
||||
.phy_3_rx_error_count(),
|
||||
.phy_3_rx_bad_block(),
|
||||
.phy_3_rx_sequence_error(),
|
||||
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
|
||||
.phy_3_rx_status(),
|
||||
.phy_3_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_3_cfg_rx_prbs31_enable(1'b0),
|
||||
|
||||
.phy_4_tx_clk(eth_tx_clk[1*4+3 +: 1]),
|
||||
.phy_4_tx_rst(eth_tx_rst[1*4+3 +: 1]),
|
||||
.phy_4_xgmii_txd(eth_txd[(1*4+3)*64 +: 64]),
|
||||
.phy_4_xgmii_txc(eth_txc[(1*4+3)*8 +: 8]),
|
||||
.phy_4_rx_clk(eth_rx_clk[1*4+3 +: 1]),
|
||||
.phy_4_rx_rst(eth_rx_rst[1*4+3 +: 1]),
|
||||
.phy_4_xgmii_rxd(eth_rxd[(1*4+3)*64 +: 64]),
|
||||
.phy_4_xgmii_rxc(eth_rxc[(1*4+3)*8 +: 8]),
|
||||
.phy_4_tx_bad_block(),
|
||||
.phy_4_rx_error_count(),
|
||||
.phy_4_rx_bad_block(),
|
||||
.phy_4_rx_sequence_error(),
|
||||
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
|
||||
.phy_4_rx_status(),
|
||||
.phy_4_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_4_cfg_rx_prbs31_enable(1'b0)
|
||||
);
|
||||
|
||||
fpga_core #(
|
||||
.UART_CNT(UART_CNT),
|
||||
.QSFP_CNT(QSFP_CNT),
|
||||
.CH_CNT(CH_CNT)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
* Clock: 156.25 MHz
|
||||
* Synchronous reset
|
||||
*/
|
||||
.clk(clk_156mhz_int),
|
||||
.rst(rst_156mhz_int),
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
.sw(0),
|
||||
.led(),
|
||||
.qsfp_led_act(qsfp_led_act),
|
||||
.qsfp_led_stat_g(qsfp_led_stat_g),
|
||||
.qsfp_led_stat_y(qsfp_led_stat_y),
|
||||
|
||||
/*
|
||||
* UART
|
||||
*/
|
||||
.uart_txd(uart_txd),
|
||||
.uart_rxd(uart_rxd),
|
||||
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
.eth_tx_clk(eth_tx_clk),
|
||||
.eth_tx_rst(eth_tx_rst),
|
||||
.eth_txd(eth_txd),
|
||||
.eth_txc(eth_txc),
|
||||
.eth_rx_clk(eth_rx_clk),
|
||||
.eth_rx_rst(eth_rx_rst),
|
||||
.eth_rxd(eth_rxd),
|
||||
.eth_rxc(eth_rxc)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
Loading…
x
Reference in New Issue
Block a user