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Add AXI stream FIFO
This commit is contained in:
Alex Forencich
parent
95fd206382
commit
35f39a6f4b
128
rtl/axis_fifo.v
Normal file
128
rtl/axis_fifo.v
Normal file
@ -0,0 +1,128 @@
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/*
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Copyright (c) 2013 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
|
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of this software and associated documentation files (the "Software"), to deal
|
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in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream FIFO
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*/
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module axis_fifo #
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(
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parameter ADDR_WIDTH = 12,
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parameter DATA_WIDTH = 8
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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input wire input_axis_tlast,
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input wire input_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire output_axis_tuser
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);
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reg [ADDR_WIDTH-1:0] wr_ptr = {ADDR_WIDTH{1'b0}};
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reg [ADDR_WIDTH-1:0] rd_ptr = {ADDR_WIDTH{1'b0}};
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reg [ADDR_WIDTH-1:0] counter = {ADDR_WIDTH{1'b0}};
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reg [DATA_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {DATA_WIDTH{1'b0}}};
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//(* RAM_STYLE="BLOCK" *)
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reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
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reg output_read = 1'b0;
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reg output_axis_tvalid_reg = 1'b0;
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wire [DATA_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tuser, input_axis_tdata};
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wire full = (counter == (2**ADDR_WIDTH)-1);
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wire empty = (counter == 0);
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wire write = input_axis_tvalid & ~full;
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wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
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assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_out_reg;
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assign input_axis_tready = ~full;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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// write
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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wr_ptr <= 0;
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end else if (write) begin
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mem[wr_ptr] <= data_in;
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wr_ptr <= wr_ptr + 1;
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end
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end
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// read
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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rd_ptr <= 0;
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end else if (read) begin
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data_out_reg <= mem[rd_ptr];
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rd_ptr <= rd_ptr + 1;
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end
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end
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// counter
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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counter <= 0;
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end else if (~read & write) begin
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counter <= counter + 1;
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end else if (read & ~write) begin
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counter <= counter - 1;
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end
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end
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// source ready output
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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output_axis_tvalid_reg <= 1'b0;
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end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
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output_axis_tvalid_reg <= ~empty;
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end else begin
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output_axis_tvalid_reg <= output_axis_tvalid_reg;
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end
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end
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endmodule
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131
rtl/axis_fifo_64.v
Normal file
131
rtl/axis_fifo_64.v
Normal file
@ -0,0 +1,131 @@
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/*
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Copyright (c) 2013 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
|
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in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream FIFO (64 bit datapath)
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*/
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module axis_fifo_64 #
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(
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parameter ADDR_WIDTH = 12,
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parameter DATA_WIDTH = 64,
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parameter KEEP_WIDTH = (DATA_WIDTH/8)
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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input wire input_axis_tlast,
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input wire input_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast,
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output wire output_axis_tuser
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);
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reg [ADDR_WIDTH-1:0] wr_ptr = {ADDR_WIDTH{1'b0}};
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reg [ADDR_WIDTH-1:0] rd_ptr = {ADDR_WIDTH{1'b0}};
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reg [ADDR_WIDTH-1:0] counter = {ADDR_WIDTH{1'b0}};
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reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {KEEP_WIDTH{1'b0}}, {DATA_WIDTH{1'b0}}};
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//(* RAM_STYLE="BLOCK" *)
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reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
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reg output_read = 1'b0;
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reg output_axis_tvalid_reg = 1'b0;
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wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tuser, input_axis_tkeep, input_axis_tdata};
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wire full = (counter == (2**ADDR_WIDTH)-1);
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wire empty = (counter == 0);
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wire write = input_axis_tvalid & ~full;
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wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
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assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = data_out_reg;
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assign input_axis_tready = ~full;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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// write
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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wr_ptr <= 0;
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end else if (write) begin
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mem[wr_ptr] <= data_in;
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wr_ptr <= wr_ptr + 1;
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end
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end
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// read
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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rd_ptr <= 0;
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end else if (read) begin
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data_out_reg <= mem[rd_ptr];
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rd_ptr <= rd_ptr + 1;
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end
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end
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// counter
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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counter <= 0;
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end else if (~read & write) begin
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counter <= counter + 1;
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end else if (read & ~write) begin
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counter <= counter - 1;
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end
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end
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// source ready output
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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output_axis_tvalid_reg <= 1'b0;
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end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
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output_axis_tvalid_reg <= ~empty;
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end else begin
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output_axis_tvalid_reg <= output_axis_tvalid_reg;
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end
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end
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endmodule
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259
tb/axis_ep.py
Normal file
259
tb/axis_ep.py
Normal file
@ -0,0 +1,259 @@
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"""
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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"""
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from myhdl import *
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class AXIStreamFrame(object):
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def __init__(self, data=b'', keep=None, user=None):
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self.N = 8
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self.M = 1
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self.WL = 8
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self.data = b''
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self.keep = None
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self.user = None
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if type(data) is bytes:
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data = bytearray(data)
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if type(data) is bytearray:
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self.data = data
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if type(data) is AXIStreamFrame:
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self.N = data.N
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self.WL = data.WL
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self.data = data.data
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if data.keep is not None:
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self.keep = list(data.keep)
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if data.user is not None:
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if type(data.user) is int or type(data.user) is bool:
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self.user = data.user
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else:
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self.user = list(data.user)
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def build(self):
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if self.data is None:
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return
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f = list(self.data)
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tdata = []
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tkeep = []
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tuser = []
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i = 0
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assert_tuser = False
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if (type(self.user) is int or type(self.user) is bool) and self.user:
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assert_tuser = True
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self.user = None
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while len(f) > 0:
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data = 0
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keep = 0
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for j in range(self.M):
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data = data | (f.pop(0) << (j*self.WL))
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keep = keep | (1 << j)
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if len(f) == 0: break
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tdata.append(data)
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if self.keep is None:
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tkeep.append(keep)
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else:
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tkeep.append(self.keep[i])
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if self.user is None:
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tuser.append(0)
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else:
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tuser.append(self.user[i])
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i += 1
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if assert_tuser:
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tuser[-1] = 1
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self.user = 1
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return tdata, tkeep, tuser
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def parse(self, tdata, tkeep, tuser):
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if tdata is None or tkeep is None or tuser is None:
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return
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if len(tdata) != len(tkeep) or len(tdata) != len(tuser):
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raise Exception("Invalid data")
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self.data = []
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self.keep = []
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self.user = []
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mask = 2**self.WL-1
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for i in range(len(tdata)):
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for j in range(self.M):
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if tkeep[i] & (1 << j):
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self.data.append((tdata[i] >> (j*self.WL)) & mask)
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self.keep.append(tkeep[i])
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self.user.append(tuser[i])
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if self.WL == 8:
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self.data = bytearray(self.data)
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def __eq__(self, other):
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if type(other) is AXIStreamFrame:
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return self.data == other.data
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def __repr__(self):
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return 'AXIStreamFrame(data=%s, keep=%s, user=%s)' % (repr(self.data), repr(self.keep), repr(self.user))
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def __iter__(self):
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return self.data.__iter__()
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def AXIStreamSource(clk, rst,
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tdata=None,
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tkeep=Signal(bool(True)),
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tvalid=Signal(bool(False)),
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tready=Signal(bool(True)),
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tlast=Signal(bool(False)),
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tuser=Signal(bool(False)),
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fifo=None,
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pause=0,
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name=None):
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tready_int = Signal(bool(False))
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tvalid_int = Signal(bool(False))
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@always_comb
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def pause_logic():
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tready_int.next = tready and not pause
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tvalid.next = tvalid_int and not pause
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@instance
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def logic():
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frame = AXIStreamFrame()
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data = []
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keep = []
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user = []
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N = len(tdata)
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M = 1
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b = False
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if tkeep is not None:
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M = len(tkeep)
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WL = (len(tdata)+M-1)/M
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if WL == 8:
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b = True
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while True:
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yield clk.posedge, rst.posedge
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if rst:
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tdata.next = 0
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tkeep.next = 0
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tvalid_int.next = False
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tlast.next = False
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else:
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if tready_int and tvalid:
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if len(data) > 0:
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tdata.next = data.pop(0)
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tkeep.next = keep.pop(0)
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tuser.next = user.pop(0)
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tvalid_int.next = True
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tlast.next = len(data) == 0
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else:
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tvalid_int.next = False
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tlast.next = False
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if (tlast and tready_int and tvalid) or not tvalid_int:
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if not fifo.empty():
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frame = fifo.get()
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frame = AXIStreamFrame(frame)
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frame.N = N
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frame.M = M
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frame.WL = WL
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frame.build()
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if name is not None:
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print("[%s] Sending frame %s" % (name, repr(frame)))
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data, keep, user = frame.build()
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tdata.next = data.pop(0)
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tkeep.next = keep.pop(0)
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tuser.next = user.pop(0)
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tvalid_int.next = True
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tlast.next = len(data) == 0
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return logic, pause_logic
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def AXIStreamSink(clk, rst,
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tdata=None,
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tkeep=Signal(bool(True)),
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tvalid=Signal(bool(True)),
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tready=Signal(bool(True)),
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tlast=Signal(bool(True)),
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tuser=Signal(bool(False)),
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fifo=None,
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pause=0,
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name=None):
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tready_int = Signal(bool(False))
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tvalid_int = Signal(bool(False))
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@always_comb
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def pause_logic():
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tready.next = tready_int and not pause
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tvalid_int.next = tvalid and not pause
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@instance
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def logic():
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frame = AXIStreamFrame()
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data = []
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keep = []
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user = []
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N = len(tdata)
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M = 1
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b = False
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M = len(tkeep)
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WL = (len(tdata)+M-1)/M
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if WL == 8:
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b = True
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while True:
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yield clk.posedge, rst.posedge
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if rst:
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tready_int.next = False
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||||
frame = AXIStreamFrame()
|
||||
data = []
|
||||
keep = []
|
||||
user = []
|
||||
else:
|
||||
tready_int.next = True
|
||||
|
||||
if tvalid_int:
|
||||
data.append(int(tdata))
|
||||
keep.append(int(tkeep))
|
||||
user.append(int(tuser))
|
||||
if tlast:
|
||||
frame.N = N
|
||||
frame.M = M
|
||||
frame.WL = WL
|
||||
frame.parse(data, keep, user)
|
||||
if fifo is not None:
|
||||
fifo.put(frame)
|
||||
if name is not None:
|
||||
print("[%s] Got frame %s" % (name, repr(frame)))
|
||||
frame = AXIStreamFrame()
|
||||
data = []
|
||||
keep = []
|
||||
user = []
|
||||
|
||||
return logic, pause_logic
|
||||
|
||||
396
tb/test_axis_fifo.py
Executable file
396
tb/test_axis_fifo.py
Executable file
@ -0,0 +1,396 @@
|
||||
#!/usr/bin/env python2
|
||||
"""
|
||||
|
||||
Copyright (c) 2014 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
"""
|
||||
|
||||
from myhdl import *
|
||||
import os
|
||||
from Queue import Queue
|
||||
|
||||
import axis_ep
|
||||
|
||||
module = 'axis_fifo'
|
||||
|
||||
srcs = []
|
||||
|
||||
srcs.append("../rtl/%s.v" % module)
|
||||
srcs.append("test_%s.v" % module)
|
||||
|
||||
src = ' '.join(srcs)
|
||||
|
||||
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
|
||||
|
||||
def dut_axis_fifo(clk,
|
||||
rst,
|
||||
current_test,
|
||||
|
||||
input_axis_tdata,
|
||||
input_axis_tvalid,
|
||||
input_axis_tready,
|
||||
input_axis_tlast,
|
||||
input_axis_tuser,
|
||||
|
||||
output_axis_tdata,
|
||||
output_axis_tvalid,
|
||||
output_axis_tready,
|
||||
output_axis_tlast,
|
||||
output_axis_tuser):
|
||||
|
||||
if os.system(build_cmd):
|
||||
raise Exception("Error running build command")
|
||||
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
|
||||
clk=clk,
|
||||
rst=rst,
|
||||
current_test=current_test,
|
||||
|
||||
input_axis_tdata=input_axis_tdata,
|
||||
input_axis_tvalid=input_axis_tvalid,
|
||||
input_axis_tready=input_axis_tready,
|
||||
input_axis_tlast=input_axis_tlast,
|
||||
input_axis_tuser=input_axis_tuser,
|
||||
|
||||
output_axis_tdata=output_axis_tdata,
|
||||
output_axis_tvalid=output_axis_tvalid,
|
||||
output_axis_tready=output_axis_tready,
|
||||
output_axis_tlast=output_axis_tlast,
|
||||
output_axis_tuser=output_axis_tuser)
|
||||
|
||||
def bench():
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
input_axis_tdata = Signal(intbv(0)[8:])
|
||||
input_axis_tvalid = Signal(bool(0))
|
||||
input_axis_tlast = Signal(bool(0))
|
||||
input_axis_tuser = Signal(bool(0))
|
||||
output_axis_tready = Signal(bool(0))
|
||||
|
||||
# Outputs
|
||||
input_axis_tready = Signal(bool(0))
|
||||
output_axis_tdata = Signal(intbv(0)[8:])
|
||||
output_axis_tvalid = Signal(bool(0))
|
||||
output_axis_tlast = Signal(bool(0))
|
||||
output_axis_tuser = Signal(bool(0))
|
||||
|
||||
# sources and sinks
|
||||
source_queue = Queue()
|
||||
source_pause = Signal(bool(0))
|
||||
sink_queue = Queue()
|
||||
sink_pause = Signal(bool(0))
|
||||
|
||||
source = axis_ep.AXIStreamSource(clk,
|
||||
rst,
|
||||
tdata=input_axis_tdata,
|
||||
tvalid=input_axis_tvalid,
|
||||
tready=input_axis_tready,
|
||||
tlast=input_axis_tlast,
|
||||
tuser=input_axis_tuser,
|
||||
fifo=source_queue,
|
||||
pause=source_pause,
|
||||
name='source')
|
||||
|
||||
sink = axis_ep.AXIStreamSink(clk,
|
||||
rst,
|
||||
tdata=output_axis_tdata,
|
||||
tvalid=output_axis_tvalid,
|
||||
tready=output_axis_tready,
|
||||
tlast=output_axis_tlast,
|
||||
tuser=output_axis_tuser,
|
||||
fifo=sink_queue,
|
||||
pause=sink_pause,
|
||||
name='sink')
|
||||
|
||||
# DUT
|
||||
dut = dut_axis_fifo(clk,
|
||||
rst,
|
||||
current_test,
|
||||
|
||||
input_axis_tdata,
|
||||
input_axis_tvalid,
|
||||
input_axis_tready,
|
||||
input_axis_tlast,
|
||||
input_axis_tuser,
|
||||
|
||||
output_axis_tdata,
|
||||
output_axis_tvalid,
|
||||
output_axis_tready,
|
||||
output_axis_tlast,
|
||||
output_axis_tuser)
|
||||
|
||||
@always(delay(4))
|
||||
def clkgen():
|
||||
clk.next = not clk
|
||||
|
||||
@instance
|
||||
def check():
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
rst.next = 1
|
||||
yield clk.posedge
|
||||
rst.next = 0
|
||||
yield clk.posedge
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
|
||||
yield clk.posedge
|
||||
|
||||
yield clk.posedge
|
||||
print("test 1: test packet")
|
||||
current_test.next = 1
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 2: longer packet")
|
||||
current_test.next = 2
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
bytearray(range(256)))
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
|
||||
yield clk.posedge
|
||||
print("test 3: test packet with pauses")
|
||||
current_test.next = 3
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield delay(64)
|
||||
yield clk.posedge
|
||||
source_pause.next = True
|
||||
yield delay(32)
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
|
||||
yield delay(64)
|
||||
yield clk.posedge
|
||||
sink_pause.next = True
|
||||
yield delay(32)
|
||||
yield clk.posedge
|
||||
sink_pause.next = False
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 4: back-to-back packets")
|
||||
current_test.next = 4
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame1)
|
||||
source_queue.put(test_frame2)
|
||||
yield clk.posedge
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame1
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 5: alternate pause source")
|
||||
current_test.next = 5
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame1)
|
||||
source_queue.put(test_frame2)
|
||||
yield clk.posedge
|
||||
|
||||
while input_axis_tvalid or output_axis_tvalid:
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
yield clk.posedge
|
||||
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame1
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 6: alternate pause sink")
|
||||
current_test.next = 6
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame1)
|
||||
source_queue.put(test_frame2)
|
||||
yield clk.posedge
|
||||
|
||||
while input_axis_tvalid or output_axis_tvalid:
|
||||
sink_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
sink_pause.next = False
|
||||
yield clk.posedge
|
||||
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame1
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 7: tuser assert")
|
||||
current_test.next = 7
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame.user = 1
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
assert rx_frame.user[-1]
|
||||
|
||||
yield delay(100)
|
||||
|
||||
raise StopSimulation
|
||||
|
||||
return dut, source, sink, clkgen, check
|
||||
|
||||
def test_bench():
|
||||
os.chdir(os.path.dirname(os.path.abspath(__file__)))
|
||||
sim = Simulation(bench())
|
||||
sim.run()
|
||||
|
||||
if __name__ == '__main__':
|
||||
print("Running test...")
|
||||
test_bench()
|
||||
|
||||
91
tb/test_axis_fifo.v
Normal file
91
tb/test_axis_fifo.v
Normal file
@ -0,0 +1,91 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module test_axis_fifo;
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg [7:0] input_axis_tdata = 0;
|
||||
reg input_axis_tvalid = 0;
|
||||
reg input_axis_tlast = 0;
|
||||
reg input_axis_tuser = 0;
|
||||
reg output_axis_tready = 0;
|
||||
|
||||
// Outputs
|
||||
wire input_axis_tready;
|
||||
wire [7:0] output_axis_tdata;
|
||||
wire output_axis_tvalid;
|
||||
wire output_axis_tlast;
|
||||
wire output_axis_tuser;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(clk,
|
||||
rst,
|
||||
current_test,
|
||||
input_axis_tdata,
|
||||
input_axis_tvalid,
|
||||
input_axis_tlast,
|
||||
input_axis_tuser,
|
||||
output_axis_tready);
|
||||
$to_myhdl(input_axis_tready,
|
||||
output_axis_tdata,
|
||||
output_axis_tvalid,
|
||||
output_axis_tlast,
|
||||
output_axis_tuser);
|
||||
|
||||
// dump file
|
||||
$dumpfile("test_axis_fifo.lxt");
|
||||
$dumpvars(0, test_axis_fifo);
|
||||
end
|
||||
|
||||
axis_fifo #(
|
||||
.ADDR_WIDTH(2),
|
||||
.DATA_WIDTH(8)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// AXI input
|
||||
.input_axis_tdata(input_axis_tdata),
|
||||
.input_axis_tvalid(input_axis_tvalid),
|
||||
.input_axis_tready(input_axis_tready),
|
||||
.input_axis_tlast(input_axis_tlast),
|
||||
.input_axis_tuser(input_axis_tuser),
|
||||
// AXI output
|
||||
.output_axis_tdata(output_axis_tdata),
|
||||
.output_axis_tvalid(output_axis_tvalid),
|
||||
.output_axis_tready(output_axis_tready),
|
||||
.output_axis_tlast(output_axis_tlast),
|
||||
.output_axis_tuser(output_axis_tuser)
|
||||
);
|
||||
|
||||
endmodule
|
||||
406
tb/test_axis_fifo_64.py
Executable file
406
tb/test_axis_fifo_64.py
Executable file
@ -0,0 +1,406 @@
|
||||
#!/usr/bin/env python2
|
||||
"""
|
||||
|
||||
Copyright (c) 2014 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
"""
|
||||
|
||||
from myhdl import *
|
||||
import os
|
||||
from Queue import Queue
|
||||
|
||||
import axis_ep
|
||||
|
||||
module = 'axis_fifo_64'
|
||||
|
||||
srcs = []
|
||||
|
||||
srcs.append("../rtl/%s.v" % module)
|
||||
srcs.append("test_%s.v" % module)
|
||||
|
||||
src = ' '.join(srcs)
|
||||
|
||||
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
|
||||
|
||||
def dut_axis_fifo_64(clk,
|
||||
rst,
|
||||
current_test,
|
||||
|
||||
input_axis_tdata,
|
||||
input_axis_tkeep,
|
||||
input_axis_tvalid,
|
||||
input_axis_tready,
|
||||
input_axis_tlast,
|
||||
input_axis_tuser,
|
||||
|
||||
output_axis_tdata,
|
||||
output_axis_tkeep,
|
||||
output_axis_tvalid,
|
||||
output_axis_tready,
|
||||
output_axis_tlast,
|
||||
output_axis_tuser):
|
||||
|
||||
if os.system(build_cmd):
|
||||
raise Exception("Error running build command")
|
||||
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
|
||||
clk=clk,
|
||||
rst=rst,
|
||||
current_test=current_test,
|
||||
|
||||
input_axis_tdata=input_axis_tdata,
|
||||
input_axis_tkeep=input_axis_tkeep,
|
||||
input_axis_tvalid=input_axis_tvalid,
|
||||
input_axis_tready=input_axis_tready,
|
||||
input_axis_tlast=input_axis_tlast,
|
||||
input_axis_tuser=input_axis_tuser,
|
||||
|
||||
output_axis_tdata=output_axis_tdata,
|
||||
output_axis_tkeep=output_axis_tkeep,
|
||||
output_axis_tvalid=output_axis_tvalid,
|
||||
output_axis_tready=output_axis_tready,
|
||||
output_axis_tlast=output_axis_tlast,
|
||||
output_axis_tuser=output_axis_tuser)
|
||||
|
||||
def bench():
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
input_axis_tdata = Signal(intbv(0)[64:])
|
||||
input_axis_tkeep = Signal(intbv(0)[8:])
|
||||
input_axis_tvalid = Signal(bool(0))
|
||||
input_axis_tlast = Signal(bool(0))
|
||||
input_axis_tuser = Signal(bool(0))
|
||||
output_axis_tready = Signal(bool(0))
|
||||
|
||||
# Outputs
|
||||
input_axis_tready = Signal(bool(0))
|
||||
output_axis_tdata = Signal(intbv(0)[64:])
|
||||
output_axis_tkeep = Signal(intbv(0)[8:])
|
||||
output_axis_tvalid = Signal(bool(0))
|
||||
output_axis_tlast = Signal(bool(0))
|
||||
output_axis_tuser = Signal(bool(0))
|
||||
|
||||
# sources and sinks
|
||||
source_queue = Queue()
|
||||
source_pause = Signal(bool(0))
|
||||
sink_queue = Queue()
|
||||
sink_pause = Signal(bool(0))
|
||||
|
||||
source = axis_ep.AXIStreamSource(clk,
|
||||
rst,
|
||||
tdata=input_axis_tdata,
|
||||
tkeep=input_axis_tkeep,
|
||||
tvalid=input_axis_tvalid,
|
||||
tready=input_axis_tready,
|
||||
tlast=input_axis_tlast,
|
||||
tuser=input_axis_tuser,
|
||||
fifo=source_queue,
|
||||
pause=source_pause,
|
||||
name='source')
|
||||
|
||||
sink = axis_ep.AXIStreamSink(clk,
|
||||
rst,
|
||||
tdata=output_axis_tdata,
|
||||
tkeep=output_axis_tkeep,
|
||||
tvalid=output_axis_tvalid,
|
||||
tready=output_axis_tready,
|
||||
tlast=output_axis_tlast,
|
||||
tuser=output_axis_tuser,
|
||||
fifo=sink_queue,
|
||||
pause=sink_pause,
|
||||
name='sink')
|
||||
|
||||
# DUT
|
||||
dut = dut_axis_fifo_64(clk,
|
||||
rst,
|
||||
current_test,
|
||||
|
||||
input_axis_tdata,
|
||||
input_axis_tkeep,
|
||||
input_axis_tvalid,
|
||||
input_axis_tready,
|
||||
input_axis_tlast,
|
||||
input_axis_tuser,
|
||||
|
||||
output_axis_tdata,
|
||||
output_axis_tkeep,
|
||||
output_axis_tvalid,
|
||||
output_axis_tready,
|
||||
output_axis_tlast,
|
||||
output_axis_tuser)
|
||||
|
||||
@always(delay(4))
|
||||
def clkgen():
|
||||
clk.next = not clk
|
||||
|
||||
@instance
|
||||
def check():
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
rst.next = 1
|
||||
yield clk.posedge
|
||||
rst.next = 0
|
||||
yield clk.posedge
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
|
||||
yield clk.posedge
|
||||
|
||||
yield clk.posedge
|
||||
print("test 1: test packet")
|
||||
current_test.next = 1
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 2: longer packet")
|
||||
current_test.next = 2
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
bytearray(range(256)))
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
|
||||
yield clk.posedge
|
||||
print("test 3: test packet with pauses")
|
||||
current_test.next = 3
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
bytearray(range(256)))
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield delay(64)
|
||||
yield clk.posedge
|
||||
source_pause.next = True
|
||||
yield delay(32)
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
|
||||
yield delay(64)
|
||||
yield clk.posedge
|
||||
sink_pause.next = True
|
||||
yield delay(32)
|
||||
yield clk.posedge
|
||||
sink_pause.next = False
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 4: back-to-back packets")
|
||||
current_test.next = 4
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame1)
|
||||
source_queue.put(test_frame2)
|
||||
yield clk.posedge
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame1
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 5: alternate pause source")
|
||||
current_test.next = 5
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame1)
|
||||
source_queue.put(test_frame2)
|
||||
yield clk.posedge
|
||||
|
||||
while input_axis_tvalid or output_axis_tvalid:
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
yield clk.posedge
|
||||
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame1
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 6: alternate pause sink")
|
||||
current_test.next = 6
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame1)
|
||||
source_queue.put(test_frame2)
|
||||
yield clk.posedge
|
||||
|
||||
while input_axis_tvalid or output_axis_tvalid:
|
||||
sink_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
sink_pause.next = False
|
||||
yield clk.posedge
|
||||
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame1
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 7: tuser assert")
|
||||
current_test.next = 7
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame(b'\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
b'\x5A\x51\x52\x53\x54\x55' +
|
||||
b'\x80\x00' +
|
||||
b'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame.user = 1
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
assert rx_frame.user[-1]
|
||||
|
||||
yield delay(100)
|
||||
|
||||
raise StopSimulation
|
||||
|
||||
return dut, source, sink, clkgen, check
|
||||
|
||||
def test_bench():
|
||||
os.chdir(os.path.dirname(os.path.abspath(__file__)))
|
||||
sim = Simulation(bench())
|
||||
sim.run()
|
||||
|
||||
if __name__ == '__main__':
|
||||
print("Running test...")
|
||||
test_bench()
|
||||
|
||||
97
tb/test_axis_fifo_64.v
Normal file
97
tb/test_axis_fifo_64.v
Normal file
@ -0,0 +1,97 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module test_axis_fifo_64;
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg [63:0] input_axis_tdata = 0;
|
||||
reg [7:0] input_axis_tkeep = 0;
|
||||
reg input_axis_tvalid = 0;
|
||||
reg input_axis_tlast = 0;
|
||||
reg input_axis_tuser = 0;
|
||||
reg output_axis_tready = 0;
|
||||
|
||||
// Outputs
|
||||
wire input_axis_tready;
|
||||
wire [63:0] output_axis_tdata;
|
||||
wire [7:0] output_axis_tkeep;
|
||||
wire output_axis_tvalid;
|
||||
wire output_axis_tlast;
|
||||
wire output_axis_tuser;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(clk,
|
||||
rst,
|
||||
current_test,
|
||||
input_axis_tdata,
|
||||
input_axis_tkeep,
|
||||
input_axis_tvalid,
|
||||
input_axis_tlast,
|
||||
input_axis_tuser,
|
||||
output_axis_tready);
|
||||
$to_myhdl(input_axis_tready,
|
||||
output_axis_tdata,
|
||||
output_axis_tkeep,
|
||||
output_axis_tvalid,
|
||||
output_axis_tlast,
|
||||
output_axis_tuser);
|
||||
|
||||
// dump file
|
||||
$dumpfile("test_axis_fifo_64.lxt");
|
||||
$dumpvars(0, test_axis_fifo_64);
|
||||
end
|
||||
|
||||
axis_fifo_64 #(
|
||||
.ADDR_WIDTH(2),
|
||||
.DATA_WIDTH(64)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// AXI input
|
||||
.input_axis_tdata(input_axis_tdata),
|
||||
.input_axis_tkeep(input_axis_tkeep),
|
||||
.input_axis_tvalid(input_axis_tvalid),
|
||||
.input_axis_tready(input_axis_tready),
|
||||
.input_axis_tlast(input_axis_tlast),
|
||||
.input_axis_tuser(input_axis_tuser),
|
||||
// AXI output
|
||||
.output_axis_tdata(output_axis_tdata),
|
||||
.output_axis_tkeep(output_axis_tkeep),
|
||||
.output_axis_tvalid(output_axis_tvalid),
|
||||
.output_axis_tready(output_axis_tready),
|
||||
.output_axis_tlast(output_axis_tlast),
|
||||
.output_axis_tuser(output_axis_tuser)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user