FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

Update MAC and PHY instances

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-08-28 17:22:34 -07:00
parent 9095e7ae0b
commit 36576d8981
56 changed files with 1924 additions and 1876 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
fpga/common/rtl/eth_xcvr_phy_10g_gty_quad_wrapper.v
View File

@ -136,8 +136,8 @@ module eth_xcvr_phy_10g_gty_quad_wrapper #
output wire phy_1_rx_block_lock,
output wire phy_1_rx_high_ber,
output wire phy_1_rx_status,
input wire phy_1_tx_prbs31_enable,
input wire phy_1_rx_prbs31_enable,
input wire phy_1_cfg_tx_prbs31_enable,
input wire phy_1_cfg_rx_prbs31_enable,
output wire phy_2_tx_clk,
output wire phy_2_tx_rst,
@ -154,8 +154,8 @@ module eth_xcvr_phy_10g_gty_quad_wrapper #
output wire phy_2_rx_block_lock,
output wire phy_2_rx_high_ber,
output wire phy_2_rx_status,
input wire phy_2_tx_prbs31_enable,
input wire phy_2_rx_prbs31_enable,
input wire phy_2_cfg_tx_prbs31_enable,
input wire phy_2_cfg_rx_prbs31_enable,
output wire phy_3_tx_clk,
output wire phy_3_tx_rst,
@ -172,8 +172,8 @@ module eth_xcvr_phy_10g_gty_quad_wrapper #
output wire phy_3_rx_block_lock,
output wire phy_3_rx_high_ber,
output wire phy_3_rx_status,
input wire phy_3_tx_prbs31_enable,
input wire phy_3_rx_prbs31_enable,
input wire phy_3_cfg_tx_prbs31_enable,
input wire phy_3_cfg_rx_prbs31_enable,
output wire phy_4_tx_clk,
output wire phy_4_tx_rst,
@ -190,8 +190,8 @@ module eth_xcvr_phy_10g_gty_quad_wrapper #
output wire phy_4_rx_block_lock,
output wire phy_4_rx_high_ber,
output wire phy_4_rx_status,
input wire phy_4_tx_prbs31_enable,
input wire phy_4_rx_prbs31_enable
input wire phy_4_cfg_tx_prbs31_enable,
input wire phy_4_cfg_rx_prbs31_enable
);
generate
@ -366,8 +366,8 @@ if (COUNT > 0) begin : phy1
.phy_rx_block_lock(phy_1_rx_block_lock),
.phy_rx_high_ber(phy_1_rx_high_ber),
.phy_rx_status(phy_1_rx_status),
.phy_tx_prbs31_enable(phy_1_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_1_rx_prbs31_enable)
.phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable)
);
end else begin
@ -464,8 +464,8 @@ if (COUNT > 1) begin : phy2
.phy_rx_block_lock(phy_2_rx_block_lock),
.phy_rx_high_ber(phy_2_rx_high_ber),
.phy_rx_status(phy_2_rx_status),
.phy_tx_prbs31_enable(phy_2_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_2_rx_prbs31_enable)
.phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable)
);
end else begin
@ -562,8 +562,8 @@ if (COUNT > 2) begin : phy3
.phy_rx_block_lock(phy_3_rx_block_lock),
.phy_rx_high_ber(phy_3_rx_high_ber),
.phy_rx_status(phy_3_rx_status),
.phy_tx_prbs31_enable(phy_3_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_3_rx_prbs31_enable)
.phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable)
);
end else begin
@ -660,8 +660,8 @@ if (COUNT > 3) begin : phy4
.phy_rx_block_lock(phy_4_rx_block_lock),
.phy_rx_high_ber(phy_4_rx_high_ber),
.phy_rx_status(phy_4_rx_status),
.phy_tx_prbs31_enable(phy_4_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_4_rx_prbs31_enable)
.phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable)
);
end else begin

8
fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v
View File

@ -119,8 +119,8 @@ module eth_xcvr_phy_10g_gty_wrapper #
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
output wire phy_rx_status,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
// DRP
@ -1588,8 +1588,8 @@ phy_inst (
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.rx_status(phy_rx_status),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

8
fpga/common/rtl/tdma_ber.v
View File

@ -55,8 +55,8 @@ module tdma_ber #
input wire [COUNT-1:0] phy_tx_clk,
input wire [COUNT-1:0] phy_rx_clk,
input wire [COUNT*7-1:0] phy_rx_error_count,
output wire [COUNT-1:0] phy_tx_prbs31_enable,
output wire [COUNT-1:0] phy_rx_prbs31_enable,
output wire [COUNT-1:0] phy_cfg_tx_prbs31_enable,
output wire [COUNT-1:0] phy_cfg_rx_prbs31_enable,
/*
* AXI-Lite slave interface
@ -406,8 +406,8 @@ generate
.phy_tx_clk(phy_tx_clk[n]),
.phy_rx_clk(phy_rx_clk[n]),
.phy_rx_error_count(phy_rx_error_count[n*7 +: 7]),
.phy_tx_prbs31_enable(phy_tx_prbs31_enable[n]),
.phy_rx_prbs31_enable(phy_rx_prbs31_enable[n]),
.phy_cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable[n]),
.phy_cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable[n]),
.s_axil_awaddr(axil_ch_awaddr[n*AXIL_ADDR_WIDTH +: AXIL_ADDR_WIDTH]),
.s_axil_awprot(axil_ch_awprot[n*3 +: 3]),
.s_axil_awvalid(axil_ch_awvalid[n]),

48
fpga/common/rtl/tdma_ber_ch.v
View File

@ -37,8 +37,8 @@ module tdma_ber_ch #
input wire phy_tx_clk,
input wire phy_rx_clk,
input wire [6:0] phy_rx_error_count,
output wire phy_tx_prbs31_enable,
output wire phy_rx_prbs31_enable,
output wire phy_cfg_tx_prbs31_enable,
output wire phy_cfg_rx_prbs31_enable,
/*
* AXI-Lite slave interface
@ -93,23 +93,23 @@ initial begin
end
end
reg tx_prbs31_enable_reg = 1'b0, tx_prbs31_enable_next;
reg rx_prbs31_enable_reg = 1'b0, rx_prbs31_enable_next;
reg cfg_tx_prbs31_enable_reg = 1'b0, cfg_tx_prbs31_enable_next;
reg cfg_rx_prbs31_enable_reg = 1'b0, cfg_rx_prbs31_enable_next;
// PHY TX BER interface
reg phy_tx_prbs31_enable_reg = 1'b0;
reg [PHY_PIPELINE-1:0] phy_tx_prbs31_enable_pipe_reg = 0;
reg phy_cfg_tx_prbs31_enable_reg = 1'b0;
reg [PHY_PIPELINE-1:0] phy_cfg_tx_prbs31_enable_pipe_reg = 0;
always @(posedge phy_tx_clk) begin
phy_tx_prbs31_enable_reg <= tx_prbs31_enable_reg;
phy_tx_prbs31_enable_pipe_reg <= {phy_tx_prbs31_enable_pipe_reg, phy_tx_prbs31_enable_reg};
phy_cfg_tx_prbs31_enable_reg <= cfg_tx_prbs31_enable_reg;
phy_cfg_tx_prbs31_enable_pipe_reg <= {phy_cfg_tx_prbs31_enable_pipe_reg, phy_cfg_tx_prbs31_enable_reg};
end
assign phy_tx_prbs31_enable = PHY_PIPELINE ? phy_tx_prbs31_enable_pipe_reg[PHY_PIPELINE-1] : phy_tx_prbs31_enable_reg;
assign phy_cfg_tx_prbs31_enable = PHY_PIPELINE ? phy_cfg_tx_prbs31_enable_pipe_reg[PHY_PIPELINE-1] : phy_cfg_tx_prbs31_enable_reg;
// PHY RX BER interface
reg phy_rx_prbs31_enable_reg = 1'b0;
reg [PHY_PIPELINE-1:0] phy_rx_prbs31_enable_pipe_reg = 0;
reg phy_cfg_rx_prbs31_enable_reg = 1'b0;
reg [PHY_PIPELINE-1:0] phy_cfg_rx_prbs31_enable_pipe_reg = 0;
reg [PHY_PIPELINE*7-1:0] phy_rx_error_count_pipe_reg = 0;
// accumulate errors, dump every 16 cycles
@ -119,8 +119,8 @@ reg [3:0] phy_rx_count_reg = 4'd0;
reg phy_rx_flag_reg = 1'b0;
always @(posedge phy_rx_clk) begin
phy_rx_prbs31_enable_reg <= rx_prbs31_enable_reg;
phy_rx_prbs31_enable_pipe_reg <= {phy_rx_prbs31_enable_pipe_reg, phy_rx_prbs31_enable_reg};
phy_cfg_rx_prbs31_enable_reg <= cfg_rx_prbs31_enable_reg;
phy_cfg_rx_prbs31_enable_pipe_reg <= {phy_cfg_rx_prbs31_enable_pipe_reg, phy_cfg_rx_prbs31_enable_reg};
phy_rx_error_count_pipe_reg <= {phy_rx_error_count_pipe_reg, phy_rx_error_count};
phy_rx_count_reg <= phy_rx_count_reg + 1;
@ -134,7 +134,7 @@ always @(posedge phy_rx_clk) begin
end
end
assign phy_rx_prbs31_enable = PHY_PIPELINE ? phy_rx_prbs31_enable_pipe_reg[PHY_PIPELINE-1] : phy_rx_prbs31_enable_reg;
assign phy_cfg_rx_prbs31_enable = PHY_PIPELINE ? phy_cfg_rx_prbs31_enable_pipe_reg[PHY_PIPELINE-1] : phy_cfg_rx_prbs31_enable_reg;
// synchronize dumped counts to control clock domain
reg rx_flag_sync_reg_1 = 1'b0;
@ -354,8 +354,8 @@ always @* begin
slice_select_next = slice_select_reg;
tx_prbs31_enable_next = tx_prbs31_enable_reg;
rx_prbs31_enable_next = rx_prbs31_enable_reg;
cfg_tx_prbs31_enable_next = cfg_tx_prbs31_enable_reg;
cfg_rx_prbs31_enable_next = cfg_rx_prbs31_enable_reg;
write_eligible = s_axil_awvalid && s_axil_wvalid && (!s_axil_bvalid || s_axil_bready) && (!s_axil_awready && !s_axil_wready);
read_eligible = s_axil_arvalid && (!s_axil_rvalid || s_axil_rready) && (!s_axil_arready);
@ -373,8 +373,8 @@ always @* begin
case (s_axil_awaddr & ({AXIL_ADDR_WIDTH{1'b1}} << 2))
16'h0000: begin
// control
tx_prbs31_enable_next = s_axil_wdata[0];
rx_prbs31_enable_next = s_axil_wdata[1];
cfg_tx_prbs31_enable_next = s_axil_wdata[0];
cfg_rx_prbs31_enable_next = s_axil_wdata[1];
end
16'h0004: begin
// cycle count
@ -432,8 +432,8 @@ always @* begin
case (s_axil_araddr & ({AXIL_ADDR_WIDTH{1'b1}} << 2))
16'h0000: begin
// control
s_axil_rdata_next[0] = tx_prbs31_enable_reg;
s_axil_rdata_next[1] = rx_prbs31_enable_reg;
s_axil_rdata_next[0] = cfg_tx_prbs31_enable_reg;
s_axil_rdata_next[1] = cfg_rx_prbs31_enable_reg;
end
16'h0004: begin
// cycle count
@ -511,8 +511,8 @@ always @(posedge clk) begin
slice_select_reg <= 0;
tx_prbs31_enable_reg <= 1'b0;
rx_prbs31_enable_reg <= 1'b0;
cfg_tx_prbs31_enable_reg <= 1'b0;
cfg_rx_prbs31_enable_reg <= 1'b0;
end else begin
last_read_reg <= last_read_next;
@ -539,8 +539,8 @@ always @(posedge clk) begin
slice_select_reg <= slice_select_next;
tx_prbs31_enable_reg <= tx_prbs31_enable_next;
rx_prbs31_enable_reg <= rx_prbs31_enable_next;
cfg_tx_prbs31_enable_reg <= cfg_tx_prbs31_enable_next;
cfg_rx_prbs31_enable_reg <= cfg_rx_prbs31_enable_next;
end
s_axil_rdata_reg <= s_axil_rdata_next;

12
fpga/common/syn/vivado/tdma_ber_ch.tcl
View File

@ -7,19 +7,19 @@ foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == tdma_ber_ch || REF_NAME
puts "Inserting timing constraints for tdma_ber_ch instance $inst"
# get clock periods
set clk [get_clocks -of_objects [get_cells "$inst/tx_prbs31_enable_reg_reg"]]
set tx_clk [get_clocks -of_objects [get_cells "$inst/phy_tx_prbs31_enable_reg_reg"]]
set rx_clk [get_clocks -of_objects [get_cells "$inst/phy_rx_prbs31_enable_reg_reg"]]
set clk [get_clocks -of_objects [get_cells "$inst/cfg_tx_prbs31_enable_reg_reg"]]
set tx_clk [get_clocks -of_objects [get_cells "$inst/phy_cfg_tx_prbs31_enable_reg_reg"]]
set rx_clk [get_clocks -of_objects [get_cells "$inst/phy_cfg_rx_prbs31_enable_reg_reg"]]
set clk_period [if {[llength $clk]} {get_property -min PERIOD $clk} {expr 1.0}]
set tx_clk_period [if {[llength $tx_clk]} {get_property -min PERIOD $tx_clk} {expr 1.0}]
set rx_clk_period [if {[llength $rx_clk]} {get_property -min PERIOD $rx_clk} {expr 1.0}]
# control synchronization
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/phy_(rx|tx)_prbs31_enable_reg_reg" -filter "PARENT == $inst"]
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/phy_(rx|tcfg_x)_prbs31_enable_reg_reg" -filter "PARENT == $inst"]
set_max_delay -from [get_cells "$inst/tx_prbs31_enable_reg_reg"] -to [get_cells "$inst/phy_tx_prbs31_enable_reg_reg"] -datapath_only $clk_period
set_max_delay -from [get_cells "$inst/rx_prbs31_enable_reg_reg"] -to [get_cells "$inst/phy_rx_prbs31_enable_reg_reg"] -datapath_only $clk_period
set_max_delay -from [get_cells "$inst/cfg_tx_prbs31_enable_reg_reg"] -to [get_cells "$inst/phy_cfg_tx_prbs31_enable_reg_reg"] -datapath_only $clk_period
set_max_delay -from [get_cells "$inst/cfg_rx_prbs31_enable_reg_reg"] -to [get_cells "$inst/phy_cfg_rx_prbs31_enable_reg_reg"] -datapath_only $clk_period
# data synchronization
set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/rx_flag_sync_reg_\[123\]_reg" -filter "PARENT == $inst"]

96
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v
View File

@ -699,45 +699,45 @@ wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int;
wire qsfp0_tx_prbs31_enable_1_int;
wire qsfp0_cfg_tx_prbs31_enable_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int;
wire qsfp0_rx_prbs31_enable_1_int;
wire qsfp0_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp0_rx_error_count_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int;
wire qsfp0_tx_prbs31_enable_2_int;
wire qsfp0_cfg_tx_prbs31_enable_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int;
wire qsfp0_rx_prbs31_enable_2_int;
wire qsfp0_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp0_rx_error_count_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int;
wire qsfp0_tx_prbs31_enable_3_int;
wire qsfp0_cfg_tx_prbs31_enable_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int;
wire qsfp0_rx_prbs31_enable_3_int;
wire qsfp0_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp0_rx_error_count_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int;
wire qsfp0_tx_prbs31_enable_4_int;
wire qsfp0_cfg_tx_prbs31_enable_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int;
wire qsfp0_rx_prbs31_enable_4_int;
wire qsfp0_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp0_rx_error_count_4_int;
wire qsfp0_drp_clk = clk_125mhz_int;
@ -847,8 +847,8 @@ qsfp0_phy_quad_inst (
.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp0_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp0_tx_clk_2_int),
.phy_2_tx_rst(qsfp0_tx_rst_2_int),
@ -865,8 +865,8 @@ qsfp0_phy_quad_inst (
.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp0_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp0_tx_clk_3_int),
.phy_3_tx_rst(qsfp0_tx_rst_3_int),
@ -883,8 +883,8 @@ qsfp0_phy_quad_inst (
.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp0_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp0_tx_clk_4_int),
.phy_4_tx_rst(qsfp0_tx_rst_4_int),
@ -901,8 +901,8 @@ qsfp0_phy_quad_inst (
.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp0_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_4_int)
);
// QSFP1
@ -910,45 +910,45 @@ wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int;
wire qsfp1_tx_prbs31_enable_1_int;
wire qsfp1_cfg_tx_prbs31_enable_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int;
wire qsfp1_rx_prbs31_enable_1_int;
wire qsfp1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp1_rx_error_count_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int;
wire qsfp1_tx_prbs31_enable_2_int;
wire qsfp1_cfg_tx_prbs31_enable_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int;
wire qsfp1_rx_prbs31_enable_2_int;
wire qsfp1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp1_rx_error_count_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int;
wire qsfp1_tx_prbs31_enable_3_int;
wire qsfp1_cfg_tx_prbs31_enable_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int;
wire qsfp1_rx_prbs31_enable_3_int;
wire qsfp1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp1_rx_error_count_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int;
wire qsfp1_tx_prbs31_enable_4_int;
wire qsfp1_cfg_tx_prbs31_enable_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int;
wire qsfp1_rx_prbs31_enable_4_int;
wire qsfp1_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp1_rx_error_count_4_int;
wire qsfp1_drp_clk = clk_125mhz_int;
@ -1058,8 +1058,8 @@ qsfp1_phy_quad_inst (
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp1_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp1_tx_clk_2_int),
.phy_2_tx_rst(qsfp1_tx_rst_2_int),
@ -1076,8 +1076,8 @@ qsfp1_phy_quad_inst (
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp1_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp1_tx_clk_3_int),
.phy_3_tx_rst(qsfp1_tx_rst_3_int),
@ -1094,8 +1094,8 @@ qsfp1_phy_quad_inst (
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp1_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp1_tx_clk_4_int),
.phy_4_tx_rst(qsfp1_tx_rst_4_int),
@ -1112,8 +1112,8 @@ qsfp1_phy_quad_inst (
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp1_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_4_int)
);
wire ptp_clk;
@ -1584,48 +1584,48 @@ core_inst (
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_tx_prbs31_enable_1(qsfp0_tx_prbs31_enable_1_int),
.qsfp0_cfg_tx_prbs31_enable_1(qsfp0_cfg_tx_prbs31_enable_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
.qsfp0_cfg_rx_prbs31_enable_1(qsfp0_cfg_rx_prbs31_enable_1_int),
.qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
.qsfp0_rx_status_1(qsfp0_rx_status_1),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_tx_prbs31_enable_2(qsfp0_tx_prbs31_enable_2_int),
.qsfp0_cfg_tx_prbs31_enable_2(qsfp0_cfg_tx_prbs31_enable_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
.qsfp0_cfg_rx_prbs31_enable_2(qsfp0_cfg_rx_prbs31_enable_2_int),
.qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
.qsfp0_rx_status_2(qsfp0_rx_status_2),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_tx_prbs31_enable_3(qsfp0_tx_prbs31_enable_3_int),
.qsfp0_cfg_tx_prbs31_enable_3(qsfp0_cfg_tx_prbs31_enable_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
.qsfp0_cfg_rx_prbs31_enable_3(qsfp0_cfg_rx_prbs31_enable_3_int),
.qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
.qsfp0_rx_status_3(qsfp0_rx_status_3),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_tx_prbs31_enable_4(qsfp0_tx_prbs31_enable_4_int),
.qsfp0_cfg_tx_prbs31_enable_4(qsfp0_cfg_tx_prbs31_enable_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
.qsfp0_cfg_rx_prbs31_enable_4(qsfp0_cfg_rx_prbs31_enable_4_int),
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_status_4),
@ -1647,48 +1647,48 @@ core_inst (
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_tx_prbs31_enable_1(qsfp1_tx_prbs31_enable_1_int),
.qsfp1_cfg_tx_prbs31_enable_1(qsfp1_cfg_tx_prbs31_enable_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_cfg_rx_prbs31_enable_1(qsfp1_cfg_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_status_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_tx_prbs31_enable_2(qsfp1_tx_prbs31_enable_2_int),
.qsfp1_cfg_tx_prbs31_enable_2(qsfp1_cfg_tx_prbs31_enable_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_cfg_rx_prbs31_enable_2(qsfp1_cfg_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_status_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_tx_prbs31_enable_3(qsfp1_tx_prbs31_enable_3_int),
.qsfp1_cfg_tx_prbs31_enable_3(qsfp1_cfg_tx_prbs31_enable_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_cfg_rx_prbs31_enable_3(qsfp1_cfg_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_status_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_tx_prbs31_enable_4(qsfp1_tx_prbs31_enable_4_int),
.qsfp1_cfg_tx_prbs31_enable_4(qsfp1_cfg_tx_prbs31_enable_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_cfg_rx_prbs31_enable_4(qsfp1_cfg_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_status_4),

72
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v
View File

@ -294,48 +294,48 @@ module fpga_core #
input wire qsfp0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1,
output wire qsfp0_tx_prbs31_enable_1,
output wire qsfp0_cfg_tx_prbs31_enable_1,
input wire qsfp0_rx_clk_1,
input wire qsfp0_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1,
output wire qsfp0_rx_prbs31_enable_1,
output wire qsfp0_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp0_rx_error_count_1,
input wire qsfp0_rx_status_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2,
output wire qsfp0_tx_prbs31_enable_2,
output wire qsfp0_cfg_tx_prbs31_enable_2,
input wire qsfp0_rx_clk_2,
input wire qsfp0_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2,
output wire qsfp0_rx_prbs31_enable_2,
output wire qsfp0_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp0_rx_error_count_2,
input wire qsfp0_rx_status_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3,
output wire qsfp0_tx_prbs31_enable_3,
output wire qsfp0_cfg_tx_prbs31_enable_3,
input wire qsfp0_rx_clk_3,
input wire qsfp0_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3,
output wire qsfp0_rx_prbs31_enable_3,
output wire qsfp0_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp0_rx_error_count_3,
input wire qsfp0_rx_status_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4,
output wire qsfp0_tx_prbs31_enable_4,
output wire qsfp0_cfg_tx_prbs31_enable_4,
input wire qsfp0_rx_clk_4,
input wire qsfp0_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4,
output wire qsfp0_rx_prbs31_enable_4,
output wire qsfp0_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
@ -357,48 +357,48 @@ module fpga_core #
input wire qsfp1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1,
output wire qsfp1_tx_prbs31_enable_1,
output wire qsfp1_cfg_tx_prbs31_enable_1,
input wire qsfp1_rx_clk_1,
input wire qsfp1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
output wire qsfp1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2,
output wire qsfp1_tx_prbs31_enable_2,
output wire qsfp1_cfg_tx_prbs31_enable_2,
input wire qsfp1_rx_clk_2,
input wire qsfp1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
output wire qsfp1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3,
output wire qsfp1_tx_prbs31_enable_3,
output wire qsfp1_cfg_tx_prbs31_enable_3,
input wire qsfp1_rx_clk_3,
input wire qsfp1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
output wire qsfp1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4,
output wire qsfp1_tx_prbs31_enable_4,
output wire qsfp1_cfg_tx_prbs31_enable_4,
input wire qsfp1_rx_clk_4,
input wire qsfp1_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
output wire qsfp1_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
@ -833,8 +833,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}),
.phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
.phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}),
.phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}),
.phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}),
.phy_cfg_tx_prbs31_enable({qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1, qsfp0_cfg_tx_prbs31_enable_4, qsfp0_cfg_tx_prbs31_enable_3, qsfp0_cfg_tx_prbs31_enable_2, qsfp0_cfg_tx_prbs31_enable_1}),
.phy_cfg_rx_prbs31_enable({qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1, qsfp0_cfg_rx_prbs31_enable_4, qsfp0_cfg_rx_prbs31_enable_3, qsfp0_cfg_rx_prbs31_enable_2, qsfp0_cfg_rx_prbs31_enable_1}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -860,22 +860,22 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp0_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_rx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0;
end
@ -1031,7 +1031,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

32
fpga/mqnic/520N_MX/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v
View File

@ -60,8 +60,8 @@ module eth_xcvr_phy_quad_wrapper #
output wire phy_1_rx_block_lock,
output wire phy_1_rx_high_ber,
output wire phy_1_rx_status,
input wire phy_1_tx_prbs31_enable,
input wire phy_1_rx_prbs31_enable,
input wire phy_1_cfg_tx_prbs31_enable,
input wire phy_1_cfg_rx_prbs31_enable,
output wire phy_2_tx_clk,
output wire phy_2_tx_rst,
@ -78,8 +78,8 @@ module eth_xcvr_phy_quad_wrapper #
output wire phy_2_rx_block_lock,
output wire phy_2_rx_high_ber,
output wire phy_2_rx_status,
input wire phy_2_tx_prbs31_enable,
input wire phy_2_rx_prbs31_enable,
input wire phy_2_cfg_tx_prbs31_enable,
input wire phy_2_cfg_rx_prbs31_enable,
output wire phy_3_tx_clk,
output wire phy_3_tx_rst,
@ -96,8 +96,8 @@ module eth_xcvr_phy_quad_wrapper #
output wire phy_3_rx_block_lock,
output wire phy_3_rx_high_ber,
output wire phy_3_rx_status,
input wire phy_3_tx_prbs31_enable,
input wire phy_3_rx_prbs31_enable,
input wire phy_3_cfg_tx_prbs31_enable,
input wire phy_3_cfg_rx_prbs31_enable,
output wire phy_4_tx_clk,
output wire phy_4_tx_rst,
@ -114,8 +114,8 @@ module eth_xcvr_phy_quad_wrapper #
output wire phy_4_rx_block_lock,
output wire phy_4_rx_high_ber,
output wire phy_4_rx_status,
input wire phy_4_tx_prbs31_enable,
input wire phy_4_rx_prbs31_enable
input wire phy_4_cfg_tx_prbs31_enable,
input wire phy_4_cfg_rx_prbs31_enable
);
wire xcvr_gx_pll_locked;
@ -208,8 +208,8 @@ eth_xcvr_phy_1 (
.phy_rx_block_lock(phy_1_rx_block_lock),
.phy_rx_high_ber(phy_1_rx_high_ber),
.phy_rx_status(phy_1_rx_status),
.phy_tx_prbs31_enable(phy_1_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_1_rx_prbs31_enable)
.phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable)
);
eth_xcvr_phy_wrapper #(
@ -255,8 +255,8 @@ eth_xcvr_phy_2 (
.phy_rx_block_lock(phy_2_rx_block_lock),
.phy_rx_high_ber(phy_2_rx_high_ber),
.phy_rx_status(phy_2_rx_status),
.phy_tx_prbs31_enable(phy_2_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_2_rx_prbs31_enable)
.phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable)
);
eth_xcvr_phy_wrapper #(
@ -302,8 +302,8 @@ eth_xcvr_phy_3 (
.phy_rx_block_lock(phy_3_rx_block_lock),
.phy_rx_high_ber(phy_3_rx_high_ber),
.phy_rx_status(phy_3_rx_status),
.phy_tx_prbs31_enable(phy_3_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_3_rx_prbs31_enable)
.phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable)
);
eth_xcvr_phy_wrapper #(
@ -349,8 +349,8 @@ eth_xcvr_phy_4 (
.phy_rx_block_lock(phy_4_rx_block_lock),
.phy_rx_high_ber(phy_4_rx_high_ber),
.phy_rx_status(phy_4_rx_status),
.phy_tx_prbs31_enable(phy_4_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_4_rx_prbs31_enable)
.phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable)
);
endmodule

8
fpga/mqnic/520N_MX/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -62,8 +62,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
output wire phy_rx_status,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire xcvr_tx_analogreset;
@ -293,8 +293,8 @@ phy_inst (
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.rx_status(phy_rx_status),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

192
fpga/mqnic/520N_MX/fpga_25g/rtl/fpga.v
View File

@ -645,45 +645,45 @@ wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int;
wire qsfp0_tx_prbs31_enable_1_int;
wire qsfp0_cfg_tx_prbs31_enable_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int;
wire qsfp0_rx_prbs31_enable_1_int;
wire qsfp0_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp0_rx_error_count_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int;
wire qsfp0_tx_prbs31_enable_2_int;
wire qsfp0_cfg_tx_prbs31_enable_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int;
wire qsfp0_rx_prbs31_enable_2_int;
wire qsfp0_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp0_rx_error_count_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int;
wire qsfp0_tx_prbs31_enable_3_int;
wire qsfp0_cfg_tx_prbs31_enable_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int;
wire qsfp0_rx_prbs31_enable_3_int;
wire qsfp0_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp0_rx_error_count_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int;
wire qsfp0_tx_prbs31_enable_4_int;
wire qsfp0_cfg_tx_prbs31_enable_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int;
wire qsfp0_rx_prbs31_enable_4_int;
wire qsfp0_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp0_rx_error_count_4_int;
wire qsfp0_rx_block_lock_1;
@ -729,8 +729,8 @@ qsfp0_eth_xcvr_phy_quad (
.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp0_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp0_tx_clk_2_int),
.phy_2_tx_rst(qsfp0_tx_rst_2_int),
@ -747,8 +747,8 @@ qsfp0_eth_xcvr_phy_quad (
.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp0_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp0_tx_clk_3_int),
.phy_3_tx_rst(qsfp0_tx_rst_3_int),
@ -765,8 +765,8 @@ qsfp0_eth_xcvr_phy_quad (
.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp0_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp0_tx_clk_4_int),
.phy_4_tx_rst(qsfp0_tx_rst_4_int),
@ -783,8 +783,8 @@ qsfp0_eth_xcvr_phy_quad (
.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp0_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_4_int)
);
// QSFP1
@ -792,45 +792,45 @@ wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int;
wire qsfp1_tx_prbs31_enable_1_int;
wire qsfp1_cfg_tx_prbs31_enable_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int;
wire qsfp1_rx_prbs31_enable_1_int;
wire qsfp1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp1_rx_error_count_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int;
wire qsfp1_tx_prbs31_enable_2_int;
wire qsfp1_cfg_tx_prbs31_enable_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int;
wire qsfp1_rx_prbs31_enable_2_int;
wire qsfp1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp1_rx_error_count_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int;
wire qsfp1_tx_prbs31_enable_3_int;
wire qsfp1_cfg_tx_prbs31_enable_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int;
wire qsfp1_rx_prbs31_enable_3_int;
wire qsfp1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp1_rx_error_count_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int;
wire qsfp1_tx_prbs31_enable_4_int;
wire qsfp1_cfg_tx_prbs31_enable_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int;
wire qsfp1_rx_prbs31_enable_4_int;
wire qsfp1_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp1_rx_error_count_4_int;
wire qsfp1_rx_block_lock_1;
@ -876,8 +876,8 @@ qsfp1_eth_xcvr_phy_quad (
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp1_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp1_tx_clk_2_int),
.phy_2_tx_rst(qsfp1_tx_rst_2_int),
@ -894,8 +894,8 @@ qsfp1_eth_xcvr_phy_quad (
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp1_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp1_tx_clk_3_int),
.phy_3_tx_rst(qsfp1_tx_rst_3_int),
@ -912,8 +912,8 @@ qsfp1_eth_xcvr_phy_quad (
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp1_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp1_tx_clk_4_int),
.phy_4_tx_rst(qsfp1_tx_rst_4_int),
@ -930,8 +930,8 @@ qsfp1_eth_xcvr_phy_quad (
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp1_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_4_int)
);
// QSFP2
@ -939,45 +939,45 @@ wire qsfp2_tx_clk_1_int;
wire qsfp2_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_1_int;
wire qsfp2_tx_prbs31_enable_1_int;
wire qsfp2_cfg_tx_prbs31_enable_1_int;
wire qsfp2_rx_clk_1_int;
wire qsfp2_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_1_int;
wire qsfp2_rx_prbs31_enable_1_int;
wire qsfp2_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp2_rx_error_count_1_int;
wire qsfp2_tx_clk_2_int;
wire qsfp2_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_2_int;
wire qsfp2_tx_prbs31_enable_2_int;
wire qsfp2_cfg_tx_prbs31_enable_2_int;
wire qsfp2_rx_clk_2_int;
wire qsfp2_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_2_int;
wire qsfp2_rx_prbs31_enable_2_int;
wire qsfp2_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp2_rx_error_count_2_int;
wire qsfp2_tx_clk_3_int;
wire qsfp2_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_3_int;
wire qsfp2_tx_prbs31_enable_3_int;
wire qsfp2_cfg_tx_prbs31_enable_3_int;
wire qsfp2_rx_clk_3_int;
wire qsfp2_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_3_int;
wire qsfp2_rx_prbs31_enable_3_int;
wire qsfp2_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp2_rx_error_count_3_int;
wire qsfp2_tx_clk_4_int;
wire qsfp2_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_4_int;
wire qsfp2_tx_prbs31_enable_4_int;
wire qsfp2_cfg_tx_prbs31_enable_4_int;
wire qsfp2_rx_clk_4_int;
wire qsfp2_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_4_int;
wire qsfp2_rx_prbs31_enable_4_int;
wire qsfp2_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp2_rx_error_count_4_int;
wire qsfp2_rx_block_lock_1;
@ -1023,8 +1023,8 @@ qsfp2_eth_xcvr_phy_quad (
.phy_1_rx_block_lock(qsfp2_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp2_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp2_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp2_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp2_tx_clk_2_int),
.phy_2_tx_rst(qsfp2_tx_rst_2_int),
@ -1041,8 +1041,8 @@ qsfp2_eth_xcvr_phy_quad (
.phy_2_rx_block_lock(qsfp2_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp2_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp2_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp2_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp2_tx_clk_3_int),
.phy_3_tx_rst(qsfp2_tx_rst_3_int),
@ -1059,8 +1059,8 @@ qsfp2_eth_xcvr_phy_quad (
.phy_3_rx_block_lock(qsfp2_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp2_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp2_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp2_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp2_tx_clk_4_int),
.phy_4_tx_rst(qsfp2_tx_rst_4_int),
@ -1077,8 +1077,8 @@ qsfp2_eth_xcvr_phy_quad (
.phy_4_rx_block_lock(qsfp2_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp2_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp2_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp2_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_4_int)
);
// QSFP3
@ -1086,45 +1086,45 @@ wire qsfp3_tx_clk_1_int;
wire qsfp3_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_1_int;
wire qsfp3_tx_prbs31_enable_1_int;
wire qsfp3_cfg_tx_prbs31_enable_1_int;
wire qsfp3_rx_clk_1_int;
wire qsfp3_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_1_int;
wire qsfp3_rx_prbs31_enable_1_int;
wire qsfp3_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp3_rx_error_count_1_int;
wire qsfp3_tx_clk_2_int;
wire qsfp3_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_2_int;
wire qsfp3_tx_prbs31_enable_2_int;
wire qsfp3_cfg_tx_prbs31_enable_2_int;
wire qsfp3_rx_clk_2_int;
wire qsfp3_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_2_int;
wire qsfp3_rx_prbs31_enable_2_int;
wire qsfp3_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp3_rx_error_count_2_int;
wire qsfp3_tx_clk_3_int;
wire qsfp3_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_3_int;
wire qsfp3_tx_prbs31_enable_3_int;
wire qsfp3_cfg_tx_prbs31_enable_3_int;
wire qsfp3_rx_clk_3_int;
wire qsfp3_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_3_int;
wire qsfp3_rx_prbs31_enable_3_int;
wire qsfp3_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp3_rx_error_count_3_int;
wire qsfp3_tx_clk_4_int;
wire qsfp3_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_4_int;
wire qsfp3_tx_prbs31_enable_4_int;
wire qsfp3_cfg_tx_prbs31_enable_4_int;
wire qsfp3_rx_clk_4_int;
wire qsfp3_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_4_int;
wire qsfp3_rx_prbs31_enable_4_int;
wire qsfp3_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp3_rx_error_count_4_int;
wire qsfp3_rx_block_lock_1;
@ -1170,8 +1170,8 @@ qsfp3_eth_xcvr_phy_quad (
.phy_1_rx_block_lock(qsfp3_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp3_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp3_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp3_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp3_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp3_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp3_tx_clk_2_int),
.phy_2_tx_rst(qsfp3_tx_rst_2_int),
@ -1188,8 +1188,8 @@ qsfp3_eth_xcvr_phy_quad (
.phy_2_rx_block_lock(qsfp3_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp3_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp3_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp3_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp3_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp3_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp3_tx_clk_3_int),
.phy_3_tx_rst(qsfp3_tx_rst_3_int),
@ -1206,8 +1206,8 @@ qsfp3_eth_xcvr_phy_quad (
.phy_3_rx_block_lock(qsfp3_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp3_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp3_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp3_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp3_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp3_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp3_tx_clk_4_int),
.phy_4_tx_rst(qsfp3_tx_rst_4_int),
@ -1224,8 +1224,8 @@ qsfp3_eth_xcvr_phy_quad (
.phy_4_rx_block_lock(qsfp3_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp3_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp3_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp3_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp3_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp3_cfg_rx_prbs31_enable_4_int)
);
wire ptp_clk;
@ -1461,48 +1461,48 @@ core_inst (
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_tx_prbs31_enable_1(qsfp0_tx_prbs31_enable_1_int),
.qsfp0_cfg_tx_prbs31_enable_1(qsfp0_cfg_tx_prbs31_enable_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
.qsfp0_cfg_rx_prbs31_enable_1(qsfp0_cfg_rx_prbs31_enable_1_int),
.qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
.qsfp0_rx_status_1(qsfp0_rx_status_1),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_tx_prbs31_enable_2(qsfp0_tx_prbs31_enable_2_int),
.qsfp0_cfg_tx_prbs31_enable_2(qsfp0_cfg_tx_prbs31_enable_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
.qsfp0_cfg_rx_prbs31_enable_2(qsfp0_cfg_rx_prbs31_enable_2_int),
.qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
.qsfp0_rx_status_2(qsfp0_rx_status_2),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_tx_prbs31_enable_3(qsfp0_tx_prbs31_enable_3_int),
.qsfp0_cfg_tx_prbs31_enable_3(qsfp0_cfg_tx_prbs31_enable_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
.qsfp0_cfg_rx_prbs31_enable_3(qsfp0_cfg_rx_prbs31_enable_3_int),
.qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
.qsfp0_rx_status_3(qsfp0_rx_status_3),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_tx_prbs31_enable_4(qsfp0_tx_prbs31_enable_4_int),
.qsfp0_cfg_tx_prbs31_enable_4(qsfp0_cfg_tx_prbs31_enable_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
.qsfp0_cfg_rx_prbs31_enable_4(qsfp0_cfg_rx_prbs31_enable_4_int),
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_status_4),
@ -1510,48 +1510,48 @@ core_inst (
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_tx_prbs31_enable_1(qsfp1_tx_prbs31_enable_1_int),
.qsfp1_cfg_tx_prbs31_enable_1(qsfp1_cfg_tx_prbs31_enable_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_cfg_rx_prbs31_enable_1(qsfp1_cfg_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_status_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_tx_prbs31_enable_2(qsfp1_tx_prbs31_enable_2_int),
.qsfp1_cfg_tx_prbs31_enable_2(qsfp1_cfg_tx_prbs31_enable_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_cfg_rx_prbs31_enable_2(qsfp1_cfg_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_status_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_tx_prbs31_enable_3(qsfp1_tx_prbs31_enable_3_int),
.qsfp1_cfg_tx_prbs31_enable_3(qsfp1_cfg_tx_prbs31_enable_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_cfg_rx_prbs31_enable_3(qsfp1_cfg_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_status_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_tx_prbs31_enable_4(qsfp1_tx_prbs31_enable_4_int),
.qsfp1_cfg_tx_prbs31_enable_4(qsfp1_cfg_tx_prbs31_enable_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_cfg_rx_prbs31_enable_4(qsfp1_cfg_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_status_4),
@ -1559,48 +1559,48 @@ core_inst (
.qsfp2_tx_rst_1(qsfp2_tx_rst_1_int),
.qsfp2_txd_1(qsfp2_txd_1_int),
.qsfp2_txc_1(qsfp2_txc_1_int),
.qsfp2_tx_prbs31_enable_1(qsfp2_tx_prbs31_enable_1_int),
.qsfp2_cfg_tx_prbs31_enable_1(qsfp2_cfg_tx_prbs31_enable_1_int),
.qsfp2_rx_clk_1(qsfp2_rx_clk_1_int),
.qsfp2_rx_rst_1(qsfp2_rx_rst_1_int),
.qsfp2_rxd_1(qsfp2_rxd_1_int),
.qsfp2_rxc_1(qsfp2_rxc_1_int),
.qsfp2_rx_prbs31_enable_1(qsfp2_rx_prbs31_enable_1_int),
.qsfp2_cfg_rx_prbs31_enable_1(qsfp2_cfg_rx_prbs31_enable_1_int),
.qsfp2_rx_error_count_1(qsfp2_rx_error_count_1_int),
.qsfp2_rx_status_1(qsfp2_rx_status_1),
.qsfp2_tx_clk_2(qsfp2_tx_clk_2_int),
.qsfp2_tx_rst_2(qsfp2_tx_rst_2_int),
.qsfp2_txd_2(qsfp2_txd_2_int),
.qsfp2_txc_2(qsfp2_txc_2_int),
.qsfp2_tx_prbs31_enable_2(qsfp2_tx_prbs31_enable_2_int),
.qsfp2_cfg_tx_prbs31_enable_2(qsfp2_cfg_tx_prbs31_enable_2_int),
.qsfp2_rx_clk_2(qsfp2_rx_clk_2_int),
.qsfp2_rx_rst_2(qsfp2_rx_rst_2_int),
.qsfp2_rxd_2(qsfp2_rxd_2_int),
.qsfp2_rxc_2(qsfp2_rxc_2_int),
.qsfp2_rx_prbs31_enable_2(qsfp2_rx_prbs31_enable_2_int),
.qsfp2_cfg_rx_prbs31_enable_2(qsfp2_cfg_rx_prbs31_enable_2_int),
.qsfp2_rx_error_count_2(qsfp2_rx_error_count_2_int),
.qsfp2_rx_status_2(qsfp2_rx_status_2),
.qsfp2_tx_clk_3(qsfp2_tx_clk_3_int),
.qsfp2_tx_rst_3(qsfp2_tx_rst_3_int),
.qsfp2_txd_3(qsfp2_txd_3_int),
.qsfp2_txc_3(qsfp2_txc_3_int),
.qsfp2_tx_prbs31_enable_3(qsfp2_tx_prbs31_enable_3_int),
.qsfp2_cfg_tx_prbs31_enable_3(qsfp2_cfg_tx_prbs31_enable_3_int),
.qsfp2_rx_clk_3(qsfp2_rx_clk_3_int),
.qsfp2_rx_rst_3(qsfp2_rx_rst_3_int),
.qsfp2_rxd_3(qsfp2_rxd_3_int),
.qsfp2_rxc_3(qsfp2_rxc_3_int),
.qsfp2_rx_prbs31_enable_3(qsfp2_rx_prbs31_enable_3_int),
.qsfp2_cfg_rx_prbs31_enable_3(qsfp2_cfg_rx_prbs31_enable_3_int),
.qsfp2_rx_error_count_3(qsfp2_rx_error_count_3_int),
.qsfp2_rx_status_3(qsfp2_rx_status_3),
.qsfp2_tx_clk_4(qsfp2_tx_clk_4_int),
.qsfp2_tx_rst_4(qsfp2_tx_rst_4_int),
.qsfp2_txd_4(qsfp2_txd_4_int),
.qsfp2_txc_4(qsfp2_txc_4_int),
.qsfp2_tx_prbs31_enable_4(qsfp2_tx_prbs31_enable_4_int),
.qsfp2_cfg_tx_prbs31_enable_4(qsfp2_cfg_tx_prbs31_enable_4_int),
.qsfp2_rx_clk_4(qsfp2_rx_clk_4_int),
.qsfp2_rx_rst_4(qsfp2_rx_rst_4_int),
.qsfp2_rxd_4(qsfp2_rxd_4_int),
.qsfp2_rxc_4(qsfp2_rxc_4_int),
.qsfp2_rx_prbs31_enable_4(qsfp2_rx_prbs31_enable_4_int),
.qsfp2_cfg_rx_prbs31_enable_4(qsfp2_cfg_rx_prbs31_enable_4_int),
.qsfp2_rx_error_count_4(qsfp2_rx_error_count_4_int),
.qsfp2_rx_status_4(qsfp2_rx_status_4),
@ -1608,48 +1608,48 @@ core_inst (
.qsfp3_tx_rst_1(qsfp3_tx_rst_1_int),
.qsfp3_txd_1(qsfp3_txd_1_int),
.qsfp3_txc_1(qsfp3_txc_1_int),
.qsfp3_tx_prbs31_enable_1(qsfp3_tx_prbs31_enable_1_int),
.qsfp3_cfg_tx_prbs31_enable_1(qsfp3_cfg_tx_prbs31_enable_1_int),
.qsfp3_rx_clk_1(qsfp3_rx_clk_1_int),
.qsfp3_rx_rst_1(qsfp3_rx_rst_1_int),
.qsfp3_rxd_1(qsfp3_rxd_1_int),
.qsfp3_rxc_1(qsfp3_rxc_1_int),
.qsfp3_rx_prbs31_enable_1(qsfp3_rx_prbs31_enable_1_int),
.qsfp3_cfg_rx_prbs31_enable_1(qsfp3_cfg_rx_prbs31_enable_1_int),
.qsfp3_rx_error_count_1(qsfp3_rx_error_count_1_int),
.qsfp3_rx_status_1(qsfp3_rx_status_1),
.qsfp3_tx_clk_2(qsfp3_tx_clk_2_int),
.qsfp3_tx_rst_2(qsfp3_tx_rst_2_int),
.qsfp3_txd_2(qsfp3_txd_2_int),
.qsfp3_txc_2(qsfp3_txc_2_int),
.qsfp3_tx_prbs31_enable_2(qsfp3_tx_prbs31_enable_2_int),
.qsfp3_cfg_tx_prbs31_enable_2(qsfp3_cfg_tx_prbs31_enable_2_int),
.qsfp3_rx_clk_2(qsfp3_rx_clk_2_int),
.qsfp3_rx_rst_2(qsfp3_rx_rst_2_int),
.qsfp3_rxd_2(qsfp3_rxd_2_int),
.qsfp3_rxc_2(qsfp3_rxc_2_int),
.qsfp3_rx_prbs31_enable_2(qsfp3_rx_prbs31_enable_2_int),
.qsfp3_cfg_rx_prbs31_enable_2(qsfp3_cfg_rx_prbs31_enable_2_int),
.qsfp3_rx_error_count_2(qsfp3_rx_error_count_2_int),
.qsfp3_rx_status_2(qsfp3_rx_status_2),
.qsfp3_tx_clk_3(qsfp3_tx_clk_3_int),
.qsfp3_tx_rst_3(qsfp3_tx_rst_3_int),
.qsfp3_txd_3(qsfp3_txd_3_int),
.qsfp3_txc_3(qsfp3_txc_3_int),
.qsfp3_tx_prbs31_enable_3(qsfp3_tx_prbs31_enable_3_int),
.qsfp3_cfg_tx_prbs31_enable_3(qsfp3_cfg_tx_prbs31_enable_3_int),
.qsfp3_rx_clk_3(qsfp3_rx_clk_3_int),
.qsfp3_rx_rst_3(qsfp3_rx_rst_3_int),
.qsfp3_rxd_3(qsfp3_rxd_3_int),
.qsfp3_rxc_3(qsfp3_rxc_3_int),
.qsfp3_rx_prbs31_enable_3(qsfp3_rx_prbs31_enable_3_int),
.qsfp3_cfg_rx_prbs31_enable_3(qsfp3_cfg_rx_prbs31_enable_3_int),
.qsfp3_rx_error_count_3(qsfp3_rx_error_count_3_int),
.qsfp3_rx_status_3(qsfp3_rx_status_3),
.qsfp3_tx_clk_4(qsfp3_tx_clk_4_int),
.qsfp3_tx_rst_4(qsfp3_tx_rst_4_int),
.qsfp3_txd_4(qsfp3_txd_4_int),
.qsfp3_txc_4(qsfp3_txc_4_int),
.qsfp3_tx_prbs31_enable_4(qsfp3_tx_prbs31_enable_4_int),
.qsfp3_cfg_tx_prbs31_enable_4(qsfp3_cfg_tx_prbs31_enable_4_int),
.qsfp3_rx_clk_4(qsfp3_rx_clk_4_int),
.qsfp3_rx_rst_4(qsfp3_rx_rst_4_int),
.qsfp3_rxd_4(qsfp3_rxd_4_int),
.qsfp3_rxc_4(qsfp3_rxc_4_int),
.qsfp3_rx_prbs31_enable_4(qsfp3_rx_prbs31_enable_4_int),
.qsfp3_cfg_rx_prbs31_enable_4(qsfp3_cfg_rx_prbs31_enable_4_int),
.qsfp3_rx_error_count_4(qsfp3_rx_error_count_4_int),
.qsfp3_rx_status_4(qsfp3_rx_status_4)
);

136
fpga/mqnic/520N_MX/fpga_25g/rtl/fpga_core.v
View File

@ -227,48 +227,48 @@ module fpga_core #
input wire qsfp0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1,
output wire qsfp0_tx_prbs31_enable_1,
output wire qsfp0_cfg_tx_prbs31_enable_1,
input wire qsfp0_rx_clk_1,
input wire qsfp0_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1,
output wire qsfp0_rx_prbs31_enable_1,
output wire qsfp0_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp0_rx_error_count_1,
input wire qsfp0_rx_status_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2,
output wire qsfp0_tx_prbs31_enable_2,
output wire qsfp0_cfg_tx_prbs31_enable_2,
input wire qsfp0_rx_clk_2,
input wire qsfp0_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2,
output wire qsfp0_rx_prbs31_enable_2,
output wire qsfp0_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp0_rx_error_count_2,
input wire qsfp0_rx_status_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3,
output wire qsfp0_tx_prbs31_enable_3,
output wire qsfp0_cfg_tx_prbs31_enable_3,
input wire qsfp0_rx_clk_3,
input wire qsfp0_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3,
output wire qsfp0_rx_prbs31_enable_3,
output wire qsfp0_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp0_rx_error_count_3,
input wire qsfp0_rx_status_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4,
output wire qsfp0_tx_prbs31_enable_4,
output wire qsfp0_cfg_tx_prbs31_enable_4,
input wire qsfp0_rx_clk_4,
input wire qsfp0_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4,
output wire qsfp0_rx_prbs31_enable_4,
output wire qsfp0_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
@ -276,48 +276,48 @@ module fpga_core #
input wire qsfp1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1,
output wire qsfp1_tx_prbs31_enable_1,
output wire qsfp1_cfg_tx_prbs31_enable_1,
input wire qsfp1_rx_clk_1,
input wire qsfp1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
output wire qsfp1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2,
output wire qsfp1_tx_prbs31_enable_2,
output wire qsfp1_cfg_tx_prbs31_enable_2,
input wire qsfp1_rx_clk_2,
input wire qsfp1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
output wire qsfp1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3,
output wire qsfp1_tx_prbs31_enable_3,
output wire qsfp1_cfg_tx_prbs31_enable_3,
input wire qsfp1_rx_clk_3,
input wire qsfp1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
output wire qsfp1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4,
output wire qsfp1_tx_prbs31_enable_4,
output wire qsfp1_cfg_tx_prbs31_enable_4,
input wire qsfp1_rx_clk_4,
input wire qsfp1_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
output wire qsfp1_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
@ -325,48 +325,48 @@ module fpga_core #
input wire qsfp2_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_1,
output wire qsfp2_tx_prbs31_enable_1,
output wire qsfp2_cfg_tx_prbs31_enable_1,
input wire qsfp2_rx_clk_1,
input wire qsfp2_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_1,
output wire qsfp2_rx_prbs31_enable_1,
output wire qsfp2_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp2_rx_error_count_1,
input wire qsfp2_rx_status_1,
input wire qsfp2_tx_clk_2,
input wire qsfp2_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_2,
output wire qsfp2_tx_prbs31_enable_2,
output wire qsfp2_cfg_tx_prbs31_enable_2,
input wire qsfp2_rx_clk_2,
input wire qsfp2_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_2,
output wire qsfp2_rx_prbs31_enable_2,
output wire qsfp2_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp2_rx_error_count_2,
input wire qsfp2_rx_status_2,
input wire qsfp2_tx_clk_3,
input wire qsfp2_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_3,
output wire qsfp2_tx_prbs31_enable_3,
output wire qsfp2_cfg_tx_prbs31_enable_3,
input wire qsfp2_rx_clk_3,
input wire qsfp2_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_3,
output wire qsfp2_rx_prbs31_enable_3,
output wire qsfp2_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp2_rx_error_count_3,
input wire qsfp2_rx_status_3,
input wire qsfp2_tx_clk_4,
input wire qsfp2_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_4,
output wire qsfp2_tx_prbs31_enable_4,
output wire qsfp2_cfg_tx_prbs31_enable_4,
input wire qsfp2_rx_clk_4,
input wire qsfp2_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_4,
output wire qsfp2_rx_prbs31_enable_4,
output wire qsfp2_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp2_rx_error_count_4,
input wire qsfp2_rx_status_4,
@ -374,48 +374,48 @@ module fpga_core #
input wire qsfp3_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_1,
output wire qsfp3_tx_prbs31_enable_1,
output wire qsfp3_cfg_tx_prbs31_enable_1,
input wire qsfp3_rx_clk_1,
input wire qsfp3_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_1,
output wire qsfp3_rx_prbs31_enable_1,
output wire qsfp3_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp3_rx_error_count_1,
input wire qsfp3_rx_status_1,
input wire qsfp3_tx_clk_2,
input wire qsfp3_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_2,
output wire qsfp3_tx_prbs31_enable_2,
output wire qsfp3_cfg_tx_prbs31_enable_2,
input wire qsfp3_rx_clk_2,
input wire qsfp3_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_2,
output wire qsfp3_rx_prbs31_enable_2,
output wire qsfp3_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp3_rx_error_count_2,
input wire qsfp3_rx_status_2,
input wire qsfp3_tx_clk_3,
input wire qsfp3_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_3,
output wire qsfp3_tx_prbs31_enable_3,
output wire qsfp3_cfg_tx_prbs31_enable_3,
input wire qsfp3_rx_clk_3,
input wire qsfp3_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_3,
output wire qsfp3_rx_prbs31_enable_3,
output wire qsfp3_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp3_rx_error_count_3,
input wire qsfp3_rx_status_3,
input wire qsfp3_tx_clk_4,
input wire qsfp3_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_4,
output wire qsfp3_tx_prbs31_enable_4,
output wire qsfp3_cfg_tx_prbs31_enable_4,
input wire qsfp3_rx_clk_4,
input wire qsfp3_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_4,
output wire qsfp3_rx_prbs31_enable_4,
output wire qsfp3_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp3_rx_error_count_4,
input wire qsfp3_rx_status_4
);
@ -583,8 +583,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp3_tx_clk_4, qsfp3_tx_clk_3, qsfp3_tx_clk_2, qsfp3_tx_clk_1, qsfp2_tx_clk_4, qsfp2_tx_clk_3, qsfp2_tx_clk_2, qsfp2_tx_clk_1, qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}),
.phy_rx_clk({qsfp3_rx_clk_4, qsfp3_rx_clk_3, qsfp3_rx_clk_2, qsfp3_rx_clk_1, qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
.phy_rx_error_count({qsfp3_rx_error_count_4, qsfp3_rx_error_count_3, qsfp3_rx_error_count_2, qsfp3_rx_error_count_1, qsfp2_rx_error_count_4, qsfp2_rx_error_count_3, qsfp2_rx_error_count_2, qsfp2_rx_error_count_1, qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}),
.phy_tx_prbs31_enable({qsfp3_tx_prbs31_enable_4, qsfp3_tx_prbs31_enable_3, qsfp3_tx_prbs31_enable_2, qsfp3_tx_prbs31_enable_1, qsfp2_tx_prbs31_enable_4, qsfp2_tx_prbs31_enable_3, qsfp2_tx_prbs31_enable_2, qsfp2_tx_prbs31_enable_1, qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}),
.phy_rx_prbs31_enable({qsfp3_rx_prbs31_enable_4, qsfp3_rx_prbs31_enable_3, qsfp3_rx_prbs31_enable_2, qsfp3_rx_prbs31_enable_1, qsfp2_rx_prbs31_enable_4, qsfp2_rx_prbs31_enable_3, qsfp2_rx_prbs31_enable_2, qsfp2_rx_prbs31_enable_1, qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}),
.phy_cfg_tx_prbs31_enable({qsfp3_cfg_tx_prbs31_enable_4, qsfp3_cfg_tx_prbs31_enable_3, qsfp3_cfg_tx_prbs31_enable_2, qsfp3_cfg_tx_prbs31_enable_1, qsfp2_cfg_tx_prbs31_enable_4, qsfp2_cfg_tx_prbs31_enable_3, qsfp2_cfg_tx_prbs31_enable_2, qsfp2_cfg_tx_prbs31_enable_1, qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1, qsfp0_cfg_tx_prbs31_enable_4, qsfp0_cfg_tx_prbs31_enable_3, qsfp0_cfg_tx_prbs31_enable_2, qsfp0_cfg_tx_prbs31_enable_1}),
.phy_cfg_rx_prbs31_enable({qsfp3_cfg_rx_prbs31_enable_4, qsfp3_cfg_rx_prbs31_enable_3, qsfp3_cfg_rx_prbs31_enable_2, qsfp3_cfg_rx_prbs31_enable_1, qsfp2_cfg_rx_prbs31_enable_4, qsfp2_cfg_rx_prbs31_enable_3, qsfp2_cfg_rx_prbs31_enable_2, qsfp2_cfg_rx_prbs31_enable_1, qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1, qsfp0_cfg_rx_prbs31_enable_4, qsfp0_cfg_rx_prbs31_enable_3, qsfp0_cfg_rx_prbs31_enable_2, qsfp0_cfg_rx_prbs31_enable_1}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -610,38 +610,38 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp0_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_rx_prbs31_enable_4 = 1'b0;
assign qsfp2_tx_prbs31_enable_1 = 1'b0;
assign qsfp2_rx_prbs31_enable_1 = 1'b0;
assign qsfp2_tx_prbs31_enable_2 = 1'b0;
assign qsfp2_rx_prbs31_enable_2 = 1'b0;
assign qsfp2_tx_prbs31_enable_3 = 1'b0;
assign qsfp2_rx_prbs31_enable_3 = 1'b0;
assign qsfp2_tx_prbs31_enable_4 = 1'b0;
assign qsfp2_rx_prbs31_enable_4 = 1'b0;
assign qsfp3_tx_prbs31_enable_1 = 1'b0;
assign qsfp3_rx_prbs31_enable_1 = 1'b0;
assign qsfp3_tx_prbs31_enable_2 = 1'b0;
assign qsfp3_rx_prbs31_enable_2 = 1'b0;
assign qsfp3_tx_prbs31_enable_3 = 1'b0;
assign qsfp3_rx_prbs31_enable_3 = 1'b0;
assign qsfp3_tx_prbs31_enable_4 = 1'b0;
assign qsfp3_rx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp3_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp3_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp3_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp3_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp3_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp3_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp3_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp3_cfg_rx_prbs31_enable_4 = 1'b0;
end
@ -805,7 +805,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

96
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -931,45 +931,45 @@ wire qsfp_0_tx_clk_0_int;
wire qsfp_0_tx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_0_int;
wire qsfp_0_tx_prbs31_enable_0_int;
wire qsfp_0_cfg_tx_prbs31_enable_0_int;
wire qsfp_0_rx_clk_0_int;
wire qsfp_0_rx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_0_int;
wire qsfp_0_rx_prbs31_enable_0_int;
wire qsfp_0_cfg_rx_prbs31_enable_0_int;
wire [6:0] qsfp_0_rx_error_count_0_int;
wire qsfp_0_tx_clk_1_int;
wire qsfp_0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_1_int;
wire qsfp_0_tx_prbs31_enable_1_int;
wire qsfp_0_cfg_tx_prbs31_enable_1_int;
wire qsfp_0_rx_clk_1_int;
wire qsfp_0_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_1_int;
wire qsfp_0_rx_prbs31_enable_1_int;
wire qsfp_0_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp_0_rx_error_count_1_int;
wire qsfp_0_tx_clk_2_int;
wire qsfp_0_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_2_int;
wire qsfp_0_tx_prbs31_enable_2_int;
wire qsfp_0_cfg_tx_prbs31_enable_2_int;
wire qsfp_0_rx_clk_2_int;
wire qsfp_0_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_2_int;
wire qsfp_0_rx_prbs31_enable_2_int;
wire qsfp_0_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp_0_rx_error_count_2_int;
wire qsfp_0_tx_clk_3_int;
wire qsfp_0_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_3_int;
wire qsfp_0_tx_prbs31_enable_3_int;
wire qsfp_0_cfg_tx_prbs31_enable_3_int;
wire qsfp_0_rx_clk_3_int;
wire qsfp_0_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_3_int;
wire qsfp_0_rx_prbs31_enable_3_int;
wire qsfp_0_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp_0_rx_error_count_3_int;
wire qsfp_0_drp_clk = clk_125mhz_int;
@ -1079,8 +1079,8 @@ qsfp_0_phy_quad_inst (
.phy_1_rx_block_lock(qsfp_0_rx_block_lock_0),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp_0_rx_status_0),
.phy_1_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_0_int),
.phy_1_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_0_int),
.phy_1_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_0_int),
.phy_1_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_0_int),
.phy_2_tx_clk(qsfp_0_tx_clk_1_int),
.phy_2_tx_rst(qsfp_0_tx_rst_1_int),
@ -1097,8 +1097,8 @@ qsfp_0_phy_quad_inst (
.phy_2_rx_block_lock(qsfp_0_rx_block_lock_1),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp_0_rx_status_1),
.phy_2_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_1_int),
.phy_2_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_1_int),
.phy_2_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_1_int),
.phy_2_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_1_int),
.phy_3_tx_clk(qsfp_0_tx_clk_2_int),
.phy_3_tx_rst(qsfp_0_tx_rst_2_int),
@ -1115,8 +1115,8 @@ qsfp_0_phy_quad_inst (
.phy_3_rx_block_lock(qsfp_0_rx_block_lock_2),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp_0_rx_status_2),
.phy_3_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_2_int),
.phy_3_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_2_int),
.phy_3_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_2_int),
.phy_3_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_2_int),
.phy_4_tx_clk(qsfp_0_tx_clk_3_int),
.phy_4_tx_rst(qsfp_0_tx_rst_3_int),
@ -1133,8 +1133,8 @@ qsfp_0_phy_quad_inst (
.phy_4_rx_block_lock(qsfp_0_rx_block_lock_3),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp_0_rx_status_3),
.phy_4_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_3_int),
.phy_4_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_3_int)
.phy_4_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_3_int),
.phy_4_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_3_int)
);
// QSFP1
@ -1142,45 +1142,45 @@ wire qsfp_1_tx_clk_0_int;
wire qsfp_1_tx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_0_int;
wire qsfp_1_tx_prbs31_enable_0_int;
wire qsfp_1_cfg_tx_prbs31_enable_0_int;
wire qsfp_1_rx_clk_0_int;
wire qsfp_1_rx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_0_int;
wire qsfp_1_rx_prbs31_enable_0_int;
wire qsfp_1_cfg_rx_prbs31_enable_0_int;
wire [6:0] qsfp_1_rx_error_count_0_int;
wire qsfp_1_tx_clk_1_int;
wire qsfp_1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_1_int;
wire qsfp_1_tx_prbs31_enable_1_int;
wire qsfp_1_cfg_tx_prbs31_enable_1_int;
wire qsfp_1_rx_clk_1_int;
wire qsfp_1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_1_int;
wire qsfp_1_rx_prbs31_enable_1_int;
wire qsfp_1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp_1_rx_error_count_1_int;
wire qsfp_1_tx_clk_2_int;
wire qsfp_1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_2_int;
wire qsfp_1_tx_prbs31_enable_2_int;
wire qsfp_1_cfg_tx_prbs31_enable_2_int;
wire qsfp_1_rx_clk_2_int;
wire qsfp_1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_2_int;
wire qsfp_1_rx_prbs31_enable_2_int;
wire qsfp_1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp_1_rx_error_count_2_int;
wire qsfp_1_tx_clk_3_int;
wire qsfp_1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_3_int;
wire qsfp_1_tx_prbs31_enable_3_int;
wire qsfp_1_cfg_tx_prbs31_enable_3_int;
wire qsfp_1_rx_clk_3_int;
wire qsfp_1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_3_int;
wire qsfp_1_rx_prbs31_enable_3_int;
wire qsfp_1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp_1_rx_error_count_3_int;
wire qsfp_1_drp_clk = clk_125mhz_int;
@ -1290,8 +1290,8 @@ qsfp_1_phy_quad_inst (
.phy_1_rx_block_lock(qsfp_1_rx_block_lock_0),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp_1_rx_status_0),
.phy_1_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_0_int),
.phy_1_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_0_int),
.phy_1_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_0_int),
.phy_1_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_0_int),
.phy_2_tx_clk(qsfp_1_tx_clk_1_int),
.phy_2_tx_rst(qsfp_1_tx_rst_1_int),
@ -1308,8 +1308,8 @@ qsfp_1_phy_quad_inst (
.phy_2_rx_block_lock(qsfp_1_rx_block_lock_1),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp_1_rx_status_1),
.phy_2_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_1_int),
.phy_2_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_1_int),
.phy_2_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_1_int),
.phy_2_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_1_int),
.phy_3_tx_clk(qsfp_1_tx_clk_2_int),
.phy_3_tx_rst(qsfp_1_tx_rst_2_int),
@ -1326,8 +1326,8 @@ qsfp_1_phy_quad_inst (
.phy_3_rx_block_lock(qsfp_1_rx_block_lock_2),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp_1_rx_status_2),
.phy_3_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_2_int),
.phy_3_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_2_int),
.phy_3_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_2_int),
.phy_3_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_2_int),
.phy_4_tx_clk(qsfp_1_tx_clk_3_int),
.phy_4_tx_rst(qsfp_1_tx_rst_3_int),
@ -1344,8 +1344,8 @@ qsfp_1_phy_quad_inst (
.phy_4_rx_block_lock(qsfp_1_rx_block_lock_3),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp_1_rx_status_3),
.phy_4_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_3_int),
.phy_4_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_3_int)
.phy_4_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_3_int),
.phy_4_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_3_int)
);
wire ptp_clk;
@ -1924,48 +1924,48 @@ core_inst (
.qsfp_0_tx_rst_0(qsfp_0_tx_rst_0_int),
.qsfp_0_txd_0(qsfp_0_txd_0_int),
.qsfp_0_txc_0(qsfp_0_txc_0_int),
.qsfp_0_tx_prbs31_enable_0(qsfp_0_tx_prbs31_enable_0_int),
.qsfp_0_cfg_tx_prbs31_enable_0(qsfp_0_cfg_tx_prbs31_enable_0_int),
.qsfp_0_rx_clk_0(qsfp_0_rx_clk_0_int),
.qsfp_0_rx_rst_0(qsfp_0_rx_rst_0_int),
.qsfp_0_rxd_0(qsfp_0_rxd_0_int),
.qsfp_0_rxc_0(qsfp_0_rxc_0_int),
.qsfp_0_rx_prbs31_enable_0(qsfp_0_rx_prbs31_enable_0_int),
.qsfp_0_cfg_rx_prbs31_enable_0(qsfp_0_cfg_rx_prbs31_enable_0_int),
.qsfp_0_rx_error_count_0(qsfp_0_rx_error_count_0_int),
.qsfp_0_rx_status_0(qsfp_0_rx_status_0),
.qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int),
.qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int),
.qsfp_0_txd_1(qsfp_0_txd_1_int),
.qsfp_0_txc_1(qsfp_0_txc_1_int),
.qsfp_0_tx_prbs31_enable_1(qsfp_0_tx_prbs31_enable_1_int),
.qsfp_0_cfg_tx_prbs31_enable_1(qsfp_0_cfg_tx_prbs31_enable_1_int),
.qsfp_0_rx_clk_1(qsfp_0_rx_clk_1_int),
.qsfp_0_rx_rst_1(qsfp_0_rx_rst_1_int),
.qsfp_0_rxd_1(qsfp_0_rxd_1_int),
.qsfp_0_rxc_1(qsfp_0_rxc_1_int),
.qsfp_0_rx_prbs31_enable_1(qsfp_0_rx_prbs31_enable_1_int),
.qsfp_0_cfg_rx_prbs31_enable_1(qsfp_0_cfg_rx_prbs31_enable_1_int),
.qsfp_0_rx_error_count_1(qsfp_0_rx_error_count_1_int),
.qsfp_0_rx_status_1(qsfp_0_rx_status_1),
.qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int),
.qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int),
.qsfp_0_txd_2(qsfp_0_txd_2_int),
.qsfp_0_txc_2(qsfp_0_txc_2_int),
.qsfp_0_tx_prbs31_enable_2(qsfp_0_tx_prbs31_enable_2_int),
.qsfp_0_cfg_tx_prbs31_enable_2(qsfp_0_cfg_tx_prbs31_enable_2_int),
.qsfp_0_rx_clk_2(qsfp_0_rx_clk_2_int),
.qsfp_0_rx_rst_2(qsfp_0_rx_rst_2_int),
.qsfp_0_rxd_2(qsfp_0_rxd_2_int),
.qsfp_0_rxc_2(qsfp_0_rxc_2_int),
.qsfp_0_rx_prbs31_enable_2(qsfp_0_rx_prbs31_enable_2_int),
.qsfp_0_cfg_rx_prbs31_enable_2(qsfp_0_cfg_rx_prbs31_enable_2_int),
.qsfp_0_rx_error_count_2(qsfp_0_rx_error_count_2_int),
.qsfp_0_rx_status_2(qsfp_0_rx_status_2),
.qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int),
.qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int),
.qsfp_0_txd_3(qsfp_0_txd_3_int),
.qsfp_0_txc_3(qsfp_0_txc_3_int),
.qsfp_0_tx_prbs31_enable_3(qsfp_0_tx_prbs31_enable_3_int),
.qsfp_0_cfg_tx_prbs31_enable_3(qsfp_0_cfg_tx_prbs31_enable_3_int),
.qsfp_0_rx_clk_3(qsfp_0_rx_clk_3_int),
.qsfp_0_rx_rst_3(qsfp_0_rx_rst_3_int),
.qsfp_0_rxd_3(qsfp_0_rxd_3_int),
.qsfp_0_rxc_3(qsfp_0_rxc_3_int),
.qsfp_0_rx_prbs31_enable_3(qsfp_0_rx_prbs31_enable_3_int),
.qsfp_0_cfg_rx_prbs31_enable_3(qsfp_0_cfg_rx_prbs31_enable_3_int),
.qsfp_0_rx_error_count_3(qsfp_0_rx_error_count_3_int),
.qsfp_0_rx_status_3(qsfp_0_rx_status_3),
@ -1985,48 +1985,48 @@ core_inst (
.qsfp_1_tx_rst_0(qsfp_1_tx_rst_0_int),
.qsfp_1_txd_0(qsfp_1_txd_0_int),
.qsfp_1_txc_0(qsfp_1_txc_0_int),
.qsfp_1_tx_prbs31_enable_0(qsfp_1_tx_prbs31_enable_0_int),
.qsfp_1_cfg_tx_prbs31_enable_0(qsfp_1_cfg_tx_prbs31_enable_0_int),
.qsfp_1_rx_clk_0(qsfp_1_rx_clk_0_int),
.qsfp_1_rx_rst_0(qsfp_1_rx_rst_0_int),
.qsfp_1_rxd_0(qsfp_1_rxd_0_int),
.qsfp_1_rxc_0(qsfp_1_rxc_0_int),
.qsfp_1_rx_prbs31_enable_0(qsfp_1_rx_prbs31_enable_0_int),
.qsfp_1_cfg_rx_prbs31_enable_0(qsfp_1_cfg_rx_prbs31_enable_0_int),
.qsfp_1_rx_error_count_0(qsfp_1_rx_error_count_0_int),
.qsfp_1_rx_status_0(qsfp_1_rx_status_0),
.qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int),
.qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int),
.qsfp_1_txd_1(qsfp_1_txd_1_int),
.qsfp_1_txc_1(qsfp_1_txc_1_int),
.qsfp_1_tx_prbs31_enable_1(qsfp_1_tx_prbs31_enable_1_int),
.qsfp_1_cfg_tx_prbs31_enable_1(qsfp_1_cfg_tx_prbs31_enable_1_int),
.qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int),
.qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int),
.qsfp_1_rxd_1(qsfp_1_rxd_1_int),
.qsfp_1_rxc_1(qsfp_1_rxc_1_int),
.qsfp_1_rx_prbs31_enable_1(qsfp_1_rx_prbs31_enable_1_int),
.qsfp_1_cfg_rx_prbs31_enable_1(qsfp_1_cfg_rx_prbs31_enable_1_int),
.qsfp_1_rx_error_count_1(qsfp_1_rx_error_count_1_int),
.qsfp_1_rx_status_1(qsfp_1_rx_status_1),
.qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int),
.qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int),
.qsfp_1_txd_2(qsfp_1_txd_2_int),
.qsfp_1_txc_2(qsfp_1_txc_2_int),
.qsfp_1_tx_prbs31_enable_2(qsfp_1_tx_prbs31_enable_2_int),
.qsfp_1_cfg_tx_prbs31_enable_2(qsfp_1_cfg_tx_prbs31_enable_2_int),
.qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int),
.qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int),
.qsfp_1_rxd_2(qsfp_1_rxd_2_int),
.qsfp_1_rxc_2(qsfp_1_rxc_2_int),
.qsfp_1_rx_prbs31_enable_2(qsfp_1_rx_prbs31_enable_2_int),
.qsfp_1_cfg_rx_prbs31_enable_2(qsfp_1_cfg_rx_prbs31_enable_2_int),
.qsfp_1_rx_error_count_2(qsfp_1_rx_error_count_2_int),
.qsfp_1_rx_status_2(qsfp_1_rx_status_2),
.qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int),
.qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int),
.qsfp_1_txd_3(qsfp_1_txd_3_int),
.qsfp_1_txc_3(qsfp_1_txc_3_int),
.qsfp_1_tx_prbs31_enable_3(qsfp_1_tx_prbs31_enable_3_int),
.qsfp_1_cfg_tx_prbs31_enable_3(qsfp_1_cfg_tx_prbs31_enable_3_int),
.qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int),
.qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int),
.qsfp_1_rxd_3(qsfp_1_rxd_3_int),
.qsfp_1_rxc_3(qsfp_1_rxc_3_int),
.qsfp_1_rx_prbs31_enable_3(qsfp_1_rx_prbs31_enable_3_int),
.qsfp_1_cfg_rx_prbs31_enable_3(qsfp_1_cfg_rx_prbs31_enable_3_int),
.qsfp_1_rx_error_count_3(qsfp_1_rx_error_count_3_int),
.qsfp_1_rx_status_3(qsfp_1_rx_status_3),

72
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -273,48 +273,48 @@ module fpga_core #
input wire qsfp_0_tx_rst_0,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_0,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_0,
output wire qsfp_0_tx_prbs31_enable_0,
output wire qsfp_0_cfg_tx_prbs31_enable_0,
input wire qsfp_0_rx_clk_0,
input wire qsfp_0_rx_rst_0,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_0,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_0,
output wire qsfp_0_rx_prbs31_enable_0,
output wire qsfp_0_cfg_rx_prbs31_enable_0,
input wire [6:0] qsfp_0_rx_error_count_0,
input wire qsfp_0_rx_status_0,
input wire qsfp_0_tx_clk_1,
input wire qsfp_0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_1,
output wire qsfp_0_tx_prbs31_enable_1,
output wire qsfp_0_cfg_tx_prbs31_enable_1,
input wire qsfp_0_rx_clk_1,
input wire qsfp_0_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_1,
output wire qsfp_0_rx_prbs31_enable_1,
output wire qsfp_0_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp_0_rx_error_count_1,
input wire qsfp_0_rx_status_1,
input wire qsfp_0_tx_clk_2,
input wire qsfp_0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_2,
output wire qsfp_0_tx_prbs31_enable_2,
output wire qsfp_0_cfg_tx_prbs31_enable_2,
input wire qsfp_0_rx_clk_2,
input wire qsfp_0_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_2,
output wire qsfp_0_rx_prbs31_enable_2,
output wire qsfp_0_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp_0_rx_error_count_2,
input wire qsfp_0_rx_status_2,
input wire qsfp_0_tx_clk_3,
input wire qsfp_0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_3,
output wire qsfp_0_tx_prbs31_enable_3,
output wire qsfp_0_cfg_tx_prbs31_enable_3,
input wire qsfp_0_rx_clk_3,
input wire qsfp_0_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_3,
output wire qsfp_0_rx_prbs31_enable_3,
output wire qsfp_0_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp_0_rx_error_count_3,
input wire qsfp_0_rx_status_3,
@ -334,48 +334,48 @@ module fpga_core #
input wire qsfp_1_tx_rst_0,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_0,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_0,
output wire qsfp_1_tx_prbs31_enable_0,
output wire qsfp_1_cfg_tx_prbs31_enable_0,
input wire qsfp_1_rx_clk_0,
input wire qsfp_1_rx_rst_0,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_0,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_0,
output wire qsfp_1_rx_prbs31_enable_0,
output wire qsfp_1_cfg_rx_prbs31_enable_0,
input wire [6:0] qsfp_1_rx_error_count_0,
input wire qsfp_1_rx_status_0,
input wire qsfp_1_tx_clk_1,
input wire qsfp_1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_1,
output wire qsfp_1_tx_prbs31_enable_1,
output wire qsfp_1_cfg_tx_prbs31_enable_1,
input wire qsfp_1_rx_clk_1,
input wire qsfp_1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_1,
output wire qsfp_1_rx_prbs31_enable_1,
output wire qsfp_1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp_1_rx_error_count_1,
input wire qsfp_1_rx_status_1,
input wire qsfp_1_tx_clk_2,
input wire qsfp_1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_2,
output wire qsfp_1_tx_prbs31_enable_2,
output wire qsfp_1_cfg_tx_prbs31_enable_2,
input wire qsfp_1_rx_clk_2,
input wire qsfp_1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_2,
output wire qsfp_1_rx_prbs31_enable_2,
output wire qsfp_1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp_1_rx_error_count_2,
input wire qsfp_1_rx_status_2,
input wire qsfp_1_tx_clk_3,
input wire qsfp_1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_3,
output wire qsfp_1_tx_prbs31_enable_3,
output wire qsfp_1_cfg_tx_prbs31_enable_3,
input wire qsfp_1_rx_clk_3,
input wire qsfp_1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_3,
output wire qsfp_1_rx_prbs31_enable_3,
output wire qsfp_1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp_1_rx_error_count_3,
input wire qsfp_1_rx_status_3,
@ -919,8 +919,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp_1_tx_clk_3, qsfp_1_tx_clk_2, qsfp_1_tx_clk_1, qsfp_1_tx_clk_0, qsfp_0_tx_clk_3, qsfp_0_tx_clk_2, qsfp_0_tx_clk_1, qsfp_0_tx_clk_0}),
.phy_rx_clk({qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}),
.phy_rx_error_count({qsfp_1_rx_error_count_3, qsfp_1_rx_error_count_2, qsfp_1_rx_error_count_1, qsfp_1_rx_error_count_0, qsfp_0_rx_error_count_3, qsfp_0_rx_error_count_2, qsfp_0_rx_error_count_1, qsfp_0_rx_error_count_0}),
.phy_tx_prbs31_enable({qsfp_1_tx_prbs31_enable_3, qsfp_1_tx_prbs31_enable_2, qsfp_1_tx_prbs31_enable_1, qsfp_1_tx_prbs31_enable_0, qsfp_0_tx_prbs31_enable_3, qsfp_0_tx_prbs31_enable_2, qsfp_0_tx_prbs31_enable_1, qsfp_0_tx_prbs31_enable_0}),
.phy_rx_prbs31_enable({qsfp_1_rx_prbs31_enable_3, qsfp_1_rx_prbs31_enable_2, qsfp_1_rx_prbs31_enable_1, qsfp_1_rx_prbs31_enable_0, qsfp_0_rx_prbs31_enable_3, qsfp_0_rx_prbs31_enable_2, qsfp_0_rx_prbs31_enable_1, qsfp_0_rx_prbs31_enable_0}),
.phy_cfg_tx_prbs31_enable({qsfp_1_cfg_tx_prbs31_enable_3, qsfp_1_cfg_tx_prbs31_enable_2, qsfp_1_cfg_tx_prbs31_enable_1, qsfp_1_cfg_tx_prbs31_enable_0, qsfp_0_cfg_tx_prbs31_enable_3, qsfp_0_cfg_tx_prbs31_enable_2, qsfp_0_cfg_tx_prbs31_enable_1, qsfp_0_cfg_tx_prbs31_enable_0}),
.phy_cfg_rx_prbs31_enable({qsfp_1_cfg_rx_prbs31_enable_3, qsfp_1_cfg_rx_prbs31_enable_2, qsfp_1_cfg_rx_prbs31_enable_1, qsfp_1_cfg_rx_prbs31_enable_0, qsfp_0_cfg_rx_prbs31_enable_3, qsfp_0_cfg_rx_prbs31_enable_2, qsfp_0_cfg_rx_prbs31_enable_1, qsfp_0_cfg_rx_prbs31_enable_0}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -946,22 +946,22 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp_0_tx_prbs31_enable_0 = 1'b0;
assign qsfp_0_rx_prbs31_enable_0 = 1'b0;
assign qsfp_0_tx_prbs31_enable_1 = 1'b0;
assign qsfp_0_rx_prbs31_enable_1 = 1'b0;
assign qsfp_0_tx_prbs31_enable_2 = 1'b0;
assign qsfp_0_rx_prbs31_enable_2 = 1'b0;
assign qsfp_0_tx_prbs31_enable_3 = 1'b0;
assign qsfp_0_rx_prbs31_enable_3 = 1'b0;
assign qsfp_1_tx_prbs31_enable_0 = 1'b0;
assign qsfp_1_rx_prbs31_enable_0 = 1'b0;
assign qsfp_1_tx_prbs31_enable_1 = 1'b0;
assign qsfp_1_rx_prbs31_enable_1 = 1'b0;
assign qsfp_1_tx_prbs31_enable_2 = 1'b0;
assign qsfp_1_rx_prbs31_enable_2 = 1'b0;
assign qsfp_1_tx_prbs31_enable_3 = 1'b0;
assign qsfp_1_rx_prbs31_enable_3 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_0 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_0 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_0 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_0 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_3 = 1'b0;
end
@ -1120,7 +1120,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

96
fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
View File

@ -1088,45 +1088,45 @@ wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int;
wire qsfp0_tx_prbs31_enable_1_int;
wire qsfp0_cfg_tx_prbs31_enable_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int;
wire qsfp0_rx_prbs31_enable_1_int;
wire qsfp0_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp0_rx_error_count_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int;
wire qsfp0_tx_prbs31_enable_2_int;
wire qsfp0_cfg_tx_prbs31_enable_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int;
wire qsfp0_rx_prbs31_enable_2_int;
wire qsfp0_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp0_rx_error_count_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int;
wire qsfp0_tx_prbs31_enable_3_int;
wire qsfp0_cfg_tx_prbs31_enable_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int;
wire qsfp0_rx_prbs31_enable_3_int;
wire qsfp0_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp0_rx_error_count_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int;
wire qsfp0_tx_prbs31_enable_4_int;
wire qsfp0_cfg_tx_prbs31_enable_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int;
wire qsfp0_rx_prbs31_enable_4_int;
wire qsfp0_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp0_rx_error_count_4_int;
wire qsfp0_drp_clk = clk_125mhz_int;
@ -1238,8 +1238,8 @@ qsfp0_phy_quad_inst (
.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp0_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp0_tx_clk_2_int),
.phy_2_tx_rst(qsfp0_tx_rst_2_int),
@ -1256,8 +1256,8 @@ qsfp0_phy_quad_inst (
.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp0_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp0_tx_clk_3_int),
.phy_3_tx_rst(qsfp0_tx_rst_3_int),
@ -1274,8 +1274,8 @@ qsfp0_phy_quad_inst (
.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp0_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp0_tx_clk_4_int),
.phy_4_tx_rst(qsfp0_tx_rst_4_int),
@ -1292,8 +1292,8 @@ qsfp0_phy_quad_inst (
.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp0_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_4_int)
);
// QSFP1
@ -1304,45 +1304,45 @@ wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int;
wire qsfp1_tx_prbs31_enable_1_int;
wire qsfp1_cfg_tx_prbs31_enable_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int;
wire qsfp1_rx_prbs31_enable_1_int;
wire qsfp1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp1_rx_error_count_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int;
wire qsfp1_tx_prbs31_enable_2_int;
wire qsfp1_cfg_tx_prbs31_enable_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int;
wire qsfp1_rx_prbs31_enable_2_int;
wire qsfp1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp1_rx_error_count_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int;
wire qsfp1_tx_prbs31_enable_3_int;
wire qsfp1_cfg_tx_prbs31_enable_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int;
wire qsfp1_rx_prbs31_enable_3_int;
wire qsfp1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp1_rx_error_count_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int;
wire qsfp1_tx_prbs31_enable_4_int;
wire qsfp1_cfg_tx_prbs31_enable_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int;
wire qsfp1_rx_prbs31_enable_4_int;
wire qsfp1_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp1_rx_error_count_4_int;
wire qsfp1_drp_clk = clk_125mhz_int;
@ -1452,8 +1452,8 @@ qsfp1_phy_quad_inst (
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp1_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp1_tx_clk_2_int),
.phy_2_tx_rst(qsfp1_tx_rst_2_int),
@ -1470,8 +1470,8 @@ qsfp1_phy_quad_inst (
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp1_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp1_tx_clk_3_int),
.phy_3_tx_rst(qsfp1_tx_rst_3_int),
@ -1488,8 +1488,8 @@ qsfp1_phy_quad_inst (
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp1_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp1_tx_clk_4_int),
.phy_4_tx_rst(qsfp1_tx_rst_4_int),
@ -1506,8 +1506,8 @@ qsfp1_phy_quad_inst (
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp1_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_4_int)
);
wire ptp_clk;
@ -2332,48 +2332,48 @@ core_inst (
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_tx_prbs31_enable_1(qsfp0_tx_prbs31_enable_1_int),
.qsfp0_cfg_tx_prbs31_enable_1(qsfp0_cfg_tx_prbs31_enable_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
.qsfp0_cfg_rx_prbs31_enable_1(qsfp0_cfg_rx_prbs31_enable_1_int),
.qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
.qsfp0_rx_status_1(qsfp0_rx_status_1),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_tx_prbs31_enable_2(qsfp0_tx_prbs31_enable_2_int),
.qsfp0_cfg_tx_prbs31_enable_2(qsfp0_cfg_tx_prbs31_enable_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
.qsfp0_cfg_rx_prbs31_enable_2(qsfp0_cfg_rx_prbs31_enable_2_int),
.qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
.qsfp0_rx_status_2(qsfp0_rx_status_2),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_tx_prbs31_enable_3(qsfp0_tx_prbs31_enable_3_int),
.qsfp0_cfg_tx_prbs31_enable_3(qsfp0_cfg_tx_prbs31_enable_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
.qsfp0_cfg_rx_prbs31_enable_3(qsfp0_cfg_rx_prbs31_enable_3_int),
.qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
.qsfp0_rx_status_3(qsfp0_rx_status_3),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_tx_prbs31_enable_4(qsfp0_tx_prbs31_enable_4_int),
.qsfp0_cfg_tx_prbs31_enable_4(qsfp0_cfg_tx_prbs31_enable_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
.qsfp0_cfg_rx_prbs31_enable_4(qsfp0_cfg_rx_prbs31_enable_4_int),
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_status_4),
@ -2396,48 +2396,48 @@ core_inst (
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_tx_prbs31_enable_1(qsfp1_tx_prbs31_enable_1_int),
.qsfp1_cfg_tx_prbs31_enable_1(qsfp1_cfg_tx_prbs31_enable_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_cfg_rx_prbs31_enable_1(qsfp1_cfg_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_status_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_tx_prbs31_enable_2(qsfp1_tx_prbs31_enable_2_int),
.qsfp1_cfg_tx_prbs31_enable_2(qsfp1_cfg_tx_prbs31_enable_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_cfg_rx_prbs31_enable_2(qsfp1_cfg_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_status_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_tx_prbs31_enable_3(qsfp1_tx_prbs31_enable_3_int),
.qsfp1_cfg_tx_prbs31_enable_3(qsfp1_cfg_tx_prbs31_enable_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_cfg_rx_prbs31_enable_3(qsfp1_cfg_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_status_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_tx_prbs31_enable_4(qsfp1_tx_prbs31_enable_4_int),
.qsfp1_cfg_tx_prbs31_enable_4(qsfp1_cfg_tx_prbs31_enable_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_cfg_rx_prbs31_enable_4(qsfp1_cfg_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_status_4),

72
fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
View File

@ -281,48 +281,48 @@ module fpga_core #
input wire qsfp0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1,
output wire qsfp0_tx_prbs31_enable_1,
output wire qsfp0_cfg_tx_prbs31_enable_1,
input wire qsfp0_rx_clk_1,
input wire qsfp0_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1,
output wire qsfp0_rx_prbs31_enable_1,
output wire qsfp0_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp0_rx_error_count_1,
input wire qsfp0_rx_status_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2,
output wire qsfp0_tx_prbs31_enable_2,
output wire qsfp0_cfg_tx_prbs31_enable_2,
input wire qsfp0_rx_clk_2,
input wire qsfp0_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2,
output wire qsfp0_rx_prbs31_enable_2,
output wire qsfp0_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp0_rx_error_count_2,
input wire qsfp0_rx_status_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3,
output wire qsfp0_tx_prbs31_enable_3,
output wire qsfp0_cfg_tx_prbs31_enable_3,
input wire qsfp0_rx_clk_3,
input wire qsfp0_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3,
output wire qsfp0_rx_prbs31_enable_3,
output wire qsfp0_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp0_rx_error_count_3,
input wire qsfp0_rx_status_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4,
output wire qsfp0_tx_prbs31_enable_4,
output wire qsfp0_cfg_tx_prbs31_enable_4,
input wire qsfp0_rx_clk_4,
input wire qsfp0_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4,
output wire qsfp0_rx_prbs31_enable_4,
output wire qsfp0_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
@ -345,48 +345,48 @@ module fpga_core #
input wire qsfp1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1,
output wire qsfp1_tx_prbs31_enable_1,
output wire qsfp1_cfg_tx_prbs31_enable_1,
input wire qsfp1_rx_clk_1,
input wire qsfp1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
output wire qsfp1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2,
output wire qsfp1_tx_prbs31_enable_2,
output wire qsfp1_cfg_tx_prbs31_enable_2,
input wire qsfp1_rx_clk_2,
input wire qsfp1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
output wire qsfp1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3,
output wire qsfp1_tx_prbs31_enable_3,
output wire qsfp1_cfg_tx_prbs31_enable_3,
input wire qsfp1_rx_clk_3,
input wire qsfp1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
output wire qsfp1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4,
output wire qsfp1_tx_prbs31_enable_4,
output wire qsfp1_cfg_tx_prbs31_enable_4,
input wire qsfp1_rx_clk_4,
input wire qsfp1_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
output wire qsfp1_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
@ -910,8 +910,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}),
.phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
.phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}),
.phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}),
.phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}),
.phy_cfg_tx_prbs31_enable({qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1, qsfp0_cfg_tx_prbs31_enable_4, qsfp0_cfg_tx_prbs31_enable_3, qsfp0_cfg_tx_prbs31_enable_2, qsfp0_cfg_tx_prbs31_enable_1}),
.phy_cfg_rx_prbs31_enable({qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1, qsfp0_cfg_rx_prbs31_enable_4, qsfp0_cfg_rx_prbs31_enable_3, qsfp0_cfg_rx_prbs31_enable_2, qsfp0_cfg_rx_prbs31_enable_1}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -937,22 +937,22 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp0_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_rx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0;
end
@ -1108,7 +1108,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

96
fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
View File

@ -1088,45 +1088,45 @@ wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int;
wire qsfp0_tx_prbs31_enable_1_int;
wire qsfp0_cfg_tx_prbs31_enable_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int;
wire qsfp0_rx_prbs31_enable_1_int;
wire qsfp0_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp0_rx_error_count_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int;
wire qsfp0_tx_prbs31_enable_2_int;
wire qsfp0_cfg_tx_prbs31_enable_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int;
wire qsfp0_rx_prbs31_enable_2_int;
wire qsfp0_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp0_rx_error_count_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int;
wire qsfp0_tx_prbs31_enable_3_int;
wire qsfp0_cfg_tx_prbs31_enable_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int;
wire qsfp0_rx_prbs31_enable_3_int;
wire qsfp0_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp0_rx_error_count_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int;
wire qsfp0_tx_prbs31_enable_4_int;
wire qsfp0_cfg_tx_prbs31_enable_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int;
wire qsfp0_rx_prbs31_enable_4_int;
wire qsfp0_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp0_rx_error_count_4_int;
wire qsfp0_drp_clk = clk_125mhz_int;
@ -1238,8 +1238,8 @@ qsfp0_phy_quad_inst (
.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp0_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp0_tx_clk_2_int),
.phy_2_tx_rst(qsfp0_tx_rst_2_int),
@ -1256,8 +1256,8 @@ qsfp0_phy_quad_inst (
.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp0_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp0_tx_clk_3_int),
.phy_3_tx_rst(qsfp0_tx_rst_3_int),
@ -1274,8 +1274,8 @@ qsfp0_phy_quad_inst (
.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp0_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp0_tx_clk_4_int),
.phy_4_tx_rst(qsfp0_tx_rst_4_int),
@ -1292,8 +1292,8 @@ qsfp0_phy_quad_inst (
.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp0_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_4_int)
);
// QSFP1
@ -1304,45 +1304,45 @@ wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int;
wire qsfp1_tx_prbs31_enable_1_int;
wire qsfp1_cfg_tx_prbs31_enable_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int;
wire qsfp1_rx_prbs31_enable_1_int;
wire qsfp1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp1_rx_error_count_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int;
wire qsfp1_tx_prbs31_enable_2_int;
wire qsfp1_cfg_tx_prbs31_enable_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int;
wire qsfp1_rx_prbs31_enable_2_int;
wire qsfp1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp1_rx_error_count_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int;
wire qsfp1_tx_prbs31_enable_3_int;
wire qsfp1_cfg_tx_prbs31_enable_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int;
wire qsfp1_rx_prbs31_enable_3_int;
wire qsfp1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp1_rx_error_count_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int;
wire qsfp1_tx_prbs31_enable_4_int;
wire qsfp1_cfg_tx_prbs31_enable_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int;
wire qsfp1_rx_prbs31_enable_4_int;
wire qsfp1_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp1_rx_error_count_4_int;
wire qsfp1_drp_clk = clk_125mhz_int;
@ -1452,8 +1452,8 @@ qsfp1_phy_quad_inst (
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp1_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp1_tx_clk_2_int),
.phy_2_tx_rst(qsfp1_tx_rst_2_int),
@ -1470,8 +1470,8 @@ qsfp1_phy_quad_inst (
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp1_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp1_tx_clk_3_int),
.phy_3_tx_rst(qsfp1_tx_rst_3_int),
@ -1488,8 +1488,8 @@ qsfp1_phy_quad_inst (
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp1_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp1_tx_clk_4_int),
.phy_4_tx_rst(qsfp1_tx_rst_4_int),
@ -1506,8 +1506,8 @@ qsfp1_phy_quad_inst (
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp1_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_4_int)
);
wire ptp_clk;
@ -2332,48 +2332,48 @@ core_inst (
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_tx_prbs31_enable_1(qsfp0_tx_prbs31_enable_1_int),
.qsfp0_cfg_tx_prbs31_enable_1(qsfp0_cfg_tx_prbs31_enable_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
.qsfp0_cfg_rx_prbs31_enable_1(qsfp0_cfg_rx_prbs31_enable_1_int),
.qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
.qsfp0_rx_status_1(qsfp0_rx_status_1),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_tx_prbs31_enable_2(qsfp0_tx_prbs31_enable_2_int),
.qsfp0_cfg_tx_prbs31_enable_2(qsfp0_cfg_tx_prbs31_enable_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
.qsfp0_cfg_rx_prbs31_enable_2(qsfp0_cfg_rx_prbs31_enable_2_int),
.qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
.qsfp0_rx_status_2(qsfp0_rx_status_2),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_tx_prbs31_enable_3(qsfp0_tx_prbs31_enable_3_int),
.qsfp0_cfg_tx_prbs31_enable_3(qsfp0_cfg_tx_prbs31_enable_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
.qsfp0_cfg_rx_prbs31_enable_3(qsfp0_cfg_rx_prbs31_enable_3_int),
.qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
.qsfp0_rx_status_3(qsfp0_rx_status_3),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_tx_prbs31_enable_4(qsfp0_tx_prbs31_enable_4_int),
.qsfp0_cfg_tx_prbs31_enable_4(qsfp0_cfg_tx_prbs31_enable_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
.qsfp0_cfg_rx_prbs31_enable_4(qsfp0_cfg_rx_prbs31_enable_4_int),
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_status_4),
@ -2396,48 +2396,48 @@ core_inst (
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_tx_prbs31_enable_1(qsfp1_tx_prbs31_enable_1_int),
.qsfp1_cfg_tx_prbs31_enable_1(qsfp1_cfg_tx_prbs31_enable_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_cfg_rx_prbs31_enable_1(qsfp1_cfg_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_status_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_tx_prbs31_enable_2(qsfp1_tx_prbs31_enable_2_int),
.qsfp1_cfg_tx_prbs31_enable_2(qsfp1_cfg_tx_prbs31_enable_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_cfg_rx_prbs31_enable_2(qsfp1_cfg_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_status_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_tx_prbs31_enable_3(qsfp1_tx_prbs31_enable_3_int),
.qsfp1_cfg_tx_prbs31_enable_3(qsfp1_cfg_tx_prbs31_enable_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_cfg_rx_prbs31_enable_3(qsfp1_cfg_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_status_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_tx_prbs31_enable_4(qsfp1_tx_prbs31_enable_4_int),
.qsfp1_cfg_tx_prbs31_enable_4(qsfp1_cfg_tx_prbs31_enable_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_cfg_rx_prbs31_enable_4(qsfp1_cfg_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_status_4),

72
fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
View File

@ -281,48 +281,48 @@ module fpga_core #
input wire qsfp0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1,
output wire qsfp0_tx_prbs31_enable_1,
output wire qsfp0_cfg_tx_prbs31_enable_1,
input wire qsfp0_rx_clk_1,
input wire qsfp0_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1,
output wire qsfp0_rx_prbs31_enable_1,
output wire qsfp0_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp0_rx_error_count_1,
input wire qsfp0_rx_status_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2,
output wire qsfp0_tx_prbs31_enable_2,
output wire qsfp0_cfg_tx_prbs31_enable_2,
input wire qsfp0_rx_clk_2,
input wire qsfp0_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2,
output wire qsfp0_rx_prbs31_enable_2,
output wire qsfp0_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp0_rx_error_count_2,
input wire qsfp0_rx_status_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3,
output wire qsfp0_tx_prbs31_enable_3,
output wire qsfp0_cfg_tx_prbs31_enable_3,
input wire qsfp0_rx_clk_3,
input wire qsfp0_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3,
output wire qsfp0_rx_prbs31_enable_3,
output wire qsfp0_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp0_rx_error_count_3,
input wire qsfp0_rx_status_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4,
output wire qsfp0_tx_prbs31_enable_4,
output wire qsfp0_cfg_tx_prbs31_enable_4,
input wire qsfp0_rx_clk_4,
input wire qsfp0_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4,
output wire qsfp0_rx_prbs31_enable_4,
output wire qsfp0_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
@ -345,48 +345,48 @@ module fpga_core #
input wire qsfp1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1,
output wire qsfp1_tx_prbs31_enable_1,
output wire qsfp1_cfg_tx_prbs31_enable_1,
input wire qsfp1_rx_clk_1,
input wire qsfp1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
output wire qsfp1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2,
output wire qsfp1_tx_prbs31_enable_2,
output wire qsfp1_cfg_tx_prbs31_enable_2,
input wire qsfp1_rx_clk_2,
input wire qsfp1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
output wire qsfp1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3,
output wire qsfp1_tx_prbs31_enable_3,
output wire qsfp1_cfg_tx_prbs31_enable_3,
input wire qsfp1_rx_clk_3,
input wire qsfp1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
output wire qsfp1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4,
output wire qsfp1_tx_prbs31_enable_4,
output wire qsfp1_cfg_tx_prbs31_enable_4,
input wire qsfp1_rx_clk_4,
input wire qsfp1_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
output wire qsfp1_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
@ -910,8 +910,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}),
.phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
.phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}),
.phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}),
.phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}),
.phy_cfg_tx_prbs31_enable({qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1, qsfp0_cfg_tx_prbs31_enable_4, qsfp0_cfg_tx_prbs31_enable_3, qsfp0_cfg_tx_prbs31_enable_2, qsfp0_cfg_tx_prbs31_enable_1}),
.phy_cfg_rx_prbs31_enable({qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1, qsfp0_cfg_rx_prbs31_enable_4, qsfp0_cfg_rx_prbs31_enable_3, qsfp0_cfg_rx_prbs31_enable_2, qsfp0_cfg_rx_prbs31_enable_1}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -937,22 +937,22 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp0_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_rx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0;
end
@ -1108,7 +1108,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

96
fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
View File

@ -970,45 +970,45 @@ wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int;
wire qsfp0_tx_prbs31_enable_1_int;
wire qsfp0_cfg_tx_prbs31_enable_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int;
wire qsfp0_rx_prbs31_enable_1_int;
wire qsfp0_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp0_rx_error_count_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int;
wire qsfp0_tx_prbs31_enable_2_int;
wire qsfp0_cfg_tx_prbs31_enable_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int;
wire qsfp0_rx_prbs31_enable_2_int;
wire qsfp0_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp0_rx_error_count_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int;
wire qsfp0_tx_prbs31_enable_3_int;
wire qsfp0_cfg_tx_prbs31_enable_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int;
wire qsfp0_rx_prbs31_enable_3_int;
wire qsfp0_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp0_rx_error_count_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int;
wire qsfp0_tx_prbs31_enable_4_int;
wire qsfp0_cfg_tx_prbs31_enable_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int;
wire qsfp0_rx_prbs31_enable_4_int;
wire qsfp0_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp0_rx_error_count_4_int;
wire qsfp0_drp_clk = clk_125mhz_int;
@ -1120,8 +1120,8 @@ qsfp0_phy_quad_inst (
.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp0_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp0_tx_clk_2_int),
.phy_2_tx_rst(qsfp0_tx_rst_2_int),
@ -1138,8 +1138,8 @@ qsfp0_phy_quad_inst (
.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp0_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp0_tx_clk_3_int),
.phy_3_tx_rst(qsfp0_tx_rst_3_int),
@ -1156,8 +1156,8 @@ qsfp0_phy_quad_inst (
.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp0_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp0_tx_clk_4_int),
.phy_4_tx_rst(qsfp0_tx_rst_4_int),
@ -1174,8 +1174,8 @@ qsfp0_phy_quad_inst (
.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp0_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_4_int)
);
// QSFP1
@ -1186,45 +1186,45 @@ wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int;
wire qsfp1_tx_prbs31_enable_1_int;
wire qsfp1_cfg_tx_prbs31_enable_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int;
wire qsfp1_rx_prbs31_enable_1_int;
wire qsfp1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp1_rx_error_count_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int;
wire qsfp1_tx_prbs31_enable_2_int;
wire qsfp1_cfg_tx_prbs31_enable_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int;
wire qsfp1_rx_prbs31_enable_2_int;
wire qsfp1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp1_rx_error_count_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int;
wire qsfp1_tx_prbs31_enable_3_int;
wire qsfp1_cfg_tx_prbs31_enable_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int;
wire qsfp1_rx_prbs31_enable_3_int;
wire qsfp1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp1_rx_error_count_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int;
wire qsfp1_tx_prbs31_enable_4_int;
wire qsfp1_cfg_tx_prbs31_enable_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int;
wire qsfp1_rx_prbs31_enable_4_int;
wire qsfp1_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp1_rx_error_count_4_int;
wire qsfp1_drp_clk = clk_125mhz_int;
@ -1334,8 +1334,8 @@ qsfp1_phy_quad_inst (
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp1_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp1_tx_clk_2_int),
.phy_2_tx_rst(qsfp1_tx_rst_2_int),
@ -1352,8 +1352,8 @@ qsfp1_phy_quad_inst (
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp1_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp1_tx_clk_3_int),
.phy_3_tx_rst(qsfp1_tx_rst_3_int),
@ -1370,8 +1370,8 @@ qsfp1_phy_quad_inst (
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp1_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp1_tx_clk_4_int),
.phy_4_tx_rst(qsfp1_tx_rst_4_int),
@ -1388,8 +1388,8 @@ qsfp1_phy_quad_inst (
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp1_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_4_int)
);
wire ptp_clk;
@ -3458,48 +3458,48 @@ core_inst (
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_tx_prbs31_enable_1(qsfp0_tx_prbs31_enable_1_int),
.qsfp0_cfg_tx_prbs31_enable_1(qsfp0_cfg_tx_prbs31_enable_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
.qsfp0_cfg_rx_prbs31_enable_1(qsfp0_cfg_rx_prbs31_enable_1_int),
.qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
.qsfp0_rx_status_1(qsfp0_rx_status_1),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_tx_prbs31_enable_2(qsfp0_tx_prbs31_enable_2_int),
.qsfp0_cfg_tx_prbs31_enable_2(qsfp0_cfg_tx_prbs31_enable_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
.qsfp0_cfg_rx_prbs31_enable_2(qsfp0_cfg_rx_prbs31_enable_2_int),
.qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
.qsfp0_rx_status_2(qsfp0_rx_status_2),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_tx_prbs31_enable_3(qsfp0_tx_prbs31_enable_3_int),
.qsfp0_cfg_tx_prbs31_enable_3(qsfp0_cfg_tx_prbs31_enable_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
.qsfp0_cfg_rx_prbs31_enable_3(qsfp0_cfg_rx_prbs31_enable_3_int),
.qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
.qsfp0_rx_status_3(qsfp0_rx_status_3),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_tx_prbs31_enable_4(qsfp0_tx_prbs31_enable_4_int),
.qsfp0_cfg_tx_prbs31_enable_4(qsfp0_cfg_tx_prbs31_enable_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
.qsfp0_cfg_rx_prbs31_enable_4(qsfp0_cfg_rx_prbs31_enable_4_int),
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_status_4),
@ -3516,48 +3516,48 @@ core_inst (
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_tx_prbs31_enable_1(qsfp1_tx_prbs31_enable_1_int),
.qsfp1_cfg_tx_prbs31_enable_1(qsfp1_cfg_tx_prbs31_enable_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_cfg_rx_prbs31_enable_1(qsfp1_cfg_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_status_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_tx_prbs31_enable_2(qsfp1_tx_prbs31_enable_2_int),
.qsfp1_cfg_tx_prbs31_enable_2(qsfp1_cfg_tx_prbs31_enable_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_cfg_rx_prbs31_enable_2(qsfp1_cfg_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_status_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_tx_prbs31_enable_3(qsfp1_tx_prbs31_enable_3_int),
.qsfp1_cfg_tx_prbs31_enable_3(qsfp1_cfg_tx_prbs31_enable_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_cfg_rx_prbs31_enable_3(qsfp1_cfg_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_status_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_tx_prbs31_enable_4(qsfp1_tx_prbs31_enable_4_int),
.qsfp1_cfg_tx_prbs31_enable_4(qsfp1_cfg_tx_prbs31_enable_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_cfg_rx_prbs31_enable_4(qsfp1_cfg_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_status_4),

72
fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -273,48 +273,48 @@ module fpga_core #
input wire qsfp0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1,
output wire qsfp0_tx_prbs31_enable_1,
output wire qsfp0_cfg_tx_prbs31_enable_1,
input wire qsfp0_rx_clk_1,
input wire qsfp0_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1,
output wire qsfp0_rx_prbs31_enable_1,
output wire qsfp0_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp0_rx_error_count_1,
input wire qsfp0_rx_status_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2,
output wire qsfp0_tx_prbs31_enable_2,
output wire qsfp0_cfg_tx_prbs31_enable_2,
input wire qsfp0_rx_clk_2,
input wire qsfp0_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2,
output wire qsfp0_rx_prbs31_enable_2,
output wire qsfp0_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp0_rx_error_count_2,
input wire qsfp0_rx_status_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3,
output wire qsfp0_tx_prbs31_enable_3,
output wire qsfp0_cfg_tx_prbs31_enable_3,
input wire qsfp0_rx_clk_3,
input wire qsfp0_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3,
output wire qsfp0_rx_prbs31_enable_3,
output wire qsfp0_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp0_rx_error_count_3,
input wire qsfp0_rx_status_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4,
output wire qsfp0_tx_prbs31_enable_4,
output wire qsfp0_cfg_tx_prbs31_enable_4,
input wire qsfp0_rx_clk_4,
input wire qsfp0_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4,
output wire qsfp0_rx_prbs31_enable_4,
output wire qsfp0_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
@ -331,48 +331,48 @@ module fpga_core #
input wire qsfp1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1,
output wire qsfp1_tx_prbs31_enable_1,
output wire qsfp1_cfg_tx_prbs31_enable_1,
input wire qsfp1_rx_clk_1,
input wire qsfp1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
output wire qsfp1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2,
output wire qsfp1_tx_prbs31_enable_2,
output wire qsfp1_cfg_tx_prbs31_enable_2,
input wire qsfp1_rx_clk_2,
input wire qsfp1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
output wire qsfp1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3,
output wire qsfp1_tx_prbs31_enable_3,
output wire qsfp1_cfg_tx_prbs31_enable_3,
input wire qsfp1_rx_clk_3,
input wire qsfp1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
output wire qsfp1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4,
output wire qsfp1_tx_prbs31_enable_4,
output wire qsfp1_cfg_tx_prbs31_enable_4,
input wire qsfp1_rx_clk_4,
input wire qsfp1_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
output wire qsfp1_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
@ -856,8 +856,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}),
.phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
.phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}),
.phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}),
.phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}),
.phy_cfg_tx_prbs31_enable({qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1, qsfp0_cfg_tx_prbs31_enable_4, qsfp0_cfg_tx_prbs31_enable_3, qsfp0_cfg_tx_prbs31_enable_2, qsfp0_cfg_tx_prbs31_enable_1}),
.phy_cfg_rx_prbs31_enable({qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1, qsfp0_cfg_rx_prbs31_enable_4, qsfp0_cfg_rx_prbs31_enable_3, qsfp0_cfg_rx_prbs31_enable_2, qsfp0_cfg_rx_prbs31_enable_1}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -883,22 +883,22 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp0_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_rx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0;
end
@ -1051,7 +1051,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

48
fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
View File

@ -915,45 +915,45 @@ wire qsfp_tx_clk_1_int;
wire qsfp_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_1_int;
wire qsfp_tx_prbs31_enable_1_int;
wire qsfp_cfg_tx_prbs31_enable_1_int;
wire qsfp_rx_clk_1_int;
wire qsfp_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_1_int;
wire qsfp_rx_prbs31_enable_1_int;
wire qsfp_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp_rx_error_count_1_int;
wire qsfp_tx_clk_2_int;
wire qsfp_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_2_int;
wire qsfp_tx_prbs31_enable_2_int;
wire qsfp_cfg_tx_prbs31_enable_2_int;
wire qsfp_rx_clk_2_int;
wire qsfp_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_2_int;
wire qsfp_rx_prbs31_enable_2_int;
wire qsfp_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp_rx_error_count_2_int;
wire qsfp_tx_clk_3_int;
wire qsfp_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_3_int;
wire qsfp_tx_prbs31_enable_3_int;
wire qsfp_cfg_tx_prbs31_enable_3_int;
wire qsfp_rx_clk_3_int;
wire qsfp_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_3_int;
wire qsfp_rx_prbs31_enable_3_int;
wire qsfp_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp_rx_error_count_3_int;
wire qsfp_tx_clk_4_int;
wire qsfp_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_4_int;
wire qsfp_tx_prbs31_enable_4_int;
wire qsfp_cfg_tx_prbs31_enable_4_int;
wire qsfp_rx_clk_4_int;
wire qsfp_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_4_int;
wire qsfp_rx_prbs31_enable_4_int;
wire qsfp_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp_rx_error_count_4_int;
wire qsfp_drp_clk = clk_125mhz_int;
@ -1065,8 +1065,8 @@ qsfp_phy_quad_inst (
.phy_1_rx_block_lock(qsfp_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp_tx_clk_2_int),
.phy_2_tx_rst(qsfp_tx_rst_2_int),
@ -1083,8 +1083,8 @@ qsfp_phy_quad_inst (
.phy_2_rx_block_lock(qsfp_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp_tx_clk_3_int),
.phy_3_tx_rst(qsfp_tx_rst_3_int),
@ -1101,8 +1101,8 @@ qsfp_phy_quad_inst (
.phy_3_rx_block_lock(qsfp_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp_tx_clk_4_int),
.phy_4_tx_rst(qsfp_tx_rst_4_int),
@ -1119,8 +1119,8 @@ qsfp_phy_quad_inst (
.phy_4_rx_block_lock(qsfp_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable_4_int)
);
wire ptp_clk;
@ -2865,48 +2865,48 @@ core_inst (
.qsfp_tx_rst_1(qsfp_tx_rst_1_int),
.qsfp_txd_1(qsfp_txd_1_int),
.qsfp_txc_1(qsfp_txc_1_int),
.qsfp_tx_prbs31_enable_1(qsfp_tx_prbs31_enable_1_int),
.qsfp_cfg_tx_prbs31_enable_1(qsfp_cfg_tx_prbs31_enable_1_int),
.qsfp_rx_clk_1(qsfp_rx_clk_1_int),
.qsfp_rx_rst_1(qsfp_rx_rst_1_int),
.qsfp_rxd_1(qsfp_rxd_1_int),
.qsfp_rxc_1(qsfp_rxc_1_int),
.qsfp_rx_prbs31_enable_1(qsfp_rx_prbs31_enable_1_int),
.qsfp_cfg_rx_prbs31_enable_1(qsfp_cfg_rx_prbs31_enable_1_int),
.qsfp_rx_error_count_1(qsfp_rx_error_count_1_int),
.qsfp_rx_status_1(qsfp_rx_status_1),
.qsfp_tx_clk_2(qsfp_tx_clk_2_int),
.qsfp_tx_rst_2(qsfp_tx_rst_2_int),
.qsfp_txd_2(qsfp_txd_2_int),
.qsfp_txc_2(qsfp_txc_2_int),
.qsfp_tx_prbs31_enable_2(qsfp_tx_prbs31_enable_2_int),
.qsfp_cfg_tx_prbs31_enable_2(qsfp_cfg_tx_prbs31_enable_2_int),
.qsfp_rx_clk_2(qsfp_rx_clk_2_int),
.qsfp_rx_rst_2(qsfp_rx_rst_2_int),
.qsfp_rxd_2(qsfp_rxd_2_int),
.qsfp_rxc_2(qsfp_rxc_2_int),
.qsfp_rx_prbs31_enable_2(qsfp_rx_prbs31_enable_2_int),
.qsfp_cfg_rx_prbs31_enable_2(qsfp_cfg_rx_prbs31_enable_2_int),
.qsfp_rx_error_count_2(qsfp_rx_error_count_2_int),
.qsfp_rx_status_2(qsfp_rx_status_2),
.qsfp_tx_clk_3(qsfp_tx_clk_3_int),
.qsfp_tx_rst_3(qsfp_tx_rst_3_int),
.qsfp_txd_3(qsfp_txd_3_int),
.qsfp_txc_3(qsfp_txc_3_int),
.qsfp_tx_prbs31_enable_3(qsfp_tx_prbs31_enable_3_int),
.qsfp_cfg_tx_prbs31_enable_3(qsfp_cfg_tx_prbs31_enable_3_int),
.qsfp_rx_clk_3(qsfp_rx_clk_3_int),
.qsfp_rx_rst_3(qsfp_rx_rst_3_int),
.qsfp_rxd_3(qsfp_rxd_3_int),
.qsfp_rxc_3(qsfp_rxc_3_int),
.qsfp_rx_prbs31_enable_3(qsfp_rx_prbs31_enable_3_int),
.qsfp_cfg_rx_prbs31_enable_3(qsfp_cfg_rx_prbs31_enable_3_int),
.qsfp_rx_error_count_3(qsfp_rx_error_count_3_int),
.qsfp_rx_status_3(qsfp_rx_status_3),
.qsfp_tx_clk_4(qsfp_tx_clk_4_int),
.qsfp_tx_rst_4(qsfp_tx_rst_4_int),
.qsfp_txd_4(qsfp_txd_4_int),
.qsfp_txc_4(qsfp_txc_4_int),
.qsfp_tx_prbs31_enable_4(qsfp_tx_prbs31_enable_4_int),
.qsfp_cfg_tx_prbs31_enable_4(qsfp_cfg_tx_prbs31_enable_4_int),
.qsfp_rx_clk_4(qsfp_rx_clk_4_int),
.qsfp_rx_rst_4(qsfp_rx_rst_4_int),
.qsfp_rxd_4(qsfp_rxd_4_int),
.qsfp_rxc_4(qsfp_rxc_4_int),
.qsfp_rx_prbs31_enable_4(qsfp_rx_prbs31_enable_4_int),
.qsfp_cfg_rx_prbs31_enable_4(qsfp_cfg_rx_prbs31_enable_4_int),
.qsfp_rx_error_count_4(qsfp_rx_error_count_4_int),
.qsfp_rx_status_4(qsfp_rx_status_4),

40
fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
View File

@ -272,48 +272,48 @@ module fpga_core #
input wire qsfp_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_1,
output wire qsfp_tx_prbs31_enable_1,
output wire qsfp_cfg_tx_prbs31_enable_1,
input wire qsfp_rx_clk_1,
input wire qsfp_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_1,
output wire qsfp_rx_prbs31_enable_1,
output wire qsfp_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp_rx_error_count_1,
input wire qsfp_rx_status_1,
input wire qsfp_tx_clk_2,
input wire qsfp_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_2,
output wire qsfp_tx_prbs31_enable_2,
output wire qsfp_cfg_tx_prbs31_enable_2,
input wire qsfp_rx_clk_2,
input wire qsfp_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_2,
output wire qsfp_rx_prbs31_enable_2,
output wire qsfp_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp_rx_error_count_2,
input wire qsfp_rx_status_2,
input wire qsfp_tx_clk_3,
input wire qsfp_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_3,
output wire qsfp_tx_prbs31_enable_3,
output wire qsfp_cfg_tx_prbs31_enable_3,
input wire qsfp_rx_clk_3,
input wire qsfp_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_3,
output wire qsfp_rx_prbs31_enable_3,
output wire qsfp_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp_rx_error_count_3,
input wire qsfp_rx_status_3,
input wire qsfp_tx_clk_4,
input wire qsfp_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_4,
output wire qsfp_tx_prbs31_enable_4,
output wire qsfp_cfg_tx_prbs31_enable_4,
input wire qsfp_rx_clk_4,
input wire qsfp_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_4,
output wire qsfp_rx_prbs31_enable_4,
output wire qsfp_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp_rx_error_count_4,
input wire qsfp_rx_status_4,
@ -702,8 +702,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp_tx_clk_4, qsfp_tx_clk_3, qsfp_tx_clk_2, qsfp_tx_clk_1}),
.phy_rx_clk({qsfp_rx_clk_4, qsfp_rx_clk_3, qsfp_rx_clk_2, qsfp_rx_clk_1}),
.phy_rx_error_count({qsfp_rx_error_count_4, qsfp_rx_error_count_3, qsfp_rx_error_count_2, qsfp_rx_error_count_1}),
.phy_tx_prbs31_enable({qsfp_tx_prbs31_enable_4, qsfp_tx_prbs31_enable_3, qsfp_tx_prbs31_enable_2, qsfp_tx_prbs31_enable_1}),
.phy_rx_prbs31_enable({qsfp_rx_prbs31_enable_4, qsfp_rx_prbs31_enable_3, qsfp_rx_prbs31_enable_2, qsfp_rx_prbs31_enable_1}),
.phy_cfg_tx_prbs31_enable({qsfp_cfg_tx_prbs31_enable_4, qsfp_cfg_tx_prbs31_enable_3, qsfp_cfg_tx_prbs31_enable_2, qsfp_cfg_tx_prbs31_enable_1}),
.phy_cfg_rx_prbs31_enable({qsfp_cfg_rx_prbs31_enable_4, qsfp_cfg_rx_prbs31_enable_3, qsfp_cfg_rx_prbs31_enable_2, qsfp_cfg_rx_prbs31_enable_1}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -729,14 +729,14 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp_tx_prbs31_enable_1 = 1'b0;
assign qsfp_rx_prbs31_enable_1 = 1'b0;
assign qsfp_tx_prbs31_enable_2 = 1'b0;
assign qsfp_rx_prbs31_enable_2 = 1'b0;
assign qsfp_tx_prbs31_enable_3 = 1'b0;
assign qsfp_rx_prbs31_enable_3 = 1'b0;
assign qsfp_tx_prbs31_enable_4 = 1'b0;
assign qsfp_rx_prbs31_enable_4 = 1'b0;
assign qsfp_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp_cfg_rx_prbs31_enable_4 = 1'b0;
end
@ -893,7 +893,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

32
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v
View File

@ -60,8 +60,8 @@ module eth_xcvr_phy_quad_wrapper #
output wire phy_1_rx_block_lock,
output wire phy_1_rx_high_ber,
output wire phy_1_rx_status,
input wire phy_1_tx_prbs31_enable,
input wire phy_1_rx_prbs31_enable,
input wire phy_1_cfg_tx_prbs31_enable,
input wire phy_1_cfg_rx_prbs31_enable,
output wire phy_2_tx_clk,
output wire phy_2_tx_rst,
@ -78,8 +78,8 @@ module eth_xcvr_phy_quad_wrapper #
output wire phy_2_rx_block_lock,
output wire phy_2_rx_high_ber,
output wire phy_2_rx_status,
input wire phy_2_tx_prbs31_enable,
input wire phy_2_rx_prbs31_enable,
input wire phy_2_cfg_tx_prbs31_enable,
input wire phy_2_cfg_rx_prbs31_enable,
output wire phy_3_tx_clk,
output wire phy_3_tx_rst,
@ -96,8 +96,8 @@ module eth_xcvr_phy_quad_wrapper #
output wire phy_3_rx_block_lock,
output wire phy_3_rx_high_ber,
output wire phy_3_rx_status,
input wire phy_3_tx_prbs31_enable,
input wire phy_3_rx_prbs31_enable,
input wire phy_3_cfg_tx_prbs31_enable,
input wire phy_3_cfg_rx_prbs31_enable,
output wire phy_4_tx_clk,
output wire phy_4_tx_rst,
@ -114,8 +114,8 @@ module eth_xcvr_phy_quad_wrapper #
output wire phy_4_rx_block_lock,
output wire phy_4_rx_high_ber,
output wire phy_4_rx_status,
input wire phy_4_tx_prbs31_enable,
input wire phy_4_rx_prbs31_enable
input wire phy_4_cfg_tx_prbs31_enable,
input wire phy_4_cfg_rx_prbs31_enable
);
wire xcvr_gx_pll_locked;
@ -208,8 +208,8 @@ eth_xcvr_phy_1 (
.phy_rx_block_lock(phy_1_rx_block_lock),
.phy_rx_high_ber(phy_1_rx_high_ber),
.phy_rx_status(phy_1_rx_status),
.phy_tx_prbs31_enable(phy_1_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_1_rx_prbs31_enable)
.phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable)
);
eth_xcvr_phy_wrapper #(
@ -255,8 +255,8 @@ eth_xcvr_phy_2 (
.phy_rx_block_lock(phy_2_rx_block_lock),
.phy_rx_high_ber(phy_2_rx_high_ber),
.phy_rx_status(phy_2_rx_status),
.phy_tx_prbs31_enable(phy_2_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_2_rx_prbs31_enable)
.phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable)
);
eth_xcvr_phy_wrapper #(
@ -302,8 +302,8 @@ eth_xcvr_phy_3 (
.phy_rx_block_lock(phy_3_rx_block_lock),
.phy_rx_high_ber(phy_3_rx_high_ber),
.phy_rx_status(phy_3_rx_status),
.phy_tx_prbs31_enable(phy_3_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_3_rx_prbs31_enable)
.phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable)
);
eth_xcvr_phy_wrapper #(
@ -349,8 +349,8 @@ eth_xcvr_phy_4 (
.phy_rx_block_lock(phy_4_rx_block_lock),
.phy_rx_high_ber(phy_4_rx_high_ber),
.phy_rx_status(phy_4_rx_status),
.phy_tx_prbs31_enable(phy_4_tx_prbs31_enable),
.phy_rx_prbs31_enable(phy_4_rx_prbs31_enable)
.phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable),
.phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable)
);
endmodule

8
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
View File

@ -62,8 +62,8 @@ module eth_xcvr_phy_wrapper #
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
output wire phy_rx_status,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
input wire phy_cfg_tx_prbs31_enable,
input wire phy_cfg_rx_prbs31_enable
);
wire xcvr_tx_analogreset;
@ -293,8 +293,8 @@ phy_inst (
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.rx_status(phy_rx_status),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
);
endmodule

96
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga.v
View File

@ -636,45 +636,45 @@ wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int;
wire qsfp0_tx_prbs31_enable_1_int;
wire qsfp0_cfg_tx_prbs31_enable_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int;
wire qsfp0_rx_prbs31_enable_1_int;
wire qsfp0_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp0_rx_error_count_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int;
wire qsfp0_tx_prbs31_enable_2_int;
wire qsfp0_cfg_tx_prbs31_enable_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int;
wire qsfp0_rx_prbs31_enable_2_int;
wire qsfp0_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp0_rx_error_count_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int;
wire qsfp0_tx_prbs31_enable_3_int;
wire qsfp0_cfg_tx_prbs31_enable_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int;
wire qsfp0_rx_prbs31_enable_3_int;
wire qsfp0_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp0_rx_error_count_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int;
wire qsfp0_tx_prbs31_enable_4_int;
wire qsfp0_cfg_tx_prbs31_enable_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int;
wire qsfp0_rx_prbs31_enable_4_int;
wire qsfp0_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp0_rx_error_count_4_int;
wire qsfp0_rx_block_lock_1;
@ -720,8 +720,8 @@ qsfp0_eth_xcvr_phy_quad (
.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp0_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp0_tx_clk_2_int),
.phy_2_tx_rst(qsfp0_tx_rst_2_int),
@ -738,8 +738,8 @@ qsfp0_eth_xcvr_phy_quad (
.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp0_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp0_tx_clk_3_int),
.phy_3_tx_rst(qsfp0_tx_rst_3_int),
@ -756,8 +756,8 @@ qsfp0_eth_xcvr_phy_quad (
.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp0_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp0_tx_clk_4_int),
.phy_4_tx_rst(qsfp0_tx_rst_4_int),
@ -774,8 +774,8 @@ qsfp0_eth_xcvr_phy_quad (
.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp0_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_4_int)
);
// QSFP1
@ -783,45 +783,45 @@ wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int;
wire qsfp1_tx_prbs31_enable_1_int;
wire qsfp1_cfg_tx_prbs31_enable_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int;
wire qsfp1_rx_prbs31_enable_1_int;
wire qsfp1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp1_rx_error_count_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int;
wire qsfp1_tx_prbs31_enable_2_int;
wire qsfp1_cfg_tx_prbs31_enable_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int;
wire qsfp1_rx_prbs31_enable_2_int;
wire qsfp1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp1_rx_error_count_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int;
wire qsfp1_tx_prbs31_enable_3_int;
wire qsfp1_cfg_tx_prbs31_enable_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int;
wire qsfp1_rx_prbs31_enable_3_int;
wire qsfp1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp1_rx_error_count_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int;
wire qsfp1_tx_prbs31_enable_4_int;
wire qsfp1_cfg_tx_prbs31_enable_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int;
wire qsfp1_rx_prbs31_enable_4_int;
wire qsfp1_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp1_rx_error_count_4_int;
wire qsfp1_rx_block_lock_1;
@ -867,8 +867,8 @@ qsfp1_eth_xcvr_phy_quad (
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp1_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp1_tx_clk_2_int),
.phy_2_tx_rst(qsfp1_tx_rst_2_int),
@ -885,8 +885,8 @@ qsfp1_eth_xcvr_phy_quad (
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp1_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp1_tx_clk_3_int),
.phy_3_tx_rst(qsfp1_tx_rst_3_int),
@ -903,8 +903,8 @@ qsfp1_eth_xcvr_phy_quad (
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp1_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp1_tx_clk_4_int),
.phy_4_tx_rst(qsfp1_tx_rst_4_int),
@ -921,8 +921,8 @@ qsfp1_eth_xcvr_phy_quad (
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp1_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_4_int)
);
wire ptp_clk;
@ -1144,48 +1144,48 @@ core_inst (
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_tx_prbs31_enable_1(qsfp0_tx_prbs31_enable_1_int),
.qsfp0_cfg_tx_prbs31_enable_1(qsfp0_cfg_tx_prbs31_enable_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
.qsfp0_cfg_rx_prbs31_enable_1(qsfp0_cfg_rx_prbs31_enable_1_int),
.qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
.qsfp0_rx_status_1(qsfp0_rx_status_1),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_tx_prbs31_enable_2(qsfp0_tx_prbs31_enable_2_int),
.qsfp0_cfg_tx_prbs31_enable_2(qsfp0_cfg_tx_prbs31_enable_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
.qsfp0_cfg_rx_prbs31_enable_2(qsfp0_cfg_rx_prbs31_enable_2_int),
.qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
.qsfp0_rx_status_2(qsfp0_rx_status_2),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_tx_prbs31_enable_3(qsfp0_tx_prbs31_enable_3_int),
.qsfp0_cfg_tx_prbs31_enable_3(qsfp0_cfg_tx_prbs31_enable_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
.qsfp0_cfg_rx_prbs31_enable_3(qsfp0_cfg_rx_prbs31_enable_3_int),
.qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
.qsfp0_rx_status_3(qsfp0_rx_status_3),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_tx_prbs31_enable_4(qsfp0_tx_prbs31_enable_4_int),
.qsfp0_cfg_tx_prbs31_enable_4(qsfp0_cfg_tx_prbs31_enable_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
.qsfp0_cfg_rx_prbs31_enable_4(qsfp0_cfg_rx_prbs31_enable_4_int),
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_status_4),
@ -1199,48 +1199,48 @@ core_inst (
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_tx_prbs31_enable_1(qsfp1_tx_prbs31_enable_1_int),
.qsfp1_cfg_tx_prbs31_enable_1(qsfp1_cfg_tx_prbs31_enable_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_cfg_rx_prbs31_enable_1(qsfp1_cfg_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_status_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_tx_prbs31_enable_2(qsfp1_tx_prbs31_enable_2_int),
.qsfp1_cfg_tx_prbs31_enable_2(qsfp1_cfg_tx_prbs31_enable_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_cfg_rx_prbs31_enable_2(qsfp1_cfg_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_status_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_tx_prbs31_enable_3(qsfp1_tx_prbs31_enable_3_int),
.qsfp1_cfg_tx_prbs31_enable_3(qsfp1_cfg_tx_prbs31_enable_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_cfg_rx_prbs31_enable_3(qsfp1_cfg_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_status_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_tx_prbs31_enable_4(qsfp1_tx_prbs31_enable_4_int),
.qsfp1_cfg_tx_prbs31_enable_4(qsfp1_cfg_tx_prbs31_enable_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_cfg_rx_prbs31_enable_4(qsfp1_cfg_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_status_4),

72
fpga/mqnic/DK_DEV_1SMX_H_A/fpga_25g/rtl/fpga_core.v
View File

@ -213,48 +213,48 @@ module fpga_core #
input wire qsfp0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1,
output wire qsfp0_tx_prbs31_enable_1,
output wire qsfp0_cfg_tx_prbs31_enable_1,
input wire qsfp0_rx_clk_1,
input wire qsfp0_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1,
output wire qsfp0_rx_prbs31_enable_1,
output wire qsfp0_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp0_rx_error_count_1,
input wire qsfp0_rx_status_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2,
output wire qsfp0_tx_prbs31_enable_2,
output wire qsfp0_cfg_tx_prbs31_enable_2,
input wire qsfp0_rx_clk_2,
input wire qsfp0_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2,
output wire qsfp0_rx_prbs31_enable_2,
output wire qsfp0_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp0_rx_error_count_2,
input wire qsfp0_rx_status_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3,
output wire qsfp0_tx_prbs31_enable_3,
output wire qsfp0_cfg_tx_prbs31_enable_3,
input wire qsfp0_rx_clk_3,
input wire qsfp0_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3,
output wire qsfp0_rx_prbs31_enable_3,
output wire qsfp0_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp0_rx_error_count_3,
input wire qsfp0_rx_status_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4,
output wire qsfp0_tx_prbs31_enable_4,
output wire qsfp0_cfg_tx_prbs31_enable_4,
input wire qsfp0_rx_clk_4,
input wire qsfp0_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4,
output wire qsfp0_rx_prbs31_enable_4,
output wire qsfp0_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
@ -268,48 +268,48 @@ module fpga_core #
input wire qsfp1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1,
output wire qsfp1_tx_prbs31_enable_1,
output wire qsfp1_cfg_tx_prbs31_enable_1,
input wire qsfp1_rx_clk_1,
input wire qsfp1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
output wire qsfp1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2,
output wire qsfp1_tx_prbs31_enable_2,
output wire qsfp1_cfg_tx_prbs31_enable_2,
input wire qsfp1_rx_clk_2,
input wire qsfp1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
output wire qsfp1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3,
output wire qsfp1_tx_prbs31_enable_3,
output wire qsfp1_cfg_tx_prbs31_enable_3,
input wire qsfp1_rx_clk_3,
input wire qsfp1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
output wire qsfp1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4,
output wire qsfp1_tx_prbs31_enable_4,
output wire qsfp1_cfg_tx_prbs31_enable_4,
input wire qsfp1_rx_clk_4,
input wire qsfp1_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
output wire qsfp1_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
@ -571,8 +571,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}),
.phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
.phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}),
.phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}),
.phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}),
.phy_cfg_tx_prbs31_enable({qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1, qsfp0_cfg_tx_prbs31_enable_4, qsfp0_cfg_tx_prbs31_enable_3, qsfp0_cfg_tx_prbs31_enable_2, qsfp0_cfg_tx_prbs31_enable_1}),
.phy_cfg_rx_prbs31_enable({qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1, qsfp0_cfg_rx_prbs31_enable_4, qsfp0_cfg_rx_prbs31_enable_3, qsfp0_cfg_rx_prbs31_enable_2, qsfp0_cfg_rx_prbs31_enable_1}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -598,22 +598,22 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp0_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_rx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0;
end
@ -771,7 +771,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

96
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
View File

@ -884,45 +884,45 @@ wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int;
wire qsfp0_tx_prbs31_enable_1_int;
wire qsfp0_cfg_tx_prbs31_enable_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int;
wire qsfp0_rx_prbs31_enable_1_int;
wire qsfp0_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp0_rx_error_count_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int;
wire qsfp0_tx_prbs31_enable_2_int;
wire qsfp0_cfg_tx_prbs31_enable_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int;
wire qsfp0_rx_prbs31_enable_2_int;
wire qsfp0_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp0_rx_error_count_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int;
wire qsfp0_tx_prbs31_enable_3_int;
wire qsfp0_cfg_tx_prbs31_enable_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int;
wire qsfp0_rx_prbs31_enable_3_int;
wire qsfp0_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp0_rx_error_count_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int;
wire qsfp0_tx_prbs31_enable_4_int;
wire qsfp0_cfg_tx_prbs31_enable_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int;
wire qsfp0_rx_prbs31_enable_4_int;
wire qsfp0_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp0_rx_error_count_4_int;
wire qsfp0_drp_clk = clk_125mhz_int;
@ -1035,8 +1035,8 @@ qsfp0_phy_quad_inst (
.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp0_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp0_tx_clk_2_int),
.phy_2_tx_rst(qsfp0_tx_rst_2_int),
@ -1053,8 +1053,8 @@ qsfp0_phy_quad_inst (
.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp0_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp0_tx_clk_3_int),
.phy_3_tx_rst(qsfp0_tx_rst_3_int),
@ -1071,8 +1071,8 @@ qsfp0_phy_quad_inst (
.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp0_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp0_tx_clk_4_int),
.phy_4_tx_rst(qsfp0_tx_rst_4_int),
@ -1089,8 +1089,8 @@ qsfp0_phy_quad_inst (
.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp0_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_4_int)
);
// QSFP1
@ -1100,45 +1100,45 @@ wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int;
wire qsfp1_tx_prbs31_enable_1_int;
wire qsfp1_cfg_tx_prbs31_enable_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int;
wire qsfp1_rx_prbs31_enable_1_int;
wire qsfp1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp1_rx_error_count_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int;
wire qsfp1_tx_prbs31_enable_2_int;
wire qsfp1_cfg_tx_prbs31_enable_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int;
wire qsfp1_rx_prbs31_enable_2_int;
wire qsfp1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp1_rx_error_count_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int;
wire qsfp1_tx_prbs31_enable_3_int;
wire qsfp1_cfg_tx_prbs31_enable_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int;
wire qsfp1_rx_prbs31_enable_3_int;
wire qsfp1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp1_rx_error_count_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int;
wire qsfp1_tx_prbs31_enable_4_int;
wire qsfp1_cfg_tx_prbs31_enable_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int;
wire qsfp1_rx_prbs31_enable_4_int;
wire qsfp1_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp1_rx_error_count_4_int;
wire qsfp1_drp_clk = clk_125mhz_int;
@ -1249,8 +1249,8 @@ qsfp1_phy_quad_inst (
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp1_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp1_tx_clk_2_int),
.phy_2_tx_rst(qsfp1_tx_rst_2_int),
@ -1267,8 +1267,8 @@ qsfp1_phy_quad_inst (
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp1_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp1_tx_clk_3_int),
.phy_3_tx_rst(qsfp1_tx_rst_3_int),
@ -1285,8 +1285,8 @@ qsfp1_phy_quad_inst (
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp1_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp1_tx_clk_4_int),
.phy_4_tx_rst(qsfp1_tx_rst_4_int),
@ -1303,8 +1303,8 @@ qsfp1_phy_quad_inst (
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp1_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_4_int)
);
wire ptp_clk;
@ -1762,48 +1762,48 @@ core_inst (
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_tx_prbs31_enable_1(qsfp0_tx_prbs31_enable_1_int),
.qsfp0_cfg_tx_prbs31_enable_1(qsfp0_cfg_tx_prbs31_enable_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
.qsfp0_cfg_rx_prbs31_enable_1(qsfp0_cfg_rx_prbs31_enable_1_int),
.qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
.qsfp0_rx_status_1(qsfp0_rx_status_1),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_tx_prbs31_enable_2(qsfp0_tx_prbs31_enable_2_int),
.qsfp0_cfg_tx_prbs31_enable_2(qsfp0_cfg_tx_prbs31_enable_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
.qsfp0_cfg_rx_prbs31_enable_2(qsfp0_cfg_rx_prbs31_enable_2_int),
.qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
.qsfp0_rx_status_2(qsfp0_rx_status_2),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_tx_prbs31_enable_3(qsfp0_tx_prbs31_enable_3_int),
.qsfp0_cfg_tx_prbs31_enable_3(qsfp0_cfg_tx_prbs31_enable_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
.qsfp0_cfg_rx_prbs31_enable_3(qsfp0_cfg_rx_prbs31_enable_3_int),
.qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
.qsfp0_rx_status_3(qsfp0_rx_status_3),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_tx_prbs31_enable_4(qsfp0_tx_prbs31_enable_4_int),
.qsfp0_cfg_tx_prbs31_enable_4(qsfp0_cfg_tx_prbs31_enable_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
.qsfp0_cfg_rx_prbs31_enable_4(qsfp0_cfg_rx_prbs31_enable_4_int),
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_status_4),
@ -1833,48 +1833,48 @@ core_inst (
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_tx_prbs31_enable_1(qsfp1_tx_prbs31_enable_1_int),
.qsfp1_cfg_tx_prbs31_enable_1(qsfp1_cfg_tx_prbs31_enable_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_cfg_rx_prbs31_enable_1(qsfp1_cfg_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_status_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_tx_prbs31_enable_2(qsfp1_tx_prbs31_enable_2_int),
.qsfp1_cfg_tx_prbs31_enable_2(qsfp1_cfg_tx_prbs31_enable_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_cfg_rx_prbs31_enable_2(qsfp1_cfg_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_status_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_tx_prbs31_enable_3(qsfp1_tx_prbs31_enable_3_int),
.qsfp1_cfg_tx_prbs31_enable_3(qsfp1_cfg_tx_prbs31_enable_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_cfg_rx_prbs31_enable_3(qsfp1_cfg_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_status_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_tx_prbs31_enable_4(qsfp1_tx_prbs31_enable_4_int),
.qsfp1_cfg_tx_prbs31_enable_4(qsfp1_cfg_tx_prbs31_enable_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_cfg_rx_prbs31_enable_4(qsfp1_cfg_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_status_4),

72
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
View File

@ -269,48 +269,48 @@ module fpga_core #
input wire qsfp0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1,
output wire qsfp0_tx_prbs31_enable_1,
output wire qsfp0_cfg_tx_prbs31_enable_1,
input wire qsfp0_rx_clk_1,
input wire qsfp0_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1,
output wire qsfp0_rx_prbs31_enable_1,
output wire qsfp0_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp0_rx_error_count_1,
input wire qsfp0_rx_status_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2,
output wire qsfp0_tx_prbs31_enable_2,
output wire qsfp0_cfg_tx_prbs31_enable_2,
input wire qsfp0_rx_clk_2,
input wire qsfp0_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2,
output wire qsfp0_rx_prbs31_enable_2,
output wire qsfp0_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp0_rx_error_count_2,
input wire qsfp0_rx_status_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3,
output wire qsfp0_tx_prbs31_enable_3,
output wire qsfp0_cfg_tx_prbs31_enable_3,
input wire qsfp0_rx_clk_3,
input wire qsfp0_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3,
output wire qsfp0_rx_prbs31_enable_3,
output wire qsfp0_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp0_rx_error_count_3,
input wire qsfp0_rx_status_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4,
output wire qsfp0_tx_prbs31_enable_4,
output wire qsfp0_cfg_tx_prbs31_enable_4,
input wire qsfp0_rx_clk_4,
input wire qsfp0_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4,
output wire qsfp0_rx_prbs31_enable_4,
output wire qsfp0_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
@ -340,48 +340,48 @@ module fpga_core #
input wire qsfp1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1,
output wire qsfp1_tx_prbs31_enable_1,
output wire qsfp1_cfg_tx_prbs31_enable_1,
input wire qsfp1_rx_clk_1,
input wire qsfp1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
output wire qsfp1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2,
output wire qsfp1_tx_prbs31_enable_2,
output wire qsfp1_cfg_tx_prbs31_enable_2,
input wire qsfp1_rx_clk_2,
input wire qsfp1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
output wire qsfp1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3,
output wire qsfp1_tx_prbs31_enable_3,
output wire qsfp1_cfg_tx_prbs31_enable_3,
input wire qsfp1_rx_clk_3,
input wire qsfp1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
output wire qsfp1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4,
output wire qsfp1_tx_prbs31_enable_4,
output wire qsfp1_cfg_tx_prbs31_enable_4,
input wire qsfp1_rx_clk_4,
input wire qsfp1_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
output wire qsfp1_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
@ -924,8 +924,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}),
.phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
.phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}),
.phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}),
.phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}),
.phy_cfg_tx_prbs31_enable({qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1, qsfp0_cfg_tx_prbs31_enable_4, qsfp0_cfg_tx_prbs31_enable_3, qsfp0_cfg_tx_prbs31_enable_2, qsfp0_cfg_tx_prbs31_enable_1}),
.phy_cfg_rx_prbs31_enable({qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1, qsfp0_cfg_rx_prbs31_enable_4, qsfp0_cfg_rx_prbs31_enable_3, qsfp0_cfg_rx_prbs31_enable_2, qsfp0_cfg_rx_prbs31_enable_1}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -951,22 +951,22 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp0_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_rx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0;
end
@ -1127,7 +1127,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

12
fpga/mqnic/KR260/fpga/rtl/fpga.v
View File

@ -503,12 +503,12 @@ wire sfp_tx_clk_int;
wire sfp_tx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp_txd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp_txc_int;
wire sfp_tx_prbs31_enable_int;
wire sfp_cfg_tx_prbs31_enable_int;
wire sfp_rx_clk_int;
wire sfp_rx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp_rxd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp_rxc_int;
wire sfp_rx_prbs31_enable_int;
wire sfp_cfg_rx_prbs31_enable_int;
wire [6:0] sfp_rx_error_count_int;
wire sfp_drp_clk = clk_125mhz_int;
@ -612,8 +612,8 @@ sfp_phy_quad_inst (
.phy_1_rx_block_lock(sfp_rx_block_lock),
.phy_1_rx_high_ber(),
.phy_1_rx_status(sfp_rx_status),
.phy_1_tx_prbs31_enable(sfp_tx_prbs31_enable_int),
.phy_1_rx_prbs31_enable(sfp_rx_prbs31_enable_int)
.phy_1_cfg_tx_prbs31_enable(sfp_cfg_tx_prbs31_enable_int),
.phy_1_cfg_rx_prbs31_enable(sfp_cfg_rx_prbs31_enable_int)
);
wire ptp_clk;
@ -875,12 +875,12 @@ core_inst (
.sfp_tx_rst(sfp_tx_rst_int),
.sfp_txd(sfp_txd_int),
.sfp_txc(sfp_txc_int),
.sfp_tx_prbs31_enable(sfp_tx_prbs31_enable_int),
.sfp_cfg_tx_prbs31_enable(sfp_cfg_tx_prbs31_enable_int),
.sfp_rx_clk(sfp_rx_clk_int),
.sfp_rx_rst(sfp_rx_rst_int),
.sfp_rxd(sfp_rxd_int),
.sfp_rxc(sfp_rxc_int),
.sfp_rx_prbs31_enable(sfp_rx_prbs31_enable_int),
.sfp_cfg_rx_prbs31_enable(sfp_cfg_rx_prbs31_enable_int),
.sfp_rx_error_count(sfp_rx_error_count_int),
.sfp_rx_status(sfp_rx_status),

16
fpga/mqnic/KR260/fpga/rtl/fpga_core.v
View File

@ -268,12 +268,12 @@ module fpga_core #
input wire sfp_tx_rst,
output wire [63:0] sfp_txd,
output wire [7:0] sfp_txc,
output wire sfp_tx_prbs31_enable,
output wire sfp_cfg_tx_prbs31_enable,
input wire sfp_rx_clk,
input wire sfp_rx_rst,
input wire [63:0] sfp_rxd,
input wire [7:0] sfp_rxc,
output wire sfp_rx_prbs31_enable,
output wire sfp_cfg_rx_prbs31_enable,
input wire [6:0] sfp_rx_error_count,
input wire sfp_rx_status,
@ -530,8 +530,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({sfp_tx_clk}),
.phy_rx_clk({sfp_rx_clk}),
.phy_rx_error_count({sfp_rx_error_count}),
.phy_tx_prbs31_enable({sfp_tx_prbs31_enable}),
.phy_rx_prbs31_enable({sfp_rx_prbs31_enable}),
.phy_cfg_tx_prbs31_enable({sfp_cfg_tx_prbs31_enable}),
.phy_cfg_rx_prbs31_enable({sfp_cfg_rx_prbs31_enable}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -557,8 +557,8 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign sfp_tx_prbs31_enable = 1'b0;
assign sfp_rx_prbs31_enable = 1'b0;
assign sfp_cfg_tx_prbs31_enable = 1'b0;
assign sfp_cfg_rx_prbs31_enable = 1'b0;
end
@ -716,7 +716,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

4
fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
View File

@ -673,7 +673,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

8
fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v
View File

@ -946,8 +946,8 @@ sfp_phy_quad_inst (
.phy_1_rx_block_lock(sfp_1_rx_block_lock),
.phy_1_rx_high_ber(),
.phy_1_rx_status(sfp_1_rx_status),
.phy_1_tx_prbs31_enable(1'b0),
.phy_1_rx_prbs31_enable(1'b0),
.phy_1_cfg_tx_prbs31_enable(1'b0),
.phy_1_cfg_rx_prbs31_enable(1'b0),
.phy_2_tx_clk(sfp_2_tx_clk_int),
.phy_2_tx_rst(sfp_2_tx_rst_int),
@ -964,8 +964,8 @@ sfp_phy_quad_inst (
.phy_2_rx_block_lock(sfp_2_rx_block_lock),
.phy_2_rx_high_ber(),
.phy_2_rx_status(sfp_2_rx_status),
.phy_2_tx_prbs31_enable(1'b0),
.phy_2_rx_prbs31_enable(1'b0)
.phy_2_cfg_tx_prbs31_enable(1'b0),
.phy_2_cfg_rx_prbs31_enable(1'b0)
);
wire ptp_clk;

4
fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v
View File

@ -848,7 +848,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

96
fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v
View File

@ -947,45 +947,45 @@ wire qsfp_0_tx_clk_0_int;
wire qsfp_0_tx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_0_int;
wire qsfp_0_tx_prbs31_enable_0_int;
wire qsfp_0_cfg_tx_prbs31_enable_0_int;
wire qsfp_0_rx_clk_0_int;
wire qsfp_0_rx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_0_int;
wire qsfp_0_rx_prbs31_enable_0_int;
wire qsfp_0_cfg_rx_prbs31_enable_0_int;
wire [6:0] qsfp_0_rx_error_count_0_int;
wire qsfp_0_tx_clk_1_int;
wire qsfp_0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_1_int;
wire qsfp_0_tx_prbs31_enable_1_int;
wire qsfp_0_cfg_tx_prbs31_enable_1_int;
wire qsfp_0_rx_clk_1_int;
wire qsfp_0_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_1_int;
wire qsfp_0_rx_prbs31_enable_1_int;
wire qsfp_0_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp_0_rx_error_count_1_int;
wire qsfp_0_tx_clk_2_int;
wire qsfp_0_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_2_int;
wire qsfp_0_tx_prbs31_enable_2_int;
wire qsfp_0_cfg_tx_prbs31_enable_2_int;
wire qsfp_0_rx_clk_2_int;
wire qsfp_0_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_2_int;
wire qsfp_0_rx_prbs31_enable_2_int;
wire qsfp_0_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp_0_rx_error_count_2_int;
wire qsfp_0_tx_clk_3_int;
wire qsfp_0_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_3_int;
wire qsfp_0_tx_prbs31_enable_3_int;
wire qsfp_0_cfg_tx_prbs31_enable_3_int;
wire qsfp_0_rx_clk_3_int;
wire qsfp_0_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_3_int;
wire qsfp_0_rx_prbs31_enable_3_int;
wire qsfp_0_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp_0_rx_error_count_3_int;
wire qsfp_0_drp_clk = clk_125mhz_int;
@ -1098,8 +1098,8 @@ qsfp_0_phy_quad_inst (
.phy_1_rx_block_lock(qsfp_0_rx_block_lock_0),
.phy_1_rx_status(qsfp_0_rx_status_0),
.phy_1_rx_high_ber(),
.phy_1_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_0_int),
.phy_1_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_0_int),
.phy_1_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_0_int),
.phy_1_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_0_int),
.phy_2_tx_clk(qsfp_0_tx_clk_1_int),
.phy_2_tx_rst(qsfp_0_tx_rst_1_int),
@ -1116,8 +1116,8 @@ qsfp_0_phy_quad_inst (
.phy_2_rx_block_lock(qsfp_0_rx_block_lock_1),
.phy_2_rx_status(qsfp_0_rx_status_1),
.phy_2_rx_high_ber(),
.phy_2_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_1_int),
.phy_2_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_1_int),
.phy_2_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_1_int),
.phy_2_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_1_int),
.phy_3_tx_clk(qsfp_0_tx_clk_2_int),
.phy_3_tx_rst(qsfp_0_tx_rst_2_int),
@ -1134,8 +1134,8 @@ qsfp_0_phy_quad_inst (
.phy_3_rx_block_lock(qsfp_0_rx_block_lock_2),
.phy_3_rx_status(qsfp_0_rx_status_2),
.phy_3_rx_high_ber(),
.phy_3_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_2_int),
.phy_3_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_2_int),
.phy_3_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_2_int),
.phy_3_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_2_int),
.phy_4_tx_clk(qsfp_0_tx_clk_3_int),
.phy_4_tx_rst(qsfp_0_tx_rst_3_int),
@ -1152,8 +1152,8 @@ qsfp_0_phy_quad_inst (
.phy_4_rx_block_lock(qsfp_0_rx_block_lock_3),
.phy_4_rx_status(qsfp_0_rx_status_3),
.phy_4_rx_high_ber(),
.phy_4_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_3_int),
.phy_4_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_3_int)
.phy_4_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_3_int),
.phy_4_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_3_int)
);
// QSFP1
@ -1161,45 +1161,45 @@ wire qsfp_1_tx_clk_0_int;
wire qsfp_1_tx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_0_int;
wire qsfp_1_tx_prbs31_enable_0_int;
wire qsfp_1_cfg_tx_prbs31_enable_0_int;
wire qsfp_1_rx_clk_0_int;
wire qsfp_1_rx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_0_int;
wire qsfp_1_rx_prbs31_enable_0_int;
wire qsfp_1_cfg_rx_prbs31_enable_0_int;
wire [6:0] qsfp_1_rx_error_count_0_int;
wire qsfp_1_tx_clk_1_int;
wire qsfp_1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_1_int;
wire qsfp_1_tx_prbs31_enable_1_int;
wire qsfp_1_cfg_tx_prbs31_enable_1_int;
wire qsfp_1_rx_clk_1_int;
wire qsfp_1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_1_int;
wire qsfp_1_rx_prbs31_enable_1_int;
wire qsfp_1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp_1_rx_error_count_1_int;
wire qsfp_1_tx_clk_2_int;
wire qsfp_1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_2_int;
wire qsfp_1_tx_prbs31_enable_2_int;
wire qsfp_1_cfg_tx_prbs31_enable_2_int;
wire qsfp_1_rx_clk_2_int;
wire qsfp_1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_2_int;
wire qsfp_1_rx_prbs31_enable_2_int;
wire qsfp_1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp_1_rx_error_count_2_int;
wire qsfp_1_tx_clk_3_int;
wire qsfp_1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_3_int;
wire qsfp_1_tx_prbs31_enable_3_int;
wire qsfp_1_cfg_tx_prbs31_enable_3_int;
wire qsfp_1_rx_clk_3_int;
wire qsfp_1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_3_int;
wire qsfp_1_rx_prbs31_enable_3_int;
wire qsfp_1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp_1_rx_error_count_3_int;
wire qsfp_1_drp_clk = clk_125mhz_int;
@ -1274,8 +1274,8 @@ qsfp_1_phy_quad_inst (
.phy_1_rx_block_lock(qsfp_1_rx_block_lock_0),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp_1_rx_status_0),
.phy_1_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_0_int),
.phy_1_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_0_int),
.phy_1_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_0_int),
.phy_1_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_0_int),
.phy_2_tx_clk(qsfp_1_tx_clk_1_int),
.phy_2_tx_rst(qsfp_1_tx_rst_1_int),
@ -1292,8 +1292,8 @@ qsfp_1_phy_quad_inst (
.phy_2_rx_block_lock(qsfp_1_rx_block_lock_1),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp_1_rx_status_1),
.phy_2_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_1_int),
.phy_2_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_1_int),
.phy_2_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_1_int),
.phy_2_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_1_int),
.phy_3_tx_clk(qsfp_1_tx_clk_2_int),
.phy_3_tx_rst(qsfp_1_tx_rst_2_int),
@ -1310,8 +1310,8 @@ qsfp_1_phy_quad_inst (
.phy_3_rx_block_lock(qsfp_1_rx_block_lock_2),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp_1_rx_status_2),
.phy_3_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_2_int),
.phy_3_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_2_int),
.phy_3_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_2_int),
.phy_3_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_2_int),
.phy_4_tx_clk(qsfp_1_tx_clk_3_int),
.phy_4_tx_rst(qsfp_1_tx_rst_3_int),
@ -1328,8 +1328,8 @@ qsfp_1_phy_quad_inst (
.phy_4_rx_block_lock(qsfp_1_rx_block_lock_3),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp_1_rx_status_3),
.phy_4_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_3_int),
.phy_4_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_3_int)
.phy_4_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_3_int),
.phy_4_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_3_int)
);
wire ptp_clk;
@ -1790,48 +1790,48 @@ core_inst (
.qsfp_0_tx_rst_0(qsfp_0_tx_rst_0_int),
.qsfp_0_txd_0(qsfp_0_txd_0_int),
.qsfp_0_txc_0(qsfp_0_txc_0_int),
.qsfp_0_tx_prbs31_enable_0(qsfp_0_tx_prbs31_enable_0_int),
.qsfp_0_cfg_tx_prbs31_enable_0(qsfp_0_cfg_tx_prbs31_enable_0_int),
.qsfp_0_rx_clk_0(qsfp_0_rx_clk_0_int),
.qsfp_0_rx_rst_0(qsfp_0_rx_rst_0_int),
.qsfp_0_rxd_0(qsfp_0_rxd_0_int),
.qsfp_0_rxc_0(qsfp_0_rxc_0_int),
.qsfp_0_rx_prbs31_enable_0(qsfp_0_rx_prbs31_enable_0_int),
.qsfp_0_cfg_rx_prbs31_enable_0(qsfp_0_cfg_rx_prbs31_enable_0_int),
.qsfp_0_rx_error_count_0(qsfp_0_rx_error_count_0_int),
.qsfp_0_rx_status_0(qsfp_0_rx_status_0),
.qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int),
.qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int),
.qsfp_0_txd_1(qsfp_0_txd_1_int),
.qsfp_0_txc_1(qsfp_0_txc_1_int),
.qsfp_0_tx_prbs31_enable_1(qsfp_0_tx_prbs31_enable_1_int),
.qsfp_0_cfg_tx_prbs31_enable_1(qsfp_0_cfg_tx_prbs31_enable_1_int),
.qsfp_0_rx_clk_1(qsfp_0_rx_clk_1_int),
.qsfp_0_rx_rst_1(qsfp_0_rx_rst_1_int),
.qsfp_0_rxd_1(qsfp_0_rxd_1_int),
.qsfp_0_rxc_1(qsfp_0_rxc_1_int),
.qsfp_0_rx_prbs31_enable_1(qsfp_0_rx_prbs31_enable_1_int),
.qsfp_0_cfg_rx_prbs31_enable_1(qsfp_0_cfg_rx_prbs31_enable_1_int),
.qsfp_0_rx_error_count_1(qsfp_0_rx_error_count_1_int),
.qsfp_0_rx_status_1(qsfp_0_rx_status_1),
.qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int),
.qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int),
.qsfp_0_txd_2(qsfp_0_txd_2_int),
.qsfp_0_txc_2(qsfp_0_txc_2_int),
.qsfp_0_tx_prbs31_enable_2(qsfp_0_tx_prbs31_enable_2_int),
.qsfp_0_cfg_tx_prbs31_enable_2(qsfp_0_cfg_tx_prbs31_enable_2_int),
.qsfp_0_rx_clk_2(qsfp_0_rx_clk_2_int),
.qsfp_0_rx_rst_2(qsfp_0_rx_rst_2_int),
.qsfp_0_rxd_2(qsfp_0_rxd_2_int),
.qsfp_0_rxc_2(qsfp_0_rxc_2_int),
.qsfp_0_rx_prbs31_enable_2(qsfp_0_rx_prbs31_enable_2_int),
.qsfp_0_cfg_rx_prbs31_enable_2(qsfp_0_cfg_rx_prbs31_enable_2_int),
.qsfp_0_rx_error_count_2(qsfp_0_rx_error_count_2_int),
.qsfp_0_rx_status_2(qsfp_0_rx_status_2),
.qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int),
.qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int),
.qsfp_0_txd_3(qsfp_0_txd_3_int),
.qsfp_0_txc_3(qsfp_0_txc_3_int),
.qsfp_0_tx_prbs31_enable_3(qsfp_0_tx_prbs31_enable_3_int),
.qsfp_0_cfg_tx_prbs31_enable_3(qsfp_0_cfg_tx_prbs31_enable_3_int),
.qsfp_0_rx_clk_3(qsfp_0_rx_clk_3_int),
.qsfp_0_rx_rst_3(qsfp_0_rx_rst_3_int),
.qsfp_0_rxd_3(qsfp_0_rxd_3_int),
.qsfp_0_rxc_3(qsfp_0_rxc_3_int),
.qsfp_0_rx_prbs31_enable_3(qsfp_0_rx_prbs31_enable_3_int),
.qsfp_0_cfg_rx_prbs31_enable_3(qsfp_0_cfg_rx_prbs31_enable_3_int),
.qsfp_0_rx_error_count_3(qsfp_0_rx_error_count_3_int),
.qsfp_0_rx_status_3(qsfp_0_rx_status_3),
@ -1861,48 +1861,48 @@ core_inst (
.qsfp_1_tx_rst_0(qsfp_1_tx_rst_0_int),
.qsfp_1_txd_0(qsfp_1_txd_0_int),
.qsfp_1_txc_0(qsfp_1_txc_0_int),
.qsfp_1_tx_prbs31_enable_0(qsfp_1_tx_prbs31_enable_0_int),
.qsfp_1_cfg_tx_prbs31_enable_0(qsfp_1_cfg_tx_prbs31_enable_0_int),
.qsfp_1_rx_clk_0(qsfp_1_rx_clk_0_int),
.qsfp_1_rx_rst_0(qsfp_1_rx_rst_0_int),
.qsfp_1_rxd_0(qsfp_1_rxd_0_int),
.qsfp_1_rxc_0(qsfp_1_rxc_0_int),
.qsfp_1_rx_prbs31_enable_0(qsfp_1_rx_prbs31_enable_0_int),
.qsfp_1_cfg_rx_prbs31_enable_0(qsfp_1_cfg_rx_prbs31_enable_0_int),
.qsfp_1_rx_error_count_0(qsfp_1_rx_error_count_0_int),
.qsfp_1_rx_status_0(qsfp_1_rx_status_0),
.qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int),
.qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int),
.qsfp_1_txd_1(qsfp_1_txd_1_int),
.qsfp_1_txc_1(qsfp_1_txc_1_int),
.qsfp_1_tx_prbs31_enable_1(qsfp_1_tx_prbs31_enable_1_int),
.qsfp_1_cfg_tx_prbs31_enable_1(qsfp_1_cfg_tx_prbs31_enable_1_int),
.qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int),
.qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int),
.qsfp_1_rxd_1(qsfp_1_rxd_1_int),
.qsfp_1_rxc_1(qsfp_1_rxc_1_int),
.qsfp_1_rx_prbs31_enable_1(qsfp_1_rx_prbs31_enable_1_int),
.qsfp_1_cfg_rx_prbs31_enable_1(qsfp_1_cfg_rx_prbs31_enable_1_int),
.qsfp_1_rx_error_count_1(qsfp_1_rx_error_count_1_int),
.qsfp_1_rx_status_1(qsfp_1_rx_status_1),
.qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int),
.qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int),
.qsfp_1_txd_2(qsfp_1_txd_2_int),
.qsfp_1_txc_2(qsfp_1_txc_2_int),
.qsfp_1_tx_prbs31_enable_2(qsfp_1_tx_prbs31_enable_2_int),
.qsfp_1_cfg_tx_prbs31_enable_2(qsfp_1_cfg_tx_prbs31_enable_2_int),
.qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int),
.qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int),
.qsfp_1_rxd_2(qsfp_1_rxd_2_int),
.qsfp_1_rxc_2(qsfp_1_rxc_2_int),
.qsfp_1_rx_prbs31_enable_2(qsfp_1_rx_prbs31_enable_2_int),
.qsfp_1_cfg_rx_prbs31_enable_2(qsfp_1_cfg_rx_prbs31_enable_2_int),
.qsfp_1_rx_error_count_2(qsfp_1_rx_error_count_2_int),
.qsfp_1_rx_status_2(qsfp_1_rx_status_2),
.qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int),
.qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int),
.qsfp_1_txd_3(qsfp_1_txd_3_int),
.qsfp_1_txc_3(qsfp_1_txc_3_int),
.qsfp_1_tx_prbs31_enable_3(qsfp_1_tx_prbs31_enable_3_int),
.qsfp_1_cfg_tx_prbs31_enable_3(qsfp_1_cfg_tx_prbs31_enable_3_int),
.qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int),
.qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int),
.qsfp_1_rxd_3(qsfp_1_rxd_3_int),
.qsfp_1_rxc_3(qsfp_1_rxc_3_int),
.qsfp_1_rx_prbs31_enable_3(qsfp_1_rx_prbs31_enable_3_int),
.qsfp_1_cfg_rx_prbs31_enable_3(qsfp_1_cfg_rx_prbs31_enable_3_int),
.qsfp_1_rx_error_count_3(qsfp_1_rx_error_count_3_int),
.qsfp_1_rx_status_3(qsfp_1_rx_status_3),

72
fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v
View File

@ -280,48 +280,48 @@ module fpga_core #
input wire qsfp_0_tx_rst_0,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_0,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_0,
output wire qsfp_0_tx_prbs31_enable_0,
output wire qsfp_0_cfg_tx_prbs31_enable_0,
input wire qsfp_0_rx_clk_0,
input wire qsfp_0_rx_rst_0,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_0,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_0,
output wire qsfp_0_rx_prbs31_enable_0,
output wire qsfp_0_cfg_rx_prbs31_enable_0,
input wire [6:0] qsfp_0_rx_error_count_0,
input wire qsfp_0_rx_status_0,
input wire qsfp_0_tx_clk_1,
input wire qsfp_0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_1,
output wire qsfp_0_tx_prbs31_enable_1,
output wire qsfp_0_cfg_tx_prbs31_enable_1,
input wire qsfp_0_rx_clk_1,
input wire qsfp_0_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_1,
output wire qsfp_0_rx_prbs31_enable_1,
output wire qsfp_0_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp_0_rx_error_count_1,
input wire qsfp_0_rx_status_1,
input wire qsfp_0_tx_clk_2,
input wire qsfp_0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_2,
output wire qsfp_0_tx_prbs31_enable_2,
output wire qsfp_0_cfg_tx_prbs31_enable_2,
input wire qsfp_0_rx_clk_2,
input wire qsfp_0_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_2,
output wire qsfp_0_rx_prbs31_enable_2,
output wire qsfp_0_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp_0_rx_error_count_2,
input wire qsfp_0_rx_status_2,
input wire qsfp_0_tx_clk_3,
input wire qsfp_0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_3,
output wire qsfp_0_tx_prbs31_enable_3,
output wire qsfp_0_cfg_tx_prbs31_enable_3,
input wire qsfp_0_rx_clk_3,
input wire qsfp_0_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_3,
output wire qsfp_0_rx_prbs31_enable_3,
output wire qsfp_0_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp_0_rx_error_count_3,
input wire qsfp_0_rx_status_3,
@ -351,48 +351,48 @@ module fpga_core #
input wire qsfp_1_tx_rst_0,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_0,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_0,
output wire qsfp_1_tx_prbs31_enable_0,
output wire qsfp_1_cfg_tx_prbs31_enable_0,
input wire qsfp_1_rx_clk_0,
input wire qsfp_1_rx_rst_0,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_0,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_0,
output wire qsfp_1_rx_prbs31_enable_0,
output wire qsfp_1_cfg_rx_prbs31_enable_0,
input wire [6:0] qsfp_1_rx_error_count_0,
input wire qsfp_1_rx_status_0,
input wire qsfp_1_tx_clk_1,
input wire qsfp_1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_1,
output wire qsfp_1_tx_prbs31_enable_1,
output wire qsfp_1_cfg_tx_prbs31_enable_1,
input wire qsfp_1_rx_clk_1,
input wire qsfp_1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_1,
output wire qsfp_1_rx_prbs31_enable_1,
output wire qsfp_1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp_1_rx_error_count_1,
input wire qsfp_1_rx_status_1,
input wire qsfp_1_tx_clk_2,
input wire qsfp_1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_2,
output wire qsfp_1_tx_prbs31_enable_2,
output wire qsfp_1_cfg_tx_prbs31_enable_2,
input wire qsfp_1_rx_clk_2,
input wire qsfp_1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_2,
output wire qsfp_1_rx_prbs31_enable_2,
output wire qsfp_1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp_1_rx_error_count_2,
input wire qsfp_1_rx_status_2,
input wire qsfp_1_tx_clk_3,
input wire qsfp_1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_3,
output wire qsfp_1_tx_prbs31_enable_3,
output wire qsfp_1_cfg_tx_prbs31_enable_3,
input wire qsfp_1_rx_clk_3,
input wire qsfp_1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_3,
output wire qsfp_1_rx_prbs31_enable_3,
output wire qsfp_1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp_1_rx_error_count_3,
input wire qsfp_1_rx_status_3,
@ -956,8 +956,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp_1_tx_clk_3, qsfp_1_tx_clk_2, qsfp_1_tx_clk_1, qsfp_1_tx_clk_0, qsfp_0_tx_clk_3, qsfp_0_tx_clk_2, qsfp_0_tx_clk_1, qsfp_0_tx_clk_0}),
.phy_rx_clk({qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}),
.phy_rx_error_count({qsfp_1_rx_error_count_3, qsfp_1_rx_error_count_2, qsfp_1_rx_error_count_1, qsfp_1_rx_error_count_0, qsfp_0_rx_error_count_3, qsfp_0_rx_error_count_2, qsfp_0_rx_error_count_1, qsfp_0_rx_error_count_0}),
.phy_tx_prbs31_enable({qsfp_1_tx_prbs31_enable_3, qsfp_1_tx_prbs31_enable_2, qsfp_1_tx_prbs31_enable_1, qsfp_1_tx_prbs31_enable_0, qsfp_0_tx_prbs31_enable_3, qsfp_0_tx_prbs31_enable_2, qsfp_0_tx_prbs31_enable_1, qsfp_0_tx_prbs31_enable_0}),
.phy_rx_prbs31_enable({qsfp_1_rx_prbs31_enable_3, qsfp_1_rx_prbs31_enable_2, qsfp_1_rx_prbs31_enable_1, qsfp_1_rx_prbs31_enable_0, qsfp_0_rx_prbs31_enable_3, qsfp_0_rx_prbs31_enable_2, qsfp_0_rx_prbs31_enable_1, qsfp_0_rx_prbs31_enable_0}),
.phy_cfg_tx_prbs31_enable({qsfp_1_cfg_tx_prbs31_enable_3, qsfp_1_cfg_tx_prbs31_enable_2, qsfp_1_cfg_tx_prbs31_enable_1, qsfp_1_cfg_tx_prbs31_enable_0, qsfp_0_cfg_tx_prbs31_enable_3, qsfp_0_cfg_tx_prbs31_enable_2, qsfp_0_cfg_tx_prbs31_enable_1, qsfp_0_cfg_tx_prbs31_enable_0}),
.phy_cfg_rx_prbs31_enable({qsfp_1_cfg_rx_prbs31_enable_3, qsfp_1_cfg_rx_prbs31_enable_2, qsfp_1_cfg_rx_prbs31_enable_1, qsfp_1_cfg_rx_prbs31_enable_0, qsfp_0_cfg_rx_prbs31_enable_3, qsfp_0_cfg_rx_prbs31_enable_2, qsfp_0_cfg_rx_prbs31_enable_1, qsfp_0_cfg_rx_prbs31_enable_0}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -983,22 +983,22 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp_0_tx_prbs31_enable_0 = 1'b0;
assign qsfp_0_rx_prbs31_enable_0 = 1'b0;
assign qsfp_0_tx_prbs31_enable_1 = 1'b0;
assign qsfp_0_rx_prbs31_enable_1 = 1'b0;
assign qsfp_0_tx_prbs31_enable_2 = 1'b0;
assign qsfp_0_rx_prbs31_enable_2 = 1'b0;
assign qsfp_0_tx_prbs31_enable_3 = 1'b0;
assign qsfp_0_rx_prbs31_enable_3 = 1'b0;
assign qsfp_1_tx_prbs31_enable_0 = 1'b0;
assign qsfp_1_rx_prbs31_enable_0 = 1'b0;
assign qsfp_1_tx_prbs31_enable_1 = 1'b0;
assign qsfp_1_rx_prbs31_enable_1 = 1'b0;
assign qsfp_1_tx_prbs31_enable_2 = 1'b0;
assign qsfp_1_rx_prbs31_enable_2 = 1'b0;
assign qsfp_1_tx_prbs31_enable_3 = 1'b0;
assign qsfp_1_rx_prbs31_enable_3 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_0 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_0 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_0 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_0 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_3 = 1'b0;
end
@ -1162,7 +1162,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

24
fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v
View File

@ -952,24 +952,24 @@ wire sfp_1_tx_clk_int;
wire sfp_1_tx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp_1_txd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp_1_txc_int;
wire sfp_1_tx_prbs31_enable_int;
wire sfp_1_cfg_tx_prbs31_enable_int;
wire sfp_1_rx_clk_int;
wire sfp_1_rx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp_1_rxd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp_1_rxc_int;
wire sfp_1_rx_prbs31_enable_int;
wire sfp_1_cfg_rx_prbs31_enable_int;
wire [6:0] sfp_1_rx_error_count_int;
wire sfp_2_tx_clk_int;
wire sfp_2_tx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp_2_txd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp_2_txc_int;
wire sfp_2_tx_prbs31_enable_int;
wire sfp_2_cfg_tx_prbs31_enable_int;
wire sfp_2_rx_clk_int;
wire sfp_2_rx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp_2_rxd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp_2_rxc_int;
wire sfp_2_rx_prbs31_enable_int;
wire sfp_2_cfg_rx_prbs31_enable_int;
wire [6:0] sfp_2_rx_error_count_int;
wire sfp_drp_clk = clk_125mhz_int;
@ -1080,8 +1080,8 @@ sfp_phy_quad_inst (
.phy_1_rx_block_lock(sfp_1_rx_block_lock),
.phy_1_rx_high_ber(),
.phy_1_rx_status(sfp_1_rx_status),
.phy_1_tx_prbs31_enable(sfp_1_tx_prbs31_enable_int),
.phy_1_rx_prbs31_enable(sfp_1_rx_prbs31_enable_int),
.phy_1_cfg_tx_prbs31_enable(sfp_1_cfg_tx_prbs31_enable_int),
.phy_1_cfg_rx_prbs31_enable(sfp_1_cfg_rx_prbs31_enable_int),
.phy_2_tx_clk(sfp_2_tx_clk_int),
.phy_2_tx_rst(sfp_2_tx_rst_int),
@ -1098,8 +1098,8 @@ sfp_phy_quad_inst (
.phy_2_rx_block_lock(sfp_2_rx_block_lock),
.phy_2_rx_high_ber(),
.phy_2_rx_status(sfp_2_rx_status),
.phy_2_tx_prbs31_enable(sfp_2_tx_prbs31_enable_int),
.phy_2_rx_prbs31_enable(sfp_2_rx_prbs31_enable_int)
.phy_2_cfg_tx_prbs31_enable(sfp_2_cfg_tx_prbs31_enable_int),
.phy_2_cfg_rx_prbs31_enable(sfp_2_cfg_rx_prbs31_enable_int)
);
wire ptp_clk;
@ -1362,12 +1362,12 @@ core_inst (
.sfp_1_tx_rst(sfp_1_tx_rst_int),
.sfp_1_txd(sfp_1_txd_int),
.sfp_1_txc(sfp_1_txc_int),
.sfp_1_tx_prbs31_enable(sfp_1_tx_prbs31_enable_int),
.sfp_1_cfg_tx_prbs31_enable(sfp_1_cfg_tx_prbs31_enable_int),
.sfp_1_rx_clk(sfp_1_rx_clk_int),
.sfp_1_rx_rst(sfp_1_rx_rst_int),
.sfp_1_rxd(sfp_1_rxd_int),
.sfp_1_rxc(sfp_1_rxc_int),
.sfp_1_rx_prbs31_enable(sfp_1_rx_prbs31_enable_int),
.sfp_1_cfg_rx_prbs31_enable(sfp_1_cfg_rx_prbs31_enable_int),
.sfp_1_rx_error_count(sfp_1_rx_error_count_int),
.sfp_1_rx_status(sfp_1_rx_status),
@ -1376,12 +1376,12 @@ core_inst (
.sfp_2_tx_rst(sfp_2_tx_rst_int),
.sfp_2_txd(sfp_2_txd_int),
.sfp_2_txc(sfp_2_txc_int),
.sfp_2_tx_prbs31_enable(sfp_2_tx_prbs31_enable_int),
.sfp_2_cfg_tx_prbs31_enable(sfp_2_cfg_tx_prbs31_enable_int),
.sfp_2_rx_clk(sfp_2_rx_clk_int),
.sfp_2_rx_rst(sfp_2_rx_rst_int),
.sfp_2_rxd(sfp_2_rxd_int),
.sfp_2_rxc(sfp_2_rxc_int),
.sfp_2_rx_prbs31_enable(sfp_2_rx_prbs31_enable_int),
.sfp_2_cfg_rx_prbs31_enable(sfp_2_cfg_rx_prbs31_enable_int),
.sfp_2_rx_error_count(sfp_2_rx_error_count_int),
.sfp_2_rx_status(sfp_2_rx_status),

24
fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
View File

@ -267,12 +267,12 @@ module fpga_core #
input wire sfp_1_tx_rst,
output wire [XGMII_DATA_WIDTH-1:0] sfp_1_txd,
output wire [XGMII_CTRL_WIDTH-1:0] sfp_1_txc,
output wire sfp_1_tx_prbs31_enable,
output wire sfp_1_cfg_tx_prbs31_enable,
input wire sfp_1_rx_clk,
input wire sfp_1_rx_rst,
input wire [XGMII_DATA_WIDTH-1:0] sfp_1_rxd,
input wire [XGMII_CTRL_WIDTH-1:0] sfp_1_rxc,
output wire sfp_1_rx_prbs31_enable,
output wire sfp_1_cfg_rx_prbs31_enable,
input wire [6:0] sfp_1_rx_error_count,
input wire sfp_1_rx_status,
@ -280,12 +280,12 @@ module fpga_core #
input wire sfp_2_tx_rst,
output wire [XGMII_DATA_WIDTH-1:0] sfp_2_txd,
output wire [XGMII_CTRL_WIDTH-1:0] sfp_2_txc,
output wire sfp_2_tx_prbs31_enable,
output wire sfp_2_cfg_tx_prbs31_enable,
input wire sfp_2_rx_clk,
input wire sfp_2_rx_rst,
input wire [XGMII_DATA_WIDTH-1:0] sfp_2_rxd,
input wire [XGMII_CTRL_WIDTH-1:0] sfp_2_rxc,
output wire sfp_2_rx_prbs31_enable,
output wire sfp_2_cfg_rx_prbs31_enable,
input wire [6:0] sfp_2_rx_error_count,
input wire sfp_2_rx_status,
@ -754,8 +754,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({sfp_2_tx_clk, sfp_1_tx_clk}),
.phy_rx_clk({sfp_2_rx_clk, sfp_1_rx_clk}),
.phy_rx_error_count({sfp_2_rx_error_count, sfp_1_rx_error_count}),
.phy_tx_prbs31_enable({sfp_2_tx_prbs31_enable, sfp_1_tx_prbs31_enable}),
.phy_rx_prbs31_enable({sfp_2_rx_prbs31_enable, sfp_1_rx_prbs31_enable}),
.phy_cfg_tx_prbs31_enable({sfp_2_cfg_tx_prbs31_enable, sfp_1_cfg_tx_prbs31_enable}),
.phy_cfg_rx_prbs31_enable({sfp_2_cfg_rx_prbs31_enable, sfp_1_cfg_rx_prbs31_enable}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -781,10 +781,10 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign sfp_1_tx_prbs31_enable = 1'b0;
assign sfp_1_rx_prbs31_enable = 1'b0;
assign sfp_2_tx_prbs31_enable = 1'b0;
assign sfp_2_rx_prbs31_enable = 1'b0;
assign sfp_1_cfg_tx_prbs31_enable = 1'b0;
assign sfp_1_cfg_rx_prbs31_enable = 1'b0;
assign sfp_2_cfg_tx_prbs31_enable = 1'b0;
assign sfp_2_cfg_rx_prbs31_enable = 1'b0;
end
@ -946,7 +946,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

48
fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v
View File

@ -901,45 +901,45 @@ wire qsfp_tx_clk_1_int;
wire qsfp_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_1_int;
wire qsfp_tx_prbs31_enable_1_int;
wire qsfp_cfg_tx_prbs31_enable_1_int;
wire qsfp_rx_clk_1_int;
wire qsfp_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_1_int;
wire qsfp_rx_prbs31_enable_1_int;
wire qsfp_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp_rx_error_count_1_int;
wire qsfp_tx_clk_2_int;
wire qsfp_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_2_int;
wire qsfp_tx_prbs31_enable_2_int;
wire qsfp_cfg_tx_prbs31_enable_2_int;
wire qsfp_rx_clk_2_int;
wire qsfp_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_2_int;
wire qsfp_rx_prbs31_enable_2_int;
wire qsfp_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp_rx_error_count_2_int;
wire qsfp_tx_clk_3_int;
wire qsfp_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_3_int;
wire qsfp_tx_prbs31_enable_3_int;
wire qsfp_cfg_tx_prbs31_enable_3_int;
wire qsfp_rx_clk_3_int;
wire qsfp_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_3_int;
wire qsfp_rx_prbs31_enable_3_int;
wire qsfp_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp_rx_error_count_3_int;
wire qsfp_tx_clk_4_int;
wire qsfp_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_4_int;
wire qsfp_tx_prbs31_enable_4_int;
wire qsfp_cfg_tx_prbs31_enable_4_int;
wire qsfp_rx_clk_4_int;
wire qsfp_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_4_int;
wire qsfp_rx_prbs31_enable_4_int;
wire qsfp_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp_rx_error_count_4_int;
wire qsfp_drp_clk = clk_125mhz_int;
@ -1049,8 +1049,8 @@ qsfp_phy_quad_inst (
.phy_1_rx_block_lock(qsfp_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp_tx_clk_2_int),
.phy_2_tx_rst(qsfp_tx_rst_2_int),
@ -1067,8 +1067,8 @@ qsfp_phy_quad_inst (
.phy_2_rx_block_lock(qsfp_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp_tx_clk_3_int),
.phy_3_tx_rst(qsfp_tx_rst_3_int),
@ -1085,8 +1085,8 @@ qsfp_phy_quad_inst (
.phy_3_rx_block_lock(qsfp_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp_tx_clk_4_int),
.phy_4_tx_rst(qsfp_tx_rst_4_int),
@ -1103,8 +1103,8 @@ qsfp_phy_quad_inst (
.phy_4_rx_block_lock(qsfp_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp_cfg_rx_prbs31_enable_4_int)
);
wire ptp_clk;
@ -1716,48 +1716,48 @@ core_inst (
.qsfp_tx_rst_1(qsfp_tx_rst_1_int),
.qsfp_txd_1(qsfp_txd_1_int),
.qsfp_txc_1(qsfp_txc_1_int),
.qsfp_tx_prbs31_enable_1(qsfp_tx_prbs31_enable_1_int),
.qsfp_cfg_tx_prbs31_enable_1(qsfp_cfg_tx_prbs31_enable_1_int),
.qsfp_rx_clk_1(qsfp_rx_clk_1_int),
.qsfp_rx_rst_1(qsfp_rx_rst_1_int),
.qsfp_rxd_1(qsfp_rxd_1_int),
.qsfp_rxc_1(qsfp_rxc_1_int),
.qsfp_rx_prbs31_enable_1(qsfp_rx_prbs31_enable_1_int),
.qsfp_cfg_rx_prbs31_enable_1(qsfp_cfg_rx_prbs31_enable_1_int),
.qsfp_rx_error_count_1(qsfp_rx_error_count_1_int),
.qsfp_rx_status_1(qsfp_rx_status_1),
.qsfp_tx_clk_2(qsfp_tx_clk_2_int),
.qsfp_tx_rst_2(qsfp_tx_rst_2_int),
.qsfp_txd_2(qsfp_txd_2_int),
.qsfp_txc_2(qsfp_txc_2_int),
.qsfp_tx_prbs31_enable_2(qsfp_tx_prbs31_enable_2_int),
.qsfp_cfg_tx_prbs31_enable_2(qsfp_cfg_tx_prbs31_enable_2_int),
.qsfp_rx_clk_2(qsfp_rx_clk_2_int),
.qsfp_rx_rst_2(qsfp_rx_rst_2_int),
.qsfp_rxd_2(qsfp_rxd_2_int),
.qsfp_rxc_2(qsfp_rxc_2_int),
.qsfp_rx_prbs31_enable_2(qsfp_rx_prbs31_enable_2_int),
.qsfp_cfg_rx_prbs31_enable_2(qsfp_cfg_rx_prbs31_enable_2_int),
.qsfp_rx_error_count_2(qsfp_rx_error_count_2_int),
.qsfp_rx_status_2(qsfp_rx_status_2),
.qsfp_tx_clk_3(qsfp_tx_clk_3_int),
.qsfp_tx_rst_3(qsfp_tx_rst_3_int),
.qsfp_txd_3(qsfp_txd_3_int),
.qsfp_txc_3(qsfp_txc_3_int),
.qsfp_tx_prbs31_enable_3(qsfp_tx_prbs31_enable_3_int),
.qsfp_cfg_tx_prbs31_enable_3(qsfp_cfg_tx_prbs31_enable_3_int),
.qsfp_rx_clk_3(qsfp_rx_clk_3_int),
.qsfp_rx_rst_3(qsfp_rx_rst_3_int),
.qsfp_rxd_3(qsfp_rxd_3_int),
.qsfp_rxc_3(qsfp_rxc_3_int),
.qsfp_rx_prbs31_enable_3(qsfp_rx_prbs31_enable_3_int),
.qsfp_cfg_rx_prbs31_enable_3(qsfp_cfg_rx_prbs31_enable_3_int),
.qsfp_rx_error_count_3(qsfp_rx_error_count_3_int),
.qsfp_rx_status_3(qsfp_rx_status_3),
.qsfp_tx_clk_4(qsfp_tx_clk_4_int),
.qsfp_tx_rst_4(qsfp_tx_rst_4_int),
.qsfp_txd_4(qsfp_txd_4_int),
.qsfp_txc_4(qsfp_txc_4_int),
.qsfp_tx_prbs31_enable_4(qsfp_tx_prbs31_enable_4_int),
.qsfp_cfg_tx_prbs31_enable_4(qsfp_cfg_tx_prbs31_enable_4_int),
.qsfp_rx_clk_4(qsfp_rx_clk_4_int),
.qsfp_rx_rst_4(qsfp_rx_rst_4_int),
.qsfp_rxd_4(qsfp_rxd_4_int),
.qsfp_rxc_4(qsfp_rxc_4_int),
.qsfp_rx_prbs31_enable_4(qsfp_rx_prbs31_enable_4_int),
.qsfp_cfg_rx_prbs31_enable_4(qsfp_cfg_rx_prbs31_enable_4_int),
.qsfp_rx_error_count_4(qsfp_rx_error_count_4_int),
.qsfp_rx_status_4(qsfp_rx_status_4),

40
fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v
View File

@ -283,48 +283,48 @@ module fpga_core #
input wire qsfp_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_1,
output wire qsfp_tx_prbs31_enable_1,
output wire qsfp_cfg_tx_prbs31_enable_1,
input wire qsfp_rx_clk_1,
input wire qsfp_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_1,
output wire qsfp_rx_prbs31_enable_1,
output wire qsfp_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp_rx_error_count_1,
input wire qsfp_rx_status_1,
input wire qsfp_tx_clk_2,
input wire qsfp_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_2,
output wire qsfp_tx_prbs31_enable_2,
output wire qsfp_cfg_tx_prbs31_enable_2,
input wire qsfp_rx_clk_2,
input wire qsfp_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_2,
output wire qsfp_rx_prbs31_enable_2,
output wire qsfp_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp_rx_error_count_2,
input wire qsfp_rx_status_2,
input wire qsfp_tx_clk_3,
input wire qsfp_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_3,
output wire qsfp_tx_prbs31_enable_3,
output wire qsfp_cfg_tx_prbs31_enable_3,
input wire qsfp_rx_clk_3,
input wire qsfp_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_3,
output wire qsfp_rx_prbs31_enable_3,
output wire qsfp_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp_rx_error_count_3,
input wire qsfp_rx_status_3,
input wire qsfp_tx_clk_4,
input wire qsfp_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_txc_4,
output wire qsfp_tx_prbs31_enable_4,
output wire qsfp_cfg_tx_prbs31_enable_4,
input wire qsfp_rx_clk_4,
input wire qsfp_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_rxc_4,
output wire qsfp_rx_prbs31_enable_4,
output wire qsfp_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp_rx_error_count_4,
input wire qsfp_rx_status_4,
@ -738,8 +738,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp_tx_clk_4, qsfp_tx_clk_3, qsfp_tx_clk_2, qsfp_tx_clk_1}),
.phy_rx_clk({qsfp_rx_clk_4, qsfp_rx_clk_3, qsfp_rx_clk_2, qsfp_rx_clk_1}),
.phy_rx_error_count({qsfp_rx_error_count_4, qsfp_rx_error_count_3, qsfp_rx_error_count_2, qsfp_rx_error_count_1}),
.phy_tx_prbs31_enable({qsfp_tx_prbs31_enable_4, qsfp_tx_prbs31_enable_3, qsfp_tx_prbs31_enable_2, qsfp_tx_prbs31_enable_1}),
.phy_rx_prbs31_enable({qsfp_rx_prbs31_enable_4, qsfp_rx_prbs31_enable_3, qsfp_rx_prbs31_enable_2, qsfp_rx_prbs31_enable_1}),
.phy_cfg_tx_prbs31_enable({qsfp_cfg_tx_prbs31_enable_4, qsfp_cfg_tx_prbs31_enable_3, qsfp_cfg_tx_prbs31_enable_2, qsfp_cfg_tx_prbs31_enable_1}),
.phy_cfg_rx_prbs31_enable({qsfp_cfg_rx_prbs31_enable_4, qsfp_cfg_rx_prbs31_enable_3, qsfp_cfg_rx_prbs31_enable_2, qsfp_cfg_rx_prbs31_enable_1}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -765,14 +765,14 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp_tx_prbs31_enable_1 = 1'b0;
assign qsfp_rx_prbs31_enable_1 = 1'b0;
assign qsfp_tx_prbs31_enable_2 = 1'b0;
assign qsfp_rx_prbs31_enable_2 = 1'b0;
assign qsfp_tx_prbs31_enable_3 = 1'b0;
assign qsfp_rx_prbs31_enable_3 = 1'b0;
assign qsfp_tx_prbs31_enable_4 = 1'b0;
assign qsfp_rx_prbs31_enable_4 = 1'b0;
assign qsfp_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp_cfg_rx_prbs31_enable_4 = 1'b0;
end
@ -933,7 +933,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

96
fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
View File

@ -917,45 +917,45 @@ wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int;
wire qsfp1_tx_prbs31_enable_1_int;
wire qsfp1_cfg_tx_prbs31_enable_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int;
wire qsfp1_rx_prbs31_enable_1_int;
wire qsfp1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp1_rx_error_count_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int;
wire qsfp1_tx_prbs31_enable_2_int;
wire qsfp1_cfg_tx_prbs31_enable_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int;
wire qsfp1_rx_prbs31_enable_2_int;
wire qsfp1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp1_rx_error_count_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int;
wire qsfp1_tx_prbs31_enable_3_int;
wire qsfp1_cfg_tx_prbs31_enable_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int;
wire qsfp1_rx_prbs31_enable_3_int;
wire qsfp1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp1_rx_error_count_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int;
wire qsfp1_tx_prbs31_enable_4_int;
wire qsfp1_cfg_tx_prbs31_enable_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int;
wire qsfp1_rx_prbs31_enable_4_int;
wire qsfp1_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp1_rx_error_count_4_int;
wire qsfp1_drp_clk = clk_125mhz_int;
@ -1065,8 +1065,8 @@ qsfp1_phy_quad_inst (
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp1_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp1_tx_clk_2_int),
.phy_2_tx_rst(qsfp1_tx_rst_2_int),
@ -1083,8 +1083,8 @@ qsfp1_phy_quad_inst (
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp1_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp1_tx_clk_3_int),
.phy_3_tx_rst(qsfp1_tx_rst_3_int),
@ -1101,8 +1101,8 @@ qsfp1_phy_quad_inst (
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp1_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp1_tx_clk_4_int),
.phy_4_tx_rst(qsfp1_tx_rst_4_int),
@ -1119,8 +1119,8 @@ qsfp1_phy_quad_inst (
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp1_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_4_int)
);
// QSFP2
@ -1128,45 +1128,45 @@ wire qsfp2_tx_clk_1_int;
wire qsfp2_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_1_int;
wire qsfp2_tx_prbs31_enable_1_int;
wire qsfp2_cfg_tx_prbs31_enable_1_int;
wire qsfp2_rx_clk_1_int;
wire qsfp2_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_1_int;
wire qsfp2_rx_prbs31_enable_1_int;
wire qsfp2_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp2_rx_error_count_1_int;
wire qsfp2_tx_clk_2_int;
wire qsfp2_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_2_int;
wire qsfp2_tx_prbs31_enable_2_int;
wire qsfp2_cfg_tx_prbs31_enable_2_int;
wire qsfp2_rx_clk_2_int;
wire qsfp2_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_2_int;
wire qsfp2_rx_prbs31_enable_2_int;
wire qsfp2_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp2_rx_error_count_2_int;
wire qsfp2_tx_clk_3_int;
wire qsfp2_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_3_int;
wire qsfp2_tx_prbs31_enable_3_int;
wire qsfp2_cfg_tx_prbs31_enable_3_int;
wire qsfp2_rx_clk_3_int;
wire qsfp2_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_3_int;
wire qsfp2_rx_prbs31_enable_3_int;
wire qsfp2_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp2_rx_error_count_3_int;
wire qsfp2_tx_clk_4_int;
wire qsfp2_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_4_int;
wire qsfp2_tx_prbs31_enable_4_int;
wire qsfp2_cfg_tx_prbs31_enable_4_int;
wire qsfp2_rx_clk_4_int;
wire qsfp2_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_4_int;
wire qsfp2_rx_prbs31_enable_4_int;
wire qsfp2_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp2_rx_error_count_4_int;
wire qsfp2_drp_clk = clk_125mhz_int;
@ -1241,8 +1241,8 @@ qsfp2_phy_quad_inst (
.phy_1_rx_block_lock(qsfp2_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp2_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp2_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp2_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp2_tx_clk_2_int),
.phy_2_tx_rst(qsfp2_tx_rst_2_int),
@ -1259,8 +1259,8 @@ qsfp2_phy_quad_inst (
.phy_2_rx_block_lock(qsfp2_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp2_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp2_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp2_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp2_tx_clk_3_int),
.phy_3_tx_rst(qsfp2_tx_rst_3_int),
@ -1277,8 +1277,8 @@ qsfp2_phy_quad_inst (
.phy_3_rx_block_lock(qsfp2_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp2_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp2_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp2_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp2_tx_clk_4_int),
.phy_4_tx_rst(qsfp2_tx_rst_4_int),
@ -1295,8 +1295,8 @@ qsfp2_phy_quad_inst (
.phy_4_rx_block_lock(qsfp2_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp2_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp2_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp2_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_4_int)
);
wire ptp_clk;
@ -1890,48 +1890,48 @@ core_inst (
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_tx_prbs31_enable_1(qsfp1_tx_prbs31_enable_1_int),
.qsfp1_cfg_tx_prbs31_enable_1(qsfp1_cfg_tx_prbs31_enable_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_cfg_rx_prbs31_enable_1(qsfp1_cfg_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_status_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_tx_prbs31_enable_2(qsfp1_tx_prbs31_enable_2_int),
.qsfp1_cfg_tx_prbs31_enable_2(qsfp1_cfg_tx_prbs31_enable_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_cfg_rx_prbs31_enable_2(qsfp1_cfg_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_status_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_tx_prbs31_enable_3(qsfp1_tx_prbs31_enable_3_int),
.qsfp1_cfg_tx_prbs31_enable_3(qsfp1_cfg_tx_prbs31_enable_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_cfg_rx_prbs31_enable_3(qsfp1_cfg_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_status_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_tx_prbs31_enable_4(qsfp1_tx_prbs31_enable_4_int),
.qsfp1_cfg_tx_prbs31_enable_4(qsfp1_cfg_tx_prbs31_enable_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_cfg_rx_prbs31_enable_4(qsfp1_cfg_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_status_4),
@ -1954,48 +1954,48 @@ core_inst (
.qsfp2_tx_rst_1(qsfp2_tx_rst_1_int),
.qsfp2_txd_1(qsfp2_txd_1_int),
.qsfp2_txc_1(qsfp2_txc_1_int),
.qsfp2_tx_prbs31_enable_1(qsfp2_tx_prbs31_enable_1_int),
.qsfp2_cfg_tx_prbs31_enable_1(qsfp2_cfg_tx_prbs31_enable_1_int),
.qsfp2_rx_clk_1(qsfp2_rx_clk_1_int),
.qsfp2_rx_rst_1(qsfp2_rx_rst_1_int),
.qsfp2_rxd_1(qsfp2_rxd_1_int),
.qsfp2_rxc_1(qsfp2_rxc_1_int),
.qsfp2_rx_prbs31_enable_1(qsfp2_rx_prbs31_enable_1_int),
.qsfp2_cfg_rx_prbs31_enable_1(qsfp2_cfg_rx_prbs31_enable_1_int),
.qsfp2_rx_error_count_1(qsfp2_rx_error_count_1_int),
.qsfp2_rx_status_1(qsfp2_rx_status_1),
.qsfp2_tx_clk_2(qsfp2_tx_clk_2_int),
.qsfp2_tx_rst_2(qsfp2_tx_rst_2_int),
.qsfp2_txd_2(qsfp2_txd_2_int),
.qsfp2_txc_2(qsfp2_txc_2_int),
.qsfp2_tx_prbs31_enable_2(qsfp2_tx_prbs31_enable_2_int),
.qsfp2_cfg_tx_prbs31_enable_2(qsfp2_cfg_tx_prbs31_enable_2_int),
.qsfp2_rx_clk_2(qsfp2_rx_clk_2_int),
.qsfp2_rx_rst_2(qsfp2_rx_rst_2_int),
.qsfp2_rxd_2(qsfp2_rxd_2_int),
.qsfp2_rxc_2(qsfp2_rxc_2_int),
.qsfp2_rx_prbs31_enable_2(qsfp2_rx_prbs31_enable_2_int),
.qsfp2_cfg_rx_prbs31_enable_2(qsfp2_cfg_rx_prbs31_enable_2_int),
.qsfp2_rx_error_count_2(qsfp2_rx_error_count_2_int),
.qsfp2_rx_status_2(qsfp2_rx_status_2),
.qsfp2_tx_clk_3(qsfp2_tx_clk_3_int),
.qsfp2_tx_rst_3(qsfp2_tx_rst_3_int),
.qsfp2_txd_3(qsfp2_txd_3_int),
.qsfp2_txc_3(qsfp2_txc_3_int),
.qsfp2_tx_prbs31_enable_3(qsfp2_tx_prbs31_enable_3_int),
.qsfp2_cfg_tx_prbs31_enable_3(qsfp2_cfg_tx_prbs31_enable_3_int),
.qsfp2_rx_clk_3(qsfp2_rx_clk_3_int),
.qsfp2_rx_rst_3(qsfp2_rx_rst_3_int),
.qsfp2_rxd_3(qsfp2_rxd_3_int),
.qsfp2_rxc_3(qsfp2_rxc_3_int),
.qsfp2_rx_prbs31_enable_3(qsfp2_rx_prbs31_enable_3_int),
.qsfp2_cfg_rx_prbs31_enable_3(qsfp2_cfg_rx_prbs31_enable_3_int),
.qsfp2_rx_error_count_3(qsfp2_rx_error_count_3_int),
.qsfp2_rx_status_3(qsfp2_rx_status_3),
.qsfp2_tx_clk_4(qsfp2_tx_clk_4_int),
.qsfp2_tx_rst_4(qsfp2_tx_rst_4_int),
.qsfp2_txd_4(qsfp2_txd_4_int),
.qsfp2_txc_4(qsfp2_txc_4_int),
.qsfp2_tx_prbs31_enable_4(qsfp2_tx_prbs31_enable_4_int),
.qsfp2_cfg_tx_prbs31_enable_4(qsfp2_cfg_tx_prbs31_enable_4_int),
.qsfp2_rx_clk_4(qsfp2_rx_clk_4_int),
.qsfp2_rx_rst_4(qsfp2_rx_rst_4_int),
.qsfp2_rxd_4(qsfp2_rxd_4_int),
.qsfp2_rxc_4(qsfp2_rxc_4_int),
.qsfp2_rx_prbs31_enable_4(qsfp2_rx_prbs31_enable_4_int),
.qsfp2_cfg_rx_prbs31_enable_4(qsfp2_cfg_rx_prbs31_enable_4_int),
.qsfp2_rx_error_count_4(qsfp2_rx_error_count_4_int),
.qsfp2_rx_status_4(qsfp2_rx_status_4),

72
fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
View File

@ -288,48 +288,48 @@ module fpga_core #
input wire qsfp1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1,
output wire qsfp1_tx_prbs31_enable_1,
output wire qsfp1_cfg_tx_prbs31_enable_1,
input wire qsfp1_rx_clk_1,
input wire qsfp1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
output wire qsfp1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2,
output wire qsfp1_tx_prbs31_enable_2,
output wire qsfp1_cfg_tx_prbs31_enable_2,
input wire qsfp1_rx_clk_2,
input wire qsfp1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
output wire qsfp1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3,
output wire qsfp1_tx_prbs31_enable_3,
output wire qsfp1_cfg_tx_prbs31_enable_3,
input wire qsfp1_rx_clk_3,
input wire qsfp1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
output wire qsfp1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4,
output wire qsfp1_tx_prbs31_enable_4,
output wire qsfp1_cfg_tx_prbs31_enable_4,
input wire qsfp1_rx_clk_4,
input wire qsfp1_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
output wire qsfp1_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
@ -352,48 +352,48 @@ module fpga_core #
input wire qsfp2_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_1,
output wire qsfp2_tx_prbs31_enable_1,
output wire qsfp2_cfg_tx_prbs31_enable_1,
input wire qsfp2_rx_clk_1,
input wire qsfp2_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_1,
output wire qsfp2_rx_prbs31_enable_1,
output wire qsfp2_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp2_rx_error_count_1,
input wire qsfp2_rx_status_1,
input wire qsfp2_tx_clk_2,
input wire qsfp2_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_2,
output wire qsfp2_tx_prbs31_enable_2,
output wire qsfp2_cfg_tx_prbs31_enable_2,
input wire qsfp2_rx_clk_2,
input wire qsfp2_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_2,
output wire qsfp2_rx_prbs31_enable_2,
output wire qsfp2_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp2_rx_error_count_2,
input wire qsfp2_rx_status_2,
input wire qsfp2_tx_clk_3,
input wire qsfp2_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_3,
output wire qsfp2_tx_prbs31_enable_3,
output wire qsfp2_cfg_tx_prbs31_enable_3,
input wire qsfp2_rx_clk_3,
input wire qsfp2_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_3,
output wire qsfp2_rx_prbs31_enable_3,
output wire qsfp2_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp2_rx_error_count_3,
input wire qsfp2_rx_status_3,
input wire qsfp2_tx_clk_4,
input wire qsfp2_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_4,
output wire qsfp2_tx_prbs31_enable_4,
output wire qsfp2_cfg_tx_prbs31_enable_4,
input wire qsfp2_rx_clk_4,
input wire qsfp2_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_4,
output wire qsfp2_rx_prbs31_enable_4,
output wire qsfp2_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp2_rx_error_count_4,
input wire qsfp2_rx_status_4,
@ -873,8 +873,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp2_tx_clk_4, qsfp2_tx_clk_3, qsfp2_tx_clk_2, qsfp2_tx_clk_1, qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1}),
.phy_rx_clk({qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1}),
.phy_rx_error_count({qsfp2_rx_error_count_4, qsfp2_rx_error_count_3, qsfp2_rx_error_count_2, qsfp2_rx_error_count_1, qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1}),
.phy_tx_prbs31_enable({qsfp2_tx_prbs31_enable_4, qsfp2_tx_prbs31_enable_3, qsfp2_tx_prbs31_enable_2, qsfp2_tx_prbs31_enable_1, qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1}),
.phy_rx_prbs31_enable({qsfp2_rx_prbs31_enable_4, qsfp2_rx_prbs31_enable_3, qsfp2_rx_prbs31_enable_2, qsfp2_rx_prbs31_enable_1, qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1}),
.phy_cfg_tx_prbs31_enable({qsfp2_cfg_tx_prbs31_enable_4, qsfp2_cfg_tx_prbs31_enable_3, qsfp2_cfg_tx_prbs31_enable_2, qsfp2_cfg_tx_prbs31_enable_1, qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1}),
.phy_cfg_rx_prbs31_enable({qsfp2_cfg_rx_prbs31_enable_4, qsfp2_cfg_rx_prbs31_enable_3, qsfp2_cfg_rx_prbs31_enable_2, qsfp2_cfg_rx_prbs31_enable_1, qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -900,22 +900,22 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp1_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_rx_prbs31_enable_4 = 1'b0;
assign qsfp2_tx_prbs31_enable_1 = 1'b0;
assign qsfp2_rx_prbs31_enable_1 = 1'b0;
assign qsfp2_tx_prbs31_enable_2 = 1'b0;
assign qsfp2_rx_prbs31_enable_2 = 1'b0;
assign qsfp2_tx_prbs31_enable_3 = 1'b0;
assign qsfp2_rx_prbs31_enable_3 = 1'b0;
assign qsfp2_tx_prbs31_enable_4 = 1'b0;
assign qsfp2_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_4 = 1'b0;
end
@ -1076,7 +1076,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

96
fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
View File

@ -933,45 +933,45 @@ wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int;
wire qsfp0_tx_prbs31_enable_1_int;
wire qsfp0_cfg_tx_prbs31_enable_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int;
wire qsfp0_rx_prbs31_enable_1_int;
wire qsfp0_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp0_rx_error_count_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int;
wire qsfp0_tx_prbs31_enable_2_int;
wire qsfp0_cfg_tx_prbs31_enable_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int;
wire qsfp0_rx_prbs31_enable_2_int;
wire qsfp0_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp0_rx_error_count_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int;
wire qsfp0_tx_prbs31_enable_3_int;
wire qsfp0_cfg_tx_prbs31_enable_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int;
wire qsfp0_rx_prbs31_enable_3_int;
wire qsfp0_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp0_rx_error_count_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int;
wire qsfp0_tx_prbs31_enable_4_int;
wire qsfp0_cfg_tx_prbs31_enable_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int;
wire qsfp0_rx_prbs31_enable_4_int;
wire qsfp0_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp0_rx_error_count_4_int;
wire qsfp0_drp_clk = clk_125mhz_int;
@ -1083,8 +1083,8 @@ qsfp0_phy_quad_inst (
.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp0_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp0_tx_clk_2_int),
.phy_2_tx_rst(qsfp0_tx_rst_2_int),
@ -1101,8 +1101,8 @@ qsfp0_phy_quad_inst (
.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp0_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp0_tx_clk_3_int),
.phy_3_tx_rst(qsfp0_tx_rst_3_int),
@ -1119,8 +1119,8 @@ qsfp0_phy_quad_inst (
.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp0_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp0_tx_clk_4_int),
.phy_4_tx_rst(qsfp0_tx_rst_4_int),
@ -1137,8 +1137,8 @@ qsfp0_phy_quad_inst (
.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp0_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_4_int)
);
// QSFP1
@ -1149,45 +1149,45 @@ wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int;
wire qsfp1_tx_prbs31_enable_1_int;
wire qsfp1_cfg_tx_prbs31_enable_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int;
wire qsfp1_rx_prbs31_enable_1_int;
wire qsfp1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp1_rx_error_count_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int;
wire qsfp1_tx_prbs31_enable_2_int;
wire qsfp1_cfg_tx_prbs31_enable_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int;
wire qsfp1_rx_prbs31_enable_2_int;
wire qsfp1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp1_rx_error_count_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int;
wire qsfp1_tx_prbs31_enable_3_int;
wire qsfp1_cfg_tx_prbs31_enable_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int;
wire qsfp1_rx_prbs31_enable_3_int;
wire qsfp1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp1_rx_error_count_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int;
wire qsfp1_tx_prbs31_enable_4_int;
wire qsfp1_cfg_tx_prbs31_enable_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int;
wire qsfp1_rx_prbs31_enable_4_int;
wire qsfp1_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp1_rx_error_count_4_int;
wire qsfp1_drp_clk = clk_125mhz_int;
@ -1297,8 +1297,8 @@ qsfp1_phy_quad_inst (
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp1_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp1_tx_clk_2_int),
.phy_2_tx_rst(qsfp1_tx_rst_2_int),
@ -1315,8 +1315,8 @@ qsfp1_phy_quad_inst (
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp1_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp1_tx_clk_3_int),
.phy_3_tx_rst(qsfp1_tx_rst_3_int),
@ -1333,8 +1333,8 @@ qsfp1_phy_quad_inst (
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp1_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp1_tx_clk_4_int),
.phy_4_tx_rst(qsfp1_tx_rst_4_int),
@ -1351,8 +1351,8 @@ qsfp1_phy_quad_inst (
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp1_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_4_int)
);
wire ptp_clk;
@ -2177,48 +2177,48 @@ core_inst (
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_tx_prbs31_enable_1(qsfp0_tx_prbs31_enable_1_int),
.qsfp0_cfg_tx_prbs31_enable_1(qsfp0_cfg_tx_prbs31_enable_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
.qsfp0_cfg_rx_prbs31_enable_1(qsfp0_cfg_rx_prbs31_enable_1_int),
.qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
.qsfp0_rx_status_1(qsfp0_rx_status_1),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_tx_prbs31_enable_2(qsfp0_tx_prbs31_enable_2_int),
.qsfp0_cfg_tx_prbs31_enable_2(qsfp0_cfg_tx_prbs31_enable_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
.qsfp0_cfg_rx_prbs31_enable_2(qsfp0_cfg_rx_prbs31_enable_2_int),
.qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
.qsfp0_rx_status_2(qsfp0_rx_status_2),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_tx_prbs31_enable_3(qsfp0_tx_prbs31_enable_3_int),
.qsfp0_cfg_tx_prbs31_enable_3(qsfp0_cfg_tx_prbs31_enable_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
.qsfp0_cfg_rx_prbs31_enable_3(qsfp0_cfg_rx_prbs31_enable_3_int),
.qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
.qsfp0_rx_status_3(qsfp0_rx_status_3),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_tx_prbs31_enable_4(qsfp0_tx_prbs31_enable_4_int),
.qsfp0_cfg_tx_prbs31_enable_4(qsfp0_cfg_tx_prbs31_enable_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
.qsfp0_cfg_rx_prbs31_enable_4(qsfp0_cfg_rx_prbs31_enable_4_int),
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_status_4),
@ -2241,48 +2241,48 @@ core_inst (
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_tx_prbs31_enable_1(qsfp1_tx_prbs31_enable_1_int),
.qsfp1_cfg_tx_prbs31_enable_1(qsfp1_cfg_tx_prbs31_enable_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_cfg_rx_prbs31_enable_1(qsfp1_cfg_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_status_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_tx_prbs31_enable_2(qsfp1_tx_prbs31_enable_2_int),
.qsfp1_cfg_tx_prbs31_enable_2(qsfp1_cfg_tx_prbs31_enable_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_cfg_rx_prbs31_enable_2(qsfp1_cfg_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_status_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_tx_prbs31_enable_3(qsfp1_tx_prbs31_enable_3_int),
.qsfp1_cfg_tx_prbs31_enable_3(qsfp1_cfg_tx_prbs31_enable_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_cfg_rx_prbs31_enable_3(qsfp1_cfg_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_status_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_tx_prbs31_enable_4(qsfp1_tx_prbs31_enable_4_int),
.qsfp1_cfg_tx_prbs31_enable_4(qsfp1_cfg_tx_prbs31_enable_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_cfg_rx_prbs31_enable_4(qsfp1_cfg_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_status_4),

72
fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
View File

@ -281,48 +281,48 @@ module fpga_core #
input wire qsfp0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1,
output wire qsfp0_tx_prbs31_enable_1,
output wire qsfp0_cfg_tx_prbs31_enable_1,
input wire qsfp0_rx_clk_1,
input wire qsfp0_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1,
output wire qsfp0_rx_prbs31_enable_1,
output wire qsfp0_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp0_rx_error_count_1,
input wire qsfp0_rx_status_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2,
output wire qsfp0_tx_prbs31_enable_2,
output wire qsfp0_cfg_tx_prbs31_enable_2,
input wire qsfp0_rx_clk_2,
input wire qsfp0_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2,
output wire qsfp0_rx_prbs31_enable_2,
output wire qsfp0_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp0_rx_error_count_2,
input wire qsfp0_rx_status_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3,
output wire qsfp0_tx_prbs31_enable_3,
output wire qsfp0_cfg_tx_prbs31_enable_3,
input wire qsfp0_rx_clk_3,
input wire qsfp0_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3,
output wire qsfp0_rx_prbs31_enable_3,
output wire qsfp0_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp0_rx_error_count_3,
input wire qsfp0_rx_status_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4,
output wire qsfp0_tx_prbs31_enable_4,
output wire qsfp0_cfg_tx_prbs31_enable_4,
input wire qsfp0_rx_clk_4,
input wire qsfp0_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4,
output wire qsfp0_rx_prbs31_enable_4,
output wire qsfp0_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
@ -345,48 +345,48 @@ module fpga_core #
input wire qsfp1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1,
output wire qsfp1_tx_prbs31_enable_1,
output wire qsfp1_cfg_tx_prbs31_enable_1,
input wire qsfp1_rx_clk_1,
input wire qsfp1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
output wire qsfp1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2,
output wire qsfp1_tx_prbs31_enable_2,
output wire qsfp1_cfg_tx_prbs31_enable_2,
input wire qsfp1_rx_clk_2,
input wire qsfp1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
output wire qsfp1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3,
output wire qsfp1_tx_prbs31_enable_3,
output wire qsfp1_cfg_tx_prbs31_enable_3,
input wire qsfp1_rx_clk_3,
input wire qsfp1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
output wire qsfp1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4,
output wire qsfp1_tx_prbs31_enable_4,
output wire qsfp1_cfg_tx_prbs31_enable_4,
input wire qsfp1_rx_clk_4,
input wire qsfp1_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
output wire qsfp1_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
@ -833,8 +833,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}),
.phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
.phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}),
.phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}),
.phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}),
.phy_cfg_tx_prbs31_enable({qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1, qsfp0_cfg_tx_prbs31_enable_4, qsfp0_cfg_tx_prbs31_enable_3, qsfp0_cfg_tx_prbs31_enable_2, qsfp0_cfg_tx_prbs31_enable_1}),
.phy_cfg_rx_prbs31_enable({qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1, qsfp0_cfg_rx_prbs31_enable_4, qsfp0_cfg_rx_prbs31_enable_3, qsfp0_cfg_rx_prbs31_enable_2, qsfp0_cfg_rx_prbs31_enable_1}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -860,22 +860,22 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp0_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_rx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0;
end
@ -1031,7 +1031,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

192
fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v
View File

@ -1025,45 +1025,45 @@ wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int;
wire qsfp0_tx_prbs31_enable_1_int;
wire qsfp0_cfg_tx_prbs31_enable_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int;
wire qsfp0_rx_prbs31_enable_1_int;
wire qsfp0_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp0_rx_error_count_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int;
wire qsfp0_tx_prbs31_enable_2_int;
wire qsfp0_cfg_tx_prbs31_enable_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int;
wire qsfp0_rx_prbs31_enable_2_int;
wire qsfp0_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp0_rx_error_count_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int;
wire qsfp0_tx_prbs31_enable_3_int;
wire qsfp0_cfg_tx_prbs31_enable_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int;
wire qsfp0_rx_prbs31_enable_3_int;
wire qsfp0_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp0_rx_error_count_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int;
wire qsfp0_tx_prbs31_enable_4_int;
wire qsfp0_cfg_tx_prbs31_enable_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int;
wire qsfp0_rx_prbs31_enable_4_int;
wire qsfp0_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp0_rx_error_count_4_int;
wire qsfp0_drp_clk = clk_125mhz_int;
@ -1173,8 +1173,8 @@ qsfp0_phy_quad_inst (
.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp0_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp0_tx_clk_2_int),
.phy_2_tx_rst(qsfp0_tx_rst_2_int),
@ -1191,8 +1191,8 @@ qsfp0_phy_quad_inst (
.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp0_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp0_tx_clk_3_int),
.phy_3_tx_rst(qsfp0_tx_rst_3_int),
@ -1209,8 +1209,8 @@ qsfp0_phy_quad_inst (
.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp0_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp0_tx_clk_4_int),
.phy_4_tx_rst(qsfp0_tx_rst_4_int),
@ -1227,8 +1227,8 @@ qsfp0_phy_quad_inst (
.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp0_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_4_int)
);
// QSFP1
@ -1236,45 +1236,45 @@ wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int;
wire qsfp1_tx_prbs31_enable_1_int;
wire qsfp1_cfg_tx_prbs31_enable_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int;
wire qsfp1_rx_prbs31_enable_1_int;
wire qsfp1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp1_rx_error_count_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int;
wire qsfp1_tx_prbs31_enable_2_int;
wire qsfp1_cfg_tx_prbs31_enable_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int;
wire qsfp1_rx_prbs31_enable_2_int;
wire qsfp1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp1_rx_error_count_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int;
wire qsfp1_tx_prbs31_enable_3_int;
wire qsfp1_cfg_tx_prbs31_enable_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int;
wire qsfp1_rx_prbs31_enable_3_int;
wire qsfp1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp1_rx_error_count_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int;
wire qsfp1_tx_prbs31_enable_4_int;
wire qsfp1_cfg_tx_prbs31_enable_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int;
wire qsfp1_rx_prbs31_enable_4_int;
wire qsfp1_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp1_rx_error_count_4_int;
wire qsfp1_drp_clk = clk_125mhz_int;
@ -1384,8 +1384,8 @@ qsfp1_phy_quad_inst (
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp1_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp1_tx_clk_2_int),
.phy_2_tx_rst(qsfp1_tx_rst_2_int),
@ -1402,8 +1402,8 @@ qsfp1_phy_quad_inst (
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp1_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp1_tx_clk_3_int),
.phy_3_tx_rst(qsfp1_tx_rst_3_int),
@ -1420,8 +1420,8 @@ qsfp1_phy_quad_inst (
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp1_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp1_tx_clk_4_int),
.phy_4_tx_rst(qsfp1_tx_rst_4_int),
@ -1438,8 +1438,8 @@ qsfp1_phy_quad_inst (
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp1_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_4_int)
);
// QSFP2
@ -1447,45 +1447,45 @@ wire qsfp2_tx_clk_1_int;
wire qsfp2_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_1_int;
wire qsfp2_tx_prbs31_enable_1_int;
wire qsfp2_cfg_tx_prbs31_enable_1_int;
wire qsfp2_rx_clk_1_int;
wire qsfp2_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_1_int;
wire qsfp2_rx_prbs31_enable_1_int;
wire qsfp2_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp2_rx_error_count_1_int;
wire qsfp2_tx_clk_2_int;
wire qsfp2_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_2_int;
wire qsfp2_tx_prbs31_enable_2_int;
wire qsfp2_cfg_tx_prbs31_enable_2_int;
wire qsfp2_rx_clk_2_int;
wire qsfp2_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_2_int;
wire qsfp2_rx_prbs31_enable_2_int;
wire qsfp2_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp2_rx_error_count_2_int;
wire qsfp2_tx_clk_3_int;
wire qsfp2_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_3_int;
wire qsfp2_tx_prbs31_enable_3_int;
wire qsfp2_cfg_tx_prbs31_enable_3_int;
wire qsfp2_rx_clk_3_int;
wire qsfp2_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_3_int;
wire qsfp2_rx_prbs31_enable_3_int;
wire qsfp2_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp2_rx_error_count_3_int;
wire qsfp2_tx_clk_4_int;
wire qsfp2_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_4_int;
wire qsfp2_tx_prbs31_enable_4_int;
wire qsfp2_cfg_tx_prbs31_enable_4_int;
wire qsfp2_rx_clk_4_int;
wire qsfp2_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_4_int;
wire qsfp2_rx_prbs31_enable_4_int;
wire qsfp2_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp2_rx_error_count_4_int;
wire qsfp2_drp_clk = clk_125mhz_int;
@ -1595,8 +1595,8 @@ qsfp2_phy_quad_inst (
.phy_1_rx_block_lock(qsfp2_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp2_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp2_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp2_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp2_tx_clk_2_int),
.phy_2_tx_rst(qsfp2_tx_rst_2_int),
@ -1613,8 +1613,8 @@ qsfp2_phy_quad_inst (
.phy_2_rx_block_lock(qsfp2_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp2_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp2_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp2_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp2_tx_clk_3_int),
.phy_3_tx_rst(qsfp2_tx_rst_3_int),
@ -1631,8 +1631,8 @@ qsfp2_phy_quad_inst (
.phy_3_rx_block_lock(qsfp2_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp2_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp2_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp2_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp2_tx_clk_4_int),
.phy_4_tx_rst(qsfp2_tx_rst_4_int),
@ -1649,8 +1649,8 @@ qsfp2_phy_quad_inst (
.phy_4_rx_block_lock(qsfp2_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp2_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp2_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp2_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_4_int)
);
// QSFP3
@ -1658,45 +1658,45 @@ wire qsfp3_tx_clk_1_int;
wire qsfp3_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_1_int;
wire qsfp3_tx_prbs31_enable_1_int;
wire qsfp3_cfg_tx_prbs31_enable_1_int;
wire qsfp3_rx_clk_1_int;
wire qsfp3_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_1_int;
wire qsfp3_rx_prbs31_enable_1_int;
wire qsfp3_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp3_rx_error_count_1_int;
wire qsfp3_tx_clk_2_int;
wire qsfp3_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_2_int;
wire qsfp3_tx_prbs31_enable_2_int;
wire qsfp3_cfg_tx_prbs31_enable_2_int;
wire qsfp3_rx_clk_2_int;
wire qsfp3_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_2_int;
wire qsfp3_rx_prbs31_enable_2_int;
wire qsfp3_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp3_rx_error_count_2_int;
wire qsfp3_tx_clk_3_int;
wire qsfp3_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_3_int;
wire qsfp3_tx_prbs31_enable_3_int;
wire qsfp3_cfg_tx_prbs31_enable_3_int;
wire qsfp3_rx_clk_3_int;
wire qsfp3_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_3_int;
wire qsfp3_rx_prbs31_enable_3_int;
wire qsfp3_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp3_rx_error_count_3_int;
wire qsfp3_tx_clk_4_int;
wire qsfp3_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_4_int;
wire qsfp3_tx_prbs31_enable_4_int;
wire qsfp3_cfg_tx_prbs31_enable_4_int;
wire qsfp3_rx_clk_4_int;
wire qsfp3_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_4_int;
wire qsfp3_rx_prbs31_enable_4_int;
wire qsfp3_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp3_rx_error_count_4_int;
wire qsfp3_drp_clk = clk_125mhz_int;
@ -1806,8 +1806,8 @@ qsfp3_phy_quad_inst (
.phy_1_rx_block_lock(qsfp3_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp3_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp3_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp3_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp3_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp3_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp3_tx_clk_2_int),
.phy_2_tx_rst(qsfp3_tx_rst_2_int),
@ -1824,8 +1824,8 @@ qsfp3_phy_quad_inst (
.phy_2_rx_block_lock(qsfp3_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp3_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp3_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp3_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp3_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp3_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp3_tx_clk_3_int),
.phy_3_tx_rst(qsfp3_tx_rst_3_int),
@ -1842,8 +1842,8 @@ qsfp3_phy_quad_inst (
.phy_3_rx_block_lock(qsfp3_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp3_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp3_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp3_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp3_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp3_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp3_tx_clk_4_int),
.phy_4_tx_rst(qsfp3_tx_rst_4_int),
@ -1860,8 +1860,8 @@ qsfp3_phy_quad_inst (
.phy_4_rx_block_lock(qsfp3_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp3_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp3_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp3_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp3_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp3_cfg_rx_prbs31_enable_4_int)
);
wire ptp_clk;
@ -2687,48 +2687,48 @@ core_inst (
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_tx_prbs31_enable_1(qsfp0_tx_prbs31_enable_1_int),
.qsfp0_cfg_tx_prbs31_enable_1(qsfp0_cfg_tx_prbs31_enable_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
.qsfp0_cfg_rx_prbs31_enable_1(qsfp0_cfg_rx_prbs31_enable_1_int),
.qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
.qsfp0_rx_status_1(qsfp0_rx_status_1),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_tx_prbs31_enable_2(qsfp0_tx_prbs31_enable_2_int),
.qsfp0_cfg_tx_prbs31_enable_2(qsfp0_cfg_tx_prbs31_enable_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
.qsfp0_cfg_rx_prbs31_enable_2(qsfp0_cfg_rx_prbs31_enable_2_int),
.qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
.qsfp0_rx_status_2(qsfp0_rx_status_2),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_tx_prbs31_enable_3(qsfp0_tx_prbs31_enable_3_int),
.qsfp0_cfg_tx_prbs31_enable_3(qsfp0_cfg_tx_prbs31_enable_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
.qsfp0_cfg_rx_prbs31_enable_3(qsfp0_cfg_rx_prbs31_enable_3_int),
.qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
.qsfp0_rx_status_3(qsfp0_rx_status_3),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_tx_prbs31_enable_4(qsfp0_tx_prbs31_enable_4_int),
.qsfp0_cfg_tx_prbs31_enable_4(qsfp0_cfg_tx_prbs31_enable_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
.qsfp0_cfg_rx_prbs31_enable_4(qsfp0_cfg_rx_prbs31_enable_4_int),
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_status_4),
@ -2757,48 +2757,48 @@ core_inst (
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_tx_prbs31_enable_1(qsfp1_tx_prbs31_enable_1_int),
.qsfp1_cfg_tx_prbs31_enable_1(qsfp1_cfg_tx_prbs31_enable_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_cfg_rx_prbs31_enable_1(qsfp1_cfg_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_status_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_tx_prbs31_enable_2(qsfp1_tx_prbs31_enable_2_int),
.qsfp1_cfg_tx_prbs31_enable_2(qsfp1_cfg_tx_prbs31_enable_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_cfg_rx_prbs31_enable_2(qsfp1_cfg_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_status_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_tx_prbs31_enable_3(qsfp1_tx_prbs31_enable_3_int),
.qsfp1_cfg_tx_prbs31_enable_3(qsfp1_cfg_tx_prbs31_enable_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_cfg_rx_prbs31_enable_3(qsfp1_cfg_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_status_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_tx_prbs31_enable_4(qsfp1_tx_prbs31_enable_4_int),
.qsfp1_cfg_tx_prbs31_enable_4(qsfp1_cfg_tx_prbs31_enable_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_cfg_rx_prbs31_enable_4(qsfp1_cfg_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_status_4),
@ -2827,48 +2827,48 @@ core_inst (
.qsfp2_tx_rst_1(qsfp2_tx_rst_1_int),
.qsfp2_txd_1(qsfp2_txd_1_int),
.qsfp2_txc_1(qsfp2_txc_1_int),
.qsfp2_tx_prbs31_enable_1(qsfp2_tx_prbs31_enable_1_int),
.qsfp2_cfg_tx_prbs31_enable_1(qsfp2_cfg_tx_prbs31_enable_1_int),
.qsfp2_rx_clk_1(qsfp2_rx_clk_1_int),
.qsfp2_rx_rst_1(qsfp2_rx_rst_1_int),
.qsfp2_rxd_1(qsfp2_rxd_1_int),
.qsfp2_rxc_1(qsfp2_rxc_1_int),
.qsfp2_rx_prbs31_enable_1(qsfp2_rx_prbs31_enable_1_int),
.qsfp2_cfg_rx_prbs31_enable_1(qsfp2_cfg_rx_prbs31_enable_1_int),
.qsfp2_rx_error_count_1(qsfp2_rx_error_count_1_int),
.qsfp2_rx_status_1(qsfp2_rx_status_1),
.qsfp2_tx_clk_2(qsfp2_tx_clk_2_int),
.qsfp2_tx_rst_2(qsfp2_tx_rst_2_int),
.qsfp2_txd_2(qsfp2_txd_2_int),
.qsfp2_txc_2(qsfp2_txc_2_int),
.qsfp2_tx_prbs31_enable_2(qsfp2_tx_prbs31_enable_2_int),
.qsfp2_cfg_tx_prbs31_enable_2(qsfp2_cfg_tx_prbs31_enable_2_int),
.qsfp2_rx_clk_2(qsfp2_rx_clk_2_int),
.qsfp2_rx_rst_2(qsfp2_rx_rst_2_int),
.qsfp2_rxd_2(qsfp2_rxd_2_int),
.qsfp2_rxc_2(qsfp2_rxc_2_int),
.qsfp2_rx_prbs31_enable_2(qsfp2_rx_prbs31_enable_2_int),
.qsfp2_cfg_rx_prbs31_enable_2(qsfp2_cfg_rx_prbs31_enable_2_int),
.qsfp2_rx_error_count_2(qsfp2_rx_error_count_2_int),
.qsfp2_rx_status_2(qsfp2_rx_status_2),
.qsfp2_tx_clk_3(qsfp2_tx_clk_3_int),
.qsfp2_tx_rst_3(qsfp2_tx_rst_3_int),
.qsfp2_txd_3(qsfp2_txd_3_int),
.qsfp2_txc_3(qsfp2_txc_3_int),
.qsfp2_tx_prbs31_enable_3(qsfp2_tx_prbs31_enable_3_int),
.qsfp2_cfg_tx_prbs31_enable_3(qsfp2_cfg_tx_prbs31_enable_3_int),
.qsfp2_rx_clk_3(qsfp2_rx_clk_3_int),
.qsfp2_rx_rst_3(qsfp2_rx_rst_3_int),
.qsfp2_rxd_3(qsfp2_rxd_3_int),
.qsfp2_rxc_3(qsfp2_rxc_3_int),
.qsfp2_rx_prbs31_enable_3(qsfp2_rx_prbs31_enable_3_int),
.qsfp2_cfg_rx_prbs31_enable_3(qsfp2_cfg_rx_prbs31_enable_3_int),
.qsfp2_rx_error_count_3(qsfp2_rx_error_count_3_int),
.qsfp2_rx_status_3(qsfp2_rx_status_3),
.qsfp2_tx_clk_4(qsfp2_tx_clk_4_int),
.qsfp2_tx_rst_4(qsfp2_tx_rst_4_int),
.qsfp2_txd_4(qsfp2_txd_4_int),
.qsfp2_txc_4(qsfp2_txc_4_int),
.qsfp2_tx_prbs31_enable_4(qsfp2_tx_prbs31_enable_4_int),
.qsfp2_cfg_tx_prbs31_enable_4(qsfp2_cfg_tx_prbs31_enable_4_int),
.qsfp2_rx_clk_4(qsfp2_rx_clk_4_int),
.qsfp2_rx_rst_4(qsfp2_rx_rst_4_int),
.qsfp2_rxd_4(qsfp2_rxd_4_int),
.qsfp2_rxc_4(qsfp2_rxc_4_int),
.qsfp2_rx_prbs31_enable_4(qsfp2_rx_prbs31_enable_4_int),
.qsfp2_cfg_rx_prbs31_enable_4(qsfp2_cfg_rx_prbs31_enable_4_int),
.qsfp2_rx_error_count_4(qsfp2_rx_error_count_4_int),
.qsfp2_rx_status_4(qsfp2_rx_status_4),
@ -2897,48 +2897,48 @@ core_inst (
.qsfp3_tx_rst_1(qsfp3_tx_rst_1_int),
.qsfp3_txd_1(qsfp3_txd_1_int),
.qsfp3_txc_1(qsfp3_txc_1_int),
.qsfp3_tx_prbs31_enable_1(qsfp3_tx_prbs31_enable_1_int),
.qsfp3_cfg_tx_prbs31_enable_1(qsfp3_cfg_tx_prbs31_enable_1_int),
.qsfp3_rx_clk_1(qsfp3_rx_clk_1_int),
.qsfp3_rx_rst_1(qsfp3_rx_rst_1_int),
.qsfp3_rxd_1(qsfp3_rxd_1_int),
.qsfp3_rxc_1(qsfp3_rxc_1_int),
.qsfp3_rx_prbs31_enable_1(qsfp3_rx_prbs31_enable_1_int),
.qsfp3_cfg_rx_prbs31_enable_1(qsfp3_cfg_rx_prbs31_enable_1_int),
.qsfp3_rx_error_count_1(qsfp3_rx_error_count_1_int),
.qsfp3_rx_status_1(qsfp3_rx_status_1),
.qsfp3_tx_clk_2(qsfp3_tx_clk_2_int),
.qsfp3_tx_rst_2(qsfp3_tx_rst_2_int),
.qsfp3_txd_2(qsfp3_txd_2_int),
.qsfp3_txc_2(qsfp3_txc_2_int),
.qsfp3_tx_prbs31_enable_2(qsfp3_tx_prbs31_enable_2_int),
.qsfp3_cfg_tx_prbs31_enable_2(qsfp3_cfg_tx_prbs31_enable_2_int),
.qsfp3_rx_clk_2(qsfp3_rx_clk_2_int),
.qsfp3_rx_rst_2(qsfp3_rx_rst_2_int),
.qsfp3_rxd_2(qsfp3_rxd_2_int),
.qsfp3_rxc_2(qsfp3_rxc_2_int),
.qsfp3_rx_prbs31_enable_2(qsfp3_rx_prbs31_enable_2_int),
.qsfp3_cfg_rx_prbs31_enable_2(qsfp3_cfg_rx_prbs31_enable_2_int),
.qsfp3_rx_error_count_2(qsfp3_rx_error_count_2_int),
.qsfp3_rx_status_2(qsfp3_rx_status_2),
.qsfp3_tx_clk_3(qsfp3_tx_clk_3_int),
.qsfp3_tx_rst_3(qsfp3_tx_rst_3_int),
.qsfp3_txd_3(qsfp3_txd_3_int),
.qsfp3_txc_3(qsfp3_txc_3_int),
.qsfp3_tx_prbs31_enable_3(qsfp3_tx_prbs31_enable_3_int),
.qsfp3_cfg_tx_prbs31_enable_3(qsfp3_cfg_tx_prbs31_enable_3_int),
.qsfp3_rx_clk_3(qsfp3_rx_clk_3_int),
.qsfp3_rx_rst_3(qsfp3_rx_rst_3_int),
.qsfp3_rxd_3(qsfp3_rxd_3_int),
.qsfp3_rxc_3(qsfp3_rxc_3_int),
.qsfp3_rx_prbs31_enable_3(qsfp3_rx_prbs31_enable_3_int),
.qsfp3_cfg_rx_prbs31_enable_3(qsfp3_cfg_rx_prbs31_enable_3_int),
.qsfp3_rx_error_count_3(qsfp3_rx_error_count_3_int),
.qsfp3_rx_status_3(qsfp3_rx_status_3),
.qsfp3_tx_clk_4(qsfp3_tx_clk_4_int),
.qsfp3_tx_rst_4(qsfp3_tx_rst_4_int),
.qsfp3_txd_4(qsfp3_txd_4_int),
.qsfp3_txc_4(qsfp3_txc_4_int),
.qsfp3_tx_prbs31_enable_4(qsfp3_tx_prbs31_enable_4_int),
.qsfp3_cfg_tx_prbs31_enable_4(qsfp3_cfg_tx_prbs31_enable_4_int),
.qsfp3_rx_clk_4(qsfp3_rx_clk_4_int),
.qsfp3_rx_rst_4(qsfp3_rx_rst_4_int),
.qsfp3_rxd_4(qsfp3_rxd_4_int),
.qsfp3_rxc_4(qsfp3_rxc_4_int),
.qsfp3_rx_prbs31_enable_4(qsfp3_rx_prbs31_enable_4_int),
.qsfp3_cfg_rx_prbs31_enable_4(qsfp3_cfg_rx_prbs31_enable_4_int),
.qsfp3_rx_error_count_4(qsfp3_rx_error_count_4_int),
.qsfp3_rx_status_4(qsfp3_rx_status_4),

136
fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
View File

@ -282,48 +282,48 @@ module fpga_core #
input wire qsfp0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1,
output wire qsfp0_tx_prbs31_enable_1,
output wire qsfp0_cfg_tx_prbs31_enable_1,
input wire qsfp0_rx_clk_1,
input wire qsfp0_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1,
output wire qsfp0_rx_prbs31_enable_1,
output wire qsfp0_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp0_rx_error_count_1,
input wire qsfp0_rx_status_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2,
output wire qsfp0_tx_prbs31_enable_2,
output wire qsfp0_cfg_tx_prbs31_enable_2,
input wire qsfp0_rx_clk_2,
input wire qsfp0_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2,
output wire qsfp0_rx_prbs31_enable_2,
output wire qsfp0_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp0_rx_error_count_2,
input wire qsfp0_rx_status_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3,
output wire qsfp0_tx_prbs31_enable_3,
output wire qsfp0_cfg_tx_prbs31_enable_3,
input wire qsfp0_rx_clk_3,
input wire qsfp0_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3,
output wire qsfp0_rx_prbs31_enable_3,
output wire qsfp0_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp0_rx_error_count_3,
input wire qsfp0_rx_status_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4,
output wire qsfp0_tx_prbs31_enable_4,
output wire qsfp0_cfg_tx_prbs31_enable_4,
input wire qsfp0_rx_clk_4,
input wire qsfp0_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4,
output wire qsfp0_rx_prbs31_enable_4,
output wire qsfp0_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
@ -352,48 +352,48 @@ module fpga_core #
input wire qsfp1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1,
output wire qsfp1_tx_prbs31_enable_1,
output wire qsfp1_cfg_tx_prbs31_enable_1,
input wire qsfp1_rx_clk_1,
input wire qsfp1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
output wire qsfp1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2,
output wire qsfp1_tx_prbs31_enable_2,
output wire qsfp1_cfg_tx_prbs31_enable_2,
input wire qsfp1_rx_clk_2,
input wire qsfp1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
output wire qsfp1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3,
output wire qsfp1_tx_prbs31_enable_3,
output wire qsfp1_cfg_tx_prbs31_enable_3,
input wire qsfp1_rx_clk_3,
input wire qsfp1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
output wire qsfp1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4,
output wire qsfp1_tx_prbs31_enable_4,
output wire qsfp1_cfg_tx_prbs31_enable_4,
input wire qsfp1_rx_clk_4,
input wire qsfp1_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
output wire qsfp1_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
@ -422,48 +422,48 @@ module fpga_core #
input wire qsfp2_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_1,
output wire qsfp2_tx_prbs31_enable_1,
output wire qsfp2_cfg_tx_prbs31_enable_1,
input wire qsfp2_rx_clk_1,
input wire qsfp2_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_1,
output wire qsfp2_rx_prbs31_enable_1,
output wire qsfp2_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp2_rx_error_count_1,
input wire qsfp2_rx_status_1,
input wire qsfp2_tx_clk_2,
input wire qsfp2_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_2,
output wire qsfp2_tx_prbs31_enable_2,
output wire qsfp2_cfg_tx_prbs31_enable_2,
input wire qsfp2_rx_clk_2,
input wire qsfp2_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_2,
output wire qsfp2_rx_prbs31_enable_2,
output wire qsfp2_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp2_rx_error_count_2,
input wire qsfp2_rx_status_2,
input wire qsfp2_tx_clk_3,
input wire qsfp2_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_3,
output wire qsfp2_tx_prbs31_enable_3,
output wire qsfp2_cfg_tx_prbs31_enable_3,
input wire qsfp2_rx_clk_3,
input wire qsfp2_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_3,
output wire qsfp2_rx_prbs31_enable_3,
output wire qsfp2_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp2_rx_error_count_3,
input wire qsfp2_rx_status_3,
input wire qsfp2_tx_clk_4,
input wire qsfp2_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_4,
output wire qsfp2_tx_prbs31_enable_4,
output wire qsfp2_cfg_tx_prbs31_enable_4,
input wire qsfp2_rx_clk_4,
input wire qsfp2_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_4,
output wire qsfp2_rx_prbs31_enable_4,
output wire qsfp2_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp2_rx_error_count_4,
input wire qsfp2_rx_status_4,
@ -492,48 +492,48 @@ module fpga_core #
input wire qsfp3_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_1,
output wire qsfp3_tx_prbs31_enable_1,
output wire qsfp3_cfg_tx_prbs31_enable_1,
input wire qsfp3_rx_clk_1,
input wire qsfp3_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_1,
output wire qsfp3_rx_prbs31_enable_1,
output wire qsfp3_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp3_rx_error_count_1,
input wire qsfp3_rx_status_1,
input wire qsfp3_tx_clk_2,
input wire qsfp3_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_2,
output wire qsfp3_tx_prbs31_enable_2,
output wire qsfp3_cfg_tx_prbs31_enable_2,
input wire qsfp3_rx_clk_2,
input wire qsfp3_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_2,
output wire qsfp3_rx_prbs31_enable_2,
output wire qsfp3_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp3_rx_error_count_2,
input wire qsfp3_rx_status_2,
input wire qsfp3_tx_clk_3,
input wire qsfp3_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_3,
output wire qsfp3_tx_prbs31_enable_3,
output wire qsfp3_cfg_tx_prbs31_enable_3,
input wire qsfp3_rx_clk_3,
input wire qsfp3_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_3,
output wire qsfp3_rx_prbs31_enable_3,
output wire qsfp3_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp3_rx_error_count_3,
input wire qsfp3_rx_status_3,
input wire qsfp3_tx_clk_4,
input wire qsfp3_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_4,
output wire qsfp3_tx_prbs31_enable_4,
output wire qsfp3_cfg_tx_prbs31_enable_4,
input wire qsfp3_rx_clk_4,
input wire qsfp3_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_4,
output wire qsfp3_rx_prbs31_enable_4,
output wire qsfp3_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp3_rx_error_count_4,
input wire qsfp3_rx_status_4,
@ -1237,8 +1237,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp3_tx_clk_4, qsfp3_tx_clk_3, qsfp3_tx_clk_2, qsfp3_tx_clk_1, qsfp2_tx_clk_4, qsfp2_tx_clk_3, qsfp2_tx_clk_2, qsfp2_tx_clk_1, qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}),
.phy_rx_clk({qsfp3_rx_clk_4, qsfp3_rx_clk_3, qsfp3_rx_clk_2, qsfp3_rx_clk_1, qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
.phy_rx_error_count({qsfp3_rx_error_count_4, qsfp3_rx_error_count_3, qsfp3_rx_error_count_2, qsfp3_rx_error_count_1, qsfp2_rx_error_count_4, qsfp2_rx_error_count_3, qsfp2_rx_error_count_2, qsfp2_rx_error_count_1, qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}),
.phy_tx_prbs31_enable({qsfp3_tx_prbs31_enable_4, qsfp3_tx_prbs31_enable_3, qsfp3_tx_prbs31_enable_2, qsfp3_tx_prbs31_enable_1, qsfp2_tx_prbs31_enable_4, qsfp2_tx_prbs31_enable_3, qsfp2_tx_prbs31_enable_2, qsfp2_tx_prbs31_enable_1, qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}),
.phy_rx_prbs31_enable({qsfp3_rx_prbs31_enable_4, qsfp3_rx_prbs31_enable_3, qsfp3_rx_prbs31_enable_2, qsfp3_rx_prbs31_enable_1, qsfp2_rx_prbs31_enable_4, qsfp2_rx_prbs31_enable_3, qsfp2_rx_prbs31_enable_2, qsfp2_rx_prbs31_enable_1, qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}),
.phy_cfg_tx_prbs31_enable({qsfp3_cfg_tx_prbs31_enable_4, qsfp3_cfg_tx_prbs31_enable_3, qsfp3_cfg_tx_prbs31_enable_2, qsfp3_cfg_tx_prbs31_enable_1, qsfp2_cfg_tx_prbs31_enable_4, qsfp2_cfg_tx_prbs31_enable_3, qsfp2_cfg_tx_prbs31_enable_2, qsfp2_cfg_tx_prbs31_enable_1, qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1, qsfp0_cfg_tx_prbs31_enable_4, qsfp0_cfg_tx_prbs31_enable_3, qsfp0_cfg_tx_prbs31_enable_2, qsfp0_cfg_tx_prbs31_enable_1}),
.phy_cfg_rx_prbs31_enable({qsfp3_cfg_rx_prbs31_enable_4, qsfp3_cfg_rx_prbs31_enable_3, qsfp3_cfg_rx_prbs31_enable_2, qsfp3_cfg_rx_prbs31_enable_1, qsfp2_cfg_rx_prbs31_enable_4, qsfp2_cfg_rx_prbs31_enable_3, qsfp2_cfg_rx_prbs31_enable_2, qsfp2_cfg_rx_prbs31_enable_1, qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1, qsfp0_cfg_rx_prbs31_enable_4, qsfp0_cfg_rx_prbs31_enable_3, qsfp0_cfg_rx_prbs31_enable_2, qsfp0_cfg_rx_prbs31_enable_1}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -1264,38 +1264,38 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp0_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_rx_prbs31_enable_4 = 1'b0;
assign qsfp2_tx_prbs31_enable_1 = 1'b0;
assign qsfp2_rx_prbs31_enable_1 = 1'b0;
assign qsfp2_tx_prbs31_enable_2 = 1'b0;
assign qsfp2_rx_prbs31_enable_2 = 1'b0;
assign qsfp2_tx_prbs31_enable_3 = 1'b0;
assign qsfp2_rx_prbs31_enable_3 = 1'b0;
assign qsfp2_tx_prbs31_enable_4 = 1'b0;
assign qsfp2_rx_prbs31_enable_4 = 1'b0;
assign qsfp3_tx_prbs31_enable_1 = 1'b0;
assign qsfp3_rx_prbs31_enable_1 = 1'b0;
assign qsfp3_tx_prbs31_enable_2 = 1'b0;
assign qsfp3_rx_prbs31_enable_2 = 1'b0;
assign qsfp3_tx_prbs31_enable_3 = 1'b0;
assign qsfp3_rx_prbs31_enable_3 = 1'b0;
assign qsfp3_tx_prbs31_enable_4 = 1'b0;
assign qsfp3_rx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp3_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp3_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp3_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp3_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp3_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp3_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp3_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp3_cfg_rx_prbs31_enable_4 = 1'b0;
end
@ -1451,7 +1451,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

192
fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga.v
View File

@ -1024,45 +1024,45 @@ wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1_int;
wire qsfp0_tx_prbs31_enable_1_int;
wire qsfp0_cfg_tx_prbs31_enable_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1_int;
wire qsfp0_rx_prbs31_enable_1_int;
wire qsfp0_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp0_rx_error_count_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2_int;
wire qsfp0_tx_prbs31_enable_2_int;
wire qsfp0_cfg_tx_prbs31_enable_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2_int;
wire qsfp0_rx_prbs31_enable_2_int;
wire qsfp0_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp0_rx_error_count_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3_int;
wire qsfp0_tx_prbs31_enable_3_int;
wire qsfp0_cfg_tx_prbs31_enable_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3_int;
wire qsfp0_rx_prbs31_enable_3_int;
wire qsfp0_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp0_rx_error_count_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4_int;
wire qsfp0_tx_prbs31_enable_4_int;
wire qsfp0_cfg_tx_prbs31_enable_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int;
wire qsfp0_rx_prbs31_enable_4_int;
wire qsfp0_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp0_rx_error_count_4_int;
wire qsfp0_drp_clk = clk_125mhz_int;
@ -1172,8 +1172,8 @@ qsfp0_phy_quad_inst (
.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp0_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp0_tx_clk_2_int),
.phy_2_tx_rst(qsfp0_tx_rst_2_int),
@ -1190,8 +1190,8 @@ qsfp0_phy_quad_inst (
.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp0_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp0_tx_clk_3_int),
.phy_3_tx_rst(qsfp0_tx_rst_3_int),
@ -1208,8 +1208,8 @@ qsfp0_phy_quad_inst (
.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp0_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp0_tx_clk_4_int),
.phy_4_tx_rst(qsfp0_tx_rst_4_int),
@ -1226,8 +1226,8 @@ qsfp0_phy_quad_inst (
.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp0_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp0_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp0_cfg_rx_prbs31_enable_4_int)
);
// QSFP1
@ -1235,45 +1235,45 @@ wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1_int;
wire qsfp1_tx_prbs31_enable_1_int;
wire qsfp1_cfg_tx_prbs31_enable_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1_int;
wire qsfp1_rx_prbs31_enable_1_int;
wire qsfp1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp1_rx_error_count_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2_int;
wire qsfp1_tx_prbs31_enable_2_int;
wire qsfp1_cfg_tx_prbs31_enable_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2_int;
wire qsfp1_rx_prbs31_enable_2_int;
wire qsfp1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp1_rx_error_count_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3_int;
wire qsfp1_tx_prbs31_enable_3_int;
wire qsfp1_cfg_tx_prbs31_enable_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3_int;
wire qsfp1_rx_prbs31_enable_3_int;
wire qsfp1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp1_rx_error_count_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4_int;
wire qsfp1_tx_prbs31_enable_4_int;
wire qsfp1_cfg_tx_prbs31_enable_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int;
wire qsfp1_rx_prbs31_enable_4_int;
wire qsfp1_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp1_rx_error_count_4_int;
wire qsfp1_drp_clk = clk_125mhz_int;
@ -1383,8 +1383,8 @@ qsfp1_phy_quad_inst (
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp1_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp1_tx_clk_2_int),
.phy_2_tx_rst(qsfp1_tx_rst_2_int),
@ -1401,8 +1401,8 @@ qsfp1_phy_quad_inst (
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp1_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp1_tx_clk_3_int),
.phy_3_tx_rst(qsfp1_tx_rst_3_int),
@ -1419,8 +1419,8 @@ qsfp1_phy_quad_inst (
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp1_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp1_tx_clk_4_int),
.phy_4_tx_rst(qsfp1_tx_rst_4_int),
@ -1437,8 +1437,8 @@ qsfp1_phy_quad_inst (
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp1_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp1_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp1_cfg_rx_prbs31_enable_4_int)
);
// QSFP2
@ -1446,45 +1446,45 @@ wire qsfp2_tx_clk_1_int;
wire qsfp2_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_1_int;
wire qsfp2_tx_prbs31_enable_1_int;
wire qsfp2_cfg_tx_prbs31_enable_1_int;
wire qsfp2_rx_clk_1_int;
wire qsfp2_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_1_int;
wire qsfp2_rx_prbs31_enable_1_int;
wire qsfp2_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp2_rx_error_count_1_int;
wire qsfp2_tx_clk_2_int;
wire qsfp2_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_2_int;
wire qsfp2_tx_prbs31_enable_2_int;
wire qsfp2_cfg_tx_prbs31_enable_2_int;
wire qsfp2_rx_clk_2_int;
wire qsfp2_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_2_int;
wire qsfp2_rx_prbs31_enable_2_int;
wire qsfp2_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp2_rx_error_count_2_int;
wire qsfp2_tx_clk_3_int;
wire qsfp2_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_3_int;
wire qsfp2_tx_prbs31_enable_3_int;
wire qsfp2_cfg_tx_prbs31_enable_3_int;
wire qsfp2_rx_clk_3_int;
wire qsfp2_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_3_int;
wire qsfp2_rx_prbs31_enable_3_int;
wire qsfp2_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp2_rx_error_count_3_int;
wire qsfp2_tx_clk_4_int;
wire qsfp2_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_4_int;
wire qsfp2_tx_prbs31_enable_4_int;
wire qsfp2_cfg_tx_prbs31_enable_4_int;
wire qsfp2_rx_clk_4_int;
wire qsfp2_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_4_int;
wire qsfp2_rx_prbs31_enable_4_int;
wire qsfp2_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp2_rx_error_count_4_int;
wire qsfp2_drp_clk = clk_125mhz_int;
@ -1594,8 +1594,8 @@ qsfp2_phy_quad_inst (
.phy_1_rx_block_lock(qsfp2_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp2_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp2_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp2_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp2_tx_clk_2_int),
.phy_2_tx_rst(qsfp2_tx_rst_2_int),
@ -1612,8 +1612,8 @@ qsfp2_phy_quad_inst (
.phy_2_rx_block_lock(qsfp2_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp2_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp2_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp2_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp2_tx_clk_3_int),
.phy_3_tx_rst(qsfp2_tx_rst_3_int),
@ -1630,8 +1630,8 @@ qsfp2_phy_quad_inst (
.phy_3_rx_block_lock(qsfp2_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp2_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp2_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp2_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp2_tx_clk_4_int),
.phy_4_tx_rst(qsfp2_tx_rst_4_int),
@ -1648,8 +1648,8 @@ qsfp2_phy_quad_inst (
.phy_4_rx_block_lock(qsfp2_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp2_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp2_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp2_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp2_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp2_cfg_rx_prbs31_enable_4_int)
);
// QSFP3
@ -1657,45 +1657,45 @@ wire qsfp3_tx_clk_1_int;
wire qsfp3_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_1_int;
wire qsfp3_tx_prbs31_enable_1_int;
wire qsfp3_cfg_tx_prbs31_enable_1_int;
wire qsfp3_rx_clk_1_int;
wire qsfp3_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_1_int;
wire qsfp3_rx_prbs31_enable_1_int;
wire qsfp3_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp3_rx_error_count_1_int;
wire qsfp3_tx_clk_2_int;
wire qsfp3_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_2_int;
wire qsfp3_tx_prbs31_enable_2_int;
wire qsfp3_cfg_tx_prbs31_enable_2_int;
wire qsfp3_rx_clk_2_int;
wire qsfp3_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_2_int;
wire qsfp3_rx_prbs31_enable_2_int;
wire qsfp3_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp3_rx_error_count_2_int;
wire qsfp3_tx_clk_3_int;
wire qsfp3_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_3_int;
wire qsfp3_tx_prbs31_enable_3_int;
wire qsfp3_cfg_tx_prbs31_enable_3_int;
wire qsfp3_rx_clk_3_int;
wire qsfp3_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_3_int;
wire qsfp3_rx_prbs31_enable_3_int;
wire qsfp3_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp3_rx_error_count_3_int;
wire qsfp3_tx_clk_4_int;
wire qsfp3_tx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_4_int;
wire qsfp3_tx_prbs31_enable_4_int;
wire qsfp3_cfg_tx_prbs31_enable_4_int;
wire qsfp3_rx_clk_4_int;
wire qsfp3_rx_rst_4_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_4_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_4_int;
wire qsfp3_rx_prbs31_enable_4_int;
wire qsfp3_cfg_rx_prbs31_enable_4_int;
wire [6:0] qsfp3_rx_error_count_4_int;
wire qsfp3_drp_clk = clk_125mhz_int;
@ -1805,8 +1805,8 @@ qsfp3_phy_quad_inst (
.phy_1_rx_block_lock(qsfp3_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp3_rx_status_1),
.phy_1_tx_prbs31_enable(qsfp3_tx_prbs31_enable_1_int),
.phy_1_rx_prbs31_enable(qsfp3_rx_prbs31_enable_1_int),
.phy_1_cfg_tx_prbs31_enable(qsfp3_cfg_tx_prbs31_enable_1_int),
.phy_1_cfg_rx_prbs31_enable(qsfp3_cfg_rx_prbs31_enable_1_int),
.phy_2_tx_clk(qsfp3_tx_clk_2_int),
.phy_2_tx_rst(qsfp3_tx_rst_2_int),
@ -1823,8 +1823,8 @@ qsfp3_phy_quad_inst (
.phy_2_rx_block_lock(qsfp3_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp3_rx_status_2),
.phy_2_tx_prbs31_enable(qsfp3_tx_prbs31_enable_2_int),
.phy_2_rx_prbs31_enable(qsfp3_rx_prbs31_enable_2_int),
.phy_2_cfg_tx_prbs31_enable(qsfp3_cfg_tx_prbs31_enable_2_int),
.phy_2_cfg_rx_prbs31_enable(qsfp3_cfg_rx_prbs31_enable_2_int),
.phy_3_tx_clk(qsfp3_tx_clk_3_int),
.phy_3_tx_rst(qsfp3_tx_rst_3_int),
@ -1841,8 +1841,8 @@ qsfp3_phy_quad_inst (
.phy_3_rx_block_lock(qsfp3_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp3_rx_status_3),
.phy_3_tx_prbs31_enable(qsfp3_tx_prbs31_enable_3_int),
.phy_3_rx_prbs31_enable(qsfp3_rx_prbs31_enable_3_int),
.phy_3_cfg_tx_prbs31_enable(qsfp3_cfg_tx_prbs31_enable_3_int),
.phy_3_cfg_rx_prbs31_enable(qsfp3_cfg_rx_prbs31_enable_3_int),
.phy_4_tx_clk(qsfp3_tx_clk_4_int),
.phy_4_tx_rst(qsfp3_tx_rst_4_int),
@ -1859,8 +1859,8 @@ qsfp3_phy_quad_inst (
.phy_4_rx_block_lock(qsfp3_rx_block_lock_4),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp3_rx_status_4),
.phy_4_tx_prbs31_enable(qsfp3_tx_prbs31_enable_4_int),
.phy_4_rx_prbs31_enable(qsfp3_rx_prbs31_enable_4_int)
.phy_4_cfg_tx_prbs31_enable(qsfp3_cfg_tx_prbs31_enable_4_int),
.phy_4_cfg_rx_prbs31_enable(qsfp3_cfg_rx_prbs31_enable_4_int)
);
wire ptp_clk;
@ -2698,48 +2698,48 @@ core_inst (
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_tx_prbs31_enable_1(qsfp0_tx_prbs31_enable_1_int),
.qsfp0_cfg_tx_prbs31_enable_1(qsfp0_cfg_tx_prbs31_enable_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_rx_prbs31_enable_1(qsfp0_rx_prbs31_enable_1_int),
.qsfp0_cfg_rx_prbs31_enable_1(qsfp0_cfg_rx_prbs31_enable_1_int),
.qsfp0_rx_error_count_1(qsfp0_rx_error_count_1_int),
.qsfp0_rx_status_1(qsfp0_rx_status_1),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_tx_prbs31_enable_2(qsfp0_tx_prbs31_enable_2_int),
.qsfp0_cfg_tx_prbs31_enable_2(qsfp0_cfg_tx_prbs31_enable_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_rx_prbs31_enable_2(qsfp0_rx_prbs31_enable_2_int),
.qsfp0_cfg_rx_prbs31_enable_2(qsfp0_cfg_rx_prbs31_enable_2_int),
.qsfp0_rx_error_count_2(qsfp0_rx_error_count_2_int),
.qsfp0_rx_status_2(qsfp0_rx_status_2),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_tx_prbs31_enable_3(qsfp0_tx_prbs31_enable_3_int),
.qsfp0_cfg_tx_prbs31_enable_3(qsfp0_cfg_tx_prbs31_enable_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_rx_prbs31_enable_3(qsfp0_rx_prbs31_enable_3_int),
.qsfp0_cfg_rx_prbs31_enable_3(qsfp0_cfg_rx_prbs31_enable_3_int),
.qsfp0_rx_error_count_3(qsfp0_rx_error_count_3_int),
.qsfp0_rx_status_3(qsfp0_rx_status_3),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_tx_prbs31_enable_4(qsfp0_tx_prbs31_enable_4_int),
.qsfp0_cfg_tx_prbs31_enable_4(qsfp0_cfg_tx_prbs31_enable_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp0_rx_prbs31_enable_4(qsfp0_rx_prbs31_enable_4_int),
.qsfp0_cfg_rx_prbs31_enable_4(qsfp0_cfg_rx_prbs31_enable_4_int),
.qsfp0_rx_error_count_4(qsfp0_rx_error_count_4_int),
.qsfp0_rx_status_4(qsfp0_rx_status_4),
@ -2768,48 +2768,48 @@ core_inst (
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_tx_prbs31_enable_1(qsfp1_tx_prbs31_enable_1_int),
.qsfp1_cfg_tx_prbs31_enable_1(qsfp1_cfg_tx_prbs31_enable_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_rx_prbs31_enable_1(qsfp1_rx_prbs31_enable_1_int),
.qsfp1_cfg_rx_prbs31_enable_1(qsfp1_cfg_rx_prbs31_enable_1_int),
.qsfp1_rx_error_count_1(qsfp1_rx_error_count_1_int),
.qsfp1_rx_status_1(qsfp1_rx_status_1),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_tx_prbs31_enable_2(qsfp1_tx_prbs31_enable_2_int),
.qsfp1_cfg_tx_prbs31_enable_2(qsfp1_cfg_tx_prbs31_enable_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_rx_prbs31_enable_2(qsfp1_rx_prbs31_enable_2_int),
.qsfp1_cfg_rx_prbs31_enable_2(qsfp1_cfg_rx_prbs31_enable_2_int),
.qsfp1_rx_error_count_2(qsfp1_rx_error_count_2_int),
.qsfp1_rx_status_2(qsfp1_rx_status_2),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_tx_prbs31_enable_3(qsfp1_tx_prbs31_enable_3_int),
.qsfp1_cfg_tx_prbs31_enable_3(qsfp1_cfg_tx_prbs31_enable_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_rx_prbs31_enable_3(qsfp1_rx_prbs31_enable_3_int),
.qsfp1_cfg_rx_prbs31_enable_3(qsfp1_cfg_rx_prbs31_enable_3_int),
.qsfp1_rx_error_count_3(qsfp1_rx_error_count_3_int),
.qsfp1_rx_status_3(qsfp1_rx_status_3),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_tx_prbs31_enable_4(qsfp1_tx_prbs31_enable_4_int),
.qsfp1_cfg_tx_prbs31_enable_4(qsfp1_cfg_tx_prbs31_enable_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int),
.qsfp1_rx_prbs31_enable_4(qsfp1_rx_prbs31_enable_4_int),
.qsfp1_cfg_rx_prbs31_enable_4(qsfp1_cfg_rx_prbs31_enable_4_int),
.qsfp1_rx_error_count_4(qsfp1_rx_error_count_4_int),
.qsfp1_rx_status_4(qsfp1_rx_status_4),
@ -2838,48 +2838,48 @@ core_inst (
.qsfp2_tx_rst_1(qsfp2_tx_rst_1_int),
.qsfp2_txd_1(qsfp2_txd_1_int),
.qsfp2_txc_1(qsfp2_txc_1_int),
.qsfp2_tx_prbs31_enable_1(qsfp2_tx_prbs31_enable_1_int),
.qsfp2_cfg_tx_prbs31_enable_1(qsfp2_cfg_tx_prbs31_enable_1_int),
.qsfp2_rx_clk_1(qsfp2_rx_clk_1_int),
.qsfp2_rx_rst_1(qsfp2_rx_rst_1_int),
.qsfp2_rxd_1(qsfp2_rxd_1_int),
.qsfp2_rxc_1(qsfp2_rxc_1_int),
.qsfp2_rx_prbs31_enable_1(qsfp2_rx_prbs31_enable_1_int),
.qsfp2_cfg_rx_prbs31_enable_1(qsfp2_cfg_rx_prbs31_enable_1_int),
.qsfp2_rx_error_count_1(qsfp2_rx_error_count_1_int),
.qsfp2_rx_status_1(qsfp2_rx_status_1),
.qsfp2_tx_clk_2(qsfp2_tx_clk_2_int),
.qsfp2_tx_rst_2(qsfp2_tx_rst_2_int),
.qsfp2_txd_2(qsfp2_txd_2_int),
.qsfp2_txc_2(qsfp2_txc_2_int),
.qsfp2_tx_prbs31_enable_2(qsfp2_tx_prbs31_enable_2_int),
.qsfp2_cfg_tx_prbs31_enable_2(qsfp2_cfg_tx_prbs31_enable_2_int),
.qsfp2_rx_clk_2(qsfp2_rx_clk_2_int),
.qsfp2_rx_rst_2(qsfp2_rx_rst_2_int),
.qsfp2_rxd_2(qsfp2_rxd_2_int),
.qsfp2_rxc_2(qsfp2_rxc_2_int),
.qsfp2_rx_prbs31_enable_2(qsfp2_rx_prbs31_enable_2_int),
.qsfp2_cfg_rx_prbs31_enable_2(qsfp2_cfg_rx_prbs31_enable_2_int),
.qsfp2_rx_error_count_2(qsfp2_rx_error_count_2_int),
.qsfp2_rx_status_2(qsfp2_rx_status_2),
.qsfp2_tx_clk_3(qsfp2_tx_clk_3_int),
.qsfp2_tx_rst_3(qsfp2_tx_rst_3_int),
.qsfp2_txd_3(qsfp2_txd_3_int),
.qsfp2_txc_3(qsfp2_txc_3_int),
.qsfp2_tx_prbs31_enable_3(qsfp2_tx_prbs31_enable_3_int),
.qsfp2_cfg_tx_prbs31_enable_3(qsfp2_cfg_tx_prbs31_enable_3_int),
.qsfp2_rx_clk_3(qsfp2_rx_clk_3_int),
.qsfp2_rx_rst_3(qsfp2_rx_rst_3_int),
.qsfp2_rxd_3(qsfp2_rxd_3_int),
.qsfp2_rxc_3(qsfp2_rxc_3_int),
.qsfp2_rx_prbs31_enable_3(qsfp2_rx_prbs31_enable_3_int),
.qsfp2_cfg_rx_prbs31_enable_3(qsfp2_cfg_rx_prbs31_enable_3_int),
.qsfp2_rx_error_count_3(qsfp2_rx_error_count_3_int),
.qsfp2_rx_status_3(qsfp2_rx_status_3),
.qsfp2_tx_clk_4(qsfp2_tx_clk_4_int),
.qsfp2_tx_rst_4(qsfp2_tx_rst_4_int),
.qsfp2_txd_4(qsfp2_txd_4_int),
.qsfp2_txc_4(qsfp2_txc_4_int),
.qsfp2_tx_prbs31_enable_4(qsfp2_tx_prbs31_enable_4_int),
.qsfp2_cfg_tx_prbs31_enable_4(qsfp2_cfg_tx_prbs31_enable_4_int),
.qsfp2_rx_clk_4(qsfp2_rx_clk_4_int),
.qsfp2_rx_rst_4(qsfp2_rx_rst_4_int),
.qsfp2_rxd_4(qsfp2_rxd_4_int),
.qsfp2_rxc_4(qsfp2_rxc_4_int),
.qsfp2_rx_prbs31_enable_4(qsfp2_rx_prbs31_enable_4_int),
.qsfp2_cfg_rx_prbs31_enable_4(qsfp2_cfg_rx_prbs31_enable_4_int),
.qsfp2_rx_error_count_4(qsfp2_rx_error_count_4_int),
.qsfp2_rx_status_4(qsfp2_rx_status_4),
@ -2908,48 +2908,48 @@ core_inst (
.qsfp3_tx_rst_1(qsfp3_tx_rst_1_int),
.qsfp3_txd_1(qsfp3_txd_1_int),
.qsfp3_txc_1(qsfp3_txc_1_int),
.qsfp3_tx_prbs31_enable_1(qsfp3_tx_prbs31_enable_1_int),
.qsfp3_cfg_tx_prbs31_enable_1(qsfp3_cfg_tx_prbs31_enable_1_int),
.qsfp3_rx_clk_1(qsfp3_rx_clk_1_int),
.qsfp3_rx_rst_1(qsfp3_rx_rst_1_int),
.qsfp3_rxd_1(qsfp3_rxd_1_int),
.qsfp3_rxc_1(qsfp3_rxc_1_int),
.qsfp3_rx_prbs31_enable_1(qsfp3_rx_prbs31_enable_1_int),
.qsfp3_cfg_rx_prbs31_enable_1(qsfp3_cfg_rx_prbs31_enable_1_int),
.qsfp3_rx_error_count_1(qsfp3_rx_error_count_1_int),
.qsfp3_rx_status_1(qsfp3_rx_status_1),
.qsfp3_tx_clk_2(qsfp3_tx_clk_2_int),
.qsfp3_tx_rst_2(qsfp3_tx_rst_2_int),
.qsfp3_txd_2(qsfp3_txd_2_int),
.qsfp3_txc_2(qsfp3_txc_2_int),
.qsfp3_tx_prbs31_enable_2(qsfp3_tx_prbs31_enable_2_int),
.qsfp3_cfg_tx_prbs31_enable_2(qsfp3_cfg_tx_prbs31_enable_2_int),
.qsfp3_rx_clk_2(qsfp3_rx_clk_2_int),
.qsfp3_rx_rst_2(qsfp3_rx_rst_2_int),
.qsfp3_rxd_2(qsfp3_rxd_2_int),
.qsfp3_rxc_2(qsfp3_rxc_2_int),
.qsfp3_rx_prbs31_enable_2(qsfp3_rx_prbs31_enable_2_int),
.qsfp3_cfg_rx_prbs31_enable_2(qsfp3_cfg_rx_prbs31_enable_2_int),
.qsfp3_rx_error_count_2(qsfp3_rx_error_count_2_int),
.qsfp3_rx_status_2(qsfp3_rx_status_2),
.qsfp3_tx_clk_3(qsfp3_tx_clk_3_int),
.qsfp3_tx_rst_3(qsfp3_tx_rst_3_int),
.qsfp3_txd_3(qsfp3_txd_3_int),
.qsfp3_txc_3(qsfp3_txc_3_int),
.qsfp3_tx_prbs31_enable_3(qsfp3_tx_prbs31_enable_3_int),
.qsfp3_cfg_tx_prbs31_enable_3(qsfp3_cfg_tx_prbs31_enable_3_int),
.qsfp3_rx_clk_3(qsfp3_rx_clk_3_int),
.qsfp3_rx_rst_3(qsfp3_rx_rst_3_int),
.qsfp3_rxd_3(qsfp3_rxd_3_int),
.qsfp3_rxc_3(qsfp3_rxc_3_int),
.qsfp3_rx_prbs31_enable_3(qsfp3_rx_prbs31_enable_3_int),
.qsfp3_cfg_rx_prbs31_enable_3(qsfp3_cfg_rx_prbs31_enable_3_int),
.qsfp3_rx_error_count_3(qsfp3_rx_error_count_3_int),
.qsfp3_rx_status_3(qsfp3_rx_status_3),
.qsfp3_tx_clk_4(qsfp3_tx_clk_4_int),
.qsfp3_tx_rst_4(qsfp3_tx_rst_4_int),
.qsfp3_txd_4(qsfp3_txd_4_int),
.qsfp3_txc_4(qsfp3_txc_4_int),
.qsfp3_tx_prbs31_enable_4(qsfp3_tx_prbs31_enable_4_int),
.qsfp3_cfg_tx_prbs31_enable_4(qsfp3_cfg_tx_prbs31_enable_4_int),
.qsfp3_rx_clk_4(qsfp3_rx_clk_4_int),
.qsfp3_rx_rst_4(qsfp3_rx_rst_4_int),
.qsfp3_rxd_4(qsfp3_rxd_4_int),
.qsfp3_rxc_4(qsfp3_rxc_4_int),
.qsfp3_rx_prbs31_enable_4(qsfp3_rx_prbs31_enable_4_int),
.qsfp3_cfg_rx_prbs31_enable_4(qsfp3_cfg_rx_prbs31_enable_4_int),
.qsfp3_rx_error_count_4(qsfp3_rx_error_count_4_int),
.qsfp3_rx_status_4(qsfp3_rx_status_4),

136
fpga/mqnic/XUSP3S/fpga_25g/rtl/fpga_core.v
View File

@ -277,48 +277,48 @@ module fpga_core #
input wire qsfp0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_1,
output wire qsfp0_tx_prbs31_enable_1,
output wire qsfp0_cfg_tx_prbs31_enable_1,
input wire qsfp0_rx_clk_1,
input wire qsfp0_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_1,
output wire qsfp0_rx_prbs31_enable_1,
output wire qsfp0_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp0_rx_error_count_1,
input wire qsfp0_rx_status_1,
input wire qsfp0_tx_clk_2,
input wire qsfp0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_2,
output wire qsfp0_tx_prbs31_enable_2,
output wire qsfp0_cfg_tx_prbs31_enable_2,
input wire qsfp0_rx_clk_2,
input wire qsfp0_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_2,
output wire qsfp0_rx_prbs31_enable_2,
output wire qsfp0_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp0_rx_error_count_2,
input wire qsfp0_rx_status_2,
input wire qsfp0_tx_clk_3,
input wire qsfp0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_3,
output wire qsfp0_tx_prbs31_enable_3,
output wire qsfp0_cfg_tx_prbs31_enable_3,
input wire qsfp0_rx_clk_3,
input wire qsfp0_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_3,
output wire qsfp0_rx_prbs31_enable_3,
output wire qsfp0_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp0_rx_error_count_3,
input wire qsfp0_rx_status_3,
input wire qsfp0_tx_clk_4,
input wire qsfp0_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp0_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp0_txc_4,
output wire qsfp0_tx_prbs31_enable_4,
output wire qsfp0_cfg_tx_prbs31_enable_4,
input wire qsfp0_rx_clk_4,
input wire qsfp0_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp0_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4,
output wire qsfp0_rx_prbs31_enable_4,
output wire qsfp0_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp0_rx_error_count_4,
input wire qsfp0_rx_status_4,
@ -347,48 +347,48 @@ module fpga_core #
input wire qsfp1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_1,
output wire qsfp1_tx_prbs31_enable_1,
output wire qsfp1_cfg_tx_prbs31_enable_1,
input wire qsfp1_rx_clk_1,
input wire qsfp1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_1,
output wire qsfp1_rx_prbs31_enable_1,
output wire qsfp1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp1_rx_error_count_1,
input wire qsfp1_rx_status_1,
input wire qsfp1_tx_clk_2,
input wire qsfp1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_2,
output wire qsfp1_tx_prbs31_enable_2,
output wire qsfp1_cfg_tx_prbs31_enable_2,
input wire qsfp1_rx_clk_2,
input wire qsfp1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_2,
output wire qsfp1_rx_prbs31_enable_2,
output wire qsfp1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp1_rx_error_count_2,
input wire qsfp1_rx_status_2,
input wire qsfp1_tx_clk_3,
input wire qsfp1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_3,
output wire qsfp1_tx_prbs31_enable_3,
output wire qsfp1_cfg_tx_prbs31_enable_3,
input wire qsfp1_rx_clk_3,
input wire qsfp1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_3,
output wire qsfp1_rx_prbs31_enable_3,
output wire qsfp1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp1_rx_error_count_3,
input wire qsfp1_rx_status_3,
input wire qsfp1_tx_clk_4,
input wire qsfp1_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp1_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp1_txc_4,
output wire qsfp1_tx_prbs31_enable_4,
output wire qsfp1_cfg_tx_prbs31_enable_4,
input wire qsfp1_rx_clk_4,
input wire qsfp1_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp1_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4,
output wire qsfp1_rx_prbs31_enable_4,
output wire qsfp1_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp1_rx_error_count_4,
input wire qsfp1_rx_status_4,
@ -417,48 +417,48 @@ module fpga_core #
input wire qsfp2_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_1,
output wire qsfp2_tx_prbs31_enable_1,
output wire qsfp2_cfg_tx_prbs31_enable_1,
input wire qsfp2_rx_clk_1,
input wire qsfp2_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_1,
output wire qsfp2_rx_prbs31_enable_1,
output wire qsfp2_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp2_rx_error_count_1,
input wire qsfp2_rx_status_1,
input wire qsfp2_tx_clk_2,
input wire qsfp2_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_2,
output wire qsfp2_tx_prbs31_enable_2,
output wire qsfp2_cfg_tx_prbs31_enable_2,
input wire qsfp2_rx_clk_2,
input wire qsfp2_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_2,
output wire qsfp2_rx_prbs31_enable_2,
output wire qsfp2_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp2_rx_error_count_2,
input wire qsfp2_rx_status_2,
input wire qsfp2_tx_clk_3,
input wire qsfp2_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_3,
output wire qsfp2_tx_prbs31_enable_3,
output wire qsfp2_cfg_tx_prbs31_enable_3,
input wire qsfp2_rx_clk_3,
input wire qsfp2_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_3,
output wire qsfp2_rx_prbs31_enable_3,
output wire qsfp2_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp2_rx_error_count_3,
input wire qsfp2_rx_status_3,
input wire qsfp2_tx_clk_4,
input wire qsfp2_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp2_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp2_txc_4,
output wire qsfp2_tx_prbs31_enable_4,
output wire qsfp2_cfg_tx_prbs31_enable_4,
input wire qsfp2_rx_clk_4,
input wire qsfp2_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp2_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp2_rxc_4,
output wire qsfp2_rx_prbs31_enable_4,
output wire qsfp2_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp2_rx_error_count_4,
input wire qsfp2_rx_status_4,
@ -487,48 +487,48 @@ module fpga_core #
input wire qsfp3_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_1,
output wire qsfp3_tx_prbs31_enable_1,
output wire qsfp3_cfg_tx_prbs31_enable_1,
input wire qsfp3_rx_clk_1,
input wire qsfp3_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_1,
output wire qsfp3_rx_prbs31_enable_1,
output wire qsfp3_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp3_rx_error_count_1,
input wire qsfp3_rx_status_1,
input wire qsfp3_tx_clk_2,
input wire qsfp3_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_2,
output wire qsfp3_tx_prbs31_enable_2,
output wire qsfp3_cfg_tx_prbs31_enable_2,
input wire qsfp3_rx_clk_2,
input wire qsfp3_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_2,
output wire qsfp3_rx_prbs31_enable_2,
output wire qsfp3_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp3_rx_error_count_2,
input wire qsfp3_rx_status_2,
input wire qsfp3_tx_clk_3,
input wire qsfp3_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_3,
output wire qsfp3_tx_prbs31_enable_3,
output wire qsfp3_cfg_tx_prbs31_enable_3,
input wire qsfp3_rx_clk_3,
input wire qsfp3_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_3,
output wire qsfp3_rx_prbs31_enable_3,
output wire qsfp3_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp3_rx_error_count_3,
input wire qsfp3_rx_status_3,
input wire qsfp3_tx_clk_4,
input wire qsfp3_tx_rst_4,
output wire [XGMII_DATA_WIDTH-1:0] qsfp3_txd_4,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp3_txc_4,
output wire qsfp3_tx_prbs31_enable_4,
output wire qsfp3_cfg_tx_prbs31_enable_4,
input wire qsfp3_rx_clk_4,
input wire qsfp3_rx_rst_4,
input wire [XGMII_DATA_WIDTH-1:0] qsfp3_rxd_4,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp3_rxc_4,
output wire qsfp3_rx_prbs31_enable_4,
output wire qsfp3_cfg_rx_prbs31_enable_4,
input wire [6:0] qsfp3_rx_error_count_4,
input wire qsfp3_rx_status_4,
@ -1232,8 +1232,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp3_tx_clk_4, qsfp3_tx_clk_3, qsfp3_tx_clk_2, qsfp3_tx_clk_1, qsfp2_tx_clk_4, qsfp2_tx_clk_3, qsfp2_tx_clk_2, qsfp2_tx_clk_1, qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}),
.phy_rx_clk({qsfp3_rx_clk_4, qsfp3_rx_clk_3, qsfp3_rx_clk_2, qsfp3_rx_clk_1, qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
.phy_rx_error_count({qsfp3_rx_error_count_4, qsfp3_rx_error_count_3, qsfp3_rx_error_count_2, qsfp3_rx_error_count_1, qsfp2_rx_error_count_4, qsfp2_rx_error_count_3, qsfp2_rx_error_count_2, qsfp2_rx_error_count_1, qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}),
.phy_tx_prbs31_enable({qsfp3_tx_prbs31_enable_4, qsfp3_tx_prbs31_enable_3, qsfp3_tx_prbs31_enable_2, qsfp3_tx_prbs31_enable_1, qsfp2_tx_prbs31_enable_4, qsfp2_tx_prbs31_enable_3, qsfp2_tx_prbs31_enable_2, qsfp2_tx_prbs31_enable_1, qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}),
.phy_rx_prbs31_enable({qsfp3_rx_prbs31_enable_4, qsfp3_rx_prbs31_enable_3, qsfp3_rx_prbs31_enable_2, qsfp3_rx_prbs31_enable_1, qsfp2_rx_prbs31_enable_4, qsfp2_rx_prbs31_enable_3, qsfp2_rx_prbs31_enable_2, qsfp2_rx_prbs31_enable_1, qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}),
.phy_cfg_tx_prbs31_enable({qsfp3_cfg_tx_prbs31_enable_4, qsfp3_cfg_tx_prbs31_enable_3, qsfp3_cfg_tx_prbs31_enable_2, qsfp3_cfg_tx_prbs31_enable_1, qsfp2_cfg_tx_prbs31_enable_4, qsfp2_cfg_tx_prbs31_enable_3, qsfp2_cfg_tx_prbs31_enable_2, qsfp2_cfg_tx_prbs31_enable_1, qsfp1_cfg_tx_prbs31_enable_4, qsfp1_cfg_tx_prbs31_enable_3, qsfp1_cfg_tx_prbs31_enable_2, qsfp1_cfg_tx_prbs31_enable_1, qsfp0_cfg_tx_prbs31_enable_4, qsfp0_cfg_tx_prbs31_enable_3, qsfp0_cfg_tx_prbs31_enable_2, qsfp0_cfg_tx_prbs31_enable_1}),
.phy_cfg_rx_prbs31_enable({qsfp3_cfg_rx_prbs31_enable_4, qsfp3_cfg_rx_prbs31_enable_3, qsfp3_cfg_rx_prbs31_enable_2, qsfp3_cfg_rx_prbs31_enable_1, qsfp2_cfg_rx_prbs31_enable_4, qsfp2_cfg_rx_prbs31_enable_3, qsfp2_cfg_rx_prbs31_enable_2, qsfp2_cfg_rx_prbs31_enable_1, qsfp1_cfg_rx_prbs31_enable_4, qsfp1_cfg_rx_prbs31_enable_3, qsfp1_cfg_rx_prbs31_enable_2, qsfp1_cfg_rx_prbs31_enable_1, qsfp0_cfg_rx_prbs31_enable_4, qsfp0_cfg_rx_prbs31_enable_3, qsfp0_cfg_rx_prbs31_enable_2, qsfp0_cfg_rx_prbs31_enable_1}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -1259,38 +1259,38 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp0_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_rx_prbs31_enable_4 = 1'b0;
assign qsfp2_tx_prbs31_enable_1 = 1'b0;
assign qsfp2_rx_prbs31_enable_1 = 1'b0;
assign qsfp2_tx_prbs31_enable_2 = 1'b0;
assign qsfp2_rx_prbs31_enable_2 = 1'b0;
assign qsfp2_tx_prbs31_enable_3 = 1'b0;
assign qsfp2_rx_prbs31_enable_3 = 1'b0;
assign qsfp2_tx_prbs31_enable_4 = 1'b0;
assign qsfp2_rx_prbs31_enable_4 = 1'b0;
assign qsfp3_tx_prbs31_enable_1 = 1'b0;
assign qsfp3_rx_prbs31_enable_1 = 1'b0;
assign qsfp3_tx_prbs31_enable_2 = 1'b0;
assign qsfp3_rx_prbs31_enable_2 = 1'b0;
assign qsfp3_tx_prbs31_enable_3 = 1'b0;
assign qsfp3_rx_prbs31_enable_3 = 1'b0;
assign qsfp3_tx_prbs31_enable_4 = 1'b0;
assign qsfp3_rx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp0_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp0_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp1_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp1_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp2_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp2_cfg_rx_prbs31_enable_4 = 1'b0;
assign qsfp3_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp3_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp3_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp3_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp3_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp3_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp3_cfg_tx_prbs31_enable_4 = 1'b0;
assign qsfp3_cfg_rx_prbs31_enable_4 = 1'b0;
end
@ -1446,7 +1446,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

48
fpga/mqnic/ZCU102/fpga/rtl/fpga.v
View File

@ -560,48 +560,48 @@ wire sfp0_tx_clk_int;
wire sfp0_tx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp0_txd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp0_txc_int;
wire sfp0_tx_prbs31_enable_int;
wire sfp0_cfg_tx_prbs31_enable_int;
wire sfp0_rx_clk_int;
wire sfp0_rx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp0_rxd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp0_rxc_int;
wire sfp0_rx_prbs31_enable_int;
wire sfp0_cfg_rx_prbs31_enable_int;
wire [6:0] sfp0_rx_error_count_int;
wire sfp1_tx_clk_int;
wire sfp1_tx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp1_txd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp1_txc_int;
wire sfp1_tx_prbs31_enable_int;
wire sfp1_cfg_tx_prbs31_enable_int;
wire sfp1_rx_clk_int;
wire sfp1_rx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp1_rxd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp1_rxc_int;
wire sfp1_rx_prbs31_enable_int;
wire sfp1_cfg_rx_prbs31_enable_int;
wire [6:0] sfp1_rx_error_count_int;
wire sfp2_tx_clk_int;
wire sfp2_tx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp2_txd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp2_txc_int;
wire sfp2_tx_prbs31_enable_int;
wire sfp2_cfg_tx_prbs31_enable_int;
wire sfp2_rx_clk_int;
wire sfp2_rx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp2_rxd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp2_rxc_int;
wire sfp2_rx_prbs31_enable_int;
wire sfp2_cfg_rx_prbs31_enable_int;
wire [6:0] sfp2_rx_error_count_int;
wire sfp3_tx_clk_int;
wire sfp3_tx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp3_txd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp3_txc_int;
wire sfp3_tx_prbs31_enable_int;
wire sfp3_cfg_tx_prbs31_enable_int;
wire sfp3_rx_clk_int;
wire sfp3_rx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp3_rxd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp3_rxc_int;
wire sfp3_rx_prbs31_enable_int;
wire sfp3_cfg_rx_prbs31_enable_int;
wire [6:0] sfp3_rx_error_count_int;
wire sfp_drp_clk = clk_125mhz_int;
@ -709,8 +709,8 @@ sfp_phy_quad_inst (
.phy_1_rx_block_lock(sfp0_rx_block_lock),
.phy_1_rx_high_ber(),
.phy_1_rx_status(sfp0_rx_status),
.phy_1_tx_prbs31_enable(sfp0_tx_prbs31_enable_int),
.phy_1_rx_prbs31_enable(sfp0_rx_prbs31_enable_int),
.phy_1_cfg_tx_prbs31_enable(sfp0_cfg_tx_prbs31_enable_int),
.phy_1_cfg_rx_prbs31_enable(sfp0_cfg_rx_prbs31_enable_int),
.phy_2_tx_clk(sfp1_tx_clk_int),
.phy_2_tx_rst(sfp1_tx_rst_int),
@ -727,8 +727,8 @@ sfp_phy_quad_inst (
.phy_2_rx_block_lock(sfp1_rx_block_lock),
.phy_2_rx_high_ber(),
.phy_2_rx_status(sfp1_rx_status),
.phy_2_tx_prbs31_enable(sfp1_tx_prbs31_enable_int),
.phy_2_rx_prbs31_enable(sfp1_rx_prbs31_enable_int),
.phy_2_cfg_tx_prbs31_enable(sfp1_cfg_tx_prbs31_enable_int),
.phy_2_cfg_rx_prbs31_enable(sfp1_cfg_rx_prbs31_enable_int),
.phy_3_tx_clk(sfp2_tx_clk_int),
.phy_3_tx_rst(sfp2_tx_rst_int),
@ -745,8 +745,8 @@ sfp_phy_quad_inst (
.phy_3_rx_block_lock(sfp2_rx_block_lock),
.phy_3_rx_high_ber(),
.phy_3_rx_status(sfp2_rx_status),
.phy_3_tx_prbs31_enable(sfp2_tx_prbs31_enable_int),
.phy_3_rx_prbs31_enable(sfp2_rx_prbs31_enable_int),
.phy_3_cfg_tx_prbs31_enable(sfp2_cfg_tx_prbs31_enable_int),
.phy_3_cfg_rx_prbs31_enable(sfp2_cfg_rx_prbs31_enable_int),
.phy_4_tx_clk(sfp3_tx_clk_int),
.phy_4_tx_rst(sfp3_tx_rst_int),
@ -763,8 +763,8 @@ sfp_phy_quad_inst (
.phy_4_rx_block_lock(sfp3_rx_block_lock),
.phy_4_rx_high_ber(),
.phy_4_rx_status(sfp3_rx_status),
.phy_4_tx_prbs31_enable(sfp3_tx_prbs31_enable_int),
.phy_4_rx_prbs31_enable(sfp3_rx_prbs31_enable_int)
.phy_4_cfg_tx_prbs31_enable(sfp3_cfg_tx_prbs31_enable_int),
.phy_4_cfg_rx_prbs31_enable(sfp3_cfg_rx_prbs31_enable_int)
);
wire ptp_clk;
@ -1207,12 +1207,12 @@ core_inst (
.sfp0_tx_rst(sfp0_tx_rst_int),
.sfp0_txd(sfp0_txd_int),
.sfp0_txc(sfp0_txc_int),
.sfp0_tx_prbs31_enable(sfp0_tx_prbs31_enable_int),
.sfp0_cfg_tx_prbs31_enable(sfp0_cfg_tx_prbs31_enable_int),
.sfp0_rx_clk(sfp0_rx_clk_int),
.sfp0_rx_rst(sfp0_rx_rst_int),
.sfp0_rxd(sfp0_rxd_int),
.sfp0_rxc(sfp0_rxc_int),
.sfp0_rx_prbs31_enable(sfp0_rx_prbs31_enable_int),
.sfp0_cfg_rx_prbs31_enable(sfp0_cfg_rx_prbs31_enable_int),
.sfp0_rx_error_count(sfp0_rx_error_count_int),
.sfp0_rx_status(sfp0_rx_status),
.sfp0_tx_disable_b(sfp0_tx_disable_b),
@ -1221,12 +1221,12 @@ core_inst (
.sfp1_tx_rst(sfp1_tx_rst_int),
.sfp1_txd(sfp1_txd_int),
.sfp1_txc(sfp1_txc_int),
.sfp1_tx_prbs31_enable(sfp1_tx_prbs31_enable_int),
.sfp1_cfg_tx_prbs31_enable(sfp1_cfg_tx_prbs31_enable_int),
.sfp1_rx_clk(sfp1_rx_clk_int),
.sfp1_rx_rst(sfp1_rx_rst_int),
.sfp1_rxd(sfp1_rxd_int),
.sfp1_rxc(sfp1_rxc_int),
.sfp1_rx_prbs31_enable(sfp1_rx_prbs31_enable_int),
.sfp1_cfg_rx_prbs31_enable(sfp1_cfg_rx_prbs31_enable_int),
.sfp1_rx_error_count(sfp1_rx_error_count_int),
.sfp1_rx_status(sfp1_rx_status),
.sfp1_tx_disable_b(sfp1_tx_disable_b),
@ -1235,12 +1235,12 @@ core_inst (
.sfp2_tx_rst(sfp2_tx_rst_int),
.sfp2_txd(sfp2_txd_int),
.sfp2_txc(sfp2_txc_int),
.sfp2_tx_prbs31_enable(sfp2_tx_prbs31_enable_int),
.sfp2_cfg_tx_prbs31_enable(sfp2_cfg_tx_prbs31_enable_int),
.sfp2_rx_clk(sfp2_rx_clk_int),
.sfp2_rx_rst(sfp2_rx_rst_int),
.sfp2_rxd(sfp2_rxd_int),
.sfp2_rxc(sfp2_rxc_int),
.sfp2_rx_prbs31_enable(sfp2_rx_prbs31_enable_int),
.sfp2_cfg_rx_prbs31_enable(sfp2_cfg_rx_prbs31_enable_int),
.sfp2_rx_error_count(sfp2_rx_error_count_int),
.sfp2_rx_status(sfp2_rx_status),
.sfp2_tx_disable_b(sfp2_tx_disable_b),
@ -1249,12 +1249,12 @@ core_inst (
.sfp3_tx_rst(sfp3_tx_rst_int),
.sfp3_txd(sfp3_txd_int),
.sfp3_txc(sfp3_txc_int),
.sfp3_tx_prbs31_enable(sfp3_tx_prbs31_enable_int),
.sfp3_cfg_tx_prbs31_enable(sfp3_cfg_tx_prbs31_enable_int),
.sfp3_rx_clk(sfp3_rx_clk_int),
.sfp3_rx_rst(sfp3_rx_rst_int),
.sfp3_rxd(sfp3_rxd_int),
.sfp3_rxc(sfp3_rxc_int),
.sfp3_rx_prbs31_enable(sfp3_rx_prbs31_enable_int),
.sfp3_cfg_rx_prbs31_enable(sfp3_cfg_rx_prbs31_enable_int),
.sfp3_rx_error_count(sfp3_rx_error_count_int),
.sfp3_rx_status(sfp3_rx_status),
.sfp3_tx_disable_b(sfp3_tx_disable_b),

40
fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v
View File

@ -284,12 +284,12 @@ module fpga_core #
input wire sfp0_tx_rst,
output wire [63:0] sfp0_txd,
output wire [7:0] sfp0_txc,
output wire sfp0_tx_prbs31_enable,
output wire sfp0_cfg_tx_prbs31_enable,
input wire sfp0_rx_clk,
input wire sfp0_rx_rst,
input wire [63:0] sfp0_rxd,
input wire [7:0] sfp0_rxc,
output wire sfp0_rx_prbs31_enable,
output wire sfp0_cfg_rx_prbs31_enable,
input wire [6:0] sfp0_rx_error_count,
input wire sfp0_rx_status,
output wire sfp0_tx_disable_b,
@ -298,12 +298,12 @@ module fpga_core #
input wire sfp1_tx_rst,
output wire [63:0] sfp1_txd,
output wire [7:0] sfp1_txc,
output wire sfp1_tx_prbs31_enable,
output wire sfp1_cfg_tx_prbs31_enable,
input wire sfp1_rx_clk,
input wire sfp1_rx_rst,
input wire [63:0] sfp1_rxd,
input wire [7:0] sfp1_rxc,
output wire sfp1_rx_prbs31_enable,
output wire sfp1_cfg_rx_prbs31_enable,
input wire [6:0] sfp1_rx_error_count,
input wire sfp1_rx_status,
output wire sfp1_tx_disable_b,
@ -312,12 +312,12 @@ module fpga_core #
input wire sfp2_tx_rst,
output wire [63:0] sfp2_txd,
output wire [7:0] sfp2_txc,
output wire sfp2_tx_prbs31_enable,
output wire sfp2_cfg_tx_prbs31_enable,
input wire sfp2_rx_clk,
input wire sfp2_rx_rst,
input wire [63:0] sfp2_rxd,
input wire [7:0] sfp2_rxc,
output wire sfp2_rx_prbs31_enable,
output wire sfp2_cfg_rx_prbs31_enable,
input wire [6:0] sfp2_rx_error_count,
input wire sfp2_rx_status,
output wire sfp2_tx_disable_b,
@ -326,12 +326,12 @@ module fpga_core #
input wire sfp3_tx_rst,
output wire [63:0] sfp3_txd,
output wire [7:0] sfp3_txc,
output wire sfp3_tx_prbs31_enable,
output wire sfp3_cfg_tx_prbs31_enable,
input wire sfp3_rx_clk,
input wire sfp3_rx_rst,
input wire [63:0] sfp3_rxd,
input wire [7:0] sfp3_rxc,
output wire sfp3_rx_prbs31_enable,
output wire sfp3_cfg_rx_prbs31_enable,
input wire [6:0] sfp3_rx_error_count,
input wire sfp3_rx_status,
output wire sfp3_tx_disable_b,
@ -610,8 +610,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({sfp3_tx_clk, sfp2_tx_clk, sfp1_tx_clk, sfp0_tx_clk}),
.phy_rx_clk({sfp3_rx_clk, sfp2_rx_clk, sfp1_rx_clk, sfp0_rx_clk}),
.phy_rx_error_count({sfp3_rx_error_count, sfp2_rx_error_count, sfp1_rx_error_count, sfp0_rx_error_count}),
.phy_tx_prbs31_enable({sfp3_tx_prbs31_enable, sfp2_tx_prbs31_enable, sfp1_tx_prbs31_enable, sfp0_tx_prbs31_enable}),
.phy_rx_prbs31_enable({sfp3_rx_prbs31_enable, sfp2_rx_prbs31_enable, sfp1_rx_prbs31_enable, sfp0_rx_prbs31_enable}),
.phy_cfg_tx_prbs31_enable({sfp3_cfg_tx_prbs31_enable, sfp2_cfg_tx_prbs31_enable, sfp1_cfg_tx_prbs31_enable, sfp0_cfg_tx_prbs31_enable}),
.phy_cfg_rx_prbs31_enable({sfp3_cfg_rx_prbs31_enable, sfp2_cfg_rx_prbs31_enable, sfp1_cfg_rx_prbs31_enable, sfp0_cfg_rx_prbs31_enable}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -637,14 +637,14 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign sfp0_tx_prbs31_enable = 1'b0;
assign sfp0_rx_prbs31_enable = 1'b0;
assign sfp1_tx_prbs31_enable = 1'b0;
assign sfp1_rx_prbs31_enable = 1'b0;
assign sfp2_tx_prbs31_enable = 1'b0;
assign sfp2_rx_prbs31_enable = 1'b0;
assign sfp3_tx_prbs31_enable = 1'b0;
assign sfp3_rx_prbs31_enable = 1'b0;
assign sfp0_cfg_tx_prbs31_enable = 1'b0;
assign sfp0_cfg_rx_prbs31_enable = 1'b0;
assign sfp1_cfg_tx_prbs31_enable = 1'b0;
assign sfp1_cfg_rx_prbs31_enable = 1'b0;
assign sfp2_cfg_tx_prbs31_enable = 1'b0;
assign sfp2_cfg_rx_prbs31_enable = 1'b0;
assign sfp3_cfg_tx_prbs31_enable = 1'b0;
assign sfp3_cfg_rx_prbs31_enable = 1'b0;
end
@ -800,7 +800,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

24
fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
View File

@ -676,24 +676,24 @@ wire sfp0_tx_clk_int;
wire sfp0_tx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp0_txd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp0_txc_int;
wire sfp0_tx_prbs31_enable_int;
wire sfp0_cfg_tx_prbs31_enable_int;
wire sfp0_rx_clk_int;
wire sfp0_rx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp0_rxd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp0_rxc_int;
wire sfp0_rx_prbs31_enable_int;
wire sfp0_cfg_rx_prbs31_enable_int;
wire [6:0] sfp0_rx_error_count_int;
wire sfp1_tx_clk_int;
wire sfp1_tx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp1_txd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp1_txc_int;
wire sfp1_tx_prbs31_enable_int;
wire sfp1_cfg_tx_prbs31_enable_int;
wire sfp1_rx_clk_int;
wire sfp1_rx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp1_rxd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp1_rxc_int;
wire sfp1_rx_prbs31_enable_int;
wire sfp1_cfg_rx_prbs31_enable_int;
wire [6:0] sfp1_rx_error_count_int;
wire sfp_drp_clk = clk_125mhz_int;
@ -798,8 +798,8 @@ sfp_phy_quad_inst (
.phy_1_rx_block_lock(sfp0_rx_block_lock),
.phy_1_rx_high_ber(),
.phy_1_rx_status(sfp0_rx_status),
.phy_1_tx_prbs31_enable(sfp0_tx_prbs31_enable_int),
.phy_1_rx_prbs31_enable(sfp0_rx_prbs31_enable_int),
.phy_1_cfg_tx_prbs31_enable(sfp0_cfg_tx_prbs31_enable_int),
.phy_1_cfg_rx_prbs31_enable(sfp0_cfg_rx_prbs31_enable_int),
.phy_2_tx_clk(sfp1_tx_clk_int),
.phy_2_tx_rst(sfp1_tx_rst_int),
@ -816,8 +816,8 @@ sfp_phy_quad_inst (
.phy_2_rx_block_lock(sfp1_rx_block_lock),
.phy_2_rx_high_ber(),
.phy_2_rx_status(sfp1_rx_status),
.phy_2_tx_prbs31_enable(sfp1_tx_prbs31_enable_int),
.phy_2_rx_prbs31_enable(sfp1_rx_prbs31_enable_int)
.phy_2_cfg_tx_prbs31_enable(sfp1_cfg_tx_prbs31_enable_int),
.phy_2_cfg_rx_prbs31_enable(sfp1_cfg_rx_prbs31_enable_int)
);
wire ptp_clk;
@ -1263,12 +1263,12 @@ core_inst (
.sfp0_tx_rst(sfp0_tx_rst_int),
.sfp0_txd(sfp0_txd_int),
.sfp0_txc(sfp0_txc_int),
.sfp0_tx_prbs31_enable(sfp0_tx_prbs31_enable_int),
.sfp0_cfg_tx_prbs31_enable(sfp0_cfg_tx_prbs31_enable_int),
.sfp0_rx_clk(sfp0_rx_clk_int),
.sfp0_rx_rst(sfp0_rx_rst_int),
.sfp0_rxd(sfp0_rxd_int),
.sfp0_rxc(sfp0_rxc_int),
.sfp0_rx_prbs31_enable(sfp0_rx_prbs31_enable_int),
.sfp0_cfg_rx_prbs31_enable(sfp0_cfg_rx_prbs31_enable_int),
.sfp0_rx_error_count(sfp0_rx_error_count_int),
.sfp0_rx_status(sfp0_rx_status),
.sfp0_tx_disable_b(sfp0_tx_disable_b),
@ -1277,12 +1277,12 @@ core_inst (
.sfp1_tx_rst(sfp1_tx_rst_int),
.sfp1_txd(sfp1_txd_int),
.sfp1_txc(sfp1_txc_int),
.sfp1_tx_prbs31_enable(sfp1_tx_prbs31_enable_int),
.sfp1_cfg_tx_prbs31_enable(sfp1_cfg_tx_prbs31_enable_int),
.sfp1_rx_clk(sfp1_rx_clk_int),
.sfp1_rx_rst(sfp1_rx_rst_int),
.sfp1_rxd(sfp1_rxd_int),
.sfp1_rxc(sfp1_rxc_int),
.sfp1_rx_prbs31_enable(sfp1_rx_prbs31_enable_int),
.sfp1_cfg_rx_prbs31_enable(sfp1_cfg_rx_prbs31_enable_int),
.sfp1_rx_error_count(sfp1_rx_error_count_int),
.sfp1_rx_status(sfp1_rx_status),
.sfp1_tx_disable_b(sfp1_tx_disable_b),

24
fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
View File

@ -286,12 +286,12 @@ module fpga_core #
input wire sfp0_tx_rst,
output wire [63:0] sfp0_txd,
output wire [7:0] sfp0_txc,
output wire sfp0_tx_prbs31_enable,
output wire sfp0_cfg_tx_prbs31_enable,
input wire sfp0_rx_clk,
input wire sfp0_rx_rst,
input wire [63:0] sfp0_rxd,
input wire [7:0] sfp0_rxc,
output wire sfp0_rx_prbs31_enable,
output wire sfp0_cfg_rx_prbs31_enable,
input wire [6:0] sfp0_rx_error_count,
input wire sfp0_rx_status,
output wire sfp0_tx_disable_b,
@ -300,12 +300,12 @@ module fpga_core #
input wire sfp1_tx_rst,
output wire [63:0] sfp1_txd,
output wire [7:0] sfp1_txc,
output wire sfp1_tx_prbs31_enable,
output wire sfp1_cfg_tx_prbs31_enable,
input wire sfp1_rx_clk,
input wire sfp1_rx_rst,
input wire [63:0] sfp1_rxd,
input wire [7:0] sfp1_rxc,
output wire sfp1_rx_prbs31_enable,
output wire sfp1_cfg_rx_prbs31_enable,
input wire [6:0] sfp1_rx_error_count,
input wire sfp1_rx_status,
output wire sfp1_tx_disable_b,
@ -605,8 +605,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({sfp1_tx_clk, sfp0_tx_clk}),
.phy_rx_clk({sfp1_rx_clk, sfp0_rx_clk}),
.phy_rx_error_count({sfp1_rx_error_count, sfp0_rx_error_count}),
.phy_tx_prbs31_enable({sfp1_tx_prbs31_enable, sfp0_tx_prbs31_enable}),
.phy_rx_prbs31_enable({sfp1_rx_prbs31_enable, sfp0_rx_prbs31_enable}),
.phy_cfg_tx_prbs31_enable({sfp1_cfg_tx_prbs31_enable, sfp0_cfg_tx_prbs31_enable}),
.phy_cfg_rx_prbs31_enable({sfp1_cfg_rx_prbs31_enable, sfp0_cfg_rx_prbs31_enable}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -632,10 +632,10 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign sfp0_tx_prbs31_enable = 1'b0;
assign sfp0_rx_prbs31_enable = 1'b0;
assign sfp1_tx_prbs31_enable = 1'b0;
assign sfp1_rx_prbs31_enable = 1'b0;
assign sfp0_cfg_tx_prbs31_enable = 1'b0;
assign sfp0_cfg_rx_prbs31_enable = 1'b0;
assign sfp1_cfg_tx_prbs31_enable = 1'b0;
assign sfp1_cfg_rx_prbs31_enable = 1'b0;
end
@ -791,7 +791,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

24
fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
View File

@ -544,24 +544,24 @@ wire sfp0_tx_clk_int;
wire sfp0_tx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp0_txd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp0_txc_int;
wire sfp0_tx_prbs31_enable_int;
wire sfp0_cfg_tx_prbs31_enable_int;
wire sfp0_rx_clk_int;
wire sfp0_rx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp0_rxd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp0_rxc_int;
wire sfp0_rx_prbs31_enable_int;
wire sfp0_cfg_rx_prbs31_enable_int;
wire [6:0] sfp0_rx_error_count_int;
wire sfp1_tx_clk_int;
wire sfp1_tx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp1_txd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp1_txc_int;
wire sfp1_tx_prbs31_enable_int;
wire sfp1_cfg_tx_prbs31_enable_int;
wire sfp1_rx_clk_int;
wire sfp1_rx_rst_int;
wire [XGMII_DATA_WIDTH-1:0] sfp1_rxd_int;
wire [XGMII_CTRL_WIDTH-1:0] sfp1_rxc_int;
wire sfp1_rx_prbs31_enable_int;
wire sfp1_cfg_rx_prbs31_enable_int;
wire [6:0] sfp1_rx_error_count_int;
wire sfp_drp_clk = clk_125mhz_int;
@ -666,8 +666,8 @@ sfp_phy_quad_inst (
.phy_1_rx_block_lock(sfp0_rx_block_lock),
.phy_1_rx_high_ber(),
.phy_1_rx_status(sfp0_rx_status),
.phy_1_tx_prbs31_enable(sfp0_tx_prbs31_enable_int),
.phy_1_rx_prbs31_enable(sfp0_rx_prbs31_enable_int),
.phy_1_cfg_tx_prbs31_enable(sfp0_cfg_tx_prbs31_enable_int),
.phy_1_cfg_rx_prbs31_enable(sfp0_cfg_rx_prbs31_enable_int),
.phy_2_tx_clk(sfp1_tx_clk_int),
.phy_2_tx_rst(sfp1_tx_rst_int),
@ -684,8 +684,8 @@ sfp_phy_quad_inst (
.phy_2_rx_block_lock(sfp1_rx_block_lock),
.phy_2_rx_high_ber(),
.phy_2_rx_status(sfp1_rx_status),
.phy_2_tx_prbs31_enable(sfp1_tx_prbs31_enable_int),
.phy_2_rx_prbs31_enable(sfp1_rx_prbs31_enable_int)
.phy_2_cfg_tx_prbs31_enable(sfp1_cfg_tx_prbs31_enable_int),
.phy_2_cfg_rx_prbs31_enable(sfp1_cfg_rx_prbs31_enable_int)
);
wire ptp_clk;
@ -1128,12 +1128,12 @@ core_inst (
.sfp0_tx_rst(sfp0_tx_rst_int),
.sfp0_txd(sfp0_txd_int),
.sfp0_txc(sfp0_txc_int),
.sfp0_tx_prbs31_enable(sfp0_tx_prbs31_enable_int),
.sfp0_cfg_tx_prbs31_enable(sfp0_cfg_tx_prbs31_enable_int),
.sfp0_rx_clk(sfp0_rx_clk_int),
.sfp0_rx_rst(sfp0_rx_rst_int),
.sfp0_rxd(sfp0_rxd_int),
.sfp0_rxc(sfp0_rxc_int),
.sfp0_rx_prbs31_enable(sfp0_rx_prbs31_enable_int),
.sfp0_cfg_rx_prbs31_enable(sfp0_cfg_rx_prbs31_enable_int),
.sfp0_rx_error_count(sfp0_rx_error_count_int),
.sfp0_rx_status(sfp0_rx_status),
.sfp0_tx_disable_b(sfp0_tx_disable_b),
@ -1142,12 +1142,12 @@ core_inst (
.sfp1_tx_rst(sfp1_tx_rst_int),
.sfp1_txd(sfp1_txd_int),
.sfp1_txc(sfp1_txc_int),
.sfp1_tx_prbs31_enable(sfp1_tx_prbs31_enable_int),
.sfp1_cfg_tx_prbs31_enable(sfp1_cfg_tx_prbs31_enable_int),
.sfp1_rx_clk(sfp1_rx_clk_int),
.sfp1_rx_rst(sfp1_rx_rst_int),
.sfp1_rxd(sfp1_rxd_int),
.sfp1_rxc(sfp1_rxc_int),
.sfp1_rx_prbs31_enable(sfp1_rx_prbs31_enable_int),
.sfp1_cfg_rx_prbs31_enable(sfp1_cfg_rx_prbs31_enable_int),
.sfp1_rx_error_count(sfp1_rx_error_count_int),
.sfp1_rx_status(sfp1_rx_status),
.sfp1_tx_disable_b(sfp1_tx_disable_b),

24
fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
View File

@ -284,12 +284,12 @@ module fpga_core #
input wire sfp0_tx_rst,
output wire [63:0] sfp0_txd,
output wire [7:0] sfp0_txc,
output wire sfp0_tx_prbs31_enable,
output wire sfp0_cfg_tx_prbs31_enable,
input wire sfp0_rx_clk,
input wire sfp0_rx_rst,
input wire [63:0] sfp0_rxd,
input wire [7:0] sfp0_rxc,
output wire sfp0_rx_prbs31_enable,
output wire sfp0_cfg_rx_prbs31_enable,
input wire [6:0] sfp0_rx_error_count,
input wire sfp0_rx_status,
output wire sfp0_tx_disable_b,
@ -298,12 +298,12 @@ module fpga_core #
input wire sfp1_tx_rst,
output wire [63:0] sfp1_txd,
output wire [7:0] sfp1_txc,
output wire sfp1_tx_prbs31_enable,
output wire sfp1_cfg_tx_prbs31_enable,
input wire sfp1_rx_clk,
input wire sfp1_rx_rst,
input wire [63:0] sfp1_rxd,
input wire [7:0] sfp1_rxc,
output wire sfp1_rx_prbs31_enable,
output wire sfp1_cfg_rx_prbs31_enable,
input wire [6:0] sfp1_rx_error_count,
input wire sfp1_rx_status,
output wire sfp1_tx_disable_b,
@ -568,8 +568,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({sfp1_tx_clk, sfp0_tx_clk}),
.phy_rx_clk({sfp1_rx_clk, sfp0_rx_clk}),
.phy_rx_error_count({sfp1_rx_error_count, sfp0_rx_error_count}),
.phy_tx_prbs31_enable({sfp1_tx_prbs31_enable, sfp0_tx_prbs31_enable}),
.phy_rx_prbs31_enable({sfp1_rx_prbs31_enable, sfp0_rx_prbs31_enable}),
.phy_cfg_tx_prbs31_enable({sfp1_cfg_tx_prbs31_enable, sfp0_cfg_tx_prbs31_enable}),
.phy_cfg_rx_prbs31_enable({sfp1_cfg_rx_prbs31_enable, sfp0_cfg_rx_prbs31_enable}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -595,10 +595,10 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign sfp0_tx_prbs31_enable = 1'b0;
assign sfp0_rx_prbs31_enable = 1'b0;
assign sfp1_tx_prbs31_enable = 1'b0;
assign sfp1_rx_prbs31_enable = 1'b0;
assign sfp0_cfg_tx_prbs31_enable = 1'b0;
assign sfp0_cfg_rx_prbs31_enable = 1'b0;
assign sfp1_cfg_tx_prbs31_enable = 1'b0;
assign sfp1_cfg_rx_prbs31_enable = 1'b0;
end
@ -754,7 +754,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

96
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
View File

@ -966,45 +966,45 @@ wire qsfp_0_tx_clk_0_int;
wire qsfp_0_tx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_0_int;
wire qsfp_0_tx_prbs31_enable_0_int;
wire qsfp_0_cfg_tx_prbs31_enable_0_int;
wire qsfp_0_rx_clk_0_int;
wire qsfp_0_rx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_0_int;
wire qsfp_0_rx_prbs31_enable_0_int;
wire qsfp_0_cfg_rx_prbs31_enable_0_int;
wire [6:0] qsfp_0_rx_error_count_0_int;
wire qsfp_0_tx_clk_1_int;
wire qsfp_0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_1_int;
wire qsfp_0_tx_prbs31_enable_1_int;
wire qsfp_0_cfg_tx_prbs31_enable_1_int;
wire qsfp_0_rx_clk_1_int;
wire qsfp_0_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_1_int;
wire qsfp_0_rx_prbs31_enable_1_int;
wire qsfp_0_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp_0_rx_error_count_1_int;
wire qsfp_0_tx_clk_2_int;
wire qsfp_0_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_2_int;
wire qsfp_0_tx_prbs31_enable_2_int;
wire qsfp_0_cfg_tx_prbs31_enable_2_int;
wire qsfp_0_rx_clk_2_int;
wire qsfp_0_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_2_int;
wire qsfp_0_rx_prbs31_enable_2_int;
wire qsfp_0_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp_0_rx_error_count_2_int;
wire qsfp_0_tx_clk_3_int;
wire qsfp_0_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_3_int;
wire qsfp_0_tx_prbs31_enable_3_int;
wire qsfp_0_cfg_tx_prbs31_enable_3_int;
wire qsfp_0_rx_clk_3_int;
wire qsfp_0_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_3_int;
wire qsfp_0_rx_prbs31_enable_3_int;
wire qsfp_0_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp_0_rx_error_count_3_int;
wire qsfp_0_drp_clk = clk_125mhz_int;
@ -1114,8 +1114,8 @@ qsfp_0_phy_quad_inst (
.phy_1_rx_block_lock(qsfp_0_rx_block_lock_0),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp_0_rx_status_0),
.phy_1_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_0_int),
.phy_1_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_0_int),
.phy_1_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_0_int),
.phy_1_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_0_int),
.phy_2_tx_clk(qsfp_0_tx_clk_1_int),
.phy_2_tx_rst(qsfp_0_tx_rst_1_int),
@ -1132,8 +1132,8 @@ qsfp_0_phy_quad_inst (
.phy_2_rx_block_lock(qsfp_0_rx_block_lock_1),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp_0_rx_status_1),
.phy_2_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_1_int),
.phy_2_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_1_int),
.phy_2_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_1_int),
.phy_2_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_1_int),
.phy_3_tx_clk(qsfp_0_tx_clk_2_int),
.phy_3_tx_rst(qsfp_0_tx_rst_2_int),
@ -1150,8 +1150,8 @@ qsfp_0_phy_quad_inst (
.phy_3_rx_block_lock(qsfp_0_rx_block_lock_2),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp_0_rx_status_2),
.phy_3_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_2_int),
.phy_3_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_2_int),
.phy_3_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_2_int),
.phy_3_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_2_int),
.phy_4_tx_clk(qsfp_0_tx_clk_3_int),
.phy_4_tx_rst(qsfp_0_tx_rst_3_int),
@ -1168,8 +1168,8 @@ qsfp_0_phy_quad_inst (
.phy_4_rx_block_lock(qsfp_0_rx_block_lock_3),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp_0_rx_status_3),
.phy_4_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_3_int),
.phy_4_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_3_int)
.phy_4_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_3_int),
.phy_4_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_3_int)
);
// QSFP1
@ -1177,45 +1177,45 @@ wire qsfp_1_tx_clk_0_int;
wire qsfp_1_tx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_0_int;
wire qsfp_1_tx_prbs31_enable_0_int;
wire qsfp_1_cfg_tx_prbs31_enable_0_int;
wire qsfp_1_rx_clk_0_int;
wire qsfp_1_rx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_0_int;
wire qsfp_1_rx_prbs31_enable_0_int;
wire qsfp_1_cfg_rx_prbs31_enable_0_int;
wire [6:0] qsfp_1_rx_error_count_0_int;
wire qsfp_1_tx_clk_1_int;
wire qsfp_1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_1_int;
wire qsfp_1_tx_prbs31_enable_1_int;
wire qsfp_1_cfg_tx_prbs31_enable_1_int;
wire qsfp_1_rx_clk_1_int;
wire qsfp_1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_1_int;
wire qsfp_1_rx_prbs31_enable_1_int;
wire qsfp_1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp_1_rx_error_count_1_int;
wire qsfp_1_tx_clk_2_int;
wire qsfp_1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_2_int;
wire qsfp_1_tx_prbs31_enable_2_int;
wire qsfp_1_cfg_tx_prbs31_enable_2_int;
wire qsfp_1_rx_clk_2_int;
wire qsfp_1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_2_int;
wire qsfp_1_rx_prbs31_enable_2_int;
wire qsfp_1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp_1_rx_error_count_2_int;
wire qsfp_1_tx_clk_3_int;
wire qsfp_1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_3_int;
wire qsfp_1_tx_prbs31_enable_3_int;
wire qsfp_1_cfg_tx_prbs31_enable_3_int;
wire qsfp_1_rx_clk_3_int;
wire qsfp_1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_3_int;
wire qsfp_1_rx_prbs31_enable_3_int;
wire qsfp_1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp_1_rx_error_count_3_int;
wire qsfp_1_drp_clk = clk_125mhz_int;
@ -1325,8 +1325,8 @@ qsfp_1_phy_quad_inst (
.phy_1_rx_block_lock(qsfp_1_rx_block_lock_0),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp_1_rx_status_0),
.phy_1_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_0_int),
.phy_1_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_0_int),
.phy_1_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_0_int),
.phy_1_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_0_int),
.phy_2_tx_clk(qsfp_1_tx_clk_1_int),
.phy_2_tx_rst(qsfp_1_tx_rst_1_int),
@ -1343,8 +1343,8 @@ qsfp_1_phy_quad_inst (
.phy_2_rx_block_lock(qsfp_1_rx_block_lock_1),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp_1_rx_status_1),
.phy_2_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_1_int),
.phy_2_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_1_int),
.phy_2_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_1_int),
.phy_2_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_1_int),
.phy_3_tx_clk(qsfp_1_tx_clk_2_int),
.phy_3_tx_rst(qsfp_1_tx_rst_2_int),
@ -1361,8 +1361,8 @@ qsfp_1_phy_quad_inst (
.phy_3_rx_block_lock(qsfp_1_rx_block_lock_2),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp_1_rx_status_2),
.phy_3_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_2_int),
.phy_3_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_2_int),
.phy_3_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_2_int),
.phy_3_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_2_int),
.phy_4_tx_clk(qsfp_1_tx_clk_3_int),
.phy_4_tx_rst(qsfp_1_tx_rst_3_int),
@ -1379,8 +1379,8 @@ qsfp_1_phy_quad_inst (
.phy_4_rx_block_lock(qsfp_1_rx_block_lock_3),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp_1_rx_status_3),
.phy_4_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_3_int),
.phy_4_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_3_int)
.phy_4_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_3_int),
.phy_4_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_3_int)
);
wire ptp_clk;
@ -2269,48 +2269,48 @@ core_inst (
.qsfp_0_tx_rst_0(qsfp_0_tx_rst_0_int),
.qsfp_0_txd_0(qsfp_0_txd_0_int),
.qsfp_0_txc_0(qsfp_0_txc_0_int),
.qsfp_0_tx_prbs31_enable_0(qsfp_0_tx_prbs31_enable_0_int),
.qsfp_0_cfg_tx_prbs31_enable_0(qsfp_0_cfg_tx_prbs31_enable_0_int),
.qsfp_0_rx_clk_0(qsfp_0_rx_clk_0_int),
.qsfp_0_rx_rst_0(qsfp_0_rx_rst_0_int),
.qsfp_0_rxd_0(qsfp_0_rxd_0_int),
.qsfp_0_rxc_0(qsfp_0_rxc_0_int),
.qsfp_0_rx_prbs31_enable_0(qsfp_0_rx_prbs31_enable_0_int),
.qsfp_0_cfg_rx_prbs31_enable_0(qsfp_0_cfg_rx_prbs31_enable_0_int),
.qsfp_0_rx_error_count_0(qsfp_0_rx_error_count_0_int),
.qsfp_0_rx_status_0(qsfp_0_rx_status_0),
.qsfp_0_tx_clk_1(qsfp_0_tx_clk_1_int),
.qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int),
.qsfp_0_txd_1(qsfp_0_txd_1_int),
.qsfp_0_txc_1(qsfp_0_txc_1_int),
.qsfp_0_tx_prbs31_enable_1(qsfp_0_tx_prbs31_enable_1_int),
.qsfp_0_cfg_tx_prbs31_enable_1(qsfp_0_cfg_tx_prbs31_enable_1_int),
.qsfp_0_rx_clk_1(qsfp_0_rx_clk_1_int),
.qsfp_0_rx_rst_1(qsfp_0_rx_rst_1_int),
.qsfp_0_rxd_1(qsfp_0_rxd_1_int),
.qsfp_0_rxc_1(qsfp_0_rxc_1_int),
.qsfp_0_rx_prbs31_enable_1(qsfp_0_rx_prbs31_enable_1_int),
.qsfp_0_cfg_rx_prbs31_enable_1(qsfp_0_cfg_rx_prbs31_enable_1_int),
.qsfp_0_rx_error_count_1(qsfp_0_rx_error_count_1_int),
.qsfp_0_rx_status_1(qsfp_0_rx_status_1),
.qsfp_0_tx_clk_2(qsfp_0_tx_clk_2_int),
.qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int),
.qsfp_0_txd_2(qsfp_0_txd_2_int),
.qsfp_0_txc_2(qsfp_0_txc_2_int),
.qsfp_0_tx_prbs31_enable_2(qsfp_0_tx_prbs31_enable_2_int),
.qsfp_0_cfg_tx_prbs31_enable_2(qsfp_0_cfg_tx_prbs31_enable_2_int),
.qsfp_0_rx_clk_2(qsfp_0_rx_clk_2_int),
.qsfp_0_rx_rst_2(qsfp_0_rx_rst_2_int),
.qsfp_0_rxd_2(qsfp_0_rxd_2_int),
.qsfp_0_rxc_2(qsfp_0_rxc_2_int),
.qsfp_0_rx_prbs31_enable_2(qsfp_0_rx_prbs31_enable_2_int),
.qsfp_0_cfg_rx_prbs31_enable_2(qsfp_0_cfg_rx_prbs31_enable_2_int),
.qsfp_0_rx_error_count_2(qsfp_0_rx_error_count_2_int),
.qsfp_0_rx_status_2(qsfp_0_rx_status_2),
.qsfp_0_tx_clk_3(qsfp_0_tx_clk_3_int),
.qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int),
.qsfp_0_txd_3(qsfp_0_txd_3_int),
.qsfp_0_txc_3(qsfp_0_txc_3_int),
.qsfp_0_tx_prbs31_enable_3(qsfp_0_tx_prbs31_enable_3_int),
.qsfp_0_cfg_tx_prbs31_enable_3(qsfp_0_cfg_tx_prbs31_enable_3_int),
.qsfp_0_rx_clk_3(qsfp_0_rx_clk_3_int),
.qsfp_0_rx_rst_3(qsfp_0_rx_rst_3_int),
.qsfp_0_rxd_3(qsfp_0_rxd_3_int),
.qsfp_0_rxc_3(qsfp_0_rxc_3_int),
.qsfp_0_rx_prbs31_enable_3(qsfp_0_rx_prbs31_enable_3_int),
.qsfp_0_cfg_rx_prbs31_enable_3(qsfp_0_cfg_rx_prbs31_enable_3_int),
.qsfp_0_rx_error_count_3(qsfp_0_rx_error_count_3_int),
.qsfp_0_rx_status_3(qsfp_0_rx_status_3),
.qsfp_0_drp_clk(qsfp_0_drp_clk),
@ -2335,48 +2335,48 @@ core_inst (
.qsfp_1_tx_rst_0(qsfp_1_tx_rst_0_int),
.qsfp_1_txd_0(qsfp_1_txd_0_int),
.qsfp_1_txc_0(qsfp_1_txc_0_int),
.qsfp_1_tx_prbs31_enable_0(qsfp_1_tx_prbs31_enable_0_int),
.qsfp_1_cfg_tx_prbs31_enable_0(qsfp_1_cfg_tx_prbs31_enable_0_int),
.qsfp_1_rx_clk_0(qsfp_1_rx_clk_0_int),
.qsfp_1_rx_rst_0(qsfp_1_rx_rst_0_int),
.qsfp_1_rxd_0(qsfp_1_rxd_0_int),
.qsfp_1_rxc_0(qsfp_1_rxc_0_int),
.qsfp_1_rx_prbs31_enable_0(qsfp_1_rx_prbs31_enable_0_int),
.qsfp_1_cfg_rx_prbs31_enable_0(qsfp_1_cfg_rx_prbs31_enable_0_int),
.qsfp_1_rx_error_count_0(qsfp_1_rx_error_count_0_int),
.qsfp_1_rx_status_0(qsfp_1_rx_status_0),
.qsfp_1_tx_clk_1(qsfp_1_tx_clk_1_int),
.qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int),
.qsfp_1_txd_1(qsfp_1_txd_1_int),
.qsfp_1_txc_1(qsfp_1_txc_1_int),
.qsfp_1_tx_prbs31_enable_1(qsfp_1_tx_prbs31_enable_1_int),
.qsfp_1_cfg_tx_prbs31_enable_1(qsfp_1_cfg_tx_prbs31_enable_1_int),
.qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int),
.qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int),
.qsfp_1_rxd_1(qsfp_1_rxd_1_int),
.qsfp_1_rxc_1(qsfp_1_rxc_1_int),
.qsfp_1_rx_prbs31_enable_1(qsfp_1_rx_prbs31_enable_1_int),
.qsfp_1_cfg_rx_prbs31_enable_1(qsfp_1_cfg_rx_prbs31_enable_1_int),
.qsfp_1_rx_error_count_1(qsfp_1_rx_error_count_1_int),
.qsfp_1_rx_status_1(qsfp_1_rx_status_1),
.qsfp_1_tx_clk_2(qsfp_1_tx_clk_2_int),
.qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int),
.qsfp_1_txd_2(qsfp_1_txd_2_int),
.qsfp_1_txc_2(qsfp_1_txc_2_int),
.qsfp_1_tx_prbs31_enable_2(qsfp_1_tx_prbs31_enable_2_int),
.qsfp_1_cfg_tx_prbs31_enable_2(qsfp_1_cfg_tx_prbs31_enable_2_int),
.qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int),
.qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int),
.qsfp_1_rxd_2(qsfp_1_rxd_2_int),
.qsfp_1_rxc_2(qsfp_1_rxc_2_int),
.qsfp_1_rx_prbs31_enable_2(qsfp_1_rx_prbs31_enable_2_int),
.qsfp_1_cfg_rx_prbs31_enable_2(qsfp_1_cfg_rx_prbs31_enable_2_int),
.qsfp_1_rx_error_count_2(qsfp_1_rx_error_count_2_int),
.qsfp_1_rx_status_2(qsfp_1_rx_status_2),
.qsfp_1_tx_clk_3(qsfp_1_tx_clk_3_int),
.qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int),
.qsfp_1_txd_3(qsfp_1_txd_3_int),
.qsfp_1_txc_3(qsfp_1_txc_3_int),
.qsfp_1_tx_prbs31_enable_3(qsfp_1_tx_prbs31_enable_3_int),
.qsfp_1_cfg_tx_prbs31_enable_3(qsfp_1_cfg_tx_prbs31_enable_3_int),
.qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int),
.qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int),
.qsfp_1_rxd_3(qsfp_1_rxd_3_int),
.qsfp_1_rxc_3(qsfp_1_rxc_3_int),
.qsfp_1_rx_prbs31_enable_3(qsfp_1_rx_prbs31_enable_3_int),
.qsfp_1_cfg_rx_prbs31_enable_3(qsfp_1_cfg_rx_prbs31_enable_3_int),
.qsfp_1_rx_error_count_3(qsfp_1_rx_error_count_3_int),
.qsfp_1_rx_status_3(qsfp_1_rx_status_3),
.qsfp_1_drp_clk(qsfp_1_drp_clk),

72
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
View File

@ -286,48 +286,48 @@ module fpga_core #
input wire qsfp_0_tx_rst_0,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_0,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_0,
output wire qsfp_0_tx_prbs31_enable_0,
output wire qsfp_0_cfg_tx_prbs31_enable_0,
input wire qsfp_0_rx_clk_0,
input wire qsfp_0_rx_rst_0,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_0,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_0,
output wire qsfp_0_rx_prbs31_enable_0,
output wire qsfp_0_cfg_rx_prbs31_enable_0,
input wire [6:0] qsfp_0_rx_error_count_0,
input wire qsfp_0_rx_status_0,
input wire qsfp_0_tx_clk_1,
input wire qsfp_0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_1,
output wire qsfp_0_tx_prbs31_enable_1,
output wire qsfp_0_cfg_tx_prbs31_enable_1,
input wire qsfp_0_rx_clk_1,
input wire qsfp_0_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_1,
output wire qsfp_0_rx_prbs31_enable_1,
output wire qsfp_0_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp_0_rx_error_count_1,
input wire qsfp_0_rx_status_1,
input wire qsfp_0_tx_clk_2,
input wire qsfp_0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_2,
output wire qsfp_0_tx_prbs31_enable_2,
output wire qsfp_0_cfg_tx_prbs31_enable_2,
input wire qsfp_0_rx_clk_2,
input wire qsfp_0_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_2,
output wire qsfp_0_rx_prbs31_enable_2,
output wire qsfp_0_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp_0_rx_error_count_2,
input wire qsfp_0_rx_status_2,
input wire qsfp_0_tx_clk_3,
input wire qsfp_0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_3,
output wire qsfp_0_tx_prbs31_enable_3,
output wire qsfp_0_cfg_tx_prbs31_enable_3,
input wire qsfp_0_rx_clk_3,
input wire qsfp_0_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_3,
output wire qsfp_0_rx_prbs31_enable_3,
output wire qsfp_0_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp_0_rx_error_count_3,
input wire qsfp_0_rx_status_3,
@ -355,48 +355,48 @@ module fpga_core #
input wire qsfp_1_tx_rst_0,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_0,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_0,
output wire qsfp_1_tx_prbs31_enable_0,
output wire qsfp_1_cfg_tx_prbs31_enable_0,
input wire qsfp_1_rx_clk_0,
input wire qsfp_1_rx_rst_0,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_0,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_0,
output wire qsfp_1_rx_prbs31_enable_0,
output wire qsfp_1_cfg_rx_prbs31_enable_0,
input wire [6:0] qsfp_1_rx_error_count_0,
input wire qsfp_1_rx_status_0,
input wire qsfp_1_tx_clk_1,
input wire qsfp_1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_1,
output wire qsfp_1_tx_prbs31_enable_1,
output wire qsfp_1_cfg_tx_prbs31_enable_1,
input wire qsfp_1_rx_clk_1,
input wire qsfp_1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_1,
output wire qsfp_1_rx_prbs31_enable_1,
output wire qsfp_1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp_1_rx_error_count_1,
input wire qsfp_1_rx_status_1,
input wire qsfp_1_tx_clk_2,
input wire qsfp_1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_2,
output wire qsfp_1_tx_prbs31_enable_2,
output wire qsfp_1_cfg_tx_prbs31_enable_2,
input wire qsfp_1_rx_clk_2,
input wire qsfp_1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_2,
output wire qsfp_1_rx_prbs31_enable_2,
output wire qsfp_1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp_1_rx_error_count_2,
input wire qsfp_1_rx_status_2,
input wire qsfp_1_tx_clk_3,
input wire qsfp_1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_3,
output wire qsfp_1_tx_prbs31_enable_3,
output wire qsfp_1_cfg_tx_prbs31_enable_3,
input wire qsfp_1_rx_clk_3,
input wire qsfp_1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_3,
output wire qsfp_1_rx_prbs31_enable_3,
output wire qsfp_1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp_1_rx_error_count_3,
input wire qsfp_1_rx_status_3,
@ -930,8 +930,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp_1_tx_clk_3, qsfp_1_tx_clk_2, qsfp_1_tx_clk_1, qsfp_1_tx_clk_0, qsfp_0_tx_clk_3, qsfp_0_tx_clk_2, qsfp_0_tx_clk_1, qsfp_0_tx_clk_0}),
.phy_rx_clk({qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}),
.phy_rx_error_count({qsfp_1_rx_error_count_3, qsfp_1_rx_error_count_2, qsfp_1_rx_error_count_1, qsfp_1_rx_error_count_0, qsfp_0_rx_error_count_3, qsfp_0_rx_error_count_2, qsfp_0_rx_error_count_1, qsfp_0_rx_error_count_0}),
.phy_tx_prbs31_enable({qsfp_1_tx_prbs31_enable_3, qsfp_1_tx_prbs31_enable_2, qsfp_1_tx_prbs31_enable_1, qsfp_1_tx_prbs31_enable_0, qsfp_0_tx_prbs31_enable_3, qsfp_0_tx_prbs31_enable_2, qsfp_0_tx_prbs31_enable_1, qsfp_0_tx_prbs31_enable_0}),
.phy_rx_prbs31_enable({qsfp_1_rx_prbs31_enable_3, qsfp_1_rx_prbs31_enable_2, qsfp_1_rx_prbs31_enable_1, qsfp_1_rx_prbs31_enable_0, qsfp_0_rx_prbs31_enable_3, qsfp_0_rx_prbs31_enable_2, qsfp_0_rx_prbs31_enable_1, qsfp_0_rx_prbs31_enable_0}),
.phy_cfg_tx_prbs31_enable({qsfp_1_cfg_tx_prbs31_enable_3, qsfp_1_cfg_tx_prbs31_enable_2, qsfp_1_cfg_tx_prbs31_enable_1, qsfp_1_cfg_tx_prbs31_enable_0, qsfp_0_cfg_tx_prbs31_enable_3, qsfp_0_cfg_tx_prbs31_enable_2, qsfp_0_cfg_tx_prbs31_enable_1, qsfp_0_cfg_tx_prbs31_enable_0}),
.phy_cfg_rx_prbs31_enable({qsfp_1_cfg_rx_prbs31_enable_3, qsfp_1_cfg_rx_prbs31_enable_2, qsfp_1_cfg_rx_prbs31_enable_1, qsfp_1_cfg_rx_prbs31_enable_0, qsfp_0_cfg_rx_prbs31_enable_3, qsfp_0_cfg_rx_prbs31_enable_2, qsfp_0_cfg_rx_prbs31_enable_1, qsfp_0_cfg_rx_prbs31_enable_0}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -957,22 +957,22 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp_0_tx_prbs31_enable_0 = 1'b0;
assign qsfp_0_rx_prbs31_enable_0 = 1'b0;
assign qsfp_0_tx_prbs31_enable_1 = 1'b0;
assign qsfp_0_rx_prbs31_enable_1 = 1'b0;
assign qsfp_0_tx_prbs31_enable_2 = 1'b0;
assign qsfp_0_rx_prbs31_enable_2 = 1'b0;
assign qsfp_0_tx_prbs31_enable_3 = 1'b0;
assign qsfp_0_rx_prbs31_enable_3 = 1'b0;
assign qsfp_1_tx_prbs31_enable_0 = 1'b0;
assign qsfp_1_rx_prbs31_enable_0 = 1'b0;
assign qsfp_1_tx_prbs31_enable_1 = 1'b0;
assign qsfp_1_rx_prbs31_enable_1 = 1'b0;
assign qsfp_1_tx_prbs31_enable_2 = 1'b0;
assign qsfp_1_rx_prbs31_enable_2 = 1'b0;
assign qsfp_1_tx_prbs31_enable_3 = 1'b0;
assign qsfp_1_rx_prbs31_enable_3 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_0 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_0 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_0 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_0 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_3 = 1'b0;
end
@ -1132,7 +1132,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end

192
fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v
View File

@ -944,45 +944,45 @@ wire qsfp_0_tx_clk_0_int;
wire qsfp_0_tx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_0_int;
wire qsfp_0_tx_prbs31_enable_0_int;
wire qsfp_0_cfg_tx_prbs31_enable_0_int;
wire qsfp_0_rx_clk_0_int;
wire qsfp_0_rx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_0_int;
wire qsfp_0_rx_prbs31_enable_0_int;
wire qsfp_0_cfg_rx_prbs31_enable_0_int;
wire [6:0] qsfp_0_rx_error_count_0_int;
wire qsfp_0_tx_clk_1_int;
wire qsfp_0_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_1_int;
wire qsfp_0_tx_prbs31_enable_1_int;
wire qsfp_0_cfg_tx_prbs31_enable_1_int;
wire qsfp_0_rx_clk_1_int;
wire qsfp_0_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_1_int;
wire qsfp_0_rx_prbs31_enable_1_int;
wire qsfp_0_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp_0_rx_error_count_1_int;
wire qsfp_0_tx_clk_2_int;
wire qsfp_0_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_2_int;
wire qsfp_0_tx_prbs31_enable_2_int;
wire qsfp_0_cfg_tx_prbs31_enable_2_int;
wire qsfp_0_rx_clk_2_int;
wire qsfp_0_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_2_int;
wire qsfp_0_rx_prbs31_enable_2_int;
wire qsfp_0_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp_0_rx_error_count_2_int;
wire qsfp_0_tx_clk_3_int;
wire qsfp_0_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_3_int;
wire qsfp_0_tx_prbs31_enable_3_int;
wire qsfp_0_cfg_tx_prbs31_enable_3_int;
wire qsfp_0_rx_clk_3_int;
wire qsfp_0_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_3_int;
wire qsfp_0_rx_prbs31_enable_3_int;
wire qsfp_0_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp_0_rx_error_count_3_int;
wire qsfp_0_drp_clk = clk_125mhz_int;
@ -1100,8 +1100,8 @@ qsfp_0_phy_quad_inst (
.phy_1_rx_block_lock(qsfp_0_rx_block_lock_0),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp_0_rx_status_0),
.phy_1_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_0_int),
.phy_1_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_0_int),
.phy_1_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_0_int),
.phy_1_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_0_int),
.phy_2_tx_clk(qsfp_0_tx_clk_1_int),
.phy_2_tx_rst(qsfp_0_tx_rst_1_int),
@ -1118,8 +1118,8 @@ qsfp_0_phy_quad_inst (
.phy_2_rx_block_lock(qsfp_0_rx_block_lock_1),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp_0_rx_status_1),
.phy_2_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_1_int),
.phy_2_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_1_int),
.phy_2_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_1_int),
.phy_2_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_1_int),
.phy_3_tx_clk(qsfp_0_tx_clk_2_int),
.phy_3_tx_rst(qsfp_0_tx_rst_2_int),
@ -1136,8 +1136,8 @@ qsfp_0_phy_quad_inst (
.phy_3_rx_block_lock(qsfp_0_rx_block_lock_2),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp_0_rx_status_2),
.phy_3_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_2_int),
.phy_3_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_2_int),
.phy_3_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_2_int),
.phy_3_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_2_int),
.phy_4_tx_clk(qsfp_0_tx_clk_3_int),
.phy_4_tx_rst(qsfp_0_tx_rst_3_int),
@ -1154,8 +1154,8 @@ qsfp_0_phy_quad_inst (
.phy_4_rx_block_lock(qsfp_0_rx_block_lock_3),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp_0_rx_status_3),
.phy_4_tx_prbs31_enable(qsfp_0_tx_prbs31_enable_3_int),
.phy_4_rx_prbs31_enable(qsfp_0_rx_prbs31_enable_3_int)
.phy_4_cfg_tx_prbs31_enable(qsfp_0_cfg_tx_prbs31_enable_3_int),
.phy_4_cfg_rx_prbs31_enable(qsfp_0_cfg_rx_prbs31_enable_3_int)
);
// QSFP1
@ -1163,45 +1163,45 @@ wire qsfp_1_tx_clk_0_int;
wire qsfp_1_tx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_0_int;
wire qsfp_1_tx_prbs31_enable_0_int;
wire qsfp_1_cfg_tx_prbs31_enable_0_int;
wire qsfp_1_rx_clk_0_int;
wire qsfp_1_rx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_0_int;
wire qsfp_1_rx_prbs31_enable_0_int;
wire qsfp_1_cfg_rx_prbs31_enable_0_int;
wire [6:0] qsfp_1_rx_error_count_0_int;
wire qsfp_1_tx_clk_1_int;
wire qsfp_1_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_1_int;
wire qsfp_1_tx_prbs31_enable_1_int;
wire qsfp_1_cfg_tx_prbs31_enable_1_int;
wire qsfp_1_rx_clk_1_int;
wire qsfp_1_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_1_int;
wire qsfp_1_rx_prbs31_enable_1_int;
wire qsfp_1_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp_1_rx_error_count_1_int;
wire qsfp_1_tx_clk_2_int;
wire qsfp_1_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_2_int;
wire qsfp_1_tx_prbs31_enable_2_int;
wire qsfp_1_cfg_tx_prbs31_enable_2_int;
wire qsfp_1_rx_clk_2_int;
wire qsfp_1_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_2_int;
wire qsfp_1_rx_prbs31_enable_2_int;
wire qsfp_1_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp_1_rx_error_count_2_int;
wire qsfp_1_tx_clk_3_int;
wire qsfp_1_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_3_int;
wire qsfp_1_tx_prbs31_enable_3_int;
wire qsfp_1_cfg_tx_prbs31_enable_3_int;
wire qsfp_1_rx_clk_3_int;
wire qsfp_1_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_3_int;
wire qsfp_1_rx_prbs31_enable_3_int;
wire qsfp_1_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp_1_rx_error_count_3_int;
wire qsfp_1_drp_clk = clk_125mhz_int;
@ -1319,8 +1319,8 @@ qsfp_1_phy_quad_inst (
.phy_1_rx_block_lock(qsfp_1_rx_block_lock_0),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp_1_rx_status_0),
.phy_1_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_0_int),
.phy_1_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_0_int),
.phy_1_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_0_int),
.phy_1_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_0_int),
.phy_2_tx_clk(qsfp_1_tx_clk_1_int),
.phy_2_tx_rst(qsfp_1_tx_rst_1_int),
@ -1337,8 +1337,8 @@ qsfp_1_phy_quad_inst (
.phy_2_rx_block_lock(qsfp_1_rx_block_lock_1),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp_1_rx_status_1),
.phy_2_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_1_int),
.phy_2_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_1_int),
.phy_2_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_1_int),
.phy_2_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_1_int),
.phy_3_tx_clk(qsfp_1_tx_clk_2_int),
.phy_3_tx_rst(qsfp_1_tx_rst_2_int),
@ -1355,8 +1355,8 @@ qsfp_1_phy_quad_inst (
.phy_3_rx_block_lock(qsfp_1_rx_block_lock_2),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp_1_rx_status_2),
.phy_3_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_2_int),
.phy_3_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_2_int),
.phy_3_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_2_int),
.phy_3_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_2_int),
.phy_4_tx_clk(qsfp_1_tx_clk_3_int),
.phy_4_tx_rst(qsfp_1_tx_rst_3_int),
@ -1373,8 +1373,8 @@ qsfp_1_phy_quad_inst (
.phy_4_rx_block_lock(qsfp_1_rx_block_lock_3),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp_1_rx_status_3),
.phy_4_tx_prbs31_enable(qsfp_1_tx_prbs31_enable_3_int),
.phy_4_rx_prbs31_enable(qsfp_1_rx_prbs31_enable_3_int)
.phy_4_cfg_tx_prbs31_enable(qsfp_1_cfg_tx_prbs31_enable_3_int),
.phy_4_cfg_rx_prbs31_enable(qsfp_1_cfg_rx_prbs31_enable_3_int)
);
// QSFP2
@ -1382,45 +1382,45 @@ wire qsfp_2_tx_clk_0_int;
wire qsfp_2_tx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_0_int;
wire qsfp_2_tx_prbs31_enable_0_int;
wire qsfp_2_cfg_tx_prbs31_enable_0_int;
wire qsfp_2_rx_clk_0_int;
wire qsfp_2_rx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_0_int;
wire qsfp_2_rx_prbs31_enable_0_int;
wire qsfp_2_cfg_rx_prbs31_enable_0_int;
wire [6:0] qsfp_2_rx_error_count_0_int;
wire qsfp_2_tx_clk_1_int;
wire qsfp_2_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_1_int;
wire qsfp_2_tx_prbs31_enable_1_int;
wire qsfp_2_cfg_tx_prbs31_enable_1_int;
wire qsfp_2_rx_clk_1_int;
wire qsfp_2_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_1_int;
wire qsfp_2_rx_prbs31_enable_1_int;
wire qsfp_2_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp_2_rx_error_count_1_int;
wire qsfp_2_tx_clk_2_int;
wire qsfp_2_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_2_int;
wire qsfp_2_tx_prbs31_enable_2_int;
wire qsfp_2_cfg_tx_prbs31_enable_2_int;
wire qsfp_2_rx_clk_2_int;
wire qsfp_2_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_2_int;
wire qsfp_2_rx_prbs31_enable_2_int;
wire qsfp_2_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp_2_rx_error_count_2_int;
wire qsfp_2_tx_clk_3_int;
wire qsfp_2_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_3_int;
wire qsfp_2_tx_prbs31_enable_3_int;
wire qsfp_2_cfg_tx_prbs31_enable_3_int;
wire qsfp_2_rx_clk_3_int;
wire qsfp_2_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_3_int;
wire qsfp_2_rx_prbs31_enable_3_int;
wire qsfp_2_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp_2_rx_error_count_3_int;
wire qsfp_2_drp_clk = clk_125mhz_int;
@ -1538,8 +1538,8 @@ qsfp_2_phy_quad_inst (
.phy_1_rx_block_lock(qsfp_2_rx_block_lock_0),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp_2_rx_status_0),
.phy_1_tx_prbs31_enable(qsfp_2_tx_prbs31_enable_0_int),
.phy_1_rx_prbs31_enable(qsfp_2_rx_prbs31_enable_0_int),
.phy_1_cfg_tx_prbs31_enable(qsfp_2_cfg_tx_prbs31_enable_0_int),
.phy_1_cfg_rx_prbs31_enable(qsfp_2_cfg_rx_prbs31_enable_0_int),
.phy_2_tx_clk(qsfp_2_tx_clk_1_int),
.phy_2_tx_rst(qsfp_2_tx_rst_1_int),
@ -1556,8 +1556,8 @@ qsfp_2_phy_quad_inst (
.phy_2_rx_block_lock(qsfp_2_rx_block_lock_1),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp_2_rx_status_1),
.phy_2_tx_prbs31_enable(qsfp_2_tx_prbs31_enable_1_int),
.phy_2_rx_prbs31_enable(qsfp_2_rx_prbs31_enable_1_int),
.phy_2_cfg_tx_prbs31_enable(qsfp_2_cfg_tx_prbs31_enable_1_int),
.phy_2_cfg_rx_prbs31_enable(qsfp_2_cfg_rx_prbs31_enable_1_int),
.phy_3_tx_clk(qsfp_2_tx_clk_2_int),
.phy_3_tx_rst(qsfp_2_tx_rst_2_int),
@ -1574,8 +1574,8 @@ qsfp_2_phy_quad_inst (
.phy_3_rx_block_lock(qsfp_2_rx_block_lock_2),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp_2_rx_status_2),
.phy_3_tx_prbs31_enable(qsfp_2_tx_prbs31_enable_2_int),
.phy_3_rx_prbs31_enable(qsfp_2_rx_prbs31_enable_2_int),
.phy_3_cfg_tx_prbs31_enable(qsfp_2_cfg_tx_prbs31_enable_2_int),
.phy_3_cfg_rx_prbs31_enable(qsfp_2_cfg_rx_prbs31_enable_2_int),
.phy_4_tx_clk(qsfp_2_tx_clk_3_int),
.phy_4_tx_rst(qsfp_2_tx_rst_3_int),
@ -1592,8 +1592,8 @@ qsfp_2_phy_quad_inst (
.phy_4_rx_block_lock(qsfp_2_rx_block_lock_3),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp_2_rx_status_3),
.phy_4_tx_prbs31_enable(qsfp_2_tx_prbs31_enable_3_int),
.phy_4_rx_prbs31_enable(qsfp_2_rx_prbs31_enable_3_int)
.phy_4_cfg_tx_prbs31_enable(qsfp_2_cfg_tx_prbs31_enable_3_int),
.phy_4_cfg_rx_prbs31_enable(qsfp_2_cfg_rx_prbs31_enable_3_int)
);
// QSFP3
@ -1601,45 +1601,45 @@ wire qsfp_3_tx_clk_0_int;
wire qsfp_3_tx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_0_int;
wire qsfp_3_tx_prbs31_enable_0_int;
wire qsfp_3_cfg_tx_prbs31_enable_0_int;
wire qsfp_3_rx_clk_0_int;
wire qsfp_3_rx_rst_0_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_0_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_0_int;
wire qsfp_3_rx_prbs31_enable_0_int;
wire qsfp_3_cfg_rx_prbs31_enable_0_int;
wire [6:0] qsfp_3_rx_error_count_0_int;
wire qsfp_3_tx_clk_1_int;
wire qsfp_3_tx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_1_int;
wire qsfp_3_tx_prbs31_enable_1_int;
wire qsfp_3_cfg_tx_prbs31_enable_1_int;
wire qsfp_3_rx_clk_1_int;
wire qsfp_3_rx_rst_1_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_1_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_1_int;
wire qsfp_3_rx_prbs31_enable_1_int;
wire qsfp_3_cfg_rx_prbs31_enable_1_int;
wire [6:0] qsfp_3_rx_error_count_1_int;
wire qsfp_3_tx_clk_2_int;
wire qsfp_3_tx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_2_int;
wire qsfp_3_tx_prbs31_enable_2_int;
wire qsfp_3_cfg_tx_prbs31_enable_2_int;
wire qsfp_3_rx_clk_2_int;
wire qsfp_3_rx_rst_2_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_2_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_2_int;
wire qsfp_3_rx_prbs31_enable_2_int;
wire qsfp_3_cfg_rx_prbs31_enable_2_int;
wire [6:0] qsfp_3_rx_error_count_2_int;
wire qsfp_3_tx_clk_3_int;
wire qsfp_3_tx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_3_int;
wire qsfp_3_tx_prbs31_enable_3_int;
wire qsfp_3_cfg_tx_prbs31_enable_3_int;
wire qsfp_3_rx_clk_3_int;
wire qsfp_3_rx_rst_3_int;
wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_3_int;
wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_3_int;
wire qsfp_3_rx_prbs31_enable_3_int;
wire qsfp_3_cfg_rx_prbs31_enable_3_int;
wire [6:0] qsfp_3_rx_error_count_3_int;
wire qsfp_3_drp_clk = clk_125mhz_int;
@ -1757,8 +1757,8 @@ qsfp_3_phy_quad_inst (
.phy_1_rx_block_lock(qsfp_3_rx_block_lock_0),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp_3_rx_status_0),
.phy_1_tx_prbs31_enable(qsfp_3_tx_prbs31_enable_0_int),
.phy_1_rx_prbs31_enable(qsfp_3_rx_prbs31_enable_0_int),
.phy_1_cfg_tx_prbs31_enable(qsfp_3_cfg_tx_prbs31_enable_0_int),
.phy_1_cfg_rx_prbs31_enable(qsfp_3_cfg_rx_prbs31_enable_0_int),
.phy_2_tx_clk(qsfp_3_tx_clk_1_int),
.phy_2_tx_rst(qsfp_3_tx_rst_1_int),
@ -1775,8 +1775,8 @@ qsfp_3_phy_quad_inst (
.phy_2_rx_block_lock(qsfp_3_rx_block_lock_1),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp_3_rx_status_1),
.phy_2_tx_prbs31_enable(qsfp_3_tx_prbs31_enable_1_int),
.phy_2_rx_prbs31_enable(qsfp_3_rx_prbs31_enable_1_int),
.phy_2_cfg_tx_prbs31_enable(qsfp_3_cfg_tx_prbs31_enable_1_int),
.phy_2_cfg_rx_prbs31_enable(qsfp_3_cfg_rx_prbs31_enable_1_int),
.phy_3_tx_clk(qsfp_3_tx_clk_2_int),
.phy_3_tx_rst(qsfp_3_tx_rst_2_int),
@ -1793,8 +1793,8 @@ qsfp_3_phy_quad_inst (
.phy_3_rx_block_lock(qsfp_3_rx_block_lock_2),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp_3_rx_status_2),
.phy_3_tx_prbs31_enable(qsfp_3_tx_prbs31_enable_2_int),
.phy_3_rx_prbs31_enable(qsfp_3_rx_prbs31_enable_2_int),
.phy_3_cfg_tx_prbs31_enable(qsfp_3_cfg_tx_prbs31_enable_2_int),
.phy_3_cfg_rx_prbs31_enable(qsfp_3_cfg_rx_prbs31_enable_2_int),
.phy_4_tx_clk(qsfp_3_tx_clk_3_int),
.phy_4_tx_rst(qsfp_3_tx_rst_3_int),
@ -1811,8 +1811,8 @@ qsfp_3_phy_quad_inst (
.phy_4_rx_block_lock(qsfp_3_rx_block_lock_3),
.phy_4_rx_high_ber(),
.phy_4_rx_status(qsfp_3_rx_status_3),
.phy_4_tx_prbs31_enable(qsfp_3_tx_prbs31_enable_3_int),
.phy_4_rx_prbs31_enable(qsfp_3_rx_prbs31_enable_3_int)
.phy_4_cfg_tx_prbs31_enable(qsfp_3_cfg_tx_prbs31_enable_3_int),
.phy_4_cfg_rx_prbs31_enable(qsfp_3_cfg_rx_prbs31_enable_3_int)
);
wire ptp_clk;
@ -2593,12 +2593,12 @@ core_inst (
.qsfp_0_tx_rst_0(qsfp_0_tx_rst_0_int),
.qsfp_0_txd_0(qsfp_0_txd_0_int),
.qsfp_0_txc_0(qsfp_0_txc_0_int),
.qsfp_0_tx_prbs31_enable_0(qsfp_0_tx_prbs31_enable_0_int),
.qsfp_0_cfg_tx_prbs31_enable_0(qsfp_0_cfg_tx_prbs31_enable_0_int),
.qsfp_0_rx_clk_0(qsfp_0_rx_clk_0_int),
.qsfp_0_rx_rst_0(qsfp_0_rx_rst_0_int),
.qsfp_0_rxd_0(qsfp_0_rxd_0_int),
.qsfp_0_rxc_0(qsfp_0_rxc_0_int),
.qsfp_0_rx_prbs31_enable_0(qsfp_0_rx_prbs31_enable_0_int),
.qsfp_0_cfg_rx_prbs31_enable_0(qsfp_0_cfg_rx_prbs31_enable_0_int),
.qsfp_0_rx_error_count_0(qsfp_0_rx_error_count_0_int),
.qsfp_0_rx_status_0(qsfp_0_rx_status_0),
@ -2606,12 +2606,12 @@ core_inst (
.qsfp_0_tx_rst_1(qsfp_0_tx_rst_1_int),
.qsfp_0_txd_1(qsfp_0_txd_1_int),
.qsfp_0_txc_1(qsfp_0_txc_1_int),
.qsfp_0_tx_prbs31_enable_1(qsfp_0_tx_prbs31_enable_1_int),
.qsfp_0_cfg_tx_prbs31_enable_1(qsfp_0_cfg_tx_prbs31_enable_1_int),
.qsfp_0_rx_clk_1(qsfp_0_rx_clk_1_int),
.qsfp_0_rx_rst_1(qsfp_0_rx_rst_1_int),
.qsfp_0_rxd_1(qsfp_0_rxd_1_int),
.qsfp_0_rxc_1(qsfp_0_rxc_1_int),
.qsfp_0_rx_prbs31_enable_1(qsfp_0_rx_prbs31_enable_1_int),
.qsfp_0_cfg_rx_prbs31_enable_1(qsfp_0_cfg_rx_prbs31_enable_1_int),
.qsfp_0_rx_error_count_1(qsfp_0_rx_error_count_1_int),
.qsfp_0_rx_status_1(qsfp_0_rx_status_1),
@ -2619,12 +2619,12 @@ core_inst (
.qsfp_0_tx_rst_2(qsfp_0_tx_rst_2_int),
.qsfp_0_txd_2(qsfp_0_txd_2_int),
.qsfp_0_txc_2(qsfp_0_txc_2_int),
.qsfp_0_tx_prbs31_enable_2(qsfp_0_tx_prbs31_enable_2_int),
.qsfp_0_cfg_tx_prbs31_enable_2(qsfp_0_cfg_tx_prbs31_enable_2_int),
.qsfp_0_rx_clk_2(qsfp_0_rx_clk_2_int),
.qsfp_0_rx_rst_2(qsfp_0_rx_rst_2_int),
.qsfp_0_rxd_2(qsfp_0_rxd_2_int),
.qsfp_0_rxc_2(qsfp_0_rxc_2_int),
.qsfp_0_rx_prbs31_enable_2(qsfp_0_rx_prbs31_enable_2_int),
.qsfp_0_cfg_rx_prbs31_enable_2(qsfp_0_cfg_rx_prbs31_enable_2_int),
.qsfp_0_rx_error_count_2(qsfp_0_rx_error_count_2_int),
.qsfp_0_rx_status_2(qsfp_0_rx_status_2),
@ -2632,12 +2632,12 @@ core_inst (
.qsfp_0_tx_rst_3(qsfp_0_tx_rst_3_int),
.qsfp_0_txd_3(qsfp_0_txd_3_int),
.qsfp_0_txc_3(qsfp_0_txc_3_int),
.qsfp_0_tx_prbs31_enable_3(qsfp_0_tx_prbs31_enable_3_int),
.qsfp_0_cfg_tx_prbs31_enable_3(qsfp_0_cfg_tx_prbs31_enable_3_int),
.qsfp_0_rx_clk_3(qsfp_0_rx_clk_3_int),
.qsfp_0_rx_rst_3(qsfp_0_rx_rst_3_int),
.qsfp_0_rxd_3(qsfp_0_rxd_3_int),
.qsfp_0_rxc_3(qsfp_0_rxc_3_int),
.qsfp_0_rx_prbs31_enable_3(qsfp_0_rx_prbs31_enable_3_int),
.qsfp_0_cfg_rx_prbs31_enable_3(qsfp_0_cfg_rx_prbs31_enable_3_int),
.qsfp_0_rx_error_count_3(qsfp_0_rx_error_count_3_int),
.qsfp_0_rx_status_3(qsfp_0_rx_status_3),
@ -2666,12 +2666,12 @@ core_inst (
.qsfp_1_tx_rst_0(qsfp_1_tx_rst_0_int),
.qsfp_1_txd_0(qsfp_1_txd_0_int),
.qsfp_1_txc_0(qsfp_1_txc_0_int),
.qsfp_1_tx_prbs31_enable_0(qsfp_1_tx_prbs31_enable_0_int),
.qsfp_1_cfg_tx_prbs31_enable_0(qsfp_1_cfg_tx_prbs31_enable_0_int),
.qsfp_1_rx_clk_0(qsfp_1_rx_clk_0_int),
.qsfp_1_rx_rst_0(qsfp_1_rx_rst_0_int),
.qsfp_1_rxd_0(qsfp_1_rxd_0_int),
.qsfp_1_rxc_0(qsfp_1_rxc_0_int),
.qsfp_1_rx_prbs31_enable_0(qsfp_1_rx_prbs31_enable_0_int),
.qsfp_1_cfg_rx_prbs31_enable_0(qsfp_1_cfg_rx_prbs31_enable_0_int),
.qsfp_1_rx_error_count_0(qsfp_1_rx_error_count_0_int),
.qsfp_1_rx_status_0(qsfp_1_rx_status_0),
@ -2679,12 +2679,12 @@ core_inst (
.qsfp_1_tx_rst_1(qsfp_1_tx_rst_1_int),
.qsfp_1_txd_1(qsfp_1_txd_1_int),
.qsfp_1_txc_1(qsfp_1_txc_1_int),
.qsfp_1_tx_prbs31_enable_1(qsfp_1_tx_prbs31_enable_1_int),
.qsfp_1_cfg_tx_prbs31_enable_1(qsfp_1_cfg_tx_prbs31_enable_1_int),
.qsfp_1_rx_clk_1(qsfp_1_rx_clk_1_int),
.qsfp_1_rx_rst_1(qsfp_1_rx_rst_1_int),
.qsfp_1_rxd_1(qsfp_1_rxd_1_int),
.qsfp_1_rxc_1(qsfp_1_rxc_1_int),
.qsfp_1_rx_prbs31_enable_1(qsfp_1_rx_prbs31_enable_1_int),
.qsfp_1_cfg_rx_prbs31_enable_1(qsfp_1_cfg_rx_prbs31_enable_1_int),
.qsfp_1_rx_error_count_1(qsfp_1_rx_error_count_1_int),
.qsfp_1_rx_status_1(qsfp_1_rx_status_1),
@ -2692,12 +2692,12 @@ core_inst (
.qsfp_1_tx_rst_2(qsfp_1_tx_rst_2_int),
.qsfp_1_txd_2(qsfp_1_txd_2_int),
.qsfp_1_txc_2(qsfp_1_txc_2_int),
.qsfp_1_tx_prbs31_enable_2(qsfp_1_tx_prbs31_enable_2_int),
.qsfp_1_cfg_tx_prbs31_enable_2(qsfp_1_cfg_tx_prbs31_enable_2_int),
.qsfp_1_rx_clk_2(qsfp_1_rx_clk_2_int),
.qsfp_1_rx_rst_2(qsfp_1_rx_rst_2_int),
.qsfp_1_rxd_2(qsfp_1_rxd_2_int),
.qsfp_1_rxc_2(qsfp_1_rxc_2_int),
.qsfp_1_rx_prbs31_enable_2(qsfp_1_rx_prbs31_enable_2_int),
.qsfp_1_cfg_rx_prbs31_enable_2(qsfp_1_cfg_rx_prbs31_enable_2_int),
.qsfp_1_rx_error_count_2(qsfp_1_rx_error_count_2_int),
.qsfp_1_rx_status_2(qsfp_1_rx_status_2),
@ -2705,12 +2705,12 @@ core_inst (
.qsfp_1_tx_rst_3(qsfp_1_tx_rst_3_int),
.qsfp_1_txd_3(qsfp_1_txd_3_int),
.qsfp_1_txc_3(qsfp_1_txc_3_int),
.qsfp_1_tx_prbs31_enable_3(qsfp_1_tx_prbs31_enable_3_int),
.qsfp_1_cfg_tx_prbs31_enable_3(qsfp_1_cfg_tx_prbs31_enable_3_int),
.qsfp_1_rx_clk_3(qsfp_1_rx_clk_3_int),
.qsfp_1_rx_rst_3(qsfp_1_rx_rst_3_int),
.qsfp_1_rxd_3(qsfp_1_rxd_3_int),
.qsfp_1_rxc_3(qsfp_1_rxc_3_int),
.qsfp_1_rx_prbs31_enable_3(qsfp_1_rx_prbs31_enable_3_int),
.qsfp_1_cfg_rx_prbs31_enable_3(qsfp_1_cfg_rx_prbs31_enable_3_int),
.qsfp_1_rx_error_count_3(qsfp_1_rx_error_count_3_int),
.qsfp_1_rx_status_3(qsfp_1_rx_status_3),
@ -2739,12 +2739,12 @@ core_inst (
.qsfp_2_tx_rst_0(qsfp_2_tx_rst_0_int),
.qsfp_2_txd_0(qsfp_2_txd_0_int),
.qsfp_2_txc_0(qsfp_2_txc_0_int),
.qsfp_2_tx_prbs31_enable_0(qsfp_2_tx_prbs31_enable_0_int),
.qsfp_2_cfg_tx_prbs31_enable_0(qsfp_2_cfg_tx_prbs31_enable_0_int),
.qsfp_2_rx_clk_0(qsfp_2_rx_clk_0_int),
.qsfp_2_rx_rst_0(qsfp_2_rx_rst_0_int),
.qsfp_2_rxd_0(qsfp_2_rxd_0_int),
.qsfp_2_rxc_0(qsfp_2_rxc_0_int),
.qsfp_2_rx_prbs31_enable_0(qsfp_2_rx_prbs31_enable_0_int),
.qsfp_2_cfg_rx_prbs31_enable_0(qsfp_2_cfg_rx_prbs31_enable_0_int),
.qsfp_2_rx_error_count_0(qsfp_2_rx_error_count_0_int),
.qsfp_2_rx_status_0(qsfp_2_rx_status_0),
@ -2752,12 +2752,12 @@ core_inst (
.qsfp_2_tx_rst_1(qsfp_2_tx_rst_1_int),
.qsfp_2_txd_1(qsfp_2_txd_1_int),
.qsfp_2_txc_1(qsfp_2_txc_1_int),
.qsfp_2_tx_prbs31_enable_1(qsfp_2_tx_prbs31_enable_1_int),
.qsfp_2_cfg_tx_prbs31_enable_1(qsfp_2_cfg_tx_prbs31_enable_1_int),
.qsfp_2_rx_clk_1(qsfp_2_rx_clk_1_int),
.qsfp_2_rx_rst_1(qsfp_2_rx_rst_1_int),
.qsfp_2_rxd_1(qsfp_2_rxd_1_int),
.qsfp_2_rxc_1(qsfp_2_rxc_1_int),
.qsfp_2_rx_prbs31_enable_1(qsfp_2_rx_prbs31_enable_1_int),
.qsfp_2_cfg_rx_prbs31_enable_1(qsfp_2_cfg_rx_prbs31_enable_1_int),
.qsfp_2_rx_error_count_1(qsfp_2_rx_error_count_1_int),
.qsfp_2_rx_status_1(qsfp_2_rx_status_1),
@ -2765,12 +2765,12 @@ core_inst (
.qsfp_2_tx_rst_2(qsfp_2_tx_rst_2_int),
.qsfp_2_txd_2(qsfp_2_txd_2_int),
.qsfp_2_txc_2(qsfp_2_txc_2_int),
.qsfp_2_tx_prbs31_enable_2(qsfp_2_tx_prbs31_enable_2_int),
.qsfp_2_cfg_tx_prbs31_enable_2(qsfp_2_cfg_tx_prbs31_enable_2_int),
.qsfp_2_rx_clk_2(qsfp_2_rx_clk_2_int),
.qsfp_2_rx_rst_2(qsfp_2_rx_rst_2_int),
.qsfp_2_rxd_2(qsfp_2_rxd_2_int),
.qsfp_2_rxc_2(qsfp_2_rxc_2_int),
.qsfp_2_rx_prbs31_enable_2(qsfp_2_rx_prbs31_enable_2_int),
.qsfp_2_cfg_rx_prbs31_enable_2(qsfp_2_cfg_rx_prbs31_enable_2_int),
.qsfp_2_rx_error_count_2(qsfp_2_rx_error_count_2_int),
.qsfp_2_rx_status_2(qsfp_2_rx_status_2),
@ -2778,12 +2778,12 @@ core_inst (
.qsfp_2_tx_rst_3(qsfp_2_tx_rst_3_int),
.qsfp_2_txd_3(qsfp_2_txd_3_int),
.qsfp_2_txc_3(qsfp_2_txc_3_int),
.qsfp_2_tx_prbs31_enable_3(qsfp_2_tx_prbs31_enable_3_int),
.qsfp_2_cfg_tx_prbs31_enable_3(qsfp_2_cfg_tx_prbs31_enable_3_int),
.qsfp_2_rx_clk_3(qsfp_2_rx_clk_3_int),
.qsfp_2_rx_rst_3(qsfp_2_rx_rst_3_int),
.qsfp_2_rxd_3(qsfp_2_rxd_3_int),
.qsfp_2_rxc_3(qsfp_2_rxc_3_int),
.qsfp_2_rx_prbs31_enable_3(qsfp_2_rx_prbs31_enable_3_int),
.qsfp_2_cfg_rx_prbs31_enable_3(qsfp_2_cfg_rx_prbs31_enable_3_int),
.qsfp_2_rx_error_count_3(qsfp_2_rx_error_count_3_int),
.qsfp_2_rx_status_3(qsfp_2_rx_status_3),
@ -2812,12 +2812,12 @@ core_inst (
.qsfp_3_tx_rst_0(qsfp_3_tx_rst_0_int),
.qsfp_3_txd_0(qsfp_3_txd_0_int),
.qsfp_3_txc_0(qsfp_3_txc_0_int),
.qsfp_3_tx_prbs31_enable_0(qsfp_3_tx_prbs31_enable_0_int),
.qsfp_3_cfg_tx_prbs31_enable_0(qsfp_3_cfg_tx_prbs31_enable_0_int),
.qsfp_3_rx_clk_0(qsfp_3_rx_clk_0_int),
.qsfp_3_rx_rst_0(qsfp_3_rx_rst_0_int),
.qsfp_3_rxd_0(qsfp_3_rxd_0_int),
.qsfp_3_rxc_0(qsfp_3_rxc_0_int),
.qsfp_3_rx_prbs31_enable_0(qsfp_3_rx_prbs31_enable_0_int),
.qsfp_3_cfg_rx_prbs31_enable_0(qsfp_3_cfg_rx_prbs31_enable_0_int),
.qsfp_3_rx_error_count_0(qsfp_3_rx_error_count_0_int),
.qsfp_3_rx_status_0(qsfp_3_rx_status_0),
@ -2825,12 +2825,12 @@ core_inst (
.qsfp_3_tx_rst_1(qsfp_3_tx_rst_1_int),
.qsfp_3_txd_1(qsfp_3_txd_1_int),
.qsfp_3_txc_1(qsfp_3_txc_1_int),
.qsfp_3_tx_prbs31_enable_1(qsfp_3_tx_prbs31_enable_1_int),
.qsfp_3_cfg_tx_prbs31_enable_1(qsfp_3_cfg_tx_prbs31_enable_1_int),
.qsfp_3_rx_clk_1(qsfp_3_rx_clk_1_int),
.qsfp_3_rx_rst_1(qsfp_3_rx_rst_1_int),
.qsfp_3_rxd_1(qsfp_3_rxd_1_int),
.qsfp_3_rxc_1(qsfp_3_rxc_1_int),
.qsfp_3_rx_prbs31_enable_1(qsfp_3_rx_prbs31_enable_1_int),
.qsfp_3_cfg_rx_prbs31_enable_1(qsfp_3_cfg_rx_prbs31_enable_1_int),
.qsfp_3_rx_error_count_1(qsfp_3_rx_error_count_1_int),
.qsfp_3_rx_status_1(qsfp_3_rx_status_1),
@ -2838,12 +2838,12 @@ core_inst (
.qsfp_3_tx_rst_2(qsfp_3_tx_rst_2_int),
.qsfp_3_txd_2(qsfp_3_txd_2_int),
.qsfp_3_txc_2(qsfp_3_txc_2_int),
.qsfp_3_tx_prbs31_enable_2(qsfp_3_tx_prbs31_enable_2_int),
.qsfp_3_cfg_tx_prbs31_enable_2(qsfp_3_cfg_tx_prbs31_enable_2_int),
.qsfp_3_rx_clk_2(qsfp_3_rx_clk_2_int),
.qsfp_3_rx_rst_2(qsfp_3_rx_rst_2_int),
.qsfp_3_rxd_2(qsfp_3_rxd_2_int),
.qsfp_3_rxc_2(qsfp_3_rxc_2_int),
.qsfp_3_rx_prbs31_enable_2(qsfp_3_rx_prbs31_enable_2_int),
.qsfp_3_cfg_rx_prbs31_enable_2(qsfp_3_cfg_rx_prbs31_enable_2_int),
.qsfp_3_rx_error_count_2(qsfp_3_rx_error_count_2_int),
.qsfp_3_rx_status_2(qsfp_3_rx_status_2),
@ -2851,12 +2851,12 @@ core_inst (
.qsfp_3_tx_rst_3(qsfp_3_tx_rst_3_int),
.qsfp_3_txd_3(qsfp_3_txd_3_int),
.qsfp_3_txc_3(qsfp_3_txc_3_int),
.qsfp_3_tx_prbs31_enable_3(qsfp_3_tx_prbs31_enable_3_int),
.qsfp_3_cfg_tx_prbs31_enable_3(qsfp_3_cfg_tx_prbs31_enable_3_int),
.qsfp_3_rx_clk_3(qsfp_3_rx_clk_3_int),
.qsfp_3_rx_rst_3(qsfp_3_rx_rst_3_int),
.qsfp_3_rxd_3(qsfp_3_rxd_3_int),
.qsfp_3_rxc_3(qsfp_3_rxc_3_int),
.qsfp_3_rx_prbs31_enable_3(qsfp_3_rx_prbs31_enable_3_int),
.qsfp_3_cfg_rx_prbs31_enable_3(qsfp_3_cfg_rx_prbs31_enable_3_int),
.qsfp_3_rx_error_count_3(qsfp_3_rx_error_count_3_int),
.qsfp_3_rx_status_3(qsfp_3_rx_status_3),

136
fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v
View File

@ -284,12 +284,12 @@ module fpga_core #
input wire qsfp_0_tx_rst_0,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_0,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_0,
output wire qsfp_0_tx_prbs31_enable_0,
output wire qsfp_0_cfg_tx_prbs31_enable_0,
input wire qsfp_0_rx_clk_0,
input wire qsfp_0_rx_rst_0,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_0,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_0,
output wire qsfp_0_rx_prbs31_enable_0,
output wire qsfp_0_cfg_rx_prbs31_enable_0,
input wire [6:0] qsfp_0_rx_error_count_0,
input wire qsfp_0_rx_status_0,
@ -297,12 +297,12 @@ module fpga_core #
input wire qsfp_0_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_1,
output wire qsfp_0_tx_prbs31_enable_1,
output wire qsfp_0_cfg_tx_prbs31_enable_1,
input wire qsfp_0_rx_clk_1,
input wire qsfp_0_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_1,
output wire qsfp_0_rx_prbs31_enable_1,
output wire qsfp_0_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp_0_rx_error_count_1,
input wire qsfp_0_rx_status_1,
@ -310,12 +310,12 @@ module fpga_core #
input wire qsfp_0_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_2,
output wire qsfp_0_tx_prbs31_enable_2,
output wire qsfp_0_cfg_tx_prbs31_enable_2,
input wire qsfp_0_rx_clk_2,
input wire qsfp_0_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_2,
output wire qsfp_0_rx_prbs31_enable_2,
output wire qsfp_0_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp_0_rx_error_count_2,
input wire qsfp_0_rx_status_2,
@ -323,12 +323,12 @@ module fpga_core #
input wire qsfp_0_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_0_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_txc_3,
output wire qsfp_0_tx_prbs31_enable_3,
output wire qsfp_0_cfg_tx_prbs31_enable_3,
input wire qsfp_0_rx_clk_3,
input wire qsfp_0_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_0_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_0_rxc_3,
output wire qsfp_0_rx_prbs31_enable_3,
output wire qsfp_0_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp_0_rx_error_count_3,
input wire qsfp_0_rx_status_3,
@ -357,12 +357,12 @@ module fpga_core #
input wire qsfp_1_tx_rst_0,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_0,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_0,
output wire qsfp_1_tx_prbs31_enable_0,
output wire qsfp_1_cfg_tx_prbs31_enable_0,
input wire qsfp_1_rx_clk_0,
input wire qsfp_1_rx_rst_0,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_0,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_0,
output wire qsfp_1_rx_prbs31_enable_0,
output wire qsfp_1_cfg_rx_prbs31_enable_0,
input wire [6:0] qsfp_1_rx_error_count_0,
input wire qsfp_1_rx_status_0,
@ -370,12 +370,12 @@ module fpga_core #
input wire qsfp_1_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_1,
output wire qsfp_1_tx_prbs31_enable_1,
output wire qsfp_1_cfg_tx_prbs31_enable_1,
input wire qsfp_1_rx_clk_1,
input wire qsfp_1_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_1,
output wire qsfp_1_rx_prbs31_enable_1,
output wire qsfp_1_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp_1_rx_error_count_1,
input wire qsfp_1_rx_status_1,
@ -383,12 +383,12 @@ module fpga_core #
input wire qsfp_1_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_2,
output wire qsfp_1_tx_prbs31_enable_2,
output wire qsfp_1_cfg_tx_prbs31_enable_2,
input wire qsfp_1_rx_clk_2,
input wire qsfp_1_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_2,
output wire qsfp_1_rx_prbs31_enable_2,
output wire qsfp_1_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp_1_rx_error_count_2,
input wire qsfp_1_rx_status_2,
@ -396,12 +396,12 @@ module fpga_core #
input wire qsfp_1_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_1_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_txc_3,
output wire qsfp_1_tx_prbs31_enable_3,
output wire qsfp_1_cfg_tx_prbs31_enable_3,
input wire qsfp_1_rx_clk_3,
input wire qsfp_1_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_1_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_1_rxc_3,
output wire qsfp_1_rx_prbs31_enable_3,
output wire qsfp_1_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp_1_rx_error_count_3,
input wire qsfp_1_rx_status_3,
@ -430,12 +430,12 @@ module fpga_core #
input wire qsfp_2_tx_rst_0,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_0,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_0,
output wire qsfp_2_tx_prbs31_enable_0,
output wire qsfp_2_cfg_tx_prbs31_enable_0,
input wire qsfp_2_rx_clk_0,
input wire qsfp_2_rx_rst_0,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_0,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_0,
output wire qsfp_2_rx_prbs31_enable_0,
output wire qsfp_2_cfg_rx_prbs31_enable_0,
input wire [6:0] qsfp_2_rx_error_count_0,
input wire qsfp_2_rx_status_0,
@ -443,12 +443,12 @@ module fpga_core #
input wire qsfp_2_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_1,
output wire qsfp_2_tx_prbs31_enable_1,
output wire qsfp_2_cfg_tx_prbs31_enable_1,
input wire qsfp_2_rx_clk_1,
input wire qsfp_2_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_1,
output wire qsfp_2_rx_prbs31_enable_1,
output wire qsfp_2_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp_2_rx_error_count_1,
input wire qsfp_2_rx_status_1,
@ -456,12 +456,12 @@ module fpga_core #
input wire qsfp_2_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_2,
output wire qsfp_2_tx_prbs31_enable_2,
output wire qsfp_2_cfg_tx_prbs31_enable_2,
input wire qsfp_2_rx_clk_2,
input wire qsfp_2_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_2,
output wire qsfp_2_rx_prbs31_enable_2,
output wire qsfp_2_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp_2_rx_error_count_2,
input wire qsfp_2_rx_status_2,
@ -469,12 +469,12 @@ module fpga_core #
input wire qsfp_2_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_2_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_txc_3,
output wire qsfp_2_tx_prbs31_enable_3,
output wire qsfp_2_cfg_tx_prbs31_enable_3,
input wire qsfp_2_rx_clk_3,
input wire qsfp_2_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_2_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_2_rxc_3,
output wire qsfp_2_rx_prbs31_enable_3,
output wire qsfp_2_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp_2_rx_error_count_3,
input wire qsfp_2_rx_status_3,
@ -503,12 +503,12 @@ module fpga_core #
input wire qsfp_3_tx_rst_0,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_0,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_0,
output wire qsfp_3_tx_prbs31_enable_0,
output wire qsfp_3_cfg_tx_prbs31_enable_0,
input wire qsfp_3_rx_clk_0,
input wire qsfp_3_rx_rst_0,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_0,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_0,
output wire qsfp_3_rx_prbs31_enable_0,
output wire qsfp_3_cfg_rx_prbs31_enable_0,
input wire [6:0] qsfp_3_rx_error_count_0,
input wire qsfp_3_rx_status_0,
@ -516,12 +516,12 @@ module fpga_core #
input wire qsfp_3_tx_rst_1,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_1,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_1,
output wire qsfp_3_tx_prbs31_enable_1,
output wire qsfp_3_cfg_tx_prbs31_enable_1,
input wire qsfp_3_rx_clk_1,
input wire qsfp_3_rx_rst_1,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_1,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_1,
output wire qsfp_3_rx_prbs31_enable_1,
output wire qsfp_3_cfg_rx_prbs31_enable_1,
input wire [6:0] qsfp_3_rx_error_count_1,
input wire qsfp_3_rx_status_1,
@ -529,12 +529,12 @@ module fpga_core #
input wire qsfp_3_tx_rst_2,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_2,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_2,
output wire qsfp_3_tx_prbs31_enable_2,
output wire qsfp_3_cfg_tx_prbs31_enable_2,
input wire qsfp_3_rx_clk_2,
input wire qsfp_3_rx_rst_2,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_2,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_2,
output wire qsfp_3_rx_prbs31_enable_2,
output wire qsfp_3_cfg_rx_prbs31_enable_2,
input wire [6:0] qsfp_3_rx_error_count_2,
input wire qsfp_3_rx_status_2,
@ -542,12 +542,12 @@ module fpga_core #
input wire qsfp_3_tx_rst_3,
output wire [XGMII_DATA_WIDTH-1:0] qsfp_3_txd_3,
output wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_txc_3,
output wire qsfp_3_tx_prbs31_enable_3,
output wire qsfp_3_cfg_tx_prbs31_enable_3,
input wire qsfp_3_rx_clk_3,
input wire qsfp_3_rx_rst_3,
input wire [XGMII_DATA_WIDTH-1:0] qsfp_3_rxd_3,
input wire [XGMII_CTRL_WIDTH-1:0] qsfp_3_rxc_3,
output wire qsfp_3_rx_prbs31_enable_3,
output wire qsfp_3_cfg_rx_prbs31_enable_3,
input wire [6:0] qsfp_3_rx_error_count_3,
input wire qsfp_3_rx_status_3,
@ -1213,8 +1213,8 @@ if (TDMA_BER_ENABLE) begin
.phy_tx_clk({qsfp_3_tx_clk_3, qsfp_3_tx_clk_2, qsfp_3_tx_clk_1, qsfp_3_tx_clk_0, qsfp_2_tx_clk_3, qsfp_2_tx_clk_2, qsfp_2_tx_clk_1, qsfp_2_tx_clk_0, qsfp_1_tx_clk_3, qsfp_1_tx_clk_2, qsfp_1_tx_clk_1, qsfp_1_tx_clk_0, qsfp_0_tx_clk_3, qsfp_0_tx_clk_2, qsfp_0_tx_clk_1, qsfp_0_tx_clk_0}),
.phy_rx_clk({qsfp_3_rx_clk_3, qsfp_3_rx_clk_2, qsfp_3_rx_clk_1, qsfp_3_rx_clk_0, qsfp_2_rx_clk_3, qsfp_2_rx_clk_2, qsfp_2_rx_clk_1, qsfp_2_rx_clk_0, qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}),
.phy_rx_error_count({qsfp_3_rx_error_count_3, qsfp_3_rx_error_count_2, qsfp_3_rx_error_count_1, qsfp_3_rx_error_count_0, qsfp_2_rx_error_count_3, qsfp_2_rx_error_count_2, qsfp_2_rx_error_count_1, qsfp_2_rx_error_count_0, qsfp_1_rx_error_count_3, qsfp_1_rx_error_count_2, qsfp_1_rx_error_count_1, qsfp_1_rx_error_count_0, qsfp_0_rx_error_count_3, qsfp_0_rx_error_count_2, qsfp_0_rx_error_count_1, qsfp_0_rx_error_count_0}),
.phy_tx_prbs31_enable({qsfp_3_tx_prbs31_enable_3, qsfp_3_tx_prbs31_enable_2, qsfp_3_tx_prbs31_enable_1, qsfp_3_tx_prbs31_enable_0, qsfp_2_tx_prbs31_enable_3, qsfp_2_tx_prbs31_enable_2, qsfp_2_tx_prbs31_enable_1, qsfp_2_tx_prbs31_enable_0, qsfp_1_tx_prbs31_enable_3, qsfp_1_tx_prbs31_enable_2, qsfp_1_tx_prbs31_enable_1, qsfp_1_tx_prbs31_enable_0, qsfp_0_tx_prbs31_enable_3, qsfp_0_tx_prbs31_enable_2, qsfp_0_tx_prbs31_enable_1, qsfp_0_tx_prbs31_enable_0}),
.phy_rx_prbs31_enable({qsfp_3_rx_prbs31_enable_3, qsfp_3_rx_prbs31_enable_2, qsfp_3_rx_prbs31_enable_1, qsfp_3_rx_prbs31_enable_0, qsfp_2_rx_prbs31_enable_3, qsfp_2_rx_prbs31_enable_2, qsfp_2_rx_prbs31_enable_1, qsfp_2_rx_prbs31_enable_0, qsfp_1_rx_prbs31_enable_3, qsfp_1_rx_prbs31_enable_2, qsfp_1_rx_prbs31_enable_1, qsfp_1_rx_prbs31_enable_0, qsfp_0_rx_prbs31_enable_3, qsfp_0_rx_prbs31_enable_2, qsfp_0_rx_prbs31_enable_1, qsfp_0_rx_prbs31_enable_0}),
.phy_cfg_tx_prbs31_enable({qsfp_3_cfg_tx_prbs31_enable_3, qsfp_3_cfg_tx_prbs31_enable_2, qsfp_3_cfg_tx_prbs31_enable_1, qsfp_3_cfg_tx_prbs31_enable_0, qsfp_2_cfg_tx_prbs31_enable_3, qsfp_2_cfg_tx_prbs31_enable_2, qsfp_2_cfg_tx_prbs31_enable_1, qsfp_2_cfg_tx_prbs31_enable_0, qsfp_1_cfg_tx_prbs31_enable_3, qsfp_1_cfg_tx_prbs31_enable_2, qsfp_1_cfg_tx_prbs31_enable_1, qsfp_1_cfg_tx_prbs31_enable_0, qsfp_0_cfg_tx_prbs31_enable_3, qsfp_0_cfg_tx_prbs31_enable_2, qsfp_0_cfg_tx_prbs31_enable_1, qsfp_0_cfg_tx_prbs31_enable_0}),
.phy_cfg_rx_prbs31_enable({qsfp_3_cfg_rx_prbs31_enable_3, qsfp_3_cfg_rx_prbs31_enable_2, qsfp_3_cfg_rx_prbs31_enable_1, qsfp_3_cfg_rx_prbs31_enable_0, qsfp_2_cfg_rx_prbs31_enable_3, qsfp_2_cfg_rx_prbs31_enable_2, qsfp_2_cfg_rx_prbs31_enable_1, qsfp_2_cfg_rx_prbs31_enable_0, qsfp_1_cfg_rx_prbs31_enable_3, qsfp_1_cfg_rx_prbs31_enable_2, qsfp_1_cfg_rx_prbs31_enable_1, qsfp_1_cfg_rx_prbs31_enable_0, qsfp_0_cfg_rx_prbs31_enable_3, qsfp_0_cfg_rx_prbs31_enable_2, qsfp_0_cfg_rx_prbs31_enable_1, qsfp_0_cfg_rx_prbs31_enable_0}),
.s_axil_awaddr(axil_csr_awaddr),
.s_axil_awprot(axil_csr_awprot),
.s_axil_awvalid(axil_csr_awvalid),
@ -1240,38 +1240,38 @@ if (TDMA_BER_ENABLE) begin
end else begin
assign qsfp_0_tx_prbs31_enable_0 = 1'b0;
assign qsfp_0_rx_prbs31_enable_0 = 1'b0;
assign qsfp_0_tx_prbs31_enable_1 = 1'b0;
assign qsfp_0_rx_prbs31_enable_1 = 1'b0;
assign qsfp_0_tx_prbs31_enable_2 = 1'b0;
assign qsfp_0_rx_prbs31_enable_2 = 1'b0;
assign qsfp_0_tx_prbs31_enable_3 = 1'b0;
assign qsfp_0_rx_prbs31_enable_3 = 1'b0;
assign qsfp_1_tx_prbs31_enable_0 = 1'b0;
assign qsfp_1_rx_prbs31_enable_0 = 1'b0;
assign qsfp_1_tx_prbs31_enable_1 = 1'b0;
assign qsfp_1_rx_prbs31_enable_1 = 1'b0;
assign qsfp_1_tx_prbs31_enable_2 = 1'b0;
assign qsfp_1_rx_prbs31_enable_2 = 1'b0;
assign qsfp_1_tx_prbs31_enable_3 = 1'b0;
assign qsfp_1_rx_prbs31_enable_3 = 1'b0;
assign qsfp_2_tx_prbs31_enable_0 = 1'b0;
assign qsfp_2_rx_prbs31_enable_0 = 1'b0;
assign qsfp_2_tx_prbs31_enable_1 = 1'b0;
assign qsfp_2_rx_prbs31_enable_1 = 1'b0;
assign qsfp_2_tx_prbs31_enable_2 = 1'b0;
assign qsfp_2_rx_prbs31_enable_2 = 1'b0;
assign qsfp_2_tx_prbs31_enable_3 = 1'b0;
assign qsfp_2_rx_prbs31_enable_3 = 1'b0;
assign qsfp_3_tx_prbs31_enable_0 = 1'b0;
assign qsfp_3_rx_prbs31_enable_0 = 1'b0;
assign qsfp_3_tx_prbs31_enable_1 = 1'b0;
assign qsfp_3_rx_prbs31_enable_1 = 1'b0;
assign qsfp_3_tx_prbs31_enable_2 = 1'b0;
assign qsfp_3_rx_prbs31_enable_2 = 1'b0;
assign qsfp_3_tx_prbs31_enable_3 = 1'b0;
assign qsfp_3_rx_prbs31_enable_3 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_0 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_0 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp_0_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp_0_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_0 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_0 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp_1_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp_1_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp_2_cfg_tx_prbs31_enable_0 = 1'b0;
assign qsfp_2_cfg_rx_prbs31_enable_0 = 1'b0;
assign qsfp_2_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp_2_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp_2_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp_2_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp_2_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp_2_cfg_rx_prbs31_enable_3 = 1'b0;
assign qsfp_3_cfg_tx_prbs31_enable_0 = 1'b0;
assign qsfp_3_cfg_rx_prbs31_enable_0 = 1'b0;
assign qsfp_3_cfg_tx_prbs31_enable_1 = 1'b0;
assign qsfp_3_cfg_rx_prbs31_enable_1 = 1'b0;
assign qsfp_3_cfg_tx_prbs31_enable_2 = 1'b0;
assign qsfp_3_cfg_rx_prbs31_enable_2 = 1'b0;
assign qsfp_3_cfg_tx_prbs31_enable_3 = 1'b0;
assign qsfp_3_cfg_rx_prbs31_enable_3 = 1'b0;
end
@ -1431,7 +1431,9 @@ generate
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.ifg_delay(8'd12)
.cfg_ifg(8'd12),
.cfg_tx_enable(1'b1),
.cfg_rx_enable(1'b1)
);
end