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Use QSFP Si570 for both QSFP modules on VCU118

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-07-19 17:00:33 -07:00
parent 1be196279f
commit 375b12865f
2 changed files with 6 additions and 16 deletions
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6
example/VCU118/fpga_25g/fpga.xdc
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@ -182,8 +182,8 @@ set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHAN
set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13
set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14
#set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13
#set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14
#set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35
#set_property -dict {LOC N8 } [get_ports qsfp2_mgt_refclk_1_n] ;# MGTREFCLK1N_232 from U57.34
#set_property -dict {LOC AP23 IOSTANDARD LVDS} [get_ports qsfp2_recclk_p] ;# to U57.12
@ -195,7 +195,7 @@ set_property -dict {LOC AT21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_i
set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_lpmode]
# 156.25 MHz MGT reference clock
create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p]
#create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p]
set_false_path -to [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}]
set_output_delay 0 [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}]

16
example/VCU118/fpga_25g/rtl/fpga.v
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@ -104,8 +104,8 @@ module fpga (
output wire qsfp2_tx4_n,
input wire qsfp2_rx4_p,
input wire qsfp2_rx4_n,
input wire qsfp2_mgt_refclk_0_p,
input wire qsfp2_mgt_refclk_0_n,
// input wire qsfp2_mgt_refclk_0_p,
// input wire qsfp2_mgt_refclk_0_n,
// input wire qsfp2_mgt_refclk_1_p,
// input wire qsfp2_mgt_refclk_1_n,
// output wire qsfp2_recclk_p,
@ -600,16 +600,6 @@ wire qsfp2_rx_block_lock_2;
wire qsfp2_rx_block_lock_3;
wire qsfp2_rx_block_lock_4;
wire qsfp2_mgt_refclk_0;
IBUFDS_GTE4 ibufds_gte4_qsfp2_mgt_refclk_0_inst (
.I (qsfp2_mgt_refclk_0_p),
.IB (qsfp2_mgt_refclk_0_n),
.CEB (1'b0),
.O (qsfp2_mgt_refclk_0),
.ODIV2 ()
);
wire qsfp2_qpll0lock;
wire qsfp2_qpll0outclk;
wire qsfp2_qpll0outrefclk;
@ -628,7 +618,7 @@ qsfp2_phy_1_inst (
.xcvr_gtpowergood_out(),
// PLL out
.xcvr_gtrefclk00_in(qsfp2_mgt_refclk_0),
.xcvr_gtrefclk00_in(qsfp1_mgt_refclk_0),
.xcvr_qpll0lock_out(qsfp2_qpll0lock),
.xcvr_qpll0outclk_out(qsfp2_qpll0outclk),
.xcvr_qpll0outrefclk_out(qsfp2_qpll0outrefclk),