FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

Fix parameters

Browse Source
This commit is contained in:
Alex Forencich 2014-11-12 02:06:18 -08:00
parent d6784d189d
commit 3816eb3c20
1 changed files with 1 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
rtl/axis_rate_limit.v
View File

@ -31,8 +31,7 @@ THE SOFTWARE.
*/
module axis_rate_limit #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
parameter DATA_WIDTH = 8
)
(
input wire clk,