From 382226ad5966198862fb676c7a5810067c2c6a19 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 8 Oct 2015 23:46:59 -0700 Subject: [PATCH] Don't accept data until reset is complete --- rtl/axis_async_fifo.v | 2 +- rtl/axis_async_fifo_64.v | 2 +- rtl/axis_async_frame_fifo.v | 2 +- rtl/axis_async_frame_fifo_64.v | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/rtl/axis_async_fifo.v b/rtl/axis_async_fifo.v index 6fc52b6e4..4edb91551 100644 --- a/rtl/axis_async_fifo.v +++ b/rtl/axis_async_fifo.v @@ -100,7 +100,7 @@ wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty; assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_out_reg; -assign input_axis_tready = ~full; +assign input_axis_tready = ~full & ~input_rst_sync3; assign output_axis_tvalid = output_axis_tvalid_reg; // reset synchronization diff --git a/rtl/axis_async_fifo_64.v b/rtl/axis_async_fifo_64.v index eaddcdd45..c7eed0e3e 100644 --- a/rtl/axis_async_fifo_64.v +++ b/rtl/axis_async_fifo_64.v @@ -103,7 +103,7 @@ wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty; assign {output_axis_tlast, output_axis_tuser, output_axis_tkeep, output_axis_tdata} = data_out_reg; -assign input_axis_tready = ~full; +assign input_axis_tready = ~full & ~input_rst_sync3; assign output_axis_tvalid = output_axis_tvalid_reg; // reset synchronization diff --git a/rtl/axis_async_frame_fifo.v b/rtl/axis_async_frame_fifo.v index 344cff6d5..3239633d3 100644 --- a/rtl/axis_async_frame_fifo.v +++ b/rtl/axis_async_frame_fifo.v @@ -116,7 +116,7 @@ wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty; assign {output_axis_tlast, output_axis_tdata} = data_out_reg; -assign input_axis_tready = (~full | DROP_WHEN_FULL); +assign input_axis_tready = (~full | DROP_WHEN_FULL) & ~input_rst_sync3; assign output_axis_tvalid = output_axis_tvalid_reg; assign overflow = overflow_reg; diff --git a/rtl/axis_async_frame_fifo_64.v b/rtl/axis_async_frame_fifo_64.v index b82d73db3..f613e5757 100644 --- a/rtl/axis_async_frame_fifo_64.v +++ b/rtl/axis_async_frame_fifo_64.v @@ -119,7 +119,7 @@ wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty; assign {output_axis_tlast, output_axis_tkeep, output_axis_tdata} = data_out_reg; -assign input_axis_tready = (~full | DROP_WHEN_FULL); +assign input_axis_tready = (~full | DROP_WHEN_FULL) & ~input_rst_sync3; assign output_axis_tvalid = output_axis_tvalid_reg; assign overflow = overflow_reg;