diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v index e2ef2afc2..6106ed268 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v @@ -400,6 +400,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -870,6 +874,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -971,6 +986,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1054,12 +1079,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index 65e932f94..fabcfffc9 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -463,6 +463,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -933,6 +937,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1034,6 +1049,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1117,12 +1142,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index d20b53d98..0eb1cbc99 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -463,6 +463,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -934,6 +938,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1035,6 +1050,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1118,12 +1143,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v index 0bee84ecb..9af3ebade 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v @@ -420,6 +420,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -884,6 +888,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -985,6 +1000,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1068,12 +1093,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v index 18464f382..315467182 100644 --- a/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_10g/rtl/fpga_core.v @@ -480,6 +480,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -944,6 +948,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1045,6 +1060,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1128,12 +1153,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v index 0a3b4f59a..fa763952e 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v @@ -420,6 +420,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -884,6 +888,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -985,6 +1000,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1068,12 +1093,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v index b8fb53252..0250ea874 100644 --- a/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_10g/rtl/fpga_core.v @@ -480,6 +480,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -944,6 +948,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1045,6 +1060,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1128,12 +1153,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v index fcb8dfb15..85497385f 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v @@ -392,6 +392,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -795,6 +799,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -896,6 +911,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -979,12 +1004,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v index 942e23a41..d8098b641 100644 --- a/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v @@ -452,6 +452,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -855,6 +859,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -956,6 +971,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1039,12 +1064,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v index 9d0dd7d4b..e6567eeca 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v @@ -374,6 +374,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -777,6 +781,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -878,6 +893,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -961,12 +986,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v index 913f208a8..d00820016 100644 --- a/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_10g/rtl/fpga_core.v @@ -414,6 +414,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -817,6 +821,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -918,6 +933,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1001,12 +1026,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v index ba36a3dc0..57f4cdf56 100644 --- a/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -375,6 +375,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -926,6 +930,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(4'd0), .s_axis_rq_seq_num_valid_1(1'b0), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1027,6 +1042,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1112,12 +1137,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v index 36dbbf9df..3ed92e35a 100644 --- a/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v @@ -377,6 +377,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -928,6 +932,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1029,6 +1044,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1112,12 +1137,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v index a0d15ea20..485e08509 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v @@ -376,6 +376,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -814,6 +818,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(4'd0), .s_axis_rq_seq_num_valid_1(1'b0), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -915,6 +930,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1000,12 +1025,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v index a6d036b7b..01d2c3b98 100644 --- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v @@ -414,6 +414,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -910,6 +914,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(4'd0), .s_axis_rq_seq_num_valid_1(1'b0), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1011,6 +1026,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1096,12 +1121,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v index 7ea908194..461afa7ea 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v @@ -406,6 +406,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -919,6 +923,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1020,6 +1035,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1103,12 +1128,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v index 65358cd25..9a036711a 100644 --- a/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v @@ -466,6 +466,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -979,6 +983,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1080,6 +1095,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1163,12 +1188,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v index e3ac67d4d..7190cc9b3 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v @@ -395,6 +395,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -812,6 +816,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -913,6 +928,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -996,12 +1021,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v index 7df35483f..96d07f87d 100644 --- a/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_10g/rtl/fpga_core.v @@ -455,6 +455,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -872,6 +876,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -973,6 +988,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1056,12 +1081,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v index d72d0d99a..29c18978a 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v @@ -348,6 +348,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -704,6 +708,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -805,6 +820,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -888,12 +913,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v index 9c024ed68..7a2149ea4 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v @@ -407,6 +407,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -967,6 +971,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1068,6 +1083,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1151,12 +1176,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v index 59a3d2df9..c08a0ef0e 100644 --- a/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_10g/rtl/fpga_core.v @@ -470,6 +470,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -1030,6 +1034,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1131,6 +1146,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1214,12 +1239,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v index 450e08ecb..4f9ece67c 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v @@ -470,6 +470,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -1030,6 +1034,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1131,6 +1146,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1214,12 +1239,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v index e3c1dbc41..661cd384a 100644 --- a/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v @@ -463,6 +463,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -933,6 +937,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1034,6 +1049,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1117,12 +1142,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v index a8672fa51..8241625b2 100644 --- a/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v @@ -375,6 +375,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -926,6 +930,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(4'd0), .s_axis_rq_seq_num_valid_1(1'b0), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1027,6 +1042,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1112,12 +1137,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v index 87ff776da..58e03d63f 100644 --- a/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v @@ -414,6 +414,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -910,6 +914,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(4'd0), .s_axis_rq_seq_num_valid_1(1'b0), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1011,6 +1026,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1096,12 +1121,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH), diff --git a/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v b/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v index 88d857238..8e586d5f9 100644 --- a/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v @@ -466,6 +466,10 @@ wire [1:0] status_error_cor_int; wire [31:0] msi_irq; +wire [7:0] pcie_tx_fc_nph_av; +wire [7:0] pcie_tx_fc_ph_av; +wire [11:0] pcie_tx_fc_pd_av; + wire ext_tag_enable; // PCIe DMA control @@ -979,6 +983,17 @@ pcie_if_inst ( .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1), .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1), + /* + * Flow control + */ + .cfg_fc_ph(cfg_fc_ph), + .cfg_fc_pd(cfg_fc_pd), + .cfg_fc_nph(cfg_fc_nph), + .cfg_fc_npd(cfg_fc_npd), + .cfg_fc_cplh(cfg_fc_cplh), + .cfg_fc_cpld(cfg_fc_cpld), + .cfg_fc_sel(cfg_fc_sel), + /* * Configuration interface */ @@ -1080,6 +1095,16 @@ pcie_if_inst ( .tx_cpl_tlp_eop(pcie_tx_cpl_tlp_eop), .tx_cpl_tlp_ready(pcie_tx_cpl_tlp_ready), + /* + * Flow control + */ + .tx_fc_ph_av(pcie_tx_fc_ph_av), + .tx_fc_pd_av(pcie_tx_fc_pd_av), + .tx_fc_nph_av(pcie_tx_fc_nph_av), + .tx_fc_npd_av(), + .tx_fc_cplh_av(), + .tx_fc_cpld_av(), + /* * Configuration outputs */ @@ -1163,12 +1188,6 @@ pcie_axil_master_inst ( .status_error_uncor(status_error_uncor_int[0]) ); -assign cfg_fc_sel = 3'b100; - -wire [7:0] pcie_tx_fc_nph_av = cfg_fc_nph; -wire [7:0] pcie_tx_fc_ph_av = cfg_fc_ph; -wire [11:0] pcie_tx_fc_pd_av = cfg_fc_pd; - dma_if_pcie #( .TLP_SEG_COUNT(TLP_SEG_COUNT), .TLP_SEG_DATA_WIDTH(TLP_SEG_DATA_WIDTH),