From 394dc2d723cf80a148e8e85aaa80360adf5b1fd7 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 5 Apr 2023 01:38:46 -0700 Subject: [PATCH] fpga/common: Add phase bit to queue managers Signed-off-by: Alex Forencich --- fpga/common/rtl/cpl_queue_manager.v | 6 ++++++ fpga/common/rtl/queue_manager.v | 6 ++++++ fpga/common/tb/cpl_queue_manager/test_cpl_queue_manager.py | 4 +++- fpga/common/tb/queue_manager/test_queue_manager.py | 4 +++- 4 files changed, 18 insertions(+), 2 deletions(-) diff --git a/fpga/common/rtl/cpl_queue_manager.v b/fpga/common/rtl/cpl_queue_manager.v index 04ded8d68..ccf3bded1 100644 --- a/fpga/common/rtl/cpl_queue_manager.v +++ b/fpga/common/rtl/cpl_queue_manager.v @@ -86,6 +86,7 @@ module cpl_queue_manager # */ output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_enqueue_resp_queue, output wire [QUEUE_PTR_WIDTH-1:0] m_axis_enqueue_resp_ptr, + output wire m_axis_enqueue_resp_phase, output wire [ADDR_WIDTH-1:0] m_axis_enqueue_resp_addr, output wire [EVENT_WIDTH-1:0] m_axis_enqueue_resp_event, output wire [REQ_TAG_WIDTH-1:0] m_axis_enqueue_resp_tag, @@ -202,6 +203,7 @@ reg s_axis_enqueue_req_ready_reg = 1'b0, s_axis_enqueue_req_ready_next; reg [QUEUE_INDEX_WIDTH-1:0] m_axis_enqueue_resp_queue_reg = 0, m_axis_enqueue_resp_queue_next; reg [QUEUE_PTR_WIDTH-1:0] m_axis_enqueue_resp_ptr_reg = 0, m_axis_enqueue_resp_ptr_next; +reg m_axis_enqueue_resp_phase_reg = 0, m_axis_enqueue_resp_phase_next; reg [ADDR_WIDTH-1:0] m_axis_enqueue_resp_addr_reg = 0, m_axis_enqueue_resp_addr_next; reg [EVENT_WIDTH-1:0] m_axis_enqueue_resp_event_reg = 0, m_axis_enqueue_resp_event_next; reg [REQ_TAG_WIDTH-1:0] m_axis_enqueue_resp_tag_reg = 0, m_axis_enqueue_resp_tag_next; @@ -262,6 +264,7 @@ assign s_axis_enqueue_req_ready = s_axis_enqueue_req_ready_reg; assign m_axis_enqueue_resp_queue = m_axis_enqueue_resp_queue_reg; assign m_axis_enqueue_resp_ptr = m_axis_enqueue_resp_ptr_reg; +assign m_axis_enqueue_resp_phase = m_axis_enqueue_resp_phase_reg; assign m_axis_enqueue_resp_addr = m_axis_enqueue_resp_addr_reg; assign m_axis_enqueue_resp_event = m_axis_enqueue_resp_event_reg; assign m_axis_enqueue_resp_tag = m_axis_enqueue_resp_tag_reg; @@ -343,6 +346,7 @@ always @* begin m_axis_enqueue_resp_queue_next = m_axis_enqueue_resp_queue_reg; m_axis_enqueue_resp_ptr_next = m_axis_enqueue_resp_ptr_reg; + m_axis_enqueue_resp_phase_next = m_axis_enqueue_resp_phase_reg; m_axis_enqueue_resp_addr_next = m_axis_enqueue_resp_addr_reg; m_axis_enqueue_resp_event_next = m_axis_enqueue_resp_event_reg; m_axis_enqueue_resp_tag_next = m_axis_enqueue_resp_tag_reg; @@ -442,6 +446,7 @@ always @* begin // request m_axis_enqueue_resp_queue_next = queue_ram_addr_pipeline_reg[PIPELINE-1]; m_axis_enqueue_resp_ptr_next = queue_ram_read_active_head_ptr; + m_axis_enqueue_resp_phase_next = !queue_ram_read_active_head_ptr[queue_ram_read_data_log_size]; m_axis_enqueue_resp_addr_next = queue_ram_read_data_base_addr + ((queue_ram_read_active_head_ptr & ({QUEUE_PTR_WIDTH{1'b1}} >> (QUEUE_PTR_WIDTH - queue_ram_read_data_log_size))) * CPL_SIZE); m_axis_enqueue_resp_event_next = queue_ram_read_data_event; m_axis_enqueue_resp_tag_next = req_tag_pipeline_reg[PIPELINE-1]; @@ -687,6 +692,7 @@ always @(posedge clk) begin m_axis_enqueue_resp_queue_reg <= m_axis_enqueue_resp_queue_next; m_axis_enqueue_resp_ptr_reg <= m_axis_enqueue_resp_ptr_next; + m_axis_enqueue_resp_phase_reg <= m_axis_enqueue_resp_phase_next; m_axis_enqueue_resp_addr_reg <= m_axis_enqueue_resp_addr_next; m_axis_enqueue_resp_event_reg <= m_axis_enqueue_resp_event_next; m_axis_enqueue_resp_tag_reg <= m_axis_enqueue_resp_tag_next; diff --git a/fpga/common/rtl/queue_manager.v b/fpga/common/rtl/queue_manager.v index 31027b27e..70611914c 100644 --- a/fpga/common/rtl/queue_manager.v +++ b/fpga/common/rtl/queue_manager.v @@ -88,6 +88,7 @@ module queue_manager # */ output wire [QUEUE_INDEX_WIDTH-1:0] m_axis_dequeue_resp_queue, output wire [QUEUE_PTR_WIDTH-1:0] m_axis_dequeue_resp_ptr, + output wire m_axis_dequeue_resp_phase, output wire [ADDR_WIDTH-1:0] m_axis_dequeue_resp_addr, output wire [LOG_BLOCK_SIZE_WIDTH-1:0] m_axis_dequeue_resp_block_size, output wire [CPL_INDEX_WIDTH-1:0] m_axis_dequeue_resp_cpl, @@ -203,6 +204,7 @@ reg s_axis_dequeue_req_ready_reg = 1'b0, s_axis_dequeue_req_ready_next; reg [QUEUE_INDEX_WIDTH-1:0] m_axis_dequeue_resp_queue_reg = 0, m_axis_dequeue_resp_queue_next; reg [QUEUE_PTR_WIDTH-1:0] m_axis_dequeue_resp_ptr_reg = 0, m_axis_dequeue_resp_ptr_next; +reg m_axis_dequeue_resp_phase_reg = 0, m_axis_dequeue_resp_phase_next; reg [ADDR_WIDTH-1:0] m_axis_dequeue_resp_addr_reg = 0, m_axis_dequeue_resp_addr_next; reg [LOG_BLOCK_SIZE_WIDTH-1:0] m_axis_dequeue_resp_block_size_reg = 0, m_axis_dequeue_resp_block_size_next; reg [CPL_INDEX_WIDTH-1:0] m_axis_dequeue_resp_cpl_reg = 0, m_axis_dequeue_resp_cpl_next; @@ -262,6 +264,7 @@ assign s_axis_dequeue_req_ready = s_axis_dequeue_req_ready_reg; assign m_axis_dequeue_resp_queue = m_axis_dequeue_resp_queue_reg; assign m_axis_dequeue_resp_ptr = m_axis_dequeue_resp_ptr_reg; +assign m_axis_dequeue_resp_phase = m_axis_dequeue_resp_phase_reg; assign m_axis_dequeue_resp_addr = m_axis_dequeue_resp_addr_reg; assign m_axis_dequeue_resp_block_size = m_axis_dequeue_resp_block_size_reg; assign m_axis_dequeue_resp_cpl = m_axis_dequeue_resp_cpl_reg; @@ -343,6 +346,7 @@ always @* begin m_axis_dequeue_resp_queue_next = m_axis_dequeue_resp_queue_reg; m_axis_dequeue_resp_ptr_next = m_axis_dequeue_resp_ptr_reg; + m_axis_dequeue_resp_phase_next = m_axis_dequeue_resp_phase_reg; m_axis_dequeue_resp_addr_next = m_axis_dequeue_resp_addr_reg; m_axis_dequeue_resp_block_size_next = m_axis_dequeue_resp_block_size_reg; m_axis_dequeue_resp_cpl_next = m_axis_dequeue_resp_cpl_reg; @@ -442,6 +446,7 @@ always @* begin // request m_axis_dequeue_resp_queue_next = queue_ram_addr_pipeline_reg[PIPELINE-1]; m_axis_dequeue_resp_ptr_next = queue_ram_read_active_tail_ptr; + m_axis_dequeue_resp_phase_next = !queue_ram_read_active_tail_ptr[queue_ram_read_data_log_queue_size]; m_axis_dequeue_resp_addr_next = queue_ram_read_data_base_addr + ((queue_ram_read_active_tail_ptr & ({QUEUE_PTR_WIDTH{1'b1}} >> (QUEUE_PTR_WIDTH - queue_ram_read_data_log_queue_size))) << (CL_DESC_SIZE+queue_ram_read_data_log_block_size)); m_axis_dequeue_resp_block_size_next = queue_ram_read_data_log_block_size; m_axis_dequeue_resp_cpl_next = queue_ram_read_data_cpl_queue; @@ -661,6 +666,7 @@ always @(posedge clk) begin m_axis_dequeue_resp_queue_reg <= m_axis_dequeue_resp_queue_next; m_axis_dequeue_resp_ptr_reg <= m_axis_dequeue_resp_ptr_next; + m_axis_dequeue_resp_phase_reg <= m_axis_dequeue_resp_phase_next; m_axis_dequeue_resp_addr_reg <= m_axis_dequeue_resp_addr_next; m_axis_dequeue_resp_block_size_reg <= m_axis_dequeue_resp_block_size_next; m_axis_dequeue_resp_cpl_reg <= m_axis_dequeue_resp_cpl_next; diff --git a/fpga/common/tb/cpl_queue_manager/test_cpl_queue_manager.py b/fpga/common/tb/cpl_queue_manager/test_cpl_queue_manager.py index 5157aa753..826c922fb 100644 --- a/fpga/common/tb/cpl_queue_manager/test_cpl_queue_manager.py +++ b/fpga/common/tb/cpl_queue_manager/test_cpl_queue_manager.py @@ -53,7 +53,7 @@ EnqueueReqBus, EnqueueReqTransaction, EnqueueReqSource, EnqueueReqSink, EnqueueR ) EnqueueRespBus, EnqueueRespTransaction, EnqueueRespSource, EnqueueRespSink, EnqueueRespMonitor = define_stream("EnqueueResp", - signals=["queue", "ptr", "addr", "event", "tag", "op_tag", "full", "error", "valid"], + signals=["queue", "ptr", "phase", "addr", "event", "tag", "op_tag", "full", "error", "valid"], optional_signals=["ready"] ) @@ -144,6 +144,7 @@ async def run_test(dut): assert resp.queue == 0 assert resp.ptr == head_ptr + assert resp.phase == ~(resp.ptr >> 4) & 1 assert resp.addr == 0x8877665544332211 assert resp.event == 1 assert resp.tag == 1 @@ -213,6 +214,7 @@ async def run_test(dut): assert resp.queue == q assert resp.ptr == queue_head_ptr[q] + assert resp.phase == ~(resp.ptr >> 4) & 1 assert (resp.addr >> 16) & 0xf == q assert (resp.addr >> 4) & 0xf == queue_head_ptr[q] & 0xf assert resp.event == q diff --git a/fpga/common/tb/queue_manager/test_queue_manager.py b/fpga/common/tb/queue_manager/test_queue_manager.py index 97c3866a4..c2e8664a6 100644 --- a/fpga/common/tb/queue_manager/test_queue_manager.py +++ b/fpga/common/tb/queue_manager/test_queue_manager.py @@ -53,7 +53,7 @@ DequeueReqBus, DequeueReqTransaction, DequeueReqSource, DequeueReqSink, DequeueR ) DequeueRespBus, DequeueRespTransaction, DequeueRespSource, DequeueRespSink, DequeueRespMonitor = define_stream("DequeueResp", - signals=["queue", "ptr", "addr", "block_size", "cpl", "tag", "op_tag", "empty", "error", "valid"], + signals=["queue", "ptr", "phase", "addr", "block_size", "cpl", "tag", "op_tag", "empty", "error", "valid"], optional_signals=["ready"] ) @@ -156,6 +156,7 @@ async def run_test(dut): assert resp.queue == 0 assert resp.ptr == tail_ptr + assert resp.phase == ~(resp.ptr >> 4) & 1 assert resp.addr == 0x8877665544332211 assert resp.block_size == 0 assert resp.cpl == 1 @@ -240,6 +241,7 @@ async def run_test(dut): assert resp.queue == q assert resp.ptr == queue_tail_ptr[q] + assert resp.phase == ~(resp.ptr >> 4) & 1 assert (resp.addr >> 16) & 0xf == q assert (resp.addr >> 4) & 0xf == queue_tail_ptr[q] & 0xf assert resp.block_size == 0