merged changes in axis

2025-01-16 08:12:53 +08:00 · 2019-07-18 11:50:56 -07:00 · 2019-07-18 11:50:56 -07:00 · 3a79b8fb17
commit 3a79b8fb17
parent 4da1a83052 8b2f37d5cc
36 changed files with 92 additions and 62 deletions
--- a/lib/axis/README.md
+++ b/lib/axis/README.md
@ -40,6 +40,13 @@ Configurable word-based or frame-based asynchronous FIFO with parametrizable
 data width, depth, type, and bad frame detection.  Supports power of two
 depths only.

+### axis_async_fifo_adapter module
+
+Configurable word-based or frame-based asynchronous FIFO with parametrizable
+data width, depth, type, and bad frame detection.  Supports different input
+and output data widths, inserting an axis_adapter instance appropriately.
+Supports power of two depths only.
+
 ### axis_broadcast module

 AXI stream broadcaster.  Duplicates one input stream across multiple output
@ -72,6 +79,13 @@ Configurable word-based or frame-based synchronous FIFO with parametrizable
 data width, depth, type, and bad frame detection.  Supports power of two
 depths only.

+### axis_fifo_adapter module
+
+Configurable word-based or frame-based synchronous FIFO with parametrizable
+data width, depth, type, and bad frame detection.  Supports different input
+and output data widths, inserting an axis_adapter instance appropriately.
+Supports power of two depths only.
+
 ### axis_frame_join module

 Frame joiner with optional tag and parametrizable port count.  8 bit data path
@ -191,12 +205,14 @@ Parametrizable priority encoder.
    axis_adapter.v                     : Parametrizable bus width adapter
    axis_arb_mux.v                     : Parametrizable arbitrated multiplexer
    axis_async_fifo.v                  : Parametrizable asynchronous FIFO
+    axis_async_fifo_adapter.v          : FIFO/width adapter wrapper
    axis_broadcast.v                   : AXI stream broadcaster
    axis_cobs_decode.v                 : COBS decoder
    axis_cobs_encode.v                 : COBS encoder
    axis_crosspoint.v                  : Parametrizable crosspoint switch
    axis_demux.v                       : Parametrizable demultiplexer
    axis_fifo.v                        : Parametrizable synchronous FIFO
+    axis_fifo_adapter.v                : FIFO/width adapter wrapper
    axis_frame_join.v                  : Parametrizable frame joiner
    axis_frame_length_adjust.v         : Frame length adjuster
    axis_frame_length_adjust_fifo.v    : Frame length adjuster with FIFO
--- a/lib/axis/rtl/axis_async_fifo.v
+++ b/lib/axis/rtl/axis_async_fifo.v
@ -31,7 +31,7 @@ THE SOFTWARE.
 */
 module axis_async_fifo #
 (
-    parameter ADDR_WIDTH = 12,
+    parameter DEPTH = 4096,
    parameter DATA_WIDTH = 8,
    parameter KEEP_ENABLE = (DATA_WIDTH>8),
    parameter KEEP_WIDTH = (DATA_WIDTH/8),
@ -91,6 +91,8 @@ module axis_async_fifo #
    output wire                   m_status_good_frame
 );

+parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH);
+
 // check configuration
 initial begin
    if (FRAME_FIFO && !LAST_ENABLE) begin
--- a/lib/axis/rtl/axis_async_fifo_adapter.v
+++ b/lib/axis/rtl/axis_async_fifo_adapter.v
@ -31,7 +31,7 @@ THE SOFTWARE.
 */
 module axis_async_fifo_adapter #
 (
-    parameter ADDR_WIDTH = 12,
+    parameter DEPTH = 4096,
    parameter S_DATA_WIDTH = 8,
    parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
    parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
@ -269,7 +269,7 @@ end
 endgenerate

 axis_async_fifo #(
-    .ADDR_WIDTH(ADDR_WIDTH),
+    .DEPTH(DEPTH),
    .DATA_WIDTH(DATA_WIDTH),
    .KEEP_ENABLE(EXPAND_BUS ? M_KEEP_ENABLE : S_KEEP_ENABLE),
    .KEEP_WIDTH(KEEP_WIDTH),
--- a/lib/axis/rtl/axis_cobs_encode.v
+++ b/lib/axis/rtl/axis_cobs_encode.v
@ -101,7 +101,7 @@ wire code_fifo_out_tuser;
 reg code_fifo_out_tready;

 axis_fifo #(
-    .ADDR_WIDTH(8),
+    .DEPTH(256),
    .DATA_WIDTH(8),
    .KEEP_ENABLE(0),
    .LAST_ENABLE(1),
@ -149,7 +149,7 @@ wire data_fifo_out_tlast;
 reg data_fifo_out_tready;

 axis_fifo #(
-    .ADDR_WIDTH(8),
+    .DEPTH(256),
    .DATA_WIDTH(8),
    .KEEP_ENABLE(0),
    .LAST_ENABLE(1),
--- a/lib/axis/rtl/axis_fifo.v
+++ b/lib/axis/rtl/axis_fifo.v
@ -31,7 +31,7 @@ THE SOFTWARE.
 */
 module axis_fifo #
 (
-    parameter ADDR_WIDTH = 12,
+    parameter DEPTH = 4096,
    parameter DATA_WIDTH = 8,
    parameter KEEP_ENABLE = (DATA_WIDTH>8),
    parameter KEEP_WIDTH = (DATA_WIDTH/8),
@ -84,6 +84,8 @@ module axis_fifo #
    output wire                   status_good_frame
 );

+parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH);
+
 // check configuration
 initial begin
    if (FRAME_FIFO && !LAST_ENABLE) begin
--- a/lib/axis/rtl/axis_fifo_adapter.v
+++ b/lib/axis/rtl/axis_fifo_adapter.v
@ -31,7 +31,7 @@ THE SOFTWARE.
 */
 module axis_fifo_adapter #
 (
-    parameter ADDR_WIDTH = 12,
+    parameter DEPTH = 4096,
    parameter S_DATA_WIDTH = 8,
    parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
    parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
@ -264,7 +264,7 @@ end
 endgenerate

 axis_fifo #(
-    .ADDR_WIDTH(ADDR_WIDTH),
+    .DEPTH(DEPTH),
    .DATA_WIDTH(DATA_WIDTH),
    .KEEP_ENABLE(EXPAND_BUS ? M_KEEP_ENABLE : S_KEEP_ENABLE),
    .KEEP_WIDTH(KEEP_WIDTH),
--- a/lib/axis/rtl/axis_frame_length_adjust.v
+++ b/lib/axis/rtl/axis_frame_length_adjust.v
@ -111,6 +111,8 @@ reg store_last_word;

 reg [15:0] frame_ptr_reg = 16'd0, frame_ptr_next;

+reg [DATA_WIDTH-1:0] s_axis_tdata_masked;
+
 // frame length counters
 reg [15:0] short_counter_reg = 16'd0, short_counter_next = 16'd0;
 reg [15:0] long_counter_reg = 16'd0, long_counter_next = 16'd0;
@ -175,13 +177,21 @@ always @* begin
    status_frame_length_next = status_frame_length_reg;
    status_frame_original_length_next = status_frame_original_length_reg;

+    if (KEEP_ENABLE) begin
+        for (i = 0; i < KEEP_WIDTH; i = i + 1) begin
+            s_axis_tdata_masked[i*DATA_WORD_WIDTH +: DATA_WORD_WIDTH] = s_axis_tkeep[i] ? s_axis_tdata[i*DATA_WORD_WIDTH +: DATA_WORD_WIDTH] : {DATA_WORD_WIDTH{1'b0}};
+        end
+    end else begin
+        s_axis_tdata_masked = s_axis_tdata;
+    end
+
    case (state_reg)
        STATE_IDLE: begin
            // idle state
            // accept data next cycle if output register ready next cycle
            s_axis_tready_next = m_axis_tready_int_early && (!status_valid_reg || status_ready);

-            m_axis_tdata_int = s_axis_tdata;
+            m_axis_tdata_int = s_axis_tdata_masked;
            m_axis_tkeep_int = s_axis_tkeep;
            m_axis_tvalid_int = s_axis_tvalid;
            m_axis_tlast_int = s_axis_tlast;
@ -279,7 +289,7 @@ always @* begin
            // accept data next cycle if output register ready next cycle
            s_axis_tready_next = m_axis_tready_int_early;

-            m_axis_tdata_int = s_axis_tdata;
+            m_axis_tdata_int = s_axis_tdata_masked;
            m_axis_tkeep_int = s_axis_tkeep;
            m_axis_tvalid_int = s_axis_tvalid;
            m_axis_tlast_int = s_axis_tlast;
--- a/lib/axis/rtl/axis_frame_length_adjust_fifo.v
+++ b/lib/axis/rtl/axis_frame_length_adjust_fifo.v
@ -40,8 +40,8 @@ module axis_frame_length_adjust_fifo #
    parameter DEST_WIDTH = 8,
    parameter USER_ENABLE = 1,
    parameter USER_WIDTH = 1,
-    parameter FRAME_FIFO_ADDR_WIDTH = 12,
-    parameter HEADER_FIFO_ADDR_WIDTH = 3
+    parameter FRAME_FIFO_DEPTH = 4096,
+    parameter HEADER_FIFO_DEPTH = 8
 )
 (
    input  wire                   clk,
@ -145,7 +145,7 @@ axis_frame_length_adjust_inst (
 );

 axis_fifo #(
-    .ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
+    .DEPTH(FRAME_FIFO_DEPTH),
    .DATA_WIDTH(DATA_WIDTH),
    .KEEP_ENABLE(KEEP_ENABLE),
    .KEEP_WIDTH(KEEP_WIDTH),
@ -186,7 +186,7 @@ frame_fifo_inst (
 );

 axis_fifo #(
-    .ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH),
+    .DEPTH(HEADER_FIFO_DEPTH),
    .DATA_WIDTH(1+1+16+16),
    .KEEP_ENABLE(0),
    .LAST_ENABLE(0),
--- a/lib/axis/tb/test_axis_async_fifo.py
+++ b/lib/axis/tb/test_axis_async_fifo.py
@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
 def bench():

    # Parameters
-    ADDR_WIDTH = 2
+    DEPTH = 4
    DATA_WIDTH = 8
    KEEP_ENABLE = (DATA_WIDTH>8)
    KEEP_WIDTH = (DATA_WIDTH/8)
--- a/lib/axis/tb/test_axis_async_fifo.v
+++ b/lib/axis/tb/test_axis_async_fifo.v
@ -32,7 +32,7 @@ THE SOFTWARE.
 module test_axis_async_fifo;

 // Parameters
-parameter ADDR_WIDTH = 2;
+parameter DEPTH = 4;
 parameter DATA_WIDTH = 8;
 parameter KEEP_ENABLE = (DATA_WIDTH>8);
 parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -107,7 +107,7 @@ initial begin
 end

 axis_async_fifo #(
-    .ADDR_WIDTH(ADDR_WIDTH),
+    .DEPTH(DEPTH),
    .DATA_WIDTH(DATA_WIDTH),
    .KEEP_ENABLE(KEEP_ENABLE),
    .KEEP_WIDTH(KEEP_WIDTH),
--- a/lib/axis/tb/test_axis_async_fifo_64.py
+++ b/lib/axis/tb/test_axis_async_fifo_64.py
@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
 def bench():

    # Parameters
-    ADDR_WIDTH = 2
+    DEPTH = 32
    DATA_WIDTH = 64
    KEEP_ENABLE = (DATA_WIDTH>8)
    KEEP_WIDTH = (DATA_WIDTH/8)
--- a/lib/axis/tb/test_axis_async_fifo_64.v
+++ b/lib/axis/tb/test_axis_async_fifo_64.v
@ -32,7 +32,7 @@ THE SOFTWARE.
 module test_axis_async_fifo_64;

 // Parameters
-parameter ADDR_WIDTH = 2;
+parameter DEPTH = 32;
 parameter DATA_WIDTH = 64;
 parameter KEEP_ENABLE = (DATA_WIDTH>8);
 parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -107,7 +107,7 @@ initial begin
 end

 axis_async_fifo #(
-    .ADDR_WIDTH(ADDR_WIDTH),
+    .DEPTH(DEPTH),
    .DATA_WIDTH(DATA_WIDTH),
    .KEEP_ENABLE(KEEP_ENABLE),
    .KEEP_WIDTH(KEEP_WIDTH),
--- a/lib/axis/tb/test_axis_async_fifo_adapter_64_8.py
+++ b/lib/axis/tb/test_axis_async_fifo_adapter_64_8.py
@ -45,7 +45,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
 def bench():

    # Parameters
-    ADDR_WIDTH = 2
+    DEPTH = 32
    S_DATA_WIDTH = 64
    S_KEEP_ENABLE = (S_DATA_WIDTH>8)
    S_KEEP_WIDTH = (S_DATA_WIDTH/8)
--- a/lib/axis/tb/test_axis_async_fifo_adapter_64_8.v
+++ b/lib/axis/tb/test_axis_async_fifo_adapter_64_8.v
@ -32,7 +32,7 @@ THE SOFTWARE.
 module test_axis_async_fifo_adapter_64_8;

 // Parameters
-parameter ADDR_WIDTH = 2;
+parameter DEPTH = 32;
 parameter S_DATA_WIDTH = 64;
 parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8);
 parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8);
@ -111,7 +111,7 @@ initial begin
 end

 axis_async_fifo_adapter #(
-    .ADDR_WIDTH(ADDR_WIDTH),
+    .DEPTH(DEPTH),
    .S_DATA_WIDTH(S_DATA_WIDTH),
    .S_KEEP_ENABLE(S_KEEP_ENABLE),
    .S_KEEP_WIDTH(S_KEEP_WIDTH),
--- a/lib/axis/tb/test_axis_async_fifo_adapter_8_64.py
+++ b/lib/axis/tb/test_axis_async_fifo_adapter_8_64.py
@ -45,7 +45,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
 def bench():

    # Parameters
-    ADDR_WIDTH = 2
+    DEPTH = 32
    S_DATA_WIDTH = 8
    S_KEEP_ENABLE = (S_DATA_WIDTH>8)
    S_KEEP_WIDTH = (S_DATA_WIDTH/8)
--- a/lib/axis/tb/test_axis_async_fifo_adapter_8_64.v
+++ b/lib/axis/tb/test_axis_async_fifo_adapter_8_64.v
@ -32,7 +32,7 @@ THE SOFTWARE.
 module test_axis_async_fifo_adapter_8_64;

 // Parameters
-parameter ADDR_WIDTH = 2;
+parameter DEPTH = 32;
 parameter S_DATA_WIDTH = 8;
 parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8);
 parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8);
@ -111,7 +111,7 @@ initial begin
 end

 axis_async_fifo_adapter #(
-    .ADDR_WIDTH(ADDR_WIDTH),
+    .DEPTH(DEPTH),
    .S_DATA_WIDTH(S_DATA_WIDTH),
    .S_KEEP_ENABLE(S_KEEP_ENABLE),
    .S_KEEP_WIDTH(S_KEEP_WIDTH),
--- a/lib/axis/tb/test_axis_async_frame_fifo.py
+++ b/lib/axis/tb/test_axis_async_frame_fifo.py
@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
 def bench():

    # Parameters
-    ADDR_WIDTH = 9
+    DEPTH = 512
    DATA_WIDTH = 8
    KEEP_ENABLE = (DATA_WIDTH>8)
    KEEP_WIDTH = (DATA_WIDTH/8)
--- a/lib/axis/tb/test_axis_async_frame_fifo.v
+++ b/lib/axis/tb/test_axis_async_frame_fifo.v
@ -32,7 +32,7 @@ THE SOFTWARE.
 module test_axis_async_frame_fifo;

 // Parameters
-parameter ADDR_WIDTH = 9;
+parameter DEPTH = 512;
 parameter DATA_WIDTH = 8;
 parameter KEEP_ENABLE = (DATA_WIDTH>8);
 parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -119,7 +119,7 @@ initial begin
 end

 axis_async_fifo #(
-    .ADDR_WIDTH(ADDR_WIDTH),
+    .DEPTH(DEPTH),
    .DATA_WIDTH(DATA_WIDTH),
    .KEEP_ENABLE(KEEP_ENABLE),
    .KEEP_WIDTH(KEEP_WIDTH),
--- a/lib/axis/tb/test_axis_async_frame_fifo_64.py
+++ b/lib/axis/tb/test_axis_async_frame_fifo_64.py
@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
 def bench():

    # Parameters
-    ADDR_WIDTH = 6
+    DEPTH = 512
    DATA_WIDTH = 64
    KEEP_ENABLE = (DATA_WIDTH>8)
    KEEP_WIDTH = (DATA_WIDTH/8)
--- a/lib/axis/tb/test_axis_async_frame_fifo_64.v
+++ b/lib/axis/tb/test_axis_async_frame_fifo_64.v
@ -32,7 +32,7 @@ THE SOFTWARE.
 module test_axis_async_frame_fifo_64;

 // Parameters
-parameter ADDR_WIDTH = 6;
+parameter DEPTH = 512;
 parameter DATA_WIDTH = 64;
 parameter KEEP_ENABLE = (DATA_WIDTH>8);
 parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -119,7 +119,7 @@ initial begin
 end

 axis_async_fifo #(
-    .ADDR_WIDTH(ADDR_WIDTH),
+    .DEPTH(DEPTH),
    .DATA_WIDTH(DATA_WIDTH),
    .KEEP_ENABLE(KEEP_ENABLE),
    .KEEP_WIDTH(KEEP_WIDTH),
--- a/lib/axis/tb/test_axis_fifo.py
+++ b/lib/axis/tb/test_axis_fifo.py
@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
 def bench():

    # Parameters
-    ADDR_WIDTH = 2
+    DEPTH = 4
    DATA_WIDTH = 8
    KEEP_ENABLE = (DATA_WIDTH>8)
    KEEP_WIDTH = (DATA_WIDTH/8)
--- a/lib/axis/tb/test_axis_fifo.v
+++ b/lib/axis/tb/test_axis_fifo.v
@ -32,7 +32,7 @@ THE SOFTWARE.
 module test_axis_fifo;

 // Parameters
-parameter ADDR_WIDTH = 2;
+parameter DEPTH = 4;
 parameter DATA_WIDTH = 8;
 parameter KEEP_ENABLE = (DATA_WIDTH>8);
 parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -105,7 +105,7 @@ initial begin
 end

 axis_fifo #(
-    .ADDR_WIDTH(ADDR_WIDTH),
+    .DEPTH(DEPTH),
    .DATA_WIDTH(DATA_WIDTH),
    .KEEP_ENABLE(KEEP_ENABLE),
    .KEEP_WIDTH(KEEP_WIDTH),
--- a/lib/axis/tb/test_axis_fifo_64.py
+++ b/lib/axis/tb/test_axis_fifo_64.py
@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
 def bench():

    # Parameters
-    ADDR_WIDTH = 2
+    DEPTH = 32
    DATA_WIDTH = 64
    KEEP_ENABLE = (DATA_WIDTH>8)
    KEEP_WIDTH = (DATA_WIDTH/8)
--- a/lib/axis/tb/test_axis_fifo_64.v
+++ b/lib/axis/tb/test_axis_fifo_64.v
@ -32,7 +32,7 @@ THE SOFTWARE.
 module test_axis_fifo_64;

 // Parameters
-parameter ADDR_WIDTH = 2;
+parameter DEPTH = 32;
 parameter DATA_WIDTH = 64;
 parameter KEEP_ENABLE = (DATA_WIDTH>8);
 parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -105,7 +105,7 @@ initial begin
 end

 axis_fifo #(
-    .ADDR_WIDTH(ADDR_WIDTH),
+    .DEPTH(DEPTH),
    .DATA_WIDTH(DATA_WIDTH),
    .KEEP_ENABLE(KEEP_ENABLE),
    .KEEP_WIDTH(KEEP_WIDTH),
--- a/lib/axis/tb/test_axis_fifo_adapter_64_8.py
+++ b/lib/axis/tb/test_axis_fifo_adapter_64_8.py
@ -45,7 +45,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
 def bench():

    # Parameters
-    ADDR_WIDTH = 2
+    DEPTH = 32
    S_DATA_WIDTH = 64
    S_KEEP_ENABLE = (S_DATA_WIDTH>8)
    S_KEEP_WIDTH = (S_DATA_WIDTH/8)
--- a/lib/axis/tb/test_axis_fifo_adapter_64_8.v
+++ b/lib/axis/tb/test_axis_fifo_adapter_64_8.v
@ -32,7 +32,7 @@ THE SOFTWARE.
 module test_axis_fifo_adapter_64_8;

 // Parameters
-parameter ADDR_WIDTH = 2;
+parameter DEPTH = 32;
 parameter S_DATA_WIDTH = 64;
 parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8);
 parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8);
@ -107,7 +107,7 @@ initial begin
 end

 axis_fifo_adapter #(
-    .ADDR_WIDTH(ADDR_WIDTH),
+    .DEPTH(DEPTH),
    .S_DATA_WIDTH(S_DATA_WIDTH),
    .S_KEEP_ENABLE(S_KEEP_ENABLE),
    .S_KEEP_WIDTH(S_KEEP_WIDTH),
--- a/lib/axis/tb/test_axis_fifo_adapter_8_64.py
+++ b/lib/axis/tb/test_axis_fifo_adapter_8_64.py
@ -45,7 +45,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
 def bench():

    # Parameters
-    ADDR_WIDTH = 2
+    DEPTH = 32
    S_DATA_WIDTH = 8
    S_KEEP_ENABLE = (S_DATA_WIDTH>8)
    S_KEEP_WIDTH = (S_DATA_WIDTH/8)
--- a/lib/axis/tb/test_axis_fifo_adapter_8_64.v
+++ b/lib/axis/tb/test_axis_fifo_adapter_8_64.v
@ -32,7 +32,7 @@ THE SOFTWARE.
 module test_axis_fifo_adapter_8_64;

 // Parameters
-parameter ADDR_WIDTH = 2;
+parameter DEPTH = 32;
 parameter S_DATA_WIDTH = 8;
 parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8);
 parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8);
@ -107,7 +107,7 @@ initial begin
 end

 axis_fifo_adapter #(
-    .ADDR_WIDTH(ADDR_WIDTH),
+    .DEPTH(DEPTH),
    .S_DATA_WIDTH(S_DATA_WIDTH),
    .S_KEEP_ENABLE(S_KEEP_ENABLE),
    .S_KEEP_WIDTH(S_KEEP_WIDTH),
--- a/lib/axis/tb/test_axis_frame_fifo.py
+++ b/lib/axis/tb/test_axis_frame_fifo.py
@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
 def bench():

    # Parameters
-    ADDR_WIDTH = 9
+    DEPTH = 512
    DATA_WIDTH = 8
    KEEP_ENABLE = (DATA_WIDTH>8)
    KEEP_WIDTH = (DATA_WIDTH/8)
--- a/lib/axis/tb/test_axis_frame_fifo.v
+++ b/lib/axis/tb/test_axis_frame_fifo.v
@ -32,7 +32,7 @@ THE SOFTWARE.
 module test_axis_frame_fifo;

 // Parameters
-parameter ADDR_WIDTH = 9;
+parameter DEPTH = 512;
 parameter DATA_WIDTH = 8;
 parameter KEEP_ENABLE = (DATA_WIDTH>8);
 parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -111,7 +111,7 @@ initial begin
 end

 axis_fifo #(
-    .ADDR_WIDTH(ADDR_WIDTH),
+    .DEPTH(DEPTH),
    .DATA_WIDTH(DATA_WIDTH),
    .KEEP_ENABLE(KEEP_ENABLE),
    .KEEP_WIDTH(KEEP_WIDTH),
--- a/lib/axis/tb/test_axis_frame_fifo_64.py
+++ b/lib/axis/tb/test_axis_frame_fifo_64.py
@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
 def bench():

    # Parameters
-    ADDR_WIDTH = 6
+    DEPTH = 512
    DATA_WIDTH = 64
    KEEP_ENABLE = (DATA_WIDTH>8)
    KEEP_WIDTH = (DATA_WIDTH/8)
--- a/lib/axis/tb/test_axis_frame_fifo_64.v
+++ b/lib/axis/tb/test_axis_frame_fifo_64.v
@ -32,7 +32,7 @@ THE SOFTWARE.
 module test_axis_frame_fifo_64;

 // Parameters
-parameter ADDR_WIDTH = 6;
+parameter DEPTH = 512;
 parameter DATA_WIDTH = 64;
 parameter KEEP_ENABLE = (DATA_WIDTH>8);
 parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -111,7 +111,7 @@ initial begin
 end

 axis_fifo #(
-    .ADDR_WIDTH(ADDR_WIDTH),
+    .DEPTH(DEPTH),
    .DATA_WIDTH(DATA_WIDTH),
    .KEEP_ENABLE(KEEP_ENABLE),
    .KEEP_WIDTH(KEEP_WIDTH),
--- a/lib/axis/tb/test_axis_frame_length_adjust_fifo.py
+++ b/lib/axis/tb/test_axis_frame_length_adjust_fifo.py
@ -54,8 +54,8 @@ def bench():
    DEST_WIDTH = 8
    USER_ENABLE = 1
    USER_WIDTH = 1
-    FRAME_FIFO_ADDR_WIDTH = 12
-    HEADER_FIFO_ADDR_WIDTH = 3
+    FRAME_FIFO_DEPTH = 4096
+    HEADER_FIFO_DEPTH = 8

    # Inputs
    clk = Signal(bool(0))
--- a/lib/axis/tb/test_axis_frame_length_adjust_fifo.v
+++ b/lib/axis/tb/test_axis_frame_length_adjust_fifo.v
@ -41,8 +41,8 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
-parameter FRAME_FIFO_ADDR_WIDTH = 12;
-parameter HEADER_FIFO_ADDR_WIDTH = 3;
+parameter FRAME_FIFO_DEPTH = 4096;
+parameter HEADER_FIFO_DEPTH = 8;

 // Inputs
 reg clk = 0;
@ -125,8 +125,8 @@ axis_frame_length_adjust_fifo #(
    .DEST_WIDTH(DEST_WIDTH),
    .USER_ENABLE(USER_ENABLE),
    .USER_WIDTH(USER_WIDTH),
-    .FRAME_FIFO_ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
-    .HEADER_FIFO_ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH)
+    .FRAME_FIFO_DEPTH(FRAME_FIFO_DEPTH),
+    .HEADER_FIFO_DEPTH(HEADER_FIFO_DEPTH)
 )
 UUT (
    .clk(clk),
--- a/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.py
+++ b/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.py
@ -54,8 +54,8 @@ def bench():
    DEST_WIDTH = 8
    USER_ENABLE = 1
    USER_WIDTH = 1
-    FRAME_FIFO_ADDR_WIDTH = 9
-    HEADER_FIFO_ADDR_WIDTH = 3
+    FRAME_FIFO_DEPTH = 4096
+    HEADER_FIFO_DEPTH = 8

    # Inputs
    clk = Signal(bool(0))
--- a/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.v
+++ b/lib/axis/tb/test_axis_frame_length_adjust_fifo_64.v
@ -41,8 +41,8 @@ parameter DEST_ENABLE = 1;
 parameter DEST_WIDTH = 8;
 parameter USER_ENABLE = 1;
 parameter USER_WIDTH = 1;
-parameter FRAME_FIFO_ADDR_WIDTH = 9;
-parameter HEADER_FIFO_ADDR_WIDTH = 3;
+parameter FRAME_FIFO_DEPTH = 4096;
+parameter HEADER_FIFO_DEPTH = 8;

 // Inputs
 reg clk = 0;
@ -125,8 +125,8 @@ axis_frame_length_adjust_fifo #(
    .DEST_WIDTH(DEST_WIDTH),
    .USER_ENABLE(USER_ENABLE),
    .USER_WIDTH(USER_WIDTH),
-    .FRAME_FIFO_ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
-    .HEADER_FIFO_ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH)
+    .FRAME_FIFO_DEPTH(FRAME_FIFO_DEPTH),
+    .HEADER_FIFO_DEPTH(HEADER_FIFO_DEPTH)
 )
 UUT (
    .clk(clk),