diff --git a/example/NexysVideo/fpga/fpga.xdc b/example/NexysVideo/fpga/fpga.xdc index b6b1580d7..c6da45b8e 100644 --- a/example/NexysVideo/fpga/fpga.xdc +++ b/example/NexysVideo/fpga/fpga.xdc @@ -8,7 +8,7 @@ set_property CONFIG_VOLTAGE 3.3 [current_design] # 100 MHz clock set_property -dict {LOC R4 IOSTANDARD LVCMOS33} [get_ports clk] create_clock -period 10.000 -name clk [get_ports clk] -set_clock_groups -asynchronous -group clk +set_clock_groups -asynchronous -group [get_clocks clk -include_generated_clocks] # LEDs set_property -dict {LOC T14 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[0]}] @@ -64,5 +64,5 @@ set_property -dict {LOC W14 IOSTANDARD LVCMOS25} [get_ports phy_pme_n] #set_property -dict {LOC AA16 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports phy_mdc] create_clock -period 8.000 -name phy_rx_clk [get_ports phy_rx_clk] -set_clock_groups -asynchronous -group phy_rx_clk +set_clock_groups -asynchronous -group [get_clocks phy_rx_clk -include_generated_clocks] diff --git a/example/VCU108/fpga_10g/fpga.xdc b/example/VCU108/fpga_10g/fpga.xdc index e28e4aa93..4ad1c74f3 100644 --- a/example/VCU108/fpga_10g/fpga.xdc +++ b/example/VCU108/fpga_10g/fpga.xdc @@ -10,23 +10,23 @@ set_property CONFIG_VOLTAGE 1.8 [current_design] #set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p] #set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n] #create_clock -period 3.333 -name clk_300_mhz_1 [get_ports clk_300mhz_1_p] -#set_clock_groups -asynchronous -group clk_300mhz_1 +#set_clock_groups -asynchronous -group [get_clocks clk_300mhz_1 -include_generated_clocks] #set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p] #set_property -dict {LOC G21 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_n] #create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] -#set_clock_groups -asynchronous -group clk_300mhz_2 +#set_clock_groups -asynchronous -group [get_clocks clk_300mhz_2 -include_generated_clocks] # 125 MHz set_property -dict {LOC BC9 IOSTANDARD LVDS} [get_ports clk_125mhz_p] set_property -dict {LOC BC8 IOSTANDARD LVDS} [get_ports clk_125mhz_n] create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] -set_clock_groups -asynchronous -group clk_125mhz +set_clock_groups -asynchronous -group [get_clocks clk_125mhz -include_generated_clocks] # 90 MHz #set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz] #create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz] -#set_clock_groups -asynchronous -group clk_90mhz +#set_clock_groups -asynchronous -group [get_clocks clk_90mhz -include_generated_clocks] # LEDs set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] @@ -74,7 +74,7 @@ set_property -dict {LOC AT21 IOSTANDARD LVCMOS18} [get_ports phy_int_n] # 625 MHz ref clock from SGMII PHY create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p] -set_clock_groups -asynchronous -group phy_sgmii_clk +set_clock_groups -asynchronous -group [get_clocks phy_sgmii_clk -include_generated_clocks] # QSFP+ Interface set_property -dict {LOC AG45} [get_ports qsfp_rx1_p] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3 diff --git a/example/VCU108/fpga_1g/fpga.xdc b/example/VCU108/fpga_1g/fpga.xdc index f6df87b7e..b7cc5658a 100644 --- a/example/VCU108/fpga_1g/fpga.xdc +++ b/example/VCU108/fpga_1g/fpga.xdc @@ -10,23 +10,23 @@ set_property CONFIG_VOLTAGE 1.8 [current_design] #set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p] #set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n] #create_clock -period 3.333 -name clk_300_mhz_1 [get_ports clk_300mhz_1_p] -#set_clock_groups -asynchronous -group clk_300mhz_1 +#set_clock_groups -asynchronous -group [get_clocks clk_300mhz_1 -include_generated_clocks] #set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p] #set_property -dict {LOC G21 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_n] #create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] -#set_clock_groups -asynchronous -group clk_300mhz_2 +#set_clock_groups -asynchronous -group [get_clocks clk_300mhz_2 -include_generated_clocks] # 125 MHz set_property -dict {LOC BC9 IOSTANDARD LVDS} [get_ports clk_125mhz_p] set_property -dict {LOC BC8 IOSTANDARD LVDS} [get_ports clk_125mhz_n] create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] -set_clock_groups -asynchronous -group clk_125mhz +set_clock_groups -asynchronous -group [get_clocks clk_125mhz -include_generated_clocks] # 90 MHz #set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz] #create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz] -#set_clock_groups -asynchronous -group clk_90mhz +#set_clock_groups -asynchronous -group [get_clocks clk_90mhz -include_generated_clocks] # LEDs set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] @@ -74,5 +74,5 @@ set_property -dict {LOC AT21 IOSTANDARD LVCMOS18} [get_ports phy_int_n] # 625 MHz ref clock from SGMII PHY create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p] -set_clock_groups -asynchronous -group phy_sgmii_clk +set_clock_groups -asynchronous -group [get_clocks phy_sgmii_clk -include_generated_clocks]