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https://github.com/corundum/corundum.git
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Fix Vivado clock groups
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parent
77ecbd7dcb
commit
3b47b422fa
@ -8,7 +8,7 @@ set_property CONFIG_VOLTAGE 3.3 [current_design]
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# 100 MHz clock
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# 100 MHz clock
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set_property -dict {LOC R4 IOSTANDARD LVCMOS33} [get_ports clk]
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set_property -dict {LOC R4 IOSTANDARD LVCMOS33} [get_ports clk]
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create_clock -period 10.000 -name clk [get_ports clk]
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create_clock -period 10.000 -name clk [get_ports clk]
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set_clock_groups -asynchronous -group clk
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set_clock_groups -asynchronous -group [get_clocks clk -include_generated_clocks]
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# LEDs
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# LEDs
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set_property -dict {LOC T14 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[0]}]
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set_property -dict {LOC T14 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports {led[0]}]
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@ -64,5 +64,5 @@ set_property -dict {LOC W14 IOSTANDARD LVCMOS25} [get_ports phy_pme_n]
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#set_property -dict {LOC AA16 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports phy_mdc]
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#set_property -dict {LOC AA16 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12} [get_ports phy_mdc]
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create_clock -period 8.000 -name phy_rx_clk [get_ports phy_rx_clk]
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create_clock -period 8.000 -name phy_rx_clk [get_ports phy_rx_clk]
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set_clock_groups -asynchronous -group phy_rx_clk
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set_clock_groups -asynchronous -group [get_clocks phy_rx_clk -include_generated_clocks]
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@ -10,23 +10,23 @@ set_property CONFIG_VOLTAGE 1.8 [current_design]
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#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p]
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#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p]
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#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n]
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#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n]
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#create_clock -period 3.333 -name clk_300_mhz_1 [get_ports clk_300mhz_1_p]
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#create_clock -period 3.333 -name clk_300_mhz_1 [get_ports clk_300mhz_1_p]
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#set_clock_groups -asynchronous -group clk_300mhz_1
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#set_clock_groups -asynchronous -group [get_clocks clk_300mhz_1 -include_generated_clocks]
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#set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p]
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#set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p]
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#set_property -dict {LOC G21 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_n]
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#set_property -dict {LOC G21 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_n]
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#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
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#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
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#set_clock_groups -asynchronous -group clk_300mhz_2
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#set_clock_groups -asynchronous -group [get_clocks clk_300mhz_2 -include_generated_clocks]
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# 125 MHz
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# 125 MHz
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set_property -dict {LOC BC9 IOSTANDARD LVDS} [get_ports clk_125mhz_p]
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set_property -dict {LOC BC9 IOSTANDARD LVDS} [get_ports clk_125mhz_p]
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set_property -dict {LOC BC8 IOSTANDARD LVDS} [get_ports clk_125mhz_n]
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set_property -dict {LOC BC8 IOSTANDARD LVDS} [get_ports clk_125mhz_n]
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create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
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create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
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set_clock_groups -asynchronous -group clk_125mhz
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set_clock_groups -asynchronous -group [get_clocks clk_125mhz -include_generated_clocks]
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# 90 MHz
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# 90 MHz
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#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
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#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
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#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
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#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
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#set_clock_groups -asynchronous -group clk_90mhz
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#set_clock_groups -asynchronous -group [get_clocks clk_90mhz -include_generated_clocks]
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# LEDs
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# LEDs
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set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
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set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
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@ -74,7 +74,7 @@ set_property -dict {LOC AT21 IOSTANDARD LVCMOS18} [get_ports phy_int_n]
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# 625 MHz ref clock from SGMII PHY
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# 625 MHz ref clock from SGMII PHY
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create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
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create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
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set_clock_groups -asynchronous -group phy_sgmii_clk
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set_clock_groups -asynchronous -group [get_clocks phy_sgmii_clk -include_generated_clocks]
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# QSFP+ Interface
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# QSFP+ Interface
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set_property -dict {LOC AG45} [get_ports qsfp_rx1_p] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AG45} [get_ports qsfp_rx1_p] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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@ -10,23 +10,23 @@ set_property CONFIG_VOLTAGE 1.8 [current_design]
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#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p]
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#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p]
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#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n]
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#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n]
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#create_clock -period 3.333 -name clk_300_mhz_1 [get_ports clk_300mhz_1_p]
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#create_clock -period 3.333 -name clk_300_mhz_1 [get_ports clk_300mhz_1_p]
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#set_clock_groups -asynchronous -group clk_300mhz_1
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#set_clock_groups -asynchronous -group [get_clocks clk_300mhz_1 -include_generated_clocks]
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#set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p]
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#set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p]
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#set_property -dict {LOC G21 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_n]
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#set_property -dict {LOC G21 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_n]
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#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
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#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
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#set_clock_groups -asynchronous -group clk_300mhz_2
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#set_clock_groups -asynchronous -group [get_clocks clk_300mhz_2 -include_generated_clocks]
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# 125 MHz
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# 125 MHz
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set_property -dict {LOC BC9 IOSTANDARD LVDS} [get_ports clk_125mhz_p]
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set_property -dict {LOC BC9 IOSTANDARD LVDS} [get_ports clk_125mhz_p]
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set_property -dict {LOC BC8 IOSTANDARD LVDS} [get_ports clk_125mhz_n]
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set_property -dict {LOC BC8 IOSTANDARD LVDS} [get_ports clk_125mhz_n]
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create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
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create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
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set_clock_groups -asynchronous -group clk_125mhz
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set_clock_groups -asynchronous -group [get_clocks clk_125mhz -include_generated_clocks]
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# 90 MHz
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# 90 MHz
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#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
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#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
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#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
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#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
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#set_clock_groups -asynchronous -group clk_90mhz
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#set_clock_groups -asynchronous -group [get_clocks clk_90mhz -include_generated_clocks]
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# LEDs
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# LEDs
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set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
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set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
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@ -74,5 +74,5 @@ set_property -dict {LOC AT21 IOSTANDARD LVCMOS18} [get_ports phy_int_n]
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# 625 MHz ref clock from SGMII PHY
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# 625 MHz ref clock from SGMII PHY
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create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
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create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
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set_clock_groups -asynchronous -group phy_sgmii_clk
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set_clock_groups -asynchronous -group [get_clocks phy_sgmii_clk -include_generated_clocks]
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