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fpga/mqnic: Rework parametrization for Intel 100G designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-11-13 19:16:32 -08:00
parent 12cb29f9ee
commit 3b70f93722
17 changed files with 2899 additions and 1780 deletions
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164
fpga/mqnic/DE10_Agilex/fpga_100g/rtl/eth_mac_dual_wrapper.v
View File

@ -33,6 +33,7 @@ THE SOFTWARE.
*/
module eth_mac_dual_wrapper #
(
parameter N_CH = 2,
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 8,
parameter DATA_WIDTH = 512,
@ -50,70 +51,39 @@ module eth_mac_dual_wrapper #
input wire [7:0] rx_serial_data_n,
input wire ref_clk,
output wire mac_1_clk,
output wire mac_1_rst,
output wire [N_CH-1:0] mac_clk,
output wire [N_CH-1:0] mac_rst,
input wire [PTP_TS_WIDTH-1:0] mac_1_ptp_time,
input wire [N_CH*PTP_TS_WIDTH-1:0] mac_ptp_time,
output wire [PTP_TS_WIDTH-1:0] mac_1_tx_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] mac_1_tx_ptp_ts_tag,
output wire mac_1_tx_ptp_ts_valid,
output wire [N_CH*PTP_TS_WIDTH-1:0] mac_tx_ptp_ts,
output wire [N_CH*PTP_TAG_WIDTH-1:0] mac_tx_ptp_ts_tag,
output wire [N_CH-1:0] mac_tx_ptp_ts_valid,
input wire [DATA_WIDTH-1:0] mac_1_tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] mac_1_tx_axis_tkeep,
input wire mac_1_tx_axis_tvalid,
output wire mac_1_tx_axis_tready,
input wire mac_1_tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] mac_1_tx_axis_tuser,
input wire [N_CH*DATA_WIDTH-1:0] mac_tx_axis_tdata,
input wire [N_CH*KEEP_WIDTH-1:0] mac_tx_axis_tkeep,
input wire [N_CH-1:0] mac_tx_axis_tvalid,
output wire [N_CH-1:0] mac_tx_axis_tready,
input wire [N_CH-1:0] mac_tx_axis_tlast,
input wire [N_CH*TX_USER_WIDTH-1:0] mac_tx_axis_tuser,
output wire mac_1_tx_status,
input wire mac_1_tx_lfc_req,
input wire [7:0] mac_1_tx_pfc_req,
output wire [N_CH*1-1:0] mac_tx_status,
input wire [N_CH*1-1:0] mac_tx_lfc_req,
input wire [N_CH*8-1:0] mac_tx_pfc_req,
output wire [DATA_WIDTH-1:0] mac_1_rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] mac_1_rx_axis_tkeep,
output wire mac_1_rx_axis_tvalid,
output wire mac_1_rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] mac_1_rx_axis_tuser,
output wire [N_CH*DATA_WIDTH-1:0] mac_rx_axis_tdata,
output wire [N_CH*KEEP_WIDTH-1:0] mac_rx_axis_tkeep,
output wire [N_CH-1:0] mac_rx_axis_tvalid,
output wire [N_CH-1:0] mac_rx_axis_tlast,
output wire [N_CH*RX_USER_WIDTH-1:0] mac_rx_axis_tuser,
output wire mac_1_rx_status,
output wire mac_1_rx_lfc_req,
output wire [7:0] mac_1_rx_pfc_req,
output wire mac_2_clk,
output wire mac_2_rst,
input wire [PTP_TS_WIDTH-1:0] mac_2_ptp_time,
output wire [PTP_TS_WIDTH-1:0] mac_2_tx_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] mac_2_tx_ptp_ts_tag,
output wire mac_2_tx_ptp_ts_valid,
input wire [DATA_WIDTH-1:0] mac_2_tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] mac_2_tx_axis_tkeep,
input wire mac_2_tx_axis_tvalid,
output wire mac_2_tx_axis_tready,
input wire mac_2_tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] mac_2_tx_axis_tuser,
output wire mac_2_tx_status,
input wire mac_2_tx_lfc_req,
input wire [7:0] mac_2_tx_pfc_req,
output wire [DATA_WIDTH-1:0] mac_2_rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] mac_2_rx_axis_tkeep,
output wire mac_2_rx_axis_tvalid,
output wire mac_2_rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] mac_2_rx_axis_tuser,
output wire mac_2_rx_status,
output wire mac_2_rx_lfc_req,
output wire [7:0] mac_2_rx_pfc_req
output wire [N_CH*1-1:0] mac_rx_status,
output wire [N_CH*1-1:0] mac_rx_lfc_req,
output wire [N_CH*8-1:0] mac_rx_pfc_req
);
parameter N_CH = 2;
parameter XCVR_PER_MAC = 4;
parameter XCVR_CH = N_CH*XCVR_PER_MAC;
localparam XCVR_PER_MAC = 4;
localparam XCVR_CH = N_CH*XCVR_PER_MAC;
wire [N_CH*6-1:0] mac_pll_clk_d64;
wire [N_CH*6-1:0] mac_pll_clk_d66;
@ -122,9 +92,6 @@ wire [N_CH*6-1:0] mac_rec_clk_d66;
wire [N_CH-1:0] mac_tx_pll_locked;
wire [N_CH-1:0] mac_clk;
wire [N_CH-1:0] mac_rst;
wire [XCVR_CH*19-1:0] xcvr_reconfig_address;
wire [XCVR_CH-1:0] xcvr_reconfig_read;
wire [XCVR_CH-1:0] xcvr_reconfig_write;
@ -351,81 +318,22 @@ mac_13 mac_13_inst (
.o_rx_pause (mac_rx_pause[1*1 +: 1])
);
wire [N_CH*DATA_WIDTH-1:0] mac_rx_axis_tdata;
wire [N_CH*KEEP_WIDTH-1:0] mac_rx_axis_tkeep;
wire [N_CH-1:0] mac_rx_axis_tvalid;
wire [N_CH-1:0] mac_rx_axis_tlast;
wire [N_CH*RX_USER_WIDTH-1:0] mac_rx_axis_tuser;
wire [N_CH*DATA_WIDTH-1:0] mac_tx_axis_tdata;
wire [N_CH*KEEP_WIDTH-1:0] mac_tx_axis_tkeep;
wire [N_CH-1:0] mac_tx_axis_tvalid;
wire [N_CH-1:0] mac_tx_axis_tready;
wire [N_CH-1:0] mac_tx_axis_tlast;
wire [N_CH*TX_USER_WIDTH-1:0] mac_tx_axis_tuser;
assign mac_clk[0] = mac_pll_clk_d64[4];
assign mac_clk[1] = mac_pll_clk_d64[10];
assign mac_1_clk = mac_clk[0];
assign mac_1_rst = mac_rst[0];
assign mac_ptp_tod = mac_ptp_time;
assign mac_ptp_tod[0*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_1_ptp_time;
assign mac_tx_ptp_ts = mac_ptp_ets;
assign mac_tx_ptp_ts_tag = mac_ptp_ets_fp;
assign mac_tx_ptp_ts_valid = mac_ptp_ets_valid;
assign mac_1_tx_ptp_ts = mac_ptp_ets[0*PTP_TS_WIDTH +: PTP_TS_WIDTH];
assign mac_1_tx_ptp_ts_tag = mac_ptp_ets_fp[0*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
assign mac_1_tx_ptp_ts_valid = mac_ptp_ets_valid[0];
assign mac_tx_status = mac_tx_lanes_stable;
assign mac_tx_pause = mac_tx_lfc_req;
assign mac_tx_pfc = mac_tx_pfc_req;
assign mac_tx_axis_tdata[0*DATA_WIDTH +: DATA_WIDTH] = mac_1_tx_axis_tdata;
assign mac_tx_axis_tkeep[0*KEEP_WIDTH +: KEEP_WIDTH] = mac_1_tx_axis_tkeep;
assign mac_tx_axis_tvalid[0] = mac_1_tx_axis_tvalid;
assign mac_1_tx_axis_tready = mac_tx_axis_tready[0];
assign mac_tx_axis_tlast[0] = mac_1_tx_axis_tlast;
assign mac_tx_axis_tuser[0*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_1_tx_axis_tuser;
assign mac_1_tx_status = mac_tx_lanes_stable[0*1 +: 1];
assign mac_tx_pause[0*1 +: 1] = mac_1_tx_lfc_req;
assign mac_tx_pfc[0*8 +: 8] = mac_1_tx_pfc_req;
assign mac_1_rx_axis_tdata = mac_rx_axis_tdata[0*DATA_WIDTH +: DATA_WIDTH];
assign mac_1_rx_axis_tkeep = mac_rx_axis_tkeep[0*KEEP_WIDTH +: KEEP_WIDTH];
assign mac_1_rx_axis_tvalid = mac_rx_axis_tvalid[0];
assign mac_1_rx_axis_tlast = mac_rx_axis_tlast[0];
assign mac_1_rx_axis_tuser = mac_rx_axis_tuser[0*RX_USER_WIDTH +: RX_USER_WIDTH];
assign mac_1_rx_status = mac_rx_pcs_ready[0*1 +: 1];
assign mac_1_rx_lfc_req = mac_rx_pause[0*1 +: 1];
assign mac_1_rx_pfc_req = mac_rx_pfc[0*8 +: 8];
assign mac_2_clk = mac_clk[1];
assign mac_2_rst = mac_rst[1];
assign mac_ptp_tod[1*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_2_ptp_time;
assign mac_2_tx_ptp_ts = mac_ptp_ets[1*PTP_TS_WIDTH +: PTP_TS_WIDTH];
assign mac_2_tx_ptp_ts_tag = mac_ptp_ets_fp[1*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
assign mac_2_tx_ptp_ts_valid = mac_ptp_ets_valid[1];
assign mac_tx_axis_tdata[1*DATA_WIDTH +: DATA_WIDTH] = mac_2_tx_axis_tdata;
assign mac_tx_axis_tkeep[1*KEEP_WIDTH +: KEEP_WIDTH] = mac_2_tx_axis_tkeep;
assign mac_tx_axis_tvalid[1] = mac_2_tx_axis_tvalid;
assign mac_2_tx_axis_tready = mac_tx_axis_tready[1];
assign mac_tx_axis_tlast[1] = mac_2_tx_axis_tlast;
assign mac_tx_axis_tuser[1*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_2_tx_axis_tuser;
assign mac_2_tx_status = mac_tx_lanes_stable[1*1 +: 1];
assign mac_tx_pause[1*1 +: 1] = mac_2_tx_lfc_req;
assign mac_tx_pfc[1*8 +: 8] = mac_2_tx_pfc_req;
assign mac_2_rx_axis_tdata = mac_rx_axis_tdata[1*DATA_WIDTH +: DATA_WIDTH];
assign mac_2_rx_axis_tkeep = mac_rx_axis_tkeep[1*KEEP_WIDTH +: KEEP_WIDTH];
assign mac_2_rx_axis_tvalid = mac_rx_axis_tvalid[1];
assign mac_2_rx_axis_tlast = mac_rx_axis_tlast[1];
assign mac_2_rx_axis_tuser = mac_rx_axis_tuser[1*RX_USER_WIDTH +: RX_USER_WIDTH];
assign mac_2_rx_status = mac_rx_pcs_ready[1*1 +: 1];
assign mac_2_rx_lfc_req = mac_rx_pause[1*1 +: 1];
assign mac_2_rx_pfc_req = mac_rx_pfc[1*8 +: 8];
assign mac_rx_status = mac_rx_pcs_ready;
assign mac_rx_lfc_req = mac_rx_pause;
assign mac_rx_pfc_req = mac_rx_pfc;
generate

458
fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v
View File

@ -446,68 +446,47 @@ pcie pcie_hip_inst (
.ninit_done(ninit_done)
);
// QSFP28 interfaces
// QSFP-DD interfaces
localparam QSFPDD_CNT = 2;
localparam CH_CNT = QSFPDD_CNT*2;
wire [CH_CNT-1:0] qsfpdd_mac_tx_clk;
wire [CH_CNT-1:0] qsfpdd_mac_tx_rst;
wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_tx_axis_tdata;
wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_tx_axis_tkeep;
wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tvalid;
wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tready;
wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tlast;
wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd_mac_tx_axis_tuser;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_time;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts;
wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts_tag;
wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_ts_valid;
wire [CH_CNT-1:0] qsfpdd_mac_tx_status;
wire [CH_CNT-1:0] qsfpdd_mac_tx_lfc_req;
wire [CH_CNT*8-1:0] qsfpdd_mac_tx_pfc_req;
wire [CH_CNT-1:0] qsfpdd_mac_rx_clk;
wire [CH_CNT-1:0] qsfpdd_mac_rx_rst;
wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_rx_axis_tdata;
wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_rx_axis_tkeep;
wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tvalid;
wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tlast;
wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd_mac_rx_axis_tuser;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_rx_ptp_time;
wire [CH_CNT-1:0] qsfpdd_mac_rx_status;
wire [CH_CNT-1:0] qsfpdd_mac_rx_lfc_req;
wire [CH_CNT*8-1:0] qsfpdd_mac_rx_pfc_req;
// QSFP-DD A
wire qsfpdda_mac_1_clk_int;
wire qsfpdda_mac_1_rst_int;
wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_1_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_1_tx_ptp_ts_int;
wire [PTP_TAG_WIDTH-1:0] qsfpdda_mac_1_tx_ptp_ts_tag_int;
wire qsfpdda_mac_1_tx_ptp_ts_valid_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_1_tx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_1_tx_axis_tkeep_int;
wire qsfpdda_mac_1_tx_axis_tvalid_int;
wire qsfpdda_mac_1_tx_axis_tready_int;
wire qsfpdda_mac_1_tx_axis_tlast_int;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_1_tx_axis_tuser_int;
wire qsfpdda_mac_1_tx_status_int;
wire qsfpdda_mac_1_tx_lfc_req_int;
wire [7:0] qsfpdda_mac_1_tx_pfc_req_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_1_rx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_1_rx_axis_tkeep_int;
wire qsfpdda_mac_1_rx_axis_tvalid_int;
wire qsfpdda_mac_1_rx_axis_tlast_int;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_1_rx_axis_tuser_int;
wire qsfpdda_mac_1_rx_status_int;
wire qsfpdda_mac_1_rx_lfc_req_int;
wire [7:0] qsfpdda_mac_1_rx_pfc_req_int;
wire qsfpdda_mac_2_clk_int;
wire qsfpdda_mac_2_rst_int;
wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_2_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_2_tx_ptp_ts_int;
wire [PTP_TAG_WIDTH-1:0] qsfpdda_mac_2_tx_ptp_ts_tag_int;
wire qsfpdda_mac_2_tx_ptp_ts_valid_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_2_tx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_2_tx_axis_tkeep_int;
wire qsfpdda_mac_2_tx_axis_tvalid_int;
wire qsfpdda_mac_2_tx_axis_tready_int;
wire qsfpdda_mac_2_tx_axis_tlast_int;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_2_tx_axis_tuser_int;
wire qsfpdda_mac_2_tx_status_int;
wire qsfpdda_mac_2_tx_lfc_req_int;
wire [7:0] qsfpdda_mac_2_tx_pfc_req_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_2_rx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_2_rx_axis_tkeep_int;
wire qsfpdda_mac_2_rx_axis_tvalid_int;
wire qsfpdda_mac_2_rx_axis_tlast_int;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_2_rx_axis_tuser_int;
wire qsfpdda_mac_2_rx_status_int;
wire qsfpdda_mac_2_rx_lfc_req_int;
wire [7:0] qsfpdda_mac_2_rx_pfc_req_int;
assign qsfpdd_mac_rx_clk[0*2 +: 2] = qsfpdd_mac_tx_clk[0*2 +: 2];
assign qsfpdd_mac_rx_rst[0*2 +: 2] = qsfpdd_mac_tx_rst[0*2 +: 2];
eth_mac_dual_wrapper #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
@ -527,127 +506,40 @@ qsfpdda_mac_inst (
// .rx_serial_data_n({qsfpdda_rx_n[7], qsfpdda_rx_n[5], qsfpdda_rx_n[6], qsfpdda_rx_n[4], qsfpdda_rx_n[3], qsfpdda_rx_n[1], qsfpdda_rx_n[2], qsfpdda_rx_n[0]}),
.ref_clk(qsfpddb_refclk_p),
.mac_1_clk(qsfpdda_mac_1_clk_int),
.mac_1_rst(qsfpdda_mac_1_rst_int),
.mac_clk(qsfpdd_mac_tx_clk[0*2 +: 2*1]),
.mac_rst(qsfpdd_mac_tx_rst[0*2 +: 2*1]),
.mac_1_ptp_time(qsfpdda_mac_1_ptp_time_int),
.mac_ptp_time(qsfpdd_mac_tx_ptp_time[0*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
.mac_1_tx_ptp_ts(qsfpdda_mac_1_tx_ptp_ts_int),
.mac_1_tx_ptp_ts_tag(qsfpdda_mac_1_tx_ptp_ts_tag_int),
.mac_1_tx_ptp_ts_valid(qsfpdda_mac_1_tx_ptp_ts_valid_int),
.mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[0*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
.mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[0*2*TX_TAG_WIDTH +: 2*TX_TAG_WIDTH]),
.mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[0*2 +: 2*1]),
.mac_1_tx_axis_tdata(qsfpdda_mac_1_tx_axis_tdata_int),
.mac_1_tx_axis_tkeep(qsfpdda_mac_1_tx_axis_tkeep_int),
.mac_1_tx_axis_tvalid(qsfpdda_mac_1_tx_axis_tvalid_int),
.mac_1_tx_axis_tready(qsfpdda_mac_1_tx_axis_tready_int),
.mac_1_tx_axis_tlast(qsfpdda_mac_1_tx_axis_tlast_int),
.mac_1_tx_axis_tuser(qsfpdda_mac_1_tx_axis_tuser_int),
.mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[0*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
.mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[0*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
.mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[0*2 +: 2*1]),
.mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[0*2 +: 2*1]),
.mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[0*2 +: 2*1]),
.mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[0*2*AXIS_ETH_TX_USER_WIDTH +: 2*AXIS_ETH_TX_USER_WIDTH]),
.mac_1_tx_status(qsfpdda_mac_1_tx_status_int),
.mac_1_tx_lfc_req(qsfpdda_mac_1_tx_lfc_req_int),
.mac_1_tx_pfc_req(qsfpdda_mac_1_tx_pfc_req_int),
.mac_tx_status(qsfpdd_mac_tx_status[0*2 +: 2*1]),
.mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[0*2 +: 2*1]),
.mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[0*2*8 +: 2*8]),
.mac_1_rx_axis_tdata(qsfpdda_mac_1_rx_axis_tdata_int),
.mac_1_rx_axis_tkeep(qsfpdda_mac_1_rx_axis_tkeep_int),
.mac_1_rx_axis_tvalid(qsfpdda_mac_1_rx_axis_tvalid_int),
.mac_1_rx_axis_tlast(qsfpdda_mac_1_rx_axis_tlast_int),
.mac_1_rx_axis_tuser(qsfpdda_mac_1_rx_axis_tuser_int),
.mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[0*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
.mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[0*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
.mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[0*2 +: 2*1]),
.mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[0*2 +: 2*1]),
.mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[0*2*AXIS_ETH_RX_USER_WIDTH +: 2*AXIS_ETH_RX_USER_WIDTH]),
.mac_1_rx_status(qsfpdda_mac_1_rx_status_int),
.mac_1_rx_lfc_req(qsfpdda_mac_1_rx_lfc_req_int),
.mac_1_rx_pfc_req(qsfpdda_mac_1_rx_pfc_req_int),
.mac_2_clk(qsfpdda_mac_2_clk_int),
.mac_2_rst(qsfpdda_mac_2_rst_int),
.mac_2_ptp_time(qsfpdda_mac_2_ptp_time_int),
.mac_2_tx_ptp_ts(qsfpdda_mac_2_tx_ptp_ts_int),
.mac_2_tx_ptp_ts_tag(qsfpdda_mac_2_tx_ptp_ts_tag_int),
.mac_2_tx_ptp_ts_valid(qsfpdda_mac_2_tx_ptp_ts_valid_int),
.mac_2_tx_axis_tdata(qsfpdda_mac_2_tx_axis_tdata_int),
.mac_2_tx_axis_tkeep(qsfpdda_mac_2_tx_axis_tkeep_int),
.mac_2_tx_axis_tvalid(qsfpdda_mac_2_tx_axis_tvalid_int),
.mac_2_tx_axis_tready(qsfpdda_mac_2_tx_axis_tready_int),
.mac_2_tx_axis_tlast(qsfpdda_mac_2_tx_axis_tlast_int),
.mac_2_tx_axis_tuser(qsfpdda_mac_2_tx_axis_tuser_int),
.mac_2_tx_status(qsfpdda_mac_2_tx_status_int),
.mac_2_tx_lfc_req(qsfpdda_mac_2_tx_lfc_req_int),
.mac_2_tx_pfc_req(qsfpdda_mac_2_tx_pfc_req_int),
.mac_2_rx_axis_tdata(qsfpdda_mac_2_rx_axis_tdata_int),
.mac_2_rx_axis_tkeep(qsfpdda_mac_2_rx_axis_tkeep_int),
.mac_2_rx_axis_tvalid(qsfpdda_mac_2_rx_axis_tvalid_int),
.mac_2_rx_axis_tlast(qsfpdda_mac_2_rx_axis_tlast_int),
.mac_2_rx_axis_tuser(qsfpdda_mac_2_rx_axis_tuser_int),
.mac_2_rx_status(qsfpdda_mac_2_rx_status_int),
.mac_2_rx_lfc_req(qsfpdda_mac_2_rx_lfc_req_int),
.mac_2_rx_pfc_req(qsfpdda_mac_2_rx_pfc_req_int)
.mac_rx_status(qsfpdd_mac_rx_status[0*2 +: 2*1]),
.mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[0*2 +: 2*1]),
.mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[0*2*8 +: 2*8])
);
// QSFP-DD B
wire qsfpddb_mac_1_clk_int;
wire qsfpddb_mac_1_rst_int;
wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_1_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_1_tx_ptp_ts_int;
wire [PTP_TAG_WIDTH-1:0] qsfpddb_mac_1_tx_ptp_ts_tag_int;
wire qsfpddb_mac_1_tx_ptp_ts_valid_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_1_tx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_1_tx_axis_tkeep_int;
wire qsfpddb_mac_1_tx_axis_tvalid_int;
wire qsfpddb_mac_1_tx_axis_tready_int;
wire qsfpddb_mac_1_tx_axis_tlast_int;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_1_tx_axis_tuser_int;
wire qsfpddb_mac_1_tx_status_int;
wire qsfpddb_mac_1_tx_lfc_req_int;
wire [7:0] qsfpddb_mac_1_tx_pfc_req_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_1_rx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_1_rx_axis_tkeep_int;
wire qsfpddb_mac_1_rx_axis_tvalid_int;
wire qsfpddb_mac_1_rx_axis_tlast_int;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_1_rx_axis_tuser_int;
wire qsfpddb_mac_1_rx_status_int;
wire qsfpddb_mac_1_rx_lfc_req_int;
wire [7:0] qsfpddb_mac_1_rx_pfc_req_int;
wire qsfpddb_mac_2_clk_int;
wire qsfpddb_mac_2_rst_int;
wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_2_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_2_tx_ptp_ts_int;
wire [PTP_TAG_WIDTH-1:0] qsfpddb_mac_2_tx_ptp_ts_tag_int;
wire qsfpddb_mac_2_tx_ptp_ts_valid_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_2_tx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_2_tx_axis_tkeep_int;
wire qsfpddb_mac_2_tx_axis_tvalid_int;
wire qsfpddb_mac_2_tx_axis_tready_int;
wire qsfpddb_mac_2_tx_axis_tlast_int;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_2_tx_axis_tuser_int;
wire qsfpddb_mac_2_tx_status_int;
wire qsfpddb_mac_2_tx_lfc_req_int;
wire [7:0] qsfpddb_mac_2_tx_pfc_req_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_2_rx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_2_rx_axis_tkeep_int;
wire qsfpddb_mac_2_rx_axis_tvalid_int;
wire qsfpddb_mac_2_rx_axis_tlast_int;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_2_rx_axis_tuser_int;
wire qsfpddb_mac_2_rx_status_int;
wire qsfpddb_mac_2_rx_lfc_req_int;
wire [7:0] qsfpddb_mac_2_rx_pfc_req_int;
assign qsfpdd_mac_rx_clk[1*2 +: 2] = qsfpdd_mac_tx_clk[1*2 +: 2];
assign qsfpdd_mac_rx_rst[1*2 +: 2] = qsfpdd_mac_tx_rst[1*2 +: 2];
eth_mac_dual_wrapper #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
@ -667,65 +559,35 @@ qsfpddb_mac_inst (
// .rx_serial_data_n({qsfpddb_rx_n[7], qsfpddb_rx_n[5], qsfpddb_rx_n[6], qsfpddb_rx_n[4], qsfpddb_rx_n[3], qsfpddb_rx_n[1], qsfpddb_rx_n[2], qsfpddb_rx_n[0]}),
.ref_clk(qsfpddb_refclk_p),
.mac_1_clk(qsfpddb_mac_1_clk_int),
.mac_1_rst(qsfpddb_mac_1_rst_int),
.mac_clk(qsfpdd_mac_tx_clk[1*2 +: 2*1]),
.mac_rst(qsfpdd_mac_tx_rst[1*2 +: 2*1]),
.mac_1_ptp_time(qsfpddb_mac_1_ptp_time_int),
.mac_ptp_time(qsfpdd_mac_tx_ptp_time[1*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
.mac_1_tx_ptp_ts(qsfpddb_mac_1_tx_ptp_ts_int),
.mac_1_tx_ptp_ts_tag(qsfpddb_mac_1_tx_ptp_ts_tag_int),
.mac_1_tx_ptp_ts_valid(qsfpddb_mac_1_tx_ptp_ts_valid_int),
.mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[1*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
.mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[1*2*TX_TAG_WIDTH +: 2*TX_TAG_WIDTH]),
.mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[1*2 +: 2*1]),
.mac_1_tx_axis_tdata(qsfpddb_mac_1_tx_axis_tdata_int),
.mac_1_tx_axis_tkeep(qsfpddb_mac_1_tx_axis_tkeep_int),
.mac_1_tx_axis_tvalid(qsfpddb_mac_1_tx_axis_tvalid_int),
.mac_1_tx_axis_tready(qsfpddb_mac_1_tx_axis_tready_int),
.mac_1_tx_axis_tlast(qsfpddb_mac_1_tx_axis_tlast_int),
.mac_1_tx_axis_tuser(qsfpddb_mac_1_tx_axis_tuser_int),
.mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[1*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
.mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[1*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
.mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[1*2 +: 2*1]),
.mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[1*2 +: 2*1]),
.mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[1*2 +: 2*1]),
.mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[1*2*AXIS_ETH_TX_USER_WIDTH +: 2*AXIS_ETH_TX_USER_WIDTH]),
.mac_1_tx_status(qsfpddb_mac_1_tx_status_int),
.mac_1_tx_lfc_req(qsfpddb_mac_1_tx_lfc_req_int),
.mac_1_tx_pfc_req(qsfpddb_mac_1_tx_pfc_req_int),
.mac_tx_status(qsfpdd_mac_tx_status[1*2 +: 2*1]),
.mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[1*2 +: 2*1]),
.mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[1*2*8 +: 2*8]),
.mac_1_rx_axis_tdata(qsfpddb_mac_1_rx_axis_tdata_int),
.mac_1_rx_axis_tkeep(qsfpddb_mac_1_rx_axis_tkeep_int),
.mac_1_rx_axis_tvalid(qsfpddb_mac_1_rx_axis_tvalid_int),
.mac_1_rx_axis_tlast(qsfpddb_mac_1_rx_axis_tlast_int),
.mac_1_rx_axis_tuser(qsfpddb_mac_1_rx_axis_tuser_int),
.mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[1*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
.mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[1*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
.mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[1*2 +: 2*1]),
.mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[1*2 +: 2*1]),
.mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[1*2*AXIS_ETH_RX_USER_WIDTH +: 2*AXIS_ETH_RX_USER_WIDTH]),
.mac_1_rx_status(qsfpddb_mac_1_rx_status_int),
.mac_1_rx_lfc_req(qsfpddb_mac_1_rx_lfc_req_int),
.mac_1_rx_pfc_req(qsfpddb_mac_1_rx_pfc_req_int),
.mac_2_clk(qsfpddb_mac_2_clk_int),
.mac_2_rst(qsfpddb_mac_2_rst_int),
.mac_2_ptp_time(qsfpddb_mac_2_ptp_time_int),
.mac_2_tx_ptp_ts(qsfpddb_mac_2_tx_ptp_ts_int),
.mac_2_tx_ptp_ts_tag(qsfpddb_mac_2_tx_ptp_ts_tag_int),
.mac_2_tx_ptp_ts_valid(qsfpddb_mac_2_tx_ptp_ts_valid_int),
.mac_2_tx_axis_tdata(qsfpddb_mac_2_tx_axis_tdata_int),
.mac_2_tx_axis_tkeep(qsfpddb_mac_2_tx_axis_tkeep_int),
.mac_2_tx_axis_tvalid(qsfpddb_mac_2_tx_axis_tvalid_int),
.mac_2_tx_axis_tready(qsfpddb_mac_2_tx_axis_tready_int),
.mac_2_tx_axis_tlast(qsfpddb_mac_2_tx_axis_tlast_int),
.mac_2_tx_axis_tuser(qsfpddb_mac_2_tx_axis_tuser_int),
.mac_2_tx_status(qsfpddb_mac_2_tx_status_int),
.mac_2_tx_lfc_req(qsfpddb_mac_2_tx_lfc_req_int),
.mac_2_tx_pfc_req(qsfpddb_mac_2_tx_pfc_req_int),
.mac_2_rx_axis_tdata(qsfpddb_mac_2_rx_axis_tdata_int),
.mac_2_rx_axis_tkeep(qsfpddb_mac_2_rx_axis_tkeep_int),
.mac_2_rx_axis_tvalid(qsfpddb_mac_2_rx_axis_tvalid_int),
.mac_2_rx_axis_tlast(qsfpddb_mac_2_rx_axis_tlast_int),
.mac_2_rx_axis_tuser(qsfpddb_mac_2_rx_axis_tuser_int),
.mac_2_rx_status(qsfpddb_mac_2_rx_status_int),
.mac_2_rx_lfc_req(qsfpddb_mac_2_rx_lfc_req_int),
.mac_2_rx_pfc_req(qsfpddb_mac_2_rx_pfc_req_int)
.mac_rx_status(qsfpdd_mac_rx_status[1*2 +: 2*1]),
.mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[1*2 +: 2*1]),
.mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[1*2*8 +: 2*8])
);
wire ptp_clk;
@ -734,8 +596,8 @@ wire ptp_sample_clk;
assign ptp_sample_clk = clk_100mhz;
assign ptp_clk = qsfpdda_mac_1_clk_int;
assign ptp_rst = qsfpdda_mac_1_rst_int;
assign ptp_clk = qsfpdd_mac_tx_clk[0];
assign ptp_rst = qsfpdd_mac_tx_rst[0];
fpga_core #(
// FW and board IDs
@ -748,6 +610,10 @@ fpga_core #(
.GIT_HASH(GIT_HASH),
.RELEASE_INFO(RELEASE_INFO),
// Board configuration
.QSFPDD_CNT(QSFPDD_CNT),
.CH_CNT(CH_CNT),
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
@ -929,65 +795,39 @@ core_inst (
/*
* Ethernet: QSFP-DD
*/
.qsfpdda_mac_1_clk(qsfpdda_mac_1_clk_int),
.qsfpdda_mac_1_rst(qsfpdda_mac_1_rst_int),
.qsfpdd_mac_tx_clk(qsfpdd_mac_tx_clk),
.qsfpdd_mac_tx_rst(qsfpdd_mac_tx_rst),
.qsfpdda_mac_1_ptp_time(qsfpdda_mac_1_ptp_time_int),
.qsfpdd_mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata),
.qsfpdd_mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep),
.qsfpdd_mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid),
.qsfpdd_mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready),
.qsfpdd_mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast),
.qsfpdd_mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser),
.qsfpdda_mac_1_tx_ptp_ts(qsfpdda_mac_1_tx_ptp_ts_int),
.qsfpdda_mac_1_tx_ptp_ts_tag(qsfpdda_mac_1_tx_ptp_ts_tag_int),
.qsfpdda_mac_1_tx_ptp_ts_valid(qsfpdda_mac_1_tx_ptp_ts_valid_int),
.qsfpdd_mac_tx_ptp_time(qsfpdd_mac_tx_ptp_time),
.qsfpdd_mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts),
.qsfpdd_mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag),
.qsfpdd_mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid),
.qsfpdda_mac_1_tx_axis_tdata(qsfpdda_mac_1_tx_axis_tdata_int),
.qsfpdda_mac_1_tx_axis_tkeep(qsfpdda_mac_1_tx_axis_tkeep_int),
.qsfpdda_mac_1_tx_axis_tvalid(qsfpdda_mac_1_tx_axis_tvalid_int),
.qsfpdda_mac_1_tx_axis_tready(qsfpdda_mac_1_tx_axis_tready_int),
.qsfpdda_mac_1_tx_axis_tlast(qsfpdda_mac_1_tx_axis_tlast_int),
.qsfpdda_mac_1_tx_axis_tuser(qsfpdda_mac_1_tx_axis_tuser_int),
.qsfpdd_mac_tx_status(qsfpdd_mac_tx_status),
.qsfpdd_mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req),
.qsfpdd_mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req),
.qsfpdda_mac_1_tx_status(qsfpdda_mac_1_tx_status_int),
.qsfpdda_mac_1_tx_lfc_req(qsfpdda_mac_1_tx_lfc_req_int),
.qsfpdda_mac_1_tx_pfc_req(qsfpdda_mac_1_tx_pfc_req_int),
.qsfpdd_mac_rx_clk(qsfpdd_mac_rx_clk),
.qsfpdd_mac_rx_rst(qsfpdd_mac_rx_rst),
.qsfpdda_mac_1_rx_axis_tdata(qsfpdda_mac_1_rx_axis_tdata_int),
.qsfpdda_mac_1_rx_axis_tkeep(qsfpdda_mac_1_rx_axis_tkeep_int),
.qsfpdda_mac_1_rx_axis_tvalid(qsfpdda_mac_1_rx_axis_tvalid_int),
.qsfpdda_mac_1_rx_axis_tlast(qsfpdda_mac_1_rx_axis_tlast_int),
.qsfpdda_mac_1_rx_axis_tuser(qsfpdda_mac_1_rx_axis_tuser_int),
.qsfpdd_mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata),
.qsfpdd_mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep),
.qsfpdd_mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid),
.qsfpdd_mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast),
.qsfpdd_mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser),
.qsfpdda_mac_1_rx_status(qsfpdda_mac_1_rx_status_int),
.qsfpdda_mac_1_rx_lfc_req(qsfpdda_mac_1_rx_lfc_req_int),
.qsfpdda_mac_1_rx_pfc_req(qsfpdda_mac_1_rx_pfc_req_int),
.qsfpdd_mac_rx_ptp_time(qsfpdd_mac_rx_ptp_time),
.qsfpdda_mac_2_clk(qsfpdda_mac_2_clk_int),
.qsfpdda_mac_2_rst(qsfpdda_mac_2_rst_int),
.qsfpdda_mac_2_ptp_time(qsfpdda_mac_2_ptp_time_int),
.qsfpdda_mac_2_tx_ptp_ts(qsfpdda_mac_2_tx_ptp_ts_int),
.qsfpdda_mac_2_tx_ptp_ts_tag(qsfpdda_mac_2_tx_ptp_ts_tag_int),
.qsfpdda_mac_2_tx_ptp_ts_valid(qsfpdda_mac_2_tx_ptp_ts_valid_int),
.qsfpdda_mac_2_tx_axis_tdata(qsfpdda_mac_2_tx_axis_tdata_int),
.qsfpdda_mac_2_tx_axis_tkeep(qsfpdda_mac_2_tx_axis_tkeep_int),
.qsfpdda_mac_2_tx_axis_tvalid(qsfpdda_mac_2_tx_axis_tvalid_int),
.qsfpdda_mac_2_tx_axis_tready(qsfpdda_mac_2_tx_axis_tready_int),
.qsfpdda_mac_2_tx_axis_tlast(qsfpdda_mac_2_tx_axis_tlast_int),
.qsfpdda_mac_2_tx_axis_tuser(qsfpdda_mac_2_tx_axis_tuser_int),
.qsfpdda_mac_2_tx_status(qsfpdda_mac_2_tx_status_int),
.qsfpdda_mac_2_tx_lfc_req(qsfpdda_mac_2_tx_lfc_req_int),
.qsfpdda_mac_2_tx_pfc_req(qsfpdda_mac_2_tx_pfc_req_int),
.qsfpdda_mac_2_rx_axis_tdata(qsfpdda_mac_2_rx_axis_tdata_int),
.qsfpdda_mac_2_rx_axis_tkeep(qsfpdda_mac_2_rx_axis_tkeep_int),
.qsfpdda_mac_2_rx_axis_tvalid(qsfpdda_mac_2_rx_axis_tvalid_int),
.qsfpdda_mac_2_rx_axis_tlast(qsfpdda_mac_2_rx_axis_tlast_int),
.qsfpdda_mac_2_rx_axis_tuser(qsfpdda_mac_2_rx_axis_tuser_int),
.qsfpdda_mac_2_rx_status(qsfpdda_mac_2_rx_status_int),
.qsfpdda_mac_2_rx_lfc_req(qsfpdda_mac_2_rx_lfc_req_int),
.qsfpdda_mac_2_rx_pfc_req(qsfpdda_mac_2_rx_pfc_req_int),
.qsfpdd_mac_rx_status(qsfpdd_mac_rx_status),
.qsfpdd_mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req),
.qsfpdd_mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req),
.qsfpdda_initmode(qsfpdda_initmode),
.qsfpdda_interrupt_n(qsfpdda_interrupt_n_int),
@ -1001,66 +841,6 @@ core_inst (
.qsfpdda_sda_o(qsfpdda_sda_o),
.qsfpdda_sda_t(qsfpdda_sda_t),
.qsfpddb_mac_1_clk(qsfpddb_mac_1_clk_int),
.qsfpddb_mac_1_rst(qsfpddb_mac_1_rst_int),
.qsfpddb_mac_1_ptp_time(qsfpddb_mac_1_ptp_time_int),
.qsfpddb_mac_1_tx_ptp_ts(qsfpddb_mac_1_tx_ptp_ts_int),
.qsfpddb_mac_1_tx_ptp_ts_tag(qsfpddb_mac_1_tx_ptp_ts_tag_int),
.qsfpddb_mac_1_tx_ptp_ts_valid(qsfpddb_mac_1_tx_ptp_ts_valid_int),
.qsfpddb_mac_1_tx_axis_tdata(qsfpddb_mac_1_tx_axis_tdata_int),
.qsfpddb_mac_1_tx_axis_tkeep(qsfpddb_mac_1_tx_axis_tkeep_int),
.qsfpddb_mac_1_tx_axis_tvalid(qsfpddb_mac_1_tx_axis_tvalid_int),
.qsfpddb_mac_1_tx_axis_tready(qsfpddb_mac_1_tx_axis_tready_int),
.qsfpddb_mac_1_tx_axis_tlast(qsfpddb_mac_1_tx_axis_tlast_int),
.qsfpddb_mac_1_tx_axis_tuser(qsfpddb_mac_1_tx_axis_tuser_int),
.qsfpddb_mac_1_tx_status(qsfpddb_mac_1_tx_status_int),
.qsfpddb_mac_1_tx_lfc_req(qsfpddb_mac_1_tx_lfc_req_int),
.qsfpddb_mac_1_tx_pfc_req(qsfpddb_mac_1_tx_pfc_req_int),
.qsfpddb_mac_1_rx_axis_tdata(qsfpddb_mac_1_rx_axis_tdata_int),
.qsfpddb_mac_1_rx_axis_tkeep(qsfpddb_mac_1_rx_axis_tkeep_int),
.qsfpddb_mac_1_rx_axis_tvalid(qsfpddb_mac_1_rx_axis_tvalid_int),
.qsfpddb_mac_1_rx_axis_tlast(qsfpddb_mac_1_rx_axis_tlast_int),
.qsfpddb_mac_1_rx_axis_tuser(qsfpddb_mac_1_rx_axis_tuser_int),
.qsfpddb_mac_1_rx_status(qsfpddb_mac_1_rx_status_int),
.qsfpddb_mac_1_rx_lfc_req(qsfpddb_mac_1_rx_lfc_req_int),
.qsfpddb_mac_1_rx_pfc_req(qsfpddb_mac_1_rx_pfc_req_int),
.qsfpddb_mac_2_clk(qsfpddb_mac_2_clk_int),
.qsfpddb_mac_2_rst(qsfpddb_mac_2_rst_int),
.qsfpddb_mac_2_ptp_time(qsfpddb_mac_2_ptp_time_int),
.qsfpddb_mac_2_tx_ptp_ts(qsfpddb_mac_2_tx_ptp_ts_int),
.qsfpddb_mac_2_tx_ptp_ts_tag(qsfpddb_mac_2_tx_ptp_ts_tag_int),
.qsfpddb_mac_2_tx_ptp_ts_valid(qsfpddb_mac_2_tx_ptp_ts_valid_int),
.qsfpddb_mac_2_tx_axis_tdata(qsfpddb_mac_2_tx_axis_tdata_int),
.qsfpddb_mac_2_tx_axis_tkeep(qsfpddb_mac_2_tx_axis_tkeep_int),
.qsfpddb_mac_2_tx_axis_tvalid(qsfpddb_mac_2_tx_axis_tvalid_int),
.qsfpddb_mac_2_tx_axis_tready(qsfpddb_mac_2_tx_axis_tready_int),
.qsfpddb_mac_2_tx_axis_tlast(qsfpddb_mac_2_tx_axis_tlast_int),
.qsfpddb_mac_2_tx_axis_tuser(qsfpddb_mac_2_tx_axis_tuser_int),
.qsfpddb_mac_2_tx_status(qsfpddb_mac_2_tx_status_int),
.qsfpddb_mac_2_tx_lfc_req(qsfpddb_mac_2_tx_lfc_req_int),
.qsfpddb_mac_2_tx_pfc_req(qsfpddb_mac_2_tx_pfc_req_int),
.qsfpddb_mac_2_rx_axis_tdata(qsfpddb_mac_2_rx_axis_tdata_int),
.qsfpddb_mac_2_rx_axis_tkeep(qsfpddb_mac_2_rx_axis_tkeep_int),
.qsfpddb_mac_2_rx_axis_tvalid(qsfpddb_mac_2_rx_axis_tvalid_int),
.qsfpddb_mac_2_rx_axis_tlast(qsfpddb_mac_2_rx_axis_tlast_int),
.qsfpddb_mac_2_rx_axis_tuser(qsfpddb_mac_2_rx_axis_tuser_int),
.qsfpddb_mac_2_rx_status(qsfpddb_mac_2_rx_status_int),
.qsfpddb_mac_2_rx_lfc_req(qsfpddb_mac_2_rx_lfc_req_int),
.qsfpddb_mac_2_rx_pfc_req(qsfpddb_mac_2_rx_pfc_req_int),
.qsfpddb_initmode(qsfpddb_initmode),
.qsfpddb_interrupt_n(qsfpddb_interrupt_n_int),
.qsfpddb_mod_prs_n(qsfpddb_mod_prs_n_int),

214
fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v
View File

@ -24,6 +24,10 @@ module fpga_core #
parameter GIT_HASH = 32'hdce357bf,
parameter RELEASE_INFO = 32'h00000000,
// Board configuration
parameter QSFPDD_CNT = 2,
parameter CH_CNT = QSFPDD_CNT*2,
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
@ -205,65 +209,39 @@ module fpga_core #
/*
* Ethernet: QSFP-DD
*/
input wire qsfpdda_mac_1_clk,
input wire qsfpdda_mac_1_rst,
input wire [CH_CNT-1:0] qsfpdd_mac_tx_clk,
input wire [CH_CNT-1:0] qsfpdd_mac_tx_rst,
output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_1_ptp_time,
output wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_tx_axis_tdata,
output wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_tx_axis_tkeep,
output wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tvalid,
input wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tready,
output wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tlast,
output wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd_mac_tx_axis_tuser,
input wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_1_tx_ptp_ts,
input wire [TX_TAG_WIDTH-1:0] qsfpdda_mac_1_tx_ptp_ts_tag,
input wire qsfpdda_mac_1_tx_ptp_ts_valid,
output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_time,
input wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts,
input wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts_tag,
input wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_ts_valid,
output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_1_tx_axis_tdata,
output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_1_tx_axis_tkeep,
output wire qsfpdda_mac_1_tx_axis_tvalid,
input wire qsfpdda_mac_1_tx_axis_tready,
output wire qsfpdda_mac_1_tx_axis_tlast,
output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_1_tx_axis_tuser,
input wire [CH_CNT-1:0] qsfpdd_mac_tx_status,
output wire [CH_CNT-1:0] qsfpdd_mac_tx_lfc_req,
output wire [CH_CNT*8-1:0] qsfpdd_mac_tx_pfc_req,
input wire qsfpdda_mac_1_tx_status,
output wire qsfpdda_mac_1_tx_lfc_req,
output wire [7:0] qsfpdda_mac_1_tx_pfc_req,
input wire [CH_CNT-1:0] qsfpdd_mac_rx_clk,
input wire [CH_CNT-1:0] qsfpdd_mac_rx_rst,
input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_1_rx_axis_tdata,
input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_1_rx_axis_tkeep,
input wire qsfpdda_mac_1_rx_axis_tvalid,
input wire qsfpdda_mac_1_rx_axis_tlast,
input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_1_rx_axis_tuser,
input wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_rx_axis_tdata,
input wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_rx_axis_tkeep,
input wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tvalid,
input wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tlast,
input wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd_mac_rx_axis_tuser,
input wire qsfpdda_mac_1_rx_status,
input wire qsfpdda_mac_1_rx_lfc_req,
input wire [7:0] qsfpdda_mac_1_rx_pfc_req,
output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_rx_ptp_time,
input wire qsfpdda_mac_2_clk,
input wire qsfpdda_mac_2_rst,
output wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_2_ptp_time,
input wire [PTP_TS_WIDTH-1:0] qsfpdda_mac_2_tx_ptp_ts,
input wire [TX_TAG_WIDTH-1:0] qsfpdda_mac_2_tx_ptp_ts_tag,
input wire qsfpdda_mac_2_tx_ptp_ts_valid,
output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_2_tx_axis_tdata,
output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_2_tx_axis_tkeep,
output wire qsfpdda_mac_2_tx_axis_tvalid,
input wire qsfpdda_mac_2_tx_axis_tready,
output wire qsfpdda_mac_2_tx_axis_tlast,
output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdda_mac_2_tx_axis_tuser,
input wire qsfpdda_mac_2_tx_status,
output wire qsfpdda_mac_2_tx_lfc_req,
output wire [7:0] qsfpdda_mac_2_tx_pfc_req,
input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdda_mac_2_rx_axis_tdata,
input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdda_mac_2_rx_axis_tkeep,
input wire qsfpdda_mac_2_rx_axis_tvalid,
input wire qsfpdda_mac_2_rx_axis_tlast,
input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdda_mac_2_rx_axis_tuser,
input wire qsfpdda_mac_2_rx_status,
input wire qsfpdda_mac_2_rx_lfc_req,
input wire [7:0] qsfpdda_mac_2_rx_pfc_req,
input wire [CH_CNT-1:0] qsfpdd_mac_rx_status,
input wire [CH_CNT-1:0] qsfpdd_mac_rx_lfc_req,
input wire [CH_CNT*8-1:0] qsfpdd_mac_rx_pfc_req,
output wire qsfpdda_initmode,
input wire qsfpdda_interrupt_n,
@ -277,66 +255,6 @@ module fpga_core #
output wire qsfpdda_sda_o,
output wire qsfpdda_sda_t,
input wire qsfpddb_mac_1_clk,
input wire qsfpddb_mac_1_rst,
output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_1_ptp_time,
input wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_1_tx_ptp_ts,
input wire [TX_TAG_WIDTH-1:0] qsfpddb_mac_1_tx_ptp_ts_tag,
input wire qsfpddb_mac_1_tx_ptp_ts_valid,
output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_1_tx_axis_tdata,
output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_1_tx_axis_tkeep,
output wire qsfpddb_mac_1_tx_axis_tvalid,
input wire qsfpddb_mac_1_tx_axis_tready,
output wire qsfpddb_mac_1_tx_axis_tlast,
output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_1_tx_axis_tuser,
input wire qsfpddb_mac_1_tx_status,
output wire qsfpddb_mac_1_tx_lfc_req,
output wire [7:0] qsfpddb_mac_1_tx_pfc_req,
input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_1_rx_axis_tdata,
input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_1_rx_axis_tkeep,
input wire qsfpddb_mac_1_rx_axis_tvalid,
input wire qsfpddb_mac_1_rx_axis_tlast,
input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_1_rx_axis_tuser,
input wire qsfpddb_mac_1_rx_status,
input wire qsfpddb_mac_1_rx_lfc_req,
input wire [7:0] qsfpddb_mac_1_rx_pfc_req,
input wire qsfpddb_mac_2_clk,
input wire qsfpddb_mac_2_rst,
output wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_2_ptp_time,
input wire [PTP_TS_WIDTH-1:0] qsfpddb_mac_2_tx_ptp_ts,
input wire [TX_TAG_WIDTH-1:0] qsfpddb_mac_2_tx_ptp_ts_tag,
input wire qsfpddb_mac_2_tx_ptp_ts_valid,
output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_2_tx_axis_tdata,
output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_2_tx_axis_tkeep,
output wire qsfpddb_mac_2_tx_axis_tvalid,
input wire qsfpddb_mac_2_tx_axis_tready,
output wire qsfpddb_mac_2_tx_axis_tlast,
output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpddb_mac_2_tx_axis_tuser,
input wire qsfpddb_mac_2_tx_status,
output wire qsfpddb_mac_2_tx_lfc_req,
output wire [7:0] qsfpddb_mac_2_tx_pfc_req,
input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpddb_mac_2_rx_axis_tdata,
input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpddb_mac_2_rx_axis_tkeep,
input wire qsfpddb_mac_2_rx_axis_tvalid,
input wire qsfpddb_mac_2_rx_axis_tlast,
input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpddb_mac_2_rx_axis_tuser,
input wire qsfpddb_mac_2_rx_status,
input wire qsfpddb_mac_2_rx_lfc_req,
input wire [7:0] qsfpddb_mac_2_rx_pfc_req,
output wire qsfpddb_initmode,
input wire qsfpddb_interrupt_n,
input wire qsfpddb_mod_prs_n,
@ -362,7 +280,7 @@ localparam RB_BASE_ADDR = 16'h1000;
localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}};
initial begin
if (PORT_COUNT > 4) begin
if (PORT_COUNT > CH_CNT) begin
$error("Error: Max port count exceeded (instance %m)");
$finish;
end
@ -577,13 +495,13 @@ always @(posedge clk_250mhz) begin
end
end
assign led[0] = !qsfpdda_mac_1_rx_status;
assign led[1] = !qsfpddb_mac_1_rx_status;
assign led[0] = 1'b1;
assign led[1] = 1'b1;
assign led[2] = 1'b1;
assign led[3] = !ptp_pps_str;
assign led_bracket[0] = !qsfpdda_mac_1_rx_status;
assign led_bracket[1] = !qsfpddb_mac_1_rx_status;
assign led_bracket[0] = 1'b1;
assign led_bracket[1] = 1'b1;
assign led_bracket[2] = 1'b1;
assign led_bracket[3] = !ptp_pps_str;
@ -627,7 +545,7 @@ wire [PORT_COUNT*AXIS_ETH_RX_USER_WIDTH-1:0] axis_eth_rx_tuser;
wire [PORT_COUNT-1:0] eth_rx_status;
mqnic_port_map_mac_axis #(
.MAC_COUNT(4),
.MAC_COUNT(CH_CNT),
.PORT_MASK(PORT_MASK),
.PORT_GROUP_SIZE(2),
@ -645,55 +563,55 @@ mqnic_port_map_mac_axis #(
)
mqnic_port_map_mac_axis_inst (
// towards MAC
.mac_tx_clk({qsfpddb_mac_2_clk, qsfpddb_mac_1_clk, qsfpdda_mac_2_clk, qsfpdda_mac_1_clk}),
.mac_tx_rst({qsfpddb_mac_2_rst, qsfpddb_mac_1_rst, qsfpdda_mac_2_rst, qsfpdda_mac_1_rst}),
.mac_tx_clk(qsfpdd_mac_tx_clk),
.mac_tx_rst(qsfpdd_mac_tx_rst),
.mac_tx_ptp_clk({qsfpddb_mac_2_clk, qsfpddb_mac_1_clk, qsfpdda_mac_2_clk, qsfpdda_mac_1_clk}),
.mac_tx_ptp_rst({qsfpddb_mac_2_rst, qsfpddb_mac_1_rst, qsfpdda_mac_2_rst, qsfpdda_mac_1_rst}),
.mac_tx_ptp_ts_96({qsfpddb_mac_2_ptp_time, qsfpddb_mac_1_ptp_time, qsfpdda_mac_2_ptp_time, qsfpdda_mac_1_ptp_time}),
.mac_tx_ptp_clk(qsfpdd_mac_tx_clk),
.mac_tx_ptp_rst(qsfpdd_mac_tx_rst),
.mac_tx_ptp_ts_96(qsfpdd_mac_tx_ptp_time),
.mac_tx_ptp_ts_step(),
.m_axis_mac_tx_tdata({qsfpddb_mac_2_tx_axis_tdata, qsfpddb_mac_1_tx_axis_tdata, qsfpdda_mac_2_tx_axis_tdata, qsfpdda_mac_1_tx_axis_tdata}),
.m_axis_mac_tx_tkeep({qsfpddb_mac_2_tx_axis_tkeep, qsfpddb_mac_1_tx_axis_tkeep, qsfpdda_mac_2_tx_axis_tkeep, qsfpdda_mac_1_tx_axis_tkeep}),
.m_axis_mac_tx_tvalid({qsfpddb_mac_2_tx_axis_tvalid, qsfpddb_mac_1_tx_axis_tvalid, qsfpdda_mac_2_tx_axis_tvalid, qsfpdda_mac_1_tx_axis_tvalid}),
.m_axis_mac_tx_tready({qsfpddb_mac_2_tx_axis_tready, qsfpddb_mac_1_tx_axis_tready, qsfpdda_mac_2_tx_axis_tready, qsfpdda_mac_1_tx_axis_tready}),
.m_axis_mac_tx_tlast({qsfpddb_mac_2_tx_axis_tlast, qsfpddb_mac_1_tx_axis_tlast, qsfpdda_mac_2_tx_axis_tlast, qsfpdda_mac_1_tx_axis_tlast}),
.m_axis_mac_tx_tuser({qsfpddb_mac_2_tx_axis_tuser, qsfpddb_mac_1_tx_axis_tuser, qsfpdda_mac_2_tx_axis_tuser, qsfpdda_mac_1_tx_axis_tuser}),
.m_axis_mac_tx_tdata(qsfpdd_mac_tx_axis_tdata),
.m_axis_mac_tx_tkeep(qsfpdd_mac_tx_axis_tkeep),
.m_axis_mac_tx_tvalid(qsfpdd_mac_tx_axis_tvalid),
.m_axis_mac_tx_tready(qsfpdd_mac_tx_axis_tready),
.m_axis_mac_tx_tlast(qsfpdd_mac_tx_axis_tlast),
.m_axis_mac_tx_tuser(qsfpdd_mac_tx_axis_tuser),
.s_axis_mac_tx_ptp_ts({qsfpddb_mac_2_tx_ptp_ts, qsfpddb_mac_1_tx_ptp_ts, qsfpdda_mac_2_tx_ptp_ts, qsfpdda_mac_1_tx_ptp_ts}),
.s_axis_mac_tx_ptp_ts_tag({qsfpddb_mac_2_tx_ptp_ts_tag, qsfpddb_mac_1_tx_ptp_ts_tag, qsfpdda_mac_2_tx_ptp_ts_tag, qsfpdda_mac_1_tx_ptp_ts_tag}),
.s_axis_mac_tx_ptp_ts_valid({qsfpddb_mac_2_tx_ptp_ts_valid, qsfpddb_mac_1_tx_ptp_ts_valid, qsfpdda_mac_2_tx_ptp_ts_valid, qsfpdda_mac_1_tx_ptp_ts_valid}),
.s_axis_mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts),
.s_axis_mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag),
.s_axis_mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid),
.s_axis_mac_tx_ptp_ts_ready(),
.mac_tx_enable(),
.mac_tx_status({qsfpddb_mac_2_tx_status, qsfpddb_mac_1_tx_status, qsfpdda_mac_2_tx_status, qsfpdda_mac_1_tx_status}),
.mac_tx_status(qsfpdd_mac_tx_status),
.mac_tx_lfc_en(),
.mac_tx_lfc_req({qsfpddb_mac_2_tx_lfc_req, qsfpddb_mac_1_tx_lfc_req, qsfpdda_mac_2_tx_lfc_req, qsfpdda_mac_1_tx_lfc_req}),
.mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req),
.mac_tx_pfc_en(),
.mac_tx_pfc_req({qsfpddb_mac_2_tx_pfc_req, qsfpddb_mac_1_tx_pfc_req, qsfpdda_mac_2_tx_pfc_req, qsfpdda_mac_1_tx_pfc_req}),
.mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req),
.mac_rx_clk({qsfpddb_mac_2_clk, qsfpddb_mac_1_clk, qsfpdda_mac_2_clk, qsfpdda_mac_1_clk}),
.mac_rx_rst({qsfpddb_mac_2_rst, qsfpddb_mac_1_rst, qsfpdda_mac_2_rst, qsfpdda_mac_1_rst}),
.mac_rx_clk(qsfpdd_mac_rx_clk),
.mac_rx_rst(qsfpdd_mac_rx_rst),
.mac_rx_ptp_clk({qsfpddb_mac_2_clk, qsfpddb_mac_1_clk, qsfpdda_mac_2_clk, qsfpdda_mac_1_clk}),
.mac_rx_ptp_rst({qsfpddb_mac_2_rst, qsfpddb_mac_1_rst, qsfpdda_mac_2_rst, qsfpdda_mac_1_rst}),
.mac_rx_ptp_ts_96(),
.mac_rx_ptp_clk(qsfpdd_mac_rx_clk),
.mac_rx_ptp_rst(qsfpdd_mac_rx_rst),
.mac_rx_ptp_ts_96(qsfpdd_mac_rx_ptp_time),
.mac_rx_ptp_ts_step(),
.s_axis_mac_rx_tdata({qsfpddb_mac_2_rx_axis_tdata, qsfpddb_mac_1_rx_axis_tdata, qsfpdda_mac_2_rx_axis_tdata, qsfpdda_mac_1_rx_axis_tdata}),
.s_axis_mac_rx_tkeep({qsfpddb_mac_2_rx_axis_tkeep, qsfpddb_mac_1_rx_axis_tkeep, qsfpdda_mac_2_rx_axis_tkeep, qsfpdda_mac_1_rx_axis_tkeep}),
.s_axis_mac_rx_tvalid({qsfpddb_mac_2_rx_axis_tvalid, qsfpddb_mac_1_rx_axis_tvalid, qsfpdda_mac_2_rx_axis_tvalid, qsfpdda_mac_1_rx_axis_tvalid}),
.s_axis_mac_rx_tdata(qsfpdd_mac_rx_axis_tdata),
.s_axis_mac_rx_tkeep(qsfpdd_mac_rx_axis_tkeep),
.s_axis_mac_rx_tvalid(qsfpdd_mac_rx_axis_tvalid),
.s_axis_mac_rx_tready(),
.s_axis_mac_rx_tlast({qsfpddb_mac_2_rx_axis_tlast, qsfpddb_mac_1_rx_axis_tlast, qsfpdda_mac_2_rx_axis_tlast, qsfpdda_mac_1_rx_axis_tlast}),
.s_axis_mac_rx_tuser({qsfpddb_mac_2_rx_axis_tuser, qsfpddb_mac_1_rx_axis_tuser, qsfpdda_mac_2_rx_axis_tuser, qsfpdda_mac_1_rx_axis_tuser}),
.s_axis_mac_rx_tlast(qsfpdd_mac_rx_axis_tlast),
.s_axis_mac_rx_tuser(qsfpdd_mac_rx_axis_tuser),
.mac_rx_enable(),
.mac_rx_status({qsfpddb_mac_2_rx_status, qsfpddb_mac_1_rx_status, qsfpdda_mac_2_rx_status, qsfpdda_mac_1_rx_status}),
.mac_rx_status(qsfpdd_mac_rx_status),
.mac_rx_lfc_en(),
.mac_rx_lfc_req({qsfpddb_mac_2_rx_lfc_req, qsfpddb_mac_1_rx_lfc_req, qsfpdda_mac_2_rx_lfc_req, qsfpdda_mac_1_rx_lfc_req}),
.mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req),
.mac_rx_lfc_ack(),
.mac_rx_pfc_en(),
.mac_rx_pfc_req({qsfpddb_mac_2_rx_pfc_req, qsfpddb_mac_1_rx_pfc_req, qsfpdda_mac_2_rx_pfc_req, qsfpdda_mac_1_rx_pfc_req}),
.mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req),
.mac_rx_pfc_ack(),
// towards datapath

3
fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/Makefile
View File

@ -10,8 +10,9 @@ COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
DUT = fpga_core
TOPLEVEL = $(DUT)
TOPLEVEL = test_$(DUT)
MODULE = test_$(DUT)
VERILOG_SOURCES += $(TOPLEVEL).v
VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_ptile.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v

94
fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -245,9 +245,9 @@ class TB(object):
self.driver = mqnic.Driver()
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
self.dev.functions[0].configure_bar(0, 2**len(dut.uut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.uut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.uut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 2.482, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
@ -256,38 +256,40 @@ class TB(object):
# Ethernet
self.qsfpdd_mac = []
for x in "ab":
macs = []
for y in range(1, 3):
cocotb.start_soon(Clock(getattr(dut, f"qsfpdd{x}_mac_{y}_clk"), 2.482, units="ns").start())
for ch in self.dut.ch:
cocotb.start_soon(Clock(ch.ch_mac_tx_clk, 2.482, units="ns").start())
cocotb.start_soon(Clock(ch.ch_mac_rx_clk, 2.482, units="ns").start())
mac = EthMac(
tx_clk=getattr(dut, f"qsfpdd{x}_mac_{y}_clk"),
tx_rst=getattr(dut, f"qsfpdd{x}_mac_{y}_rst"),
tx_bus=AxiStreamBus.from_prefix(dut, f"qsfpdd{x}_mac_{y}_tx_axis"),
tx_ptp_time=getattr(dut, f"qsfpdd{x}_mac_{y}_ptp_time"),
tx_ptp_ts=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_ptp_ts"),
tx_ptp_ts_tag=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_ptp_ts_tag"),
tx_ptp_ts_valid=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_ptp_ts_valid"),
rx_clk=getattr(dut, f"qsfpdd{x}_mac_{y}_clk"),
rx_rst=getattr(dut, f"qsfpdd{x}_mac_{y}_rst"),
rx_bus=AxiStreamBus.from_prefix(dut, f"qsfpdd{x}_mac_{y}_rx_axis"),
rx_ptp_time=getattr(dut, f"qsfpdd{x}_mac_{y}_ptp_time"),
tx_clk=ch.ch_mac_tx_clk,
tx_rst=ch.ch_mac_tx_rst,
tx_bus=AxiStreamBus.from_prefix(ch, "ch_mac_tx_axis"),
tx_ptp_time=ch.ch_mac_tx_ptp_time,
tx_ptp_ts=ch.ch_mac_tx_ptp_ts,
tx_ptp_ts_tag=ch.ch_mac_tx_ptp_ts_tag,
tx_ptp_ts_valid=ch.ch_mac_tx_ptp_ts_valid,
rx_clk=ch.ch_mac_rx_clk,
rx_rst=ch.ch_mac_rx_rst,
rx_bus=AxiStreamBus.from_prefix(ch, "ch_mac_rx_axis"),
rx_ptp_time=ch.ch_mac_rx_ptp_time,
ifg=12, speed=100e9
)
macs.append(mac)
ch.ch_mac_rx_status.setimmediatevalue(1)
ch.ch_mac_rx_lfc_req.setimmediatevalue(0)
ch.ch_mac_rx_pfc_req.setimmediatevalue(0)
getattr(dut, f"qsfpdd{x}_mac_{y}_rx_status").setimmediatevalue(1)
getattr(dut, f"qsfpdd{x}_mac_{y}_rx_lfc_req").setimmediatevalue(0)
getattr(dut, f"qsfpdd{x}_mac_{y}_rx_pfc_req").setimmediatevalue(0)
self.qsfpdd_mac.append(mac)
self.qsfpdd_mac.append(macs)
dut.qsfpdda_interrupt_n.setimmediatevalue(1)
dut.qsfpdda_mod_prs_n.setimmediatevalue(0)
dut.qsfpdda_scl_i.setimmediatevalue(1)
dut.qsfpdda_sda_i.setimmediatevalue(1)
getattr(dut, f"qsfpdd{x}_interrupt_n").setimmediatevalue(1)
getattr(dut, f"qsfpdd{x}_mod_prs_n").setimmediatevalue(0)
getattr(dut, f"qsfpdd{x}_scl_i").setimmediatevalue(1)
getattr(dut, f"qsfpdd{x}_sda_i").setimmediatevalue(1)
dut.qsfpddb_interrupt_n.setimmediatevalue(1)
dut.qsfpddb_mod_prs_n.setimmediatevalue(0)
dut.qsfpddb_scl_i.setimmediatevalue(1)
dut.qsfpddb_sda_i.setimmediatevalue(1)
dut.button.setimmediatevalue(0)
dut.sw.setimmediatevalue(0)
@ -300,17 +302,17 @@ class TB(object):
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
for x in "ab":
for y in range(1, 3):
getattr(self.dut, f"qsfpdd{x}_mac_{y}_rst").setimmediatevalue(0)
for ch in self.dut.ch:
ch.ch_mac_tx_rst.setimmediatevalue(0)
ch.ch_mac_rx_rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
for x in "ab":
for y in range(1, 3):
getattr(self.dut, f"qsfpdd{x}_mac_{y}_rst").setimmediatevalue(1)
for ch in self.dut.ch:
ch.ch_mac_tx_rst.setimmediatevalue(1)
ch.ch_mac_rx_rst.setimmediatevalue(1)
await FallingEdge(self.dut.rst_250mhz)
await Timer(100, 'ns')
@ -319,9 +321,9 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
for x in "ab":
for y in range(1, 3):
getattr(self.dut, f"qsfpdd{x}_mac_{y}_rst").setimmediatevalue(0)
for ch in self.dut.ch:
ch.ch_mac_tx_rst.setimmediatevalue(0)
ch.ch_mac_rx_rst.setimmediatevalue(0)
await self.rc.enumerate()
@ -330,8 +332,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
if self.loopback_enable:
for macs in self.qsfpdd_mac:
for mac in macs:
for mac in self.qsfpdd_mac:
if not mac.tx.empty():
await mac.rx.send(await mac.tx.recv())
@ -339,7 +340,7 @@ class TB(object):
@cocotb.test()
async def run_test_nic(dut):
tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
tb = TB(dut, msix_count=2**len(dut.uut.core_inst.core_pcie_inst.irq_index))
await tb.init()
@ -364,10 +365,10 @@ async def run_test_nic(dut):
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.qsfpdd_mac[0][0].tx.recv()
pkt = await tb.qsfpdd_mac[0].tx.recv()
tb.log.info("Packet: %s", pkt)
await tb.qsfpdd_mac[0][0].rx.send(pkt)
await tb.qsfpdd_mac[0].rx.send(pkt)
pkt = await tb.driver.interfaces[0].recv()
@ -376,10 +377,10 @@ async def run_test_nic(dut):
# await tb.driver.interfaces[1].start_xmit(data, 0)
# pkt = await tb.qsfpdd_mac[1][0].tx.recv()
# pkt = await tb.qsfpdd_mac[1].tx.recv()
# tb.log.info("Packet: %s", pkt)
# await tb.qsfpdd_mac[1][0].rx.send(pkt)
# await tb.qsfpdd_mac[1].rx.send(pkt)
# pkt = await tb.driver.interfaces[1].recv()
@ -399,10 +400,10 @@ async def run_test_nic(dut):
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
pkt = await tb.qsfpdd_mac[0][0].tx.recv()
pkt = await tb.qsfpdd_mac[0].tx.recv()
tb.log.info("Packet: %s", pkt)
await tb.qsfpdd_mac[0][0].rx.send(pkt)
await tb.qsfpdd_mac[0].rx.send(pkt)
pkt = await tb.driver.interfaces[0].recv()
@ -547,9 +548,10 @@ pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
def test_fpga_core(request):
dut = "fpga_core"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
toplevel = f"test_{dut}"
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.v"),
os.path.join(rtl_dir, f"{dut}.v"),
os.path.join(rtl_dir, "common", "mqnic_core_pcie_ptile.v"),
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),

659
fpga/mqnic/DE10_Agilex/fpga_100g/tb/fpga_core/test_fpga_core.v Normal file
View File

@ -0,0 +1,659 @@
/*
Copyright (c) 2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Testbench top-level module
*/
module test_fpga_core #
(
// FW and board IDs
parameter FPGA_ID = 32'hC341A0DD,
parameter FW_ID = 32'h00000000,
parameter FW_VER = 32'h00_00_01_00,
parameter BOARD_ID = 32'h1172_B00A,
parameter BOARD_VER = 32'h01_00_00_00,
parameter BUILD_DATE = 32'd1563227611,
parameter GIT_HASH = 32'hdce357bf,
parameter RELEASE_INFO = 32'h00000000,
// Board configuration
parameter QSFPDD_CNT = 2,
parameter CH_CNT = QSFPDD_CNT*2,
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
parameter PORT_MASK = 0,
// Clock configuration
parameter CLK_PERIOD_NS_NUM = 4,
parameter CLK_PERIOD_NS_DENOM = 1,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 2048,
parameter PTP_CLK_PERIOD_NS_DENOM = 825,
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 8,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 131072,
parameter MAX_TX_SIZE = 9214,
parameter MAX_RX_SIZE = 9214,
parameter TX_RAM_SIZE = 131072,
parameter RX_RAM_SIZE = 131072,
// Application block configuration
parameter APP_ID = 32'h00000000,
parameter APP_ENABLE = 0,
parameter APP_CTRL_ENABLE = 1,
parameter APP_DMA_ENABLE = 1,
parameter APP_AXIS_DIRECT_ENABLE = 1,
parameter APP_AXIS_SYNC_ENABLE = 1,
parameter APP_AXIS_IF_ENABLE = 1,
parameter APP_STAT_ENABLE = 1,
// DMA interface configuration
parameter DMA_IMM_ENABLE = 0,
parameter DMA_IMM_WIDTH = 32,
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
parameter RAM_PIPELINE = 2,
// PCIe interface configuration
parameter SEG_COUNT = 2,
parameter SEG_DATA_WIDTH = 256,
parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32),
parameter SEG_HDR_WIDTH = 128,
parameter SEG_PRFX_WIDTH = 32,
parameter TX_SEQ_NUM_WIDTH = 6,
parameter PF_COUNT = 1,
parameter VF_COUNT = 0,
parameter PCIE_TAG_COUNT = 256,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24,
// AXI lite interface configuration (application control)
parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH,
parameter AXIL_APP_CTRL_ADDR_WIDTH = 24,
// Ethernet interface configuration
parameter AXIS_ETH_DATA_WIDTH = 512,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 0,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 2,
parameter AXIS_ETH_TX_TS_PIPELINE = 0,
parameter AXIS_ETH_RX_PIPELINE = 0,
parameter AXIS_ETH_RX_FIFO_PIPELINE = 2,
// Statistics counter subsystem
parameter STAT_ENABLE = 1,
parameter STAT_DMA_ENABLE = 1,
parameter STAT_PCIE_ENABLE = 1,
parameter STAT_INC_WIDTH = 24,
parameter STAT_ID_WIDTH = 12
)
(
/*
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_250mhz,
input wire rst_250mhz,
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
/*
* GPIO
*/
input wire [1:0] button,
input wire [1:0] sw,
output wire [3:0] led,
output wire [3:0] led_bracket,
/*
* P-Tile interface
*/
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data,
input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty,
input wire [SEG_COUNT-1:0] rx_st_sop,
input wire [SEG_COUNT-1:0] rx_st_eop,
input wire [SEG_COUNT-1:0] rx_st_valid,
output wire rx_st_ready,
input wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] rx_st_hdr,
input wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] rx_st_tlp_prfx,
input wire [SEG_COUNT-1:0] rx_st_vf_active,
input wire [SEG_COUNT*3-1:0] rx_st_func_num,
input wire [SEG_COUNT*11-1:0] rx_st_vf_num,
input wire [SEG_COUNT*3-1:0] rx_st_bar_range,
input wire [SEG_COUNT-1:0] rx_st_tlp_abort,
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
output wire [SEG_COUNT-1:0] tx_st_sop,
output wire [SEG_COUNT-1:0] tx_st_eop,
output wire [SEG_COUNT-1:0] tx_st_valid,
input wire tx_st_ready,
output wire [SEG_COUNT-1:0] tx_st_err,
output wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr,
output wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] tx_st_tlp_prfx,
output wire [11:0] rx_buffer_limit,
output wire [1:0] rx_buffer_limit_tdm_idx,
input wire [15:0] tx_cdts_limit,
input wire [2:0] tx_cdts_limit_tdm_idx,
input wire [15:0] tl_cfg_ctl,
input wire [4:0] tl_cfg_add,
input wire [2:0] tl_cfg_func,
/*
* Ethernet: QSFP-DD
*/
// input wire [CH_CNT-1:0] qsfpdd_mac_tx_clk,
// input wire [CH_CNT-1:0] qsfpdd_mac_tx_rst,
// output wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_tx_axis_tdata,
// output wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_tx_axis_tkeep,
// output wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tvalid,
// input wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tready,
// output wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tlast,
// output wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd_mac_tx_axis_tuser,
// output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_time,
// input wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts,
// input wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts_tag,
// input wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_ts_valid,
// input wire [CH_CNT-1:0] qsfpdd_mac_tx_status,
// output wire [CH_CNT-1:0] qsfpdd_mac_tx_lfc_req,
// output wire [CH_CNT*8-1:0] qsfpdd_mac_tx_pfc_req,
// input wire [CH_CNT-1:0] qsfpdd_mac_rx_clk,
// input wire [CH_CNT-1:0] qsfpdd_mac_rx_rst,
// input wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_rx_axis_tdata,
// input wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_rx_axis_tkeep,
// input wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tvalid,
// input wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tlast,
// input wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd_mac_rx_axis_tuser,
// output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_rx_ptp_time,
// input wire [CH_CNT-1:0] qsfpdd_mac_rx_status,
// input wire [CH_CNT-1:0] qsfpdd_mac_rx_lfc_req,
// input wire [CH_CNT*8-1:0] qsfpdd_mac_rx_pfc_req,
output wire qsfpdda_initmode,
input wire qsfpdda_interrupt_n,
input wire qsfpdda_mod_prs_n,
output wire qsfpdda_mod_sel_n,
output wire qsfpdda_rst_n,
input wire qsfpdda_scl_i,
output wire qsfpdda_scl_o,
output wire qsfpdda_scl_t,
input wire qsfpdda_sda_i,
output wire qsfpdda_sda_o,
output wire qsfpdda_sda_t,
output wire qsfpddb_initmode,
input wire qsfpddb_interrupt_n,
input wire qsfpddb_mod_prs_n,
output wire qsfpddb_mod_sel_n,
output wire qsfpddb_rst_n,
input wire qsfpddb_scl_i,
output wire qsfpddb_scl_o,
output wire qsfpddb_scl_t,
input wire qsfpddb_sda_i,
output wire qsfpddb_sda_o,
output wire qsfpddb_sda_t
);
genvar n;
wire [CH_CNT-1:0] qsfpdd_mac_tx_clk;
wire [CH_CNT-1:0] qsfpdd_mac_tx_rst;
wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_tx_axis_tdata;
wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_tx_axis_tkeep;
wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tvalid;
wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tready;
wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tlast;
wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd_mac_tx_axis_tuser;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_time;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts;
wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts_tag;
wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_ts_valid;
wire [CH_CNT-1:0] qsfpdd_mac_tx_status;
wire [CH_CNT-1:0] qsfpdd_mac_tx_lfc_req;
wire [CH_CNT*8-1:0] qsfpdd_mac_tx_pfc_req;
wire [CH_CNT-1:0] qsfpdd_mac_rx_clk;
wire [CH_CNT-1:0] qsfpdd_mac_rx_rst;
wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_rx_axis_tdata;
wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_rx_axis_tkeep;
wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tvalid;
wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tlast;
wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd_mac_rx_axis_tuser;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_rx_ptp_time;
wire [CH_CNT-1:0] qsfpdd_mac_rx_status;
wire [CH_CNT-1:0] qsfpdd_mac_rx_lfc_req;
wire [CH_CNT*8-1:0] qsfpdd_mac_rx_pfc_req;
generate
for (n = 0; n < QSFPDD_CNT; n = n + 1) begin : ch
wire ch_mac_tx_clk;
wire ch_mac_tx_rst;
wire [AXIS_ETH_DATA_WIDTH-1:0] ch_mac_tx_axis_tdata;
wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_mac_tx_axis_tkeep;
wire ch_mac_tx_axis_tvalid;
wire ch_mac_tx_axis_tready;
wire ch_mac_tx_axis_tlast;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] ch_mac_tx_axis_tuser;
wire [PTP_TS_WIDTH-1:0] ch_mac_tx_ptp_time;
wire [PTP_TS_WIDTH-1:0] ch_mac_tx_ptp_ts;
wire [15:0] ch_mac_tx_ptp_ts_tag;
wire ch_mac_tx_ptp_ts_valid;
wire ch_mac_tx_status;
wire ch_mac_tx_lfc_req;
wire [7:0] ch_mac_tx_pfc_req;
wire ch_mac_rx_clk;
wire ch_mac_rx_rst;
wire [AXIS_ETH_DATA_WIDTH-1:0] ch_mac_rx_axis_tdata;
wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_mac_rx_axis_tkeep;
wire ch_mac_rx_axis_tvalid;
wire ch_mac_rx_axis_tlast;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] ch_mac_rx_axis_tuser;
wire [PTP_TS_WIDTH-1:0] ch_mac_rx_ptp_time;
wire ch_mac_rx_status;
wire ch_mac_rx_lfc_req;
wire [7:0] ch_mac_rx_pfc_req;
assign qsfpdd_mac_tx_clk[n +: 1] = ch_mac_tx_clk;
assign qsfpdd_mac_tx_rst[n +: 1] = ch_mac_tx_rst;
assign ch_mac_tx_axis_tdata = qsfpdd_mac_tx_axis_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH];
assign ch_mac_tx_axis_tkeep = qsfpdd_mac_tx_axis_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH];
assign ch_mac_tx_axis_tvalid = qsfpdd_mac_tx_axis_tvalid[n +: 1];
assign qsfpdd_mac_tx_axis_tready[n +: 1] = ch_mac_tx_axis_tready;
assign ch_mac_tx_axis_tlast = qsfpdd_mac_tx_axis_tlast[n +: 1];
assign ch_mac_tx_axis_tuser = qsfpdd_mac_tx_axis_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH];
assign ch_mac_tx_ptp_time = qsfpdd_mac_tx_ptp_time[n*PTP_TS_WIDTH +: PTP_TS_WIDTH];
assign qsfpdd_mac_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = ch_mac_tx_ptp_ts;
assign qsfpdd_mac_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH] = ch_mac_tx_ptp_ts_tag;
assign qsfpdd_mac_tx_ptp_ts_valid[n +: 1] = ch_mac_tx_ptp_ts_valid;
assign qsfpdd_mac_tx_status[n +: 1] = ch_mac_tx_status;
assign ch_mac_tx_lfc_req = qsfpdd_mac_tx_lfc_req[n +: 1];
assign ch_mac_tx_pfc_req = qsfpdd_mac_tx_pfc_req[n*8 +: 8];
assign qsfpdd_mac_rx_clk[n +: 1] = ch_mac_rx_clk;
assign qsfpdd_mac_rx_rst[n +: 1] = ch_mac_rx_rst;
assign qsfpdd_mac_rx_axis_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH] = ch_mac_rx_axis_tdata;
assign qsfpdd_mac_rx_axis_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH] = ch_mac_rx_axis_tkeep;
assign qsfpdd_mac_rx_axis_tvalid[n +: 1] = ch_mac_rx_axis_tvalid;
assign qsfpdd_mac_rx_axis_tlast[n +: 1] = ch_mac_rx_axis_tlast;
assign qsfpdd_mac_rx_axis_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH] = ch_mac_rx_axis_tuser;
assign ch_mac_rx_ptp_time = qsfpdd_mac_rx_ptp_time[n*PTP_TS_WIDTH +: PTP_TS_WIDTH];
assign qsfpdd_mac_rx_status[n +: 1] = ch_mac_rx_status;
assign qsfpdd_mac_rx_lfc_req[n +: 1] = ch_mac_rx_lfc_req;
assign qsfpdd_mac_rx_pfc_req[n*8 +: 8] = ch_mac_rx_pfc_req;
end
endgenerate
fpga_core #(
// FW and board IDs
.FPGA_ID(FPGA_ID),
.FW_ID(FW_ID),
.FW_VER(FW_VER),
.BOARD_ID(BOARD_ID),
.BOARD_VER(BOARD_VER),
.BUILD_DATE(BUILD_DATE),
.GIT_HASH(GIT_HASH),
.RELEASE_INFO(RELEASE_INFO),
// Board configuration
.QSFPDD_CNT(QSFPDD_CNT),
.CH_CNT(CH_CNT),
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_MASK(PORT_MASK),
// Clock configuration
.CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM),
.CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE),
// Application block configuration
.APP_ID(APP_ID),
.APP_ENABLE(APP_ENABLE),
.APP_CTRL_ENABLE(APP_CTRL_ENABLE),
.APP_DMA_ENABLE(APP_DMA_ENABLE),
.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
.APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE),
.APP_STAT_ENABLE(APP_STAT_ENABLE),
// DMA interface configuration
.DMA_IMM_ENABLE(DMA_IMM_ENABLE),
.DMA_IMM_WIDTH(DMA_IMM_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
// PCIe interface configuration
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH),
.SEG_HDR_WIDTH(SEG_HDR_WIDTH),
.SEG_PRFX_WIDTH(SEG_PRFX_WIDTH),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(PF_COUNT),
.VF_COUNT(VF_COUNT),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
// AXI lite interface configuration (application control)
.AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH),
.AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH),
// Ethernet interface configuration
.AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH),
.AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
.AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
.AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE),
.AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE),
.AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE),
.AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE),
.AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE),
// Statistics counter subsystem
.STAT_ENABLE(STAT_ENABLE),
.STAT_DMA_ENABLE(STAT_DMA_ENABLE),
.STAT_PCIE_ENABLE(STAT_PCIE_ENABLE),
.STAT_INC_WIDTH(STAT_INC_WIDTH),
.STAT_ID_WIDTH(STAT_ID_WIDTH)
)
uut (
/*
* Clock: 250 MHz
* Synchronous reset
*/
.clk_250mhz(clk_250mhz),
.rst_250mhz(rst_250mhz),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* GPIO
*/
.button(button),
.sw(sw),
.led(led),
.led_bracket(led_bracket),
/*
* P-Tile interface
*/
.rx_st_data(rx_st_data),
.rx_st_empty(rx_st_empty),
.rx_st_sop(rx_st_sop),
.rx_st_eop(rx_st_eop),
.rx_st_valid(rx_st_valid),
.rx_st_ready(rx_st_ready),
.rx_st_hdr(rx_st_hdr),
.rx_st_tlp_prfx(rx_st_tlp_prfx),
.rx_st_vf_active(rx_st_vf_active),
.rx_st_func_num(rx_st_func_num),
.rx_st_vf_num(rx_st_vf_num),
.rx_st_bar_range(rx_st_bar_range),
.rx_st_tlp_abort(rx_st_tlp_abort),
.tx_st_data(tx_st_data),
.tx_st_sop(tx_st_sop),
.tx_st_eop(tx_st_eop),
.tx_st_valid(tx_st_valid),
.tx_st_ready(tx_st_ready),
.tx_st_err(tx_st_err),
.tx_st_hdr(tx_st_hdr),
.tx_st_tlp_prfx(tx_st_tlp_prfx),
.rx_buffer_limit(rx_buffer_limit),
.rx_buffer_limit_tdm_idx(rx_buffer_limit_tdm_idx),
.tx_cdts_limit(tx_cdts_limit),
.tx_cdts_limit_tdm_idx(tx_cdts_limit_tdm_idx),
.tl_cfg_ctl(tl_cfg_ctl),
.tl_cfg_add(tl_cfg_add),
.tl_cfg_func(tl_cfg_func),
/*
* Ethernet: QSFP-DD
*/
.qsfpdd_mac_tx_clk(qsfpdd_mac_tx_clk),
.qsfpdd_mac_tx_rst(qsfpdd_mac_tx_rst),
.qsfpdd_mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata),
.qsfpdd_mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep),
.qsfpdd_mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid),
.qsfpdd_mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready),
.qsfpdd_mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast),
.qsfpdd_mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser),
.qsfpdd_mac_tx_ptp_time(qsfpdd_mac_tx_ptp_time),
.qsfpdd_mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts),
.qsfpdd_mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag),
.qsfpdd_mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid),
.qsfpdd_mac_tx_status(qsfpdd_mac_tx_status),
.qsfpdd_mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req),
.qsfpdd_mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req),
.qsfpdd_mac_rx_clk(qsfpdd_mac_rx_clk),
.qsfpdd_mac_rx_rst(qsfpdd_mac_rx_rst),
.qsfpdd_mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata),
.qsfpdd_mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep),
.qsfpdd_mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid),
.qsfpdd_mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast),
.qsfpdd_mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser),
.qsfpdd_mac_rx_ptp_time(qsfpdd_mac_rx_ptp_time),
.qsfpdd_mac_rx_status(qsfpdd_mac_rx_status),
.qsfpdd_mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req),
.qsfpdd_mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req),
.qsfpdda_initmode(qsfpdda_initmode),
.qsfpdda_interrupt_n(qsfpdda_interrupt_n),
.qsfpdda_mod_prs_n(qsfpdda_mod_prs_n),
.qsfpdda_mod_sel_n(qsfpdda_mod_sel_n),
.qsfpdda_rst_n(qsfpdda_rst_n),
.qsfpdda_scl_i(qsfpdda_scl_i),
.qsfpdda_scl_o(qsfpdda_scl_o),
.qsfpdda_scl_t(qsfpdda_scl_t),
.qsfpdda_sda_i(qsfpdda_sda_i),
.qsfpdda_sda_o(qsfpdda_sda_o),
.qsfpdda_sda_t(qsfpdda_sda_t),
.qsfpddb_initmode(qsfpddb_initmode),
.qsfpddb_interrupt_n(qsfpddb_interrupt_n),
.qsfpddb_mod_prs_n(qsfpddb_mod_prs_n),
.qsfpddb_mod_sel_n(qsfpddb_mod_sel_n),
.qsfpddb_rst_n(qsfpddb_rst_n),
.qsfpddb_scl_i(qsfpddb_scl_i),
.qsfpddb_scl_o(qsfpddb_scl_o),
.qsfpddb_scl_t(qsfpddb_scl_t),
.qsfpddb_sda_i(qsfpddb_sda_i),
.qsfpddb_sda_o(qsfpddb_sda_o),
.qsfpddb_sda_t(qsfpddb_sda_t)
);
endmodule
`resetall

276
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v
View File

@ -403,37 +403,46 @@ pcie pcie_hip_inst (
);
// QSFP28 interfaces
localparam QSFP_CNT = 2;
localparam CH_CNT = QSFP_CNT;
wire [CH_CNT-1:0] qsfp_mac_tx_clk;
wire [CH_CNT-1:0] qsfp_mac_tx_rst;
wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_mac_tx_axis_tdata;
wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_mac_tx_axis_tkeep;
wire [CH_CNT-1:0] qsfp_mac_tx_axis_tvalid;
wire [CH_CNT-1:0] qsfp_mac_tx_axis_tready;
wire [CH_CNT-1:0] qsfp_mac_tx_axis_tlast;
wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfp_mac_tx_axis_tuser;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_time;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_ts;
wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfp_mac_tx_ptp_ts_tag;
wire [CH_CNT-1:0] qsfp_mac_tx_ptp_ts_valid;
wire [CH_CNT-1:0] qsfp_mac_tx_status;
wire [CH_CNT-1:0] qsfp_mac_tx_lfc_req;
wire [CH_CNT*8-1:0] qsfp_mac_tx_pfc_req;
wire [CH_CNT-1:0] qsfp_mac_rx_clk;
wire [CH_CNT-1:0] qsfp_mac_rx_rst;
wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_mac_rx_axis_tdata;
wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_mac_rx_axis_tkeep;
wire [CH_CNT-1:0] qsfp_mac_rx_axis_tvalid;
wire [CH_CNT-1:0] qsfp_mac_rx_axis_tlast;
wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfp_mac_rx_axis_tuser;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_rx_ptp_time;
wire [CH_CNT-1:0] qsfp_mac_rx_status;
wire [CH_CNT-1:0] qsfp_mac_rx_lfc_req;
wire [CH_CNT*8-1:0] qsfp_mac_rx_pfc_req;
// QSFP1
wire qsfp1_mac_clk_int;
wire qsfp1_mac_rst_int;
wire [PTP_TS_WIDTH-1:0] qsfp1_mac_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp1_mac_tx_ptp_ts_int;
wire [PTP_TAG_WIDTH-1:0] qsfp1_mac_tx_ptp_ts_tag_int;
wire qsfp1_mac_tx_ptp_ts_valid_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_tx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_tx_axis_tkeep_int;
wire qsfp1_mac_tx_axis_tvalid_int;
wire qsfp1_mac_tx_axis_tready_int;
wire qsfp1_mac_tx_axis_tlast_int;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp1_mac_tx_axis_tuser_int;
wire qsfp1_mac_tx_status_int;
wire qsfp1_mac_tx_lfc_req_int;
wire [7:0] qsfp1_mac_tx_pfc_req_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_rx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_rx_axis_tkeep_int;
wire qsfp1_mac_rx_axis_tvalid_int;
wire qsfp1_mac_rx_axis_tlast_int;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp1_mac_rx_axis_tuser_int;
wire qsfp1_mac_rx_status_int;
wire qsfp1_mac_rx_lfc_req_int;
wire [7:0] qsfp1_mac_rx_pfc_req_int;
assign qsfp_mac_rx_clk[0*1 +: 1] = qsfp_mac_tx_clk[0*1 +: 1];
assign qsfp_mac_rx_rst[0*1 +: 1] = qsfp_mac_tx_rst[0*1 +: 1];
eth_mac_wrapper #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
@ -453,67 +462,40 @@ qsfp1_mac_inst (
// .rx_serial_data_n({qsfp1_rx_n[3], qsfp1_rx_n[1], qsfp1_rx_n[2], qsfp1_rx_n[0]}),
.ref_clk(clk_156p25m_qsfp0_p),
.mac_clk(qsfp1_mac_clk_int),
.mac_rst(qsfp1_mac_rst_int),
.mac_clk(qsfp_mac_tx_clk[0 +: 1]),
.mac_rst(qsfp_mac_tx_rst[0 +: 1]),
.mac_ptp_time(qsfp1_mac_ptp_time_int),
.mac_ptp_time(qsfp_mac_tx_ptp_time[0*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.mac_tx_ptp_ts(qsfp1_mac_tx_ptp_ts_int),
.mac_tx_ptp_ts_tag(qsfp1_mac_tx_ptp_ts_tag_int),
.mac_tx_ptp_ts_valid(qsfp1_mac_tx_ptp_ts_valid_int),
.mac_tx_ptp_ts(qsfp_mac_tx_ptp_ts[0*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.mac_tx_ptp_ts_tag(qsfp_mac_tx_ptp_ts_tag[0*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.mac_tx_ptp_ts_valid(qsfp_mac_tx_ptp_ts_valid[0 +: 1]),
.mac_tx_axis_tdata(qsfp1_mac_tx_axis_tdata_int),
.mac_tx_axis_tkeep(qsfp1_mac_tx_axis_tkeep_int),
.mac_tx_axis_tvalid(qsfp1_mac_tx_axis_tvalid_int),
.mac_tx_axis_tready(qsfp1_mac_tx_axis_tready_int),
.mac_tx_axis_tlast(qsfp1_mac_tx_axis_tlast_int),
.mac_tx_axis_tuser(qsfp1_mac_tx_axis_tuser_int),
.mac_tx_axis_tdata(qsfp_mac_tx_axis_tdata[0*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]),
.mac_tx_axis_tkeep(qsfp_mac_tx_axis_tkeep[0*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]),
.mac_tx_axis_tvalid(qsfp_mac_tx_axis_tvalid[0 +: 1]),
.mac_tx_axis_tready(qsfp_mac_tx_axis_tready[0 +: 1]),
.mac_tx_axis_tlast(qsfp_mac_tx_axis_tlast[0 +: 1]),
.mac_tx_axis_tuser(qsfp_mac_tx_axis_tuser[0*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]),
.mac_tx_status(qsfp1_mac_tx_status_int),
.mac_tx_lfc_req(qsfp1_mac_tx_lfc_req_int),
.mac_tx_pfc_req(qsfp1_mac_tx_pfc_req_int),
.mac_tx_status(qsfp_mac_tx_status[0 +: 1]),
.mac_tx_lfc_req(qsfp_mac_tx_lfc_req[0 +: 1]),
.mac_tx_pfc_req(qsfp_mac_tx_pfc_req[0*8 +: 8]),
.mac_rx_axis_tdata(qsfp1_mac_rx_axis_tdata_int),
.mac_rx_axis_tkeep(qsfp1_mac_rx_axis_tkeep_int),
.mac_rx_axis_tvalid(qsfp1_mac_rx_axis_tvalid_int),
.mac_rx_axis_tlast(qsfp1_mac_rx_axis_tlast_int),
.mac_rx_axis_tuser(qsfp1_mac_rx_axis_tuser_int),
.mac_rx_axis_tdata(qsfp_mac_rx_axis_tdata[0*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]),
.mac_rx_axis_tkeep(qsfp_mac_rx_axis_tkeep[0*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]),
.mac_rx_axis_tvalid(qsfp_mac_rx_axis_tvalid[0 +: 1]),
.mac_rx_axis_tlast(qsfp_mac_rx_axis_tlast[0 +: 1]),
.mac_rx_axis_tuser(qsfp_mac_rx_axis_tuser[0*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]),
.mac_rx_status(qsfp1_mac_rx_status_int),
.mac_rx_lfc_req(qsfp1_mac_rx_lfc_req_int),
.mac_rx_pfc_req(qsfp1_mac_rx_pfc_req_int)
.mac_rx_status(qsfp_mac_rx_status[0 +: 1]),
.mac_rx_lfc_req(qsfp_mac_rx_lfc_req[0 +: 1]),
.mac_rx_pfc_req(qsfp_mac_rx_pfc_req[0*8 +: 8])
);
// QSFP2
wire qsfp2_mac_clk_int;
wire qsfp2_mac_rst_int;
wire [PTP_TS_WIDTH-1:0] qsfp2_mac_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfp2_mac_tx_ptp_ts_int;
wire [PTP_TAG_WIDTH-1:0] qsfp2_mac_tx_ptp_ts_tag_int;
wire qsfp2_mac_tx_ptp_ts_valid_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_tx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_tx_axis_tkeep_int;
wire qsfp2_mac_tx_axis_tvalid_int;
wire qsfp2_mac_tx_axis_tready_int;
wire qsfp2_mac_tx_axis_tlast_int;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp2_mac_tx_axis_tuser_int;
wire qsfp2_mac_tx_status_int;
wire qsfp2_mac_tx_lfc_req_int;
wire [7:0] qsfp2_mac_tx_pfc_req_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_rx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_rx_axis_tkeep_int;
wire qsfp2_mac_rx_axis_tvalid_int;
wire qsfp2_mac_rx_axis_tlast_int;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp2_mac_rx_axis_tuser_int;
wire qsfp2_mac_rx_status_int;
wire qsfp2_mac_rx_lfc_req_int;
wire [7:0] qsfp2_mac_rx_pfc_req_int;
assign qsfp_mac_rx_clk[1*1 +: 1] = qsfp_mac_tx_clk[1*1 +: 1];
assign qsfp_mac_rx_rst[1*1 +: 1] = qsfp_mac_tx_rst[1*1 +: 1];
eth_mac_wrapper #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
@ -533,35 +515,35 @@ qsfp2_mac_inst (
// .rx_serial_data_n({qsfp2_rx_n[3], qsfp2_rx_n[1], qsfp2_rx_n[2], qsfp2_rx_n[0]}),
.ref_clk(clk_156p25m_qsfp0_p),
.mac_clk(qsfp2_mac_clk_int),
.mac_rst(qsfp2_mac_rst_int),
.mac_clk(qsfp_mac_tx_clk[1 +: 1]),
.mac_rst(qsfp_mac_tx_rst[1 +: 1]),
.mac_ptp_time(qsfp2_mac_ptp_time_int),
.mac_ptp_time(qsfp_mac_tx_ptp_time[1*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.mac_tx_ptp_ts(qsfp2_mac_tx_ptp_ts_int),
.mac_tx_ptp_ts_tag(qsfp2_mac_tx_ptp_ts_tag_int),
.mac_tx_ptp_ts_valid(qsfp2_mac_tx_ptp_ts_valid_int),
.mac_tx_ptp_ts(qsfp_mac_tx_ptp_ts[1*PTP_TS_WIDTH +: PTP_TS_WIDTH]),
.mac_tx_ptp_ts_tag(qsfp_mac_tx_ptp_ts_tag[1*TX_TAG_WIDTH +: TX_TAG_WIDTH]),
.mac_tx_ptp_ts_valid(qsfp_mac_tx_ptp_ts_valid[1 +: 1]),
.mac_tx_axis_tdata(qsfp2_mac_tx_axis_tdata_int),
.mac_tx_axis_tkeep(qsfp2_mac_tx_axis_tkeep_int),
.mac_tx_axis_tvalid(qsfp2_mac_tx_axis_tvalid_int),
.mac_tx_axis_tready(qsfp2_mac_tx_axis_tready_int),
.mac_tx_axis_tlast(qsfp2_mac_tx_axis_tlast_int),
.mac_tx_axis_tuser(qsfp2_mac_tx_axis_tuser_int),
.mac_tx_axis_tdata(qsfp_mac_tx_axis_tdata[1*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]),
.mac_tx_axis_tkeep(qsfp_mac_tx_axis_tkeep[1*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]),
.mac_tx_axis_tvalid(qsfp_mac_tx_axis_tvalid[1 +: 1]),
.mac_tx_axis_tready(qsfp_mac_tx_axis_tready[1 +: 1]),
.mac_tx_axis_tlast(qsfp_mac_tx_axis_tlast[1 +: 1]),
.mac_tx_axis_tuser(qsfp_mac_tx_axis_tuser[1*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH]),
.mac_tx_status(qsfp2_mac_tx_status_int),
.mac_tx_lfc_req(qsfp2_mac_tx_lfc_req_int),
.mac_tx_pfc_req(qsfp2_mac_tx_pfc_req_int),
.mac_tx_status(qsfp_mac_tx_status[1 +: 1]),
.mac_tx_lfc_req(qsfp_mac_tx_lfc_req[1 +: 1]),
.mac_tx_pfc_req(qsfp_mac_tx_pfc_req[1*8 +: 8]),
.mac_rx_axis_tdata(qsfp2_mac_rx_axis_tdata_int),
.mac_rx_axis_tkeep(qsfp2_mac_rx_axis_tkeep_int),
.mac_rx_axis_tvalid(qsfp2_mac_rx_axis_tvalid_int),
.mac_rx_axis_tlast(qsfp2_mac_rx_axis_tlast_int),
.mac_rx_axis_tuser(qsfp2_mac_rx_axis_tuser_int),
.mac_rx_axis_tdata(qsfp_mac_rx_axis_tdata[1*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH]),
.mac_rx_axis_tkeep(qsfp_mac_rx_axis_tkeep[1*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH]),
.mac_rx_axis_tvalid(qsfp_mac_rx_axis_tvalid[1 +: 1]),
.mac_rx_axis_tlast(qsfp_mac_rx_axis_tlast[1 +: 1]),
.mac_rx_axis_tuser(qsfp_mac_rx_axis_tuser[1*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH]),
.mac_rx_status(qsfp2_mac_rx_status_int),
.mac_rx_lfc_req(qsfp2_mac_rx_lfc_req_int),
.mac_rx_pfc_req(qsfp2_mac_rx_pfc_req_int)
.mac_rx_status(qsfp_mac_rx_status[1 +: 1]),
.mac_rx_lfc_req(qsfp_mac_rx_lfc_req[1 +: 1]),
.mac_rx_pfc_req(qsfp_mac_rx_pfc_req[1*8 +: 8])
);
wire ptp_clk;
@ -571,7 +553,7 @@ wire ptp_sample_clk;
assign ptp_sample_clk = clk_100mhz;
ref_div ref_div_inst (
.inclk(qsfp1_mac_clk_int),
.inclk(qsfp_mac_tx_clk[0]),
.clock_div1x(),
.clock_div2x(ptp_clk),
.clock_div4x()
@ -582,7 +564,7 @@ sync_reset #(
)
ptp_rst_reset_sync_inst (
.clk(ptp_clk),
.rst(qsfp1_mac_rst_int),
.rst(qsfp_mac_tx_rst[0]),
.out(ptp_rst)
);
@ -597,6 +579,10 @@ fpga_core #(
.GIT_HASH(GIT_HASH),
.RELEASE_INFO(RELEASE_INFO),
// Board configuration
.QSFP_CNT(QSFP_CNT),
.CH_CNT(CH_CNT),
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
@ -785,65 +771,39 @@ core_inst (
/*
* Ethernet: QSFP28
*/
.qsfp1_mac_clk(qsfp1_mac_clk_int),
.qsfp1_mac_rst(qsfp1_mac_rst_int),
.qsfp_mac_tx_clk(qsfp_mac_tx_clk),
.qsfp_mac_tx_rst(qsfp_mac_tx_rst),
.qsfp1_mac_ptp_time(qsfp1_mac_ptp_time_int),
.qsfp_mac_tx_axis_tdata(qsfp_mac_tx_axis_tdata),
.qsfp_mac_tx_axis_tkeep(qsfp_mac_tx_axis_tkeep),
.qsfp_mac_tx_axis_tvalid(qsfp_mac_tx_axis_tvalid),
.qsfp_mac_tx_axis_tready(qsfp_mac_tx_axis_tready),
.qsfp_mac_tx_axis_tlast(qsfp_mac_tx_axis_tlast),
.qsfp_mac_tx_axis_tuser(qsfp_mac_tx_axis_tuser),
.qsfp1_mac_tx_ptp_ts(qsfp1_mac_tx_ptp_ts_int),
.qsfp1_mac_tx_ptp_ts_tag(qsfp1_mac_tx_ptp_ts_tag_int),
.qsfp1_mac_tx_ptp_ts_valid(qsfp1_mac_tx_ptp_ts_valid_int),
.qsfp_mac_tx_ptp_time(qsfp_mac_tx_ptp_time),
.qsfp_mac_tx_ptp_ts(qsfp_mac_tx_ptp_ts),
.qsfp_mac_tx_ptp_ts_tag(qsfp_mac_tx_ptp_ts_tag),
.qsfp_mac_tx_ptp_ts_valid(qsfp_mac_tx_ptp_ts_valid),
.qsfp1_mac_tx_axis_tdata(qsfp1_mac_tx_axis_tdata_int),
.qsfp1_mac_tx_axis_tkeep(qsfp1_mac_tx_axis_tkeep_int),
.qsfp1_mac_tx_axis_tvalid(qsfp1_mac_tx_axis_tvalid_int),
.qsfp1_mac_tx_axis_tready(qsfp1_mac_tx_axis_tready_int),
.qsfp1_mac_tx_axis_tlast(qsfp1_mac_tx_axis_tlast_int),
.qsfp1_mac_tx_axis_tuser(qsfp1_mac_tx_axis_tuser_int),
.qsfp_mac_tx_status(qsfp_mac_tx_status),
.qsfp_mac_tx_lfc_req(qsfp_mac_tx_lfc_req),
.qsfp_mac_tx_pfc_req(qsfp_mac_tx_pfc_req),
.qsfp1_mac_tx_status(qsfp1_mac_tx_status_int),
.qsfp1_mac_tx_lfc_req(qsfp1_mac_tx_lfc_req_int),
.qsfp1_mac_tx_pfc_req(qsfp1_mac_tx_pfc_req_int),
.qsfp_mac_rx_clk(qsfp_mac_rx_clk),
.qsfp_mac_rx_rst(qsfp_mac_rx_rst),
.qsfp1_mac_rx_axis_tdata(qsfp1_mac_rx_axis_tdata_int),
.qsfp1_mac_rx_axis_tkeep(qsfp1_mac_rx_axis_tkeep_int),
.qsfp1_mac_rx_axis_tvalid(qsfp1_mac_rx_axis_tvalid_int),
.qsfp1_mac_rx_axis_tlast(qsfp1_mac_rx_axis_tlast_int),
.qsfp1_mac_rx_axis_tuser(qsfp1_mac_rx_axis_tuser_int),
.qsfp_mac_rx_axis_tdata(qsfp_mac_rx_axis_tdata),
.qsfp_mac_rx_axis_tkeep(qsfp_mac_rx_axis_tkeep),
.qsfp_mac_rx_axis_tvalid(qsfp_mac_rx_axis_tvalid),
.qsfp_mac_rx_axis_tlast(qsfp_mac_rx_axis_tlast),
.qsfp_mac_rx_axis_tuser(qsfp_mac_rx_axis_tuser),
.qsfp1_mac_rx_status(qsfp1_mac_rx_status_int),
.qsfp1_mac_rx_lfc_req(qsfp1_mac_rx_lfc_req_int),
.qsfp1_mac_rx_pfc_req(qsfp1_mac_rx_pfc_req_int),
.qsfp_mac_rx_ptp_time(qsfp_mac_rx_ptp_time),
.qsfp2_mac_clk(qsfp2_mac_clk_int),
.qsfp2_mac_rst(qsfp2_mac_rst_int),
.qsfp2_mac_ptp_time(qsfp2_mac_ptp_time_int),
.qsfp2_mac_tx_ptp_ts(qsfp2_mac_tx_ptp_ts_int),
.qsfp2_mac_tx_ptp_ts_tag(qsfp2_mac_tx_ptp_ts_tag_int),
.qsfp2_mac_tx_ptp_ts_valid(qsfp2_mac_tx_ptp_ts_valid_int),
.qsfp2_mac_tx_axis_tdata(qsfp2_mac_tx_axis_tdata_int),
.qsfp2_mac_tx_axis_tkeep(qsfp2_mac_tx_axis_tkeep_int),
.qsfp2_mac_tx_axis_tvalid(qsfp2_mac_tx_axis_tvalid_int),
.qsfp2_mac_tx_axis_tready(qsfp2_mac_tx_axis_tready_int),
.qsfp2_mac_tx_axis_tlast(qsfp2_mac_tx_axis_tlast_int),
.qsfp2_mac_tx_axis_tuser(qsfp2_mac_tx_axis_tuser_int),
.qsfp2_mac_tx_status(qsfp2_mac_tx_status_int),
.qsfp2_mac_tx_lfc_req(qsfp2_mac_tx_lfc_req_int),
.qsfp2_mac_tx_pfc_req(qsfp2_mac_tx_pfc_req_int),
.qsfp2_mac_rx_axis_tdata(qsfp2_mac_rx_axis_tdata_int),
.qsfp2_mac_rx_axis_tkeep(qsfp2_mac_rx_axis_tkeep_int),
.qsfp2_mac_rx_axis_tvalid(qsfp2_mac_rx_axis_tvalid_int),
.qsfp2_mac_rx_axis_tlast(qsfp2_mac_rx_axis_tlast_int),
.qsfp2_mac_rx_axis_tuser(qsfp2_mac_rx_axis_tuser_int),
.qsfp2_mac_rx_status(qsfp2_mac_rx_status_int),
.qsfp2_mac_rx_lfc_req(qsfp2_mac_rx_lfc_req_int),
.qsfp2_mac_rx_pfc_req(qsfp2_mac_rx_pfc_req_int)
.qsfp_mac_rx_status(qsfp_mac_rx_status),
.qsfp_mac_rx_lfc_req(qsfp_mac_rx_lfc_req),
.qsfp_mac_rx_pfc_req(qsfp_mac_rx_pfc_req)
);
endmodule

150
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga_core.v
View File

@ -24,6 +24,10 @@ module fpga_core #
parameter GIT_HASH = 32'hdce357bf,
parameter RELEASE_INFO = 32'h00000000,
// Board configuration
parameter QSFP_CNT = 2,
parameter CH_CNT = QSFP_CNT,
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
@ -214,65 +218,39 @@ module fpga_core #
/*
* Ethernet: QSFP28
*/
input wire qsfp1_mac_clk,
input wire qsfp1_mac_rst,
input wire [CH_CNT-1:0] qsfp_mac_tx_clk,
input wire [CH_CNT-1:0] qsfp_mac_tx_rst,
output wire [PTP_TS_WIDTH-1:0] qsfp1_mac_ptp_time,
output wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_mac_tx_axis_tdata,
output wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_mac_tx_axis_tkeep,
output wire [CH_CNT-1:0] qsfp_mac_tx_axis_tvalid,
input wire [CH_CNT-1:0] qsfp_mac_tx_axis_tready,
output wire [CH_CNT-1:0] qsfp_mac_tx_axis_tlast,
output wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfp_mac_tx_axis_tuser,
input wire [PTP_TS_WIDTH-1:0] qsfp1_mac_tx_ptp_ts,
input wire [TX_TAG_WIDTH-1:0] qsfp1_mac_tx_ptp_ts_tag,
input wire qsfp1_mac_tx_ptp_ts_valid,
output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_time,
input wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_ts,
input wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfp_mac_tx_ptp_ts_tag,
input wire [CH_CNT-1:0] qsfp_mac_tx_ptp_ts_valid,
output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_tx_axis_tdata,
output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_tx_axis_tkeep,
output wire qsfp1_mac_tx_axis_tvalid,
input wire qsfp1_mac_tx_axis_tready,
output wire qsfp1_mac_tx_axis_tlast,
output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp1_mac_tx_axis_tuser,
input wire [CH_CNT-1:0] qsfp_mac_tx_status,
output wire [CH_CNT-1:0] qsfp_mac_tx_lfc_req,
output wire [CH_CNT*8-1:0] qsfp_mac_tx_pfc_req,
input wire qsfp1_mac_tx_status,
output wire qsfp1_mac_tx_lfc_req,
output wire [7:0] qsfp1_mac_tx_pfc_req,
input wire [CH_CNT-1:0] qsfp_mac_rx_clk,
input wire [CH_CNT-1:0] qsfp_mac_rx_rst,
input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp1_mac_rx_axis_tdata,
input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp1_mac_rx_axis_tkeep,
input wire qsfp1_mac_rx_axis_tvalid,
input wire qsfp1_mac_rx_axis_tlast,
input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp1_mac_rx_axis_tuser,
input wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_mac_rx_axis_tdata,
input wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_mac_rx_axis_tkeep,
input wire [CH_CNT-1:0] qsfp_mac_rx_axis_tvalid,
input wire [CH_CNT-1:0] qsfp_mac_rx_axis_tlast,
input wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfp_mac_rx_axis_tuser,
input wire qsfp1_mac_rx_status,
input wire qsfp1_mac_rx_lfc_req,
input wire [7:0] qsfp1_mac_rx_pfc_req,
output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_rx_ptp_time,
input wire qsfp2_mac_clk,
input wire qsfp2_mac_rst,
output wire [PTP_TS_WIDTH-1:0] qsfp2_mac_ptp_time,
input wire [PTP_TS_WIDTH-1:0] qsfp2_mac_tx_ptp_ts,
input wire [TX_TAG_WIDTH-1:0] qsfp2_mac_tx_ptp_ts_tag,
input wire qsfp2_mac_tx_ptp_ts_valid,
output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_tx_axis_tdata,
output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_tx_axis_tkeep,
output wire qsfp2_mac_tx_axis_tvalid,
input wire qsfp2_mac_tx_axis_tready,
output wire qsfp2_mac_tx_axis_tlast,
output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfp2_mac_tx_axis_tuser,
input wire qsfp2_mac_tx_status,
output wire qsfp2_mac_tx_lfc_req,
output wire [7:0] qsfp2_mac_tx_pfc_req,
input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfp2_mac_rx_axis_tdata,
input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfp2_mac_rx_axis_tkeep,
input wire qsfp2_mac_rx_axis_tvalid,
input wire qsfp2_mac_rx_axis_tlast,
input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfp2_mac_rx_axis_tuser,
input wire qsfp2_mac_rx_status,
input wire qsfp2_mac_rx_lfc_req,
input wire [7:0] qsfp2_mac_rx_pfc_req
input wire [CH_CNT-1:0] qsfp_mac_rx_status,
input wire [CH_CNT-1:0] qsfp_mac_rx_lfc_req,
input wire [CH_CNT*8-1:0] qsfp_mac_rx_pfc_req
);
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
@ -287,7 +265,7 @@ localparam RB_BASE_ADDR = 16'h1000;
localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}};
initial begin
if (PORT_COUNT > 2) begin
if (PORT_COUNT > CH_CNT) begin
$error("Error: Max port count exceeded (instance %m)");
$finish;
end
@ -413,8 +391,8 @@ always @(posedge clk_250mhz) begin
end
end
assign user_led_g[0] = qsfp1_mac_rx_status;
assign user_led_g[1] = qsfp2_mac_rx_status;
assign user_led_g[0] = 1'b0;
assign user_led_g[1] = 1'b0;
assign user_led_g[2] = 1'b0;
assign user_led_g[3] = ptp_pps_str;
@ -470,7 +448,7 @@ wire [PORT_COUNT*8-1:0] eth_rx_pfc_req;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack;
mqnic_port_map_mac_axis #(
.MAC_COUNT(2),
.MAC_COUNT(CH_CNT),
.PORT_MASK(PORT_MASK),
.PORT_GROUP_SIZE(1),
@ -488,55 +466,55 @@ mqnic_port_map_mac_axis #(
)
mqnic_port_map_mac_axis_inst (
// towards MAC
.mac_tx_clk({qsfp2_mac_clk, qsfp1_mac_clk}),
.mac_tx_rst({qsfp2_mac_rst, qsfp1_mac_rst}),
.mac_tx_clk(qsfp_mac_tx_clk),
.mac_tx_rst(qsfp_mac_tx_rst),
.mac_tx_ptp_clk({qsfp2_mac_clk, qsfp1_mac_clk}),
.mac_tx_ptp_rst({qsfp2_mac_rst, qsfp1_mac_rst}),
.mac_tx_ptp_ts_96({qsfp2_mac_ptp_time, qsfp1_mac_ptp_time}),
.mac_tx_ptp_clk(qsfp_mac_tx_clk),
.mac_tx_ptp_rst(qsfp_mac_tx_rst),
.mac_tx_ptp_ts_96(qsfp_mac_tx_ptp_time),
.mac_tx_ptp_ts_step(),
.m_axis_mac_tx_tdata({qsfp2_mac_tx_axis_tdata, qsfp1_mac_tx_axis_tdata}),
.m_axis_mac_tx_tkeep({qsfp2_mac_tx_axis_tkeep, qsfp1_mac_tx_axis_tkeep}),
.m_axis_mac_tx_tvalid({qsfp2_mac_tx_axis_tvalid, qsfp1_mac_tx_axis_tvalid}),
.m_axis_mac_tx_tready({qsfp2_mac_tx_axis_tready, qsfp1_mac_tx_axis_tready}),
.m_axis_mac_tx_tlast({qsfp2_mac_tx_axis_tlast, qsfp1_mac_tx_axis_tlast}),
.m_axis_mac_tx_tuser({qsfp2_mac_tx_axis_tuser, qsfp1_mac_tx_axis_tuser}),
.m_axis_mac_tx_tdata(qsfp_mac_tx_axis_tdata),
.m_axis_mac_tx_tkeep(qsfp_mac_tx_axis_tkeep),
.m_axis_mac_tx_tvalid(qsfp_mac_tx_axis_tvalid),
.m_axis_mac_tx_tready(qsfp_mac_tx_axis_tready),
.m_axis_mac_tx_tlast(qsfp_mac_tx_axis_tlast),
.m_axis_mac_tx_tuser(qsfp_mac_tx_axis_tuser),
.s_axis_mac_tx_ptp_ts({qsfp2_mac_tx_ptp_ts, qsfp1_mac_tx_ptp_ts}),
.s_axis_mac_tx_ptp_ts_tag({qsfp2_mac_tx_ptp_ts_tag, qsfp1_mac_tx_ptp_ts_tag}),
.s_axis_mac_tx_ptp_ts_valid({qsfp2_mac_tx_ptp_ts_valid, qsfp1_mac_tx_ptp_ts_valid}),
.s_axis_mac_tx_ptp_ts(qsfp_mac_tx_ptp_ts),
.s_axis_mac_tx_ptp_ts_tag(qsfp_mac_tx_ptp_ts_tag),
.s_axis_mac_tx_ptp_ts_valid(qsfp_mac_tx_ptp_ts_valid),
.s_axis_mac_tx_ptp_ts_ready(),
.mac_tx_enable(),
.mac_tx_status({qsfp2_mac_tx_status, qsfp1_mac_tx_status}),
.mac_tx_status(qsfp_mac_tx_status),
.mac_tx_lfc_en(),
.mac_tx_lfc_req({qsfp2_mac_tx_lfc_req, qsfp1_mac_tx_lfc_req}),
.mac_tx_lfc_req(qsfp_mac_tx_lfc_req),
.mac_tx_pfc_en(),
.mac_tx_pfc_req({qsfp2_mac_tx_pfc_req, qsfp1_mac_tx_pfc_req}),
.mac_tx_pfc_req(qsfp_mac_tx_pfc_req),
.mac_rx_clk({qsfp2_mac_clk, qsfp1_mac_clk}),
.mac_rx_rst({qsfp2_mac_rst, qsfp1_mac_rst}),
.mac_rx_clk(qsfp_mac_rx_clk),
.mac_rx_rst(qsfp_mac_rx_rst),
.mac_rx_ptp_clk({qsfp2_mac_clk, qsfp1_mac_clk}),
.mac_rx_ptp_rst({qsfp2_mac_rst, qsfp1_mac_rst}),
.mac_rx_ptp_ts_96(),
.mac_rx_ptp_clk(qsfp_mac_rx_clk),
.mac_rx_ptp_rst(qsfp_mac_rx_rst),
.mac_rx_ptp_ts_96(qsfp_mac_rx_ptp_time),
.mac_rx_ptp_ts_step(),
.s_axis_mac_rx_tdata({qsfp2_mac_rx_axis_tdata, qsfp1_mac_rx_axis_tdata}),
.s_axis_mac_rx_tkeep({qsfp2_mac_rx_axis_tkeep, qsfp1_mac_rx_axis_tkeep}),
.s_axis_mac_rx_tvalid({qsfp2_mac_rx_axis_tvalid, qsfp1_mac_rx_axis_tvalid}),
.s_axis_mac_rx_tdata(qsfp_mac_rx_axis_tdata),
.s_axis_mac_rx_tkeep(qsfp_mac_rx_axis_tkeep),
.s_axis_mac_rx_tvalid(qsfp_mac_rx_axis_tvalid),
.s_axis_mac_rx_tready(),
.s_axis_mac_rx_tlast({qsfp2_mac_rx_axis_tlast, qsfp1_mac_rx_axis_tlast}),
.s_axis_mac_rx_tuser({qsfp2_mac_rx_axis_tuser, qsfp1_mac_rx_axis_tuser}),
.s_axis_mac_rx_tlast(qsfp_mac_rx_axis_tlast),
.s_axis_mac_rx_tuser(qsfp_mac_rx_axis_tuser),
.mac_rx_enable(),
.mac_rx_status({qsfp2_mac_rx_status, qsfp1_mac_rx_status}),
.mac_rx_status(qsfp_mac_rx_status),
.mac_rx_lfc_en(),
.mac_rx_lfc_req({qsfp2_mac_rx_lfc_req, qsfp1_mac_rx_lfc_req}),
.mac_rx_lfc_req(qsfp_mac_rx_lfc_req),
.mac_rx_lfc_ack(),
.mac_rx_pfc_en(),
.mac_rx_pfc_req({qsfp2_mac_rx_pfc_req, qsfp1_mac_rx_pfc_req}),
.mac_rx_pfc_req(qsfp_mac_rx_pfc_req),
.mac_rx_pfc_ack(),
// towards datapath

3
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/Makefile
View File

@ -10,8 +10,9 @@ COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
DUT = fpga_core
TOPLEVEL = $(DUT)
TOPLEVEL = test_$(DUT)
MODULE = test_$(DUT)
VERILOG_SOURCES += $(TOPLEVEL).v
VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_ptile.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v

61
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -245,9 +245,9 @@ class TB(object):
self.driver = mqnic.Driver()
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
self.dev.functions[0].configure_bar(0, 2**len(dut.uut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.uut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.uut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 4.964, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
@ -256,29 +256,30 @@ class TB(object):
# Ethernet
self.qsfp_mac = []
for k in range(1, 3):
cocotb.start_soon(Clock(getattr(dut, f"qsfp{k}_mac_clk"), 2.482, units="ns").start())
for ch in self.dut.ch:
cocotb.start_soon(Clock(ch.ch_mac_tx_clk, 2.482, units="ns").start())
cocotb.start_soon(Clock(ch.ch_mac_rx_clk, 2.482, units="ns").start())
mac = EthMac(
tx_clk=getattr(dut, f"qsfp{k}_mac_clk"),
tx_rst=getattr(dut, f"qsfp{k}_mac_rst"),
tx_bus=AxiStreamBus.from_prefix(dut, f"qsfp{k}_mac_tx_axis"),
tx_ptp_time=getattr(dut, f"qsfp{k}_mac_ptp_time"),
tx_ptp_ts=getattr(dut, f"qsfp{k}_mac_tx_ptp_ts"),
tx_ptp_ts_tag=getattr(dut, f"qsfp{k}_mac_tx_ptp_ts_tag"),
tx_ptp_ts_valid=getattr(dut, f"qsfp{k}_mac_tx_ptp_ts_valid"),
rx_clk=getattr(dut, f"qsfp{k}_mac_clk"),
rx_rst=getattr(dut, f"qsfp{k}_mac_rst"),
rx_bus=AxiStreamBus.from_prefix(dut, f"qsfp{k}_mac_rx_axis"),
rx_ptp_time=getattr(dut, f"qsfp{k}_mac_ptp_time"),
tx_clk=ch.ch_mac_tx_clk,
tx_rst=ch.ch_mac_tx_rst,
tx_bus=AxiStreamBus.from_prefix(ch, "ch_mac_tx_axis"),
tx_ptp_time=ch.ch_mac_tx_ptp_time,
tx_ptp_ts=ch.ch_mac_tx_ptp_ts,
tx_ptp_ts_tag=ch.ch_mac_tx_ptp_ts_tag,
tx_ptp_ts_valid=ch.ch_mac_tx_ptp_ts_valid,
rx_clk=ch.ch_mac_rx_clk,
rx_rst=ch.ch_mac_rx_rst,
rx_bus=AxiStreamBus.from_prefix(ch, "ch_mac_rx_axis"),
rx_ptp_time=ch.ch_mac_rx_ptp_time,
ifg=12, speed=100e9
)
self.qsfp_mac.append(mac)
ch.ch_mac_rx_status.setimmediatevalue(1)
ch.ch_mac_rx_lfc_req.setimmediatevalue(0)
ch.ch_mac_rx_pfc_req.setimmediatevalue(0)
getattr(dut, f"qsfp{k}_mac_rx_status").setimmediatevalue(1)
getattr(dut, f"qsfp{k}_mac_rx_lfc_req").setimmediatevalue(0)
getattr(dut, f"qsfp{k}_mac_rx_pfc_req").setimmediatevalue(0)
self.qsfp_mac.append(mac)
dut.user_pb.setimmediatevalue(0)
@ -291,15 +292,17 @@ class TB(object):
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
for k in range(1, 3):
getattr(self.dut, f"qsfp{k}_mac_rst").setimmediatevalue(0)
for ch in self.dut.ch:
ch.ch_mac_tx_rst.setimmediatevalue(0)
ch.ch_mac_rx_rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
for k in range(1, 3):
getattr(self.dut, f"qsfp{k}_mac_rst").setimmediatevalue(1)
for ch in self.dut.ch:
ch.ch_mac_tx_rst.setimmediatevalue(1)
ch.ch_mac_rx_rst.setimmediatevalue(1)
await FallingEdge(self.dut.rst_250mhz)
await Timer(100, 'ns')
@ -308,8 +311,9 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
for k in range(1, 3):
getattr(self.dut, f"qsfp{k}_mac_rst").setimmediatevalue(0)
for ch in self.dut.ch:
ch.ch_mac_tx_rst.setimmediatevalue(0)
ch.ch_mac_rx_rst.setimmediatevalue(0)
await self.rc.enumerate()
@ -326,7 +330,7 @@ class TB(object):
@cocotb.test()
async def run_test_nic(dut):
tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
tb = TB(dut, msix_count=2**len(dut.uut.core_inst.core_pcie_inst.irq_index))
await tb.init()
@ -534,9 +538,10 @@ pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
def test_fpga_core(request):
dut = "fpga_core"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
toplevel = f"test_{dut}"
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.v"),
os.path.join(rtl_dir, f"{dut}.v"),
os.path.join(rtl_dir, "common", "mqnic_core_pcie_ptile.v"),
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),

629
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/tb/fpga_core/test_fpga_core.v Normal file
View File

@ -0,0 +1,629 @@
/*
Copyright (c) 2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Testbench top-level module
*/
module test_fpga_core #
(
// FW and board IDs
parameter FPGA_ID = 32'hC32450DD,
parameter FW_ID = 32'h00000000,
parameter FW_VER = 32'h00_00_01_00,
parameter BOARD_ID = 32'h1172_A00D,
parameter BOARD_VER = 32'h01_00_00_00,
parameter BUILD_DATE = 32'd1563227611,
parameter GIT_HASH = 32'hdce357bf,
parameter RELEASE_INFO = 32'h00000000,
// Board configuration
parameter QSFP_CNT = 2,
parameter CH_CNT = QSFP_CNT,
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
parameter PORT_MASK = 0,
// Clock configuration
parameter CLK_PERIOD_NS_NUM = 4,
parameter CLK_PERIOD_NS_DENOM = 1,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 4096,
parameter PTP_CLK_PERIOD_NS_DENOM = 825,
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 8,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 131072,
parameter MAX_TX_SIZE = 9214,
parameter MAX_RX_SIZE = 9214,
parameter TX_RAM_SIZE = 131072,
parameter RX_RAM_SIZE = 131072,
// Application block configuration
parameter APP_ID = 32'h00000000,
parameter APP_ENABLE = 0,
parameter APP_CTRL_ENABLE = 1,
parameter APP_DMA_ENABLE = 1,
parameter APP_AXIS_DIRECT_ENABLE = 1,
parameter APP_AXIS_SYNC_ENABLE = 1,
parameter APP_AXIS_IF_ENABLE = 1,
parameter APP_STAT_ENABLE = 1,
// DMA interface configuration
parameter DMA_IMM_ENABLE = 0,
parameter DMA_IMM_WIDTH = 32,
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
parameter RAM_PIPELINE = 2,
// PCIe interface configuration
parameter SEG_COUNT = 2,
parameter SEG_DATA_WIDTH = 256,
parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32),
parameter SEG_HDR_WIDTH = 128,
parameter SEG_PRFX_WIDTH = 32,
parameter TX_SEQ_NUM_WIDTH = 6,
parameter PF_COUNT = 1,
parameter VF_COUNT = 0,
parameter PCIE_TAG_COUNT = 256,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24,
// AXI lite interface configuration (application control)
parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH,
parameter AXIL_APP_CTRL_ADDR_WIDTH = 24,
// Ethernet interface configuration
parameter AXIS_ETH_DATA_WIDTH = 512,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 0,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 2,
parameter AXIS_ETH_TX_TS_PIPELINE = 0,
parameter AXIS_ETH_RX_PIPELINE = 0,
parameter AXIS_ETH_RX_FIFO_PIPELINE = 2,
// Statistics counter subsystem
parameter STAT_ENABLE = 1,
parameter STAT_DMA_ENABLE = 1,
parameter STAT_PCIE_ENABLE = 1,
parameter STAT_INC_WIDTH = 24,
parameter STAT_ID_WIDTH = 12
)
(
/*
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_250mhz,
input wire rst_250mhz,
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
/*
* GPIO
*/
input wire user_pb,
output wire [3:0] user_led_g,
/*
* I2C
*/
input wire i2c2_scl_i,
output wire i2c2_scl_o,
output wire i2c2_scl_t,
input wire i2c2_sda_i,
output wire i2c2_sda_o,
output wire i2c2_sda_t,
output wire bmc_i2c2_disable,
/*
* P-Tile interface
*/
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data,
input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty,
input wire [SEG_COUNT-1:0] rx_st_sop,
input wire [SEG_COUNT-1:0] rx_st_eop,
input wire [SEG_COUNT-1:0] rx_st_valid,
output wire rx_st_ready,
input wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] rx_st_hdr,
input wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] rx_st_tlp_prfx,
input wire [SEG_COUNT-1:0] rx_st_vf_active,
input wire [SEG_COUNT*3-1:0] rx_st_func_num,
input wire [SEG_COUNT*11-1:0] rx_st_vf_num,
input wire [SEG_COUNT*3-1:0] rx_st_bar_range,
input wire [SEG_COUNT-1:0] rx_st_tlp_abort,
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
output wire [SEG_COUNT-1:0] tx_st_sop,
output wire [SEG_COUNT-1:0] tx_st_eop,
output wire [SEG_COUNT-1:0] tx_st_valid,
input wire tx_st_ready,
output wire [SEG_COUNT-1:0] tx_st_err,
output wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr,
output wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] tx_st_tlp_prfx,
output wire [11:0] rx_buffer_limit,
output wire [1:0] rx_buffer_limit_tdm_idx,
input wire [15:0] tx_cdts_limit,
input wire [2:0] tx_cdts_limit_tdm_idx,
input wire [15:0] tl_cfg_ctl,
input wire [4:0] tl_cfg_add,
input wire [2:0] tl_cfg_func
/*
* Ethernet: QSFP28
*/
// input wire [CH_CNT-1:0] qsfp_mac_tx_clk,
// input wire [CH_CNT-1:0] qsfp_mac_tx_rst,
// output wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_mac_tx_axis_tdata,
// output wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_mac_tx_axis_tkeep,
// output wire [CH_CNT-1:0] qsfp_mac_tx_axis_tvalid,
// input wire [CH_CNT-1:0] qsfp_mac_tx_axis_tready,
// output wire [CH_CNT-1:0] qsfp_mac_tx_axis_tlast,
// output wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfp_mac_tx_axis_tuser,
// output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_time,
// input wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_ts,
// input wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfp_mac_tx_ptp_ts_tag,
// input wire [CH_CNT-1:0] qsfp_mac_tx_ptp_ts_valid,
// input wire [CH_CNT-1:0] qsfp_mac_tx_status,
// output wire [CH_CNT-1:0] qsfp_mac_tx_lfc_req,
// output wire [CH_CNT*8-1:0] qsfp_mac_tx_pfc_req,
// input wire [CH_CNT-1:0] qsfp_mac_rx_clk,
// input wire [CH_CNT-1:0] qsfp_mac_rx_rst,
// input wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_mac_rx_axis_tdata,
// input wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_mac_rx_axis_tkeep,
// input wire [CH_CNT-1:0] qsfp_mac_rx_axis_tvalid,
// input wire [CH_CNT-1:0] qsfp_mac_rx_axis_tlast,
// input wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfp_mac_rx_axis_tuser,
// output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_rx_ptp_time,
// input wire [CH_CNT-1:0] qsfp_mac_rx_status,
// input wire [CH_CNT-1:0] qsfp_mac_rx_lfc_req,
// input wire [CH_CNT*8-1:0] qsfp_mac_rx_pfc_req
);
genvar n;
wire [CH_CNT-1:0] qsfp_mac_tx_clk;
wire [CH_CNT-1:0] qsfp_mac_tx_rst;
wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_mac_tx_axis_tdata;
wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_mac_tx_axis_tkeep;
wire [CH_CNT-1:0] qsfp_mac_tx_axis_tvalid;
wire [CH_CNT-1:0] qsfp_mac_tx_axis_tready;
wire [CH_CNT-1:0] qsfp_mac_tx_axis_tlast;
wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfp_mac_tx_axis_tuser;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_time;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_tx_ptp_ts;
wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfp_mac_tx_ptp_ts_tag;
wire [CH_CNT-1:0] qsfp_mac_tx_ptp_ts_valid;
wire [CH_CNT-1:0] qsfp_mac_tx_status;
wire [CH_CNT-1:0] qsfp_mac_tx_lfc_req;
wire [CH_CNT*8-1:0] qsfp_mac_tx_pfc_req;
wire [CH_CNT-1:0] qsfp_mac_rx_clk;
wire [CH_CNT-1:0] qsfp_mac_rx_rst;
wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfp_mac_rx_axis_tdata;
wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfp_mac_rx_axis_tkeep;
wire [CH_CNT-1:0] qsfp_mac_rx_axis_tvalid;
wire [CH_CNT-1:0] qsfp_mac_rx_axis_tlast;
wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfp_mac_rx_axis_tuser;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfp_mac_rx_ptp_time;
wire [CH_CNT-1:0] qsfp_mac_rx_status;
wire [CH_CNT-1:0] qsfp_mac_rx_lfc_req;
wire [CH_CNT*8-1:0] qsfp_mac_rx_pfc_req;
generate
for (n = 0; n < QSFP_CNT; n = n + 1) begin : ch
wire ch_mac_tx_clk;
wire ch_mac_tx_rst;
wire [AXIS_ETH_DATA_WIDTH-1:0] ch_mac_tx_axis_tdata;
wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_mac_tx_axis_tkeep;
wire ch_mac_tx_axis_tvalid;
wire ch_mac_tx_axis_tready;
wire ch_mac_tx_axis_tlast;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] ch_mac_tx_axis_tuser;
wire [PTP_TS_WIDTH-1:0] ch_mac_tx_ptp_time;
wire [PTP_TS_WIDTH-1:0] ch_mac_tx_ptp_ts;
wire [15:0] ch_mac_tx_ptp_ts_tag;
wire ch_mac_tx_ptp_ts_valid;
wire ch_mac_tx_status;
wire ch_mac_tx_lfc_req;
wire [7:0] ch_mac_tx_pfc_req;
wire ch_mac_rx_clk;
wire ch_mac_rx_rst;
wire [AXIS_ETH_DATA_WIDTH-1:0] ch_mac_rx_axis_tdata;
wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_mac_rx_axis_tkeep;
wire ch_mac_rx_axis_tvalid;
wire ch_mac_rx_axis_tlast;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] ch_mac_rx_axis_tuser;
wire [PTP_TS_WIDTH-1:0] ch_mac_rx_ptp_time;
wire ch_mac_rx_status;
wire ch_mac_rx_lfc_req;
wire [7:0] ch_mac_rx_pfc_req;
assign qsfp_mac_tx_clk[n +: 1] = ch_mac_tx_clk;
assign qsfp_mac_tx_rst[n +: 1] = ch_mac_tx_rst;
assign ch_mac_tx_axis_tdata = qsfp_mac_tx_axis_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH];
assign ch_mac_tx_axis_tkeep = qsfp_mac_tx_axis_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH];
assign ch_mac_tx_axis_tvalid = qsfp_mac_tx_axis_tvalid[n +: 1];
assign qsfp_mac_tx_axis_tready[n +: 1] = ch_mac_tx_axis_tready;
assign ch_mac_tx_axis_tlast = qsfp_mac_tx_axis_tlast[n +: 1];
assign ch_mac_tx_axis_tuser = qsfp_mac_tx_axis_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH];
assign ch_mac_tx_ptp_time = qsfp_mac_tx_ptp_time[n*PTP_TS_WIDTH +: PTP_TS_WIDTH];
assign qsfp_mac_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = ch_mac_tx_ptp_ts;
assign qsfp_mac_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH] = ch_mac_tx_ptp_ts_tag;
assign qsfp_mac_tx_ptp_ts_valid[n +: 1] = ch_mac_tx_ptp_ts_valid;
assign qsfp_mac_tx_status[n +: 1] = ch_mac_tx_status;
assign ch_mac_tx_lfc_req = qsfp_mac_tx_lfc_req[n +: 1];
assign ch_mac_tx_pfc_req = qsfp_mac_tx_pfc_req[n*8 +: 8];
assign qsfp_mac_rx_clk[n +: 1] = ch_mac_rx_clk;
assign qsfp_mac_rx_rst[n +: 1] = ch_mac_rx_rst;
assign qsfp_mac_rx_axis_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH] = ch_mac_rx_axis_tdata;
assign qsfp_mac_rx_axis_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH] = ch_mac_rx_axis_tkeep;
assign qsfp_mac_rx_axis_tvalid[n +: 1] = ch_mac_rx_axis_tvalid;
assign qsfp_mac_rx_axis_tlast[n +: 1] = ch_mac_rx_axis_tlast;
assign qsfp_mac_rx_axis_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH] = ch_mac_rx_axis_tuser;
assign ch_mac_rx_ptp_time = qsfp_mac_rx_ptp_time[n*PTP_TS_WIDTH +: PTP_TS_WIDTH];
assign qsfp_mac_rx_status[n +: 1] = ch_mac_rx_status;
assign qsfp_mac_rx_lfc_req[n +: 1] = ch_mac_rx_lfc_req;
assign qsfp_mac_rx_pfc_req[n*8 +: 8] = ch_mac_rx_pfc_req;
end
endgenerate
fpga_core #(
// FW and board IDs
.FPGA_ID(FPGA_ID),
.FW_ID(FW_ID),
.FW_VER(FW_VER),
.BOARD_ID(BOARD_ID),
.BOARD_VER(BOARD_VER),
.BUILD_DATE(BUILD_DATE),
.GIT_HASH(GIT_HASH),
.RELEASE_INFO(RELEASE_INFO),
// Board configuration
.QSFP_CNT(QSFP_CNT),
.CH_CNT(CH_CNT),
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_MASK(PORT_MASK),
// Clock configuration
.CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM),
.CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE),
// Application block configuration
.APP_ID(APP_ID),
.APP_ENABLE(APP_ENABLE),
.APP_CTRL_ENABLE(APP_CTRL_ENABLE),
.APP_DMA_ENABLE(APP_DMA_ENABLE),
.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
.APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE),
.APP_STAT_ENABLE(APP_STAT_ENABLE),
// DMA interface configuration
.DMA_IMM_ENABLE(DMA_IMM_ENABLE),
.DMA_IMM_WIDTH(DMA_IMM_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
// PCIe interface configuration
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH),
.SEG_HDR_WIDTH(SEG_HDR_WIDTH),
.SEG_PRFX_WIDTH(SEG_PRFX_WIDTH),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(PF_COUNT),
.VF_COUNT(VF_COUNT),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
// AXI lite interface configuration (application control)
.AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH),
.AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH),
// Ethernet interface configuration
.AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH),
.AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
.AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
.AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE),
.AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE),
.AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE),
.AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE),
.AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE),
// Statistics counter subsystem
.STAT_ENABLE(STAT_ENABLE),
.STAT_DMA_ENABLE(STAT_DMA_ENABLE),
.STAT_PCIE_ENABLE(STAT_PCIE_ENABLE),
.STAT_INC_WIDTH(STAT_INC_WIDTH),
.STAT_ID_WIDTH(STAT_ID_WIDTH)
)
uut (
/*
* Clock: 250 MHz
* Synchronous reset
*/
.clk_250mhz(clk_250mhz),
.rst_250mhz(rst_250mhz),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* GPIO
*/
.user_pb(user_pb),
.user_led_g(user_led_g),
/*
* I2C
*/
.i2c2_scl_i(i2c2_scl_i),
.i2c2_scl_o(i2c2_scl_o),
.i2c2_scl_t(i2c2_scl_t),
.i2c2_sda_i(i2c2_sda_i),
.i2c2_sda_o(i2c2_sda_o),
.i2c2_sda_t(i2c2_sda_t),
.bmc_i2c2_disable(bmc_i2c2_disable),
/*
* P-Tile interface
*/
.rx_st_data(rx_st_data),
.rx_st_empty(rx_st_empty),
.rx_st_sop(rx_st_sop),
.rx_st_eop(rx_st_eop),
.rx_st_valid(rx_st_valid),
.rx_st_ready(rx_st_ready),
.rx_st_hdr(rx_st_hdr),
.rx_st_tlp_prfx(rx_st_tlp_prfx),
.rx_st_vf_active(rx_st_vf_active),
.rx_st_func_num(rx_st_func_num),
.rx_st_vf_num(rx_st_vf_num),
.rx_st_bar_range(rx_st_bar_range),
.rx_st_tlp_abort(rx_st_tlp_abort),
.tx_st_data(tx_st_data),
.tx_st_sop(tx_st_sop),
.tx_st_eop(tx_st_eop),
.tx_st_valid(tx_st_valid),
.tx_st_ready(tx_st_ready),
.tx_st_err(tx_st_err),
.tx_st_hdr(tx_st_hdr),
.tx_st_tlp_prfx(tx_st_tlp_prfx),
.rx_buffer_limit(rx_buffer_limit),
.rx_buffer_limit_tdm_idx(rx_buffer_limit_tdm_idx),
.tx_cdts_limit(tx_cdts_limit),
.tx_cdts_limit_tdm_idx(tx_cdts_limit_tdm_idx),
.tl_cfg_ctl(tl_cfg_ctl),
.tl_cfg_add(tl_cfg_add),
.tl_cfg_func(tl_cfg_func),
/*
* Ethernet: QSFP28
*/
.qsfp_mac_tx_clk(qsfp_mac_tx_clk),
.qsfp_mac_tx_rst(qsfp_mac_tx_rst),
.qsfp_mac_tx_axis_tdata(qsfp_mac_tx_axis_tdata),
.qsfp_mac_tx_axis_tkeep(qsfp_mac_tx_axis_tkeep),
.qsfp_mac_tx_axis_tvalid(qsfp_mac_tx_axis_tvalid),
.qsfp_mac_tx_axis_tready(qsfp_mac_tx_axis_tready),
.qsfp_mac_tx_axis_tlast(qsfp_mac_tx_axis_tlast),
.qsfp_mac_tx_axis_tuser(qsfp_mac_tx_axis_tuser),
.qsfp_mac_tx_ptp_time(qsfp_mac_tx_ptp_time),
.qsfp_mac_tx_ptp_ts(qsfp_mac_tx_ptp_ts),
.qsfp_mac_tx_ptp_ts_tag(qsfp_mac_tx_ptp_ts_tag),
.qsfp_mac_tx_ptp_ts_valid(qsfp_mac_tx_ptp_ts_valid),
.qsfp_mac_tx_status(qsfp_mac_tx_status),
.qsfp_mac_tx_lfc_req(qsfp_mac_tx_lfc_req),
.qsfp_mac_tx_pfc_req(qsfp_mac_tx_pfc_req),
.qsfp_mac_rx_clk(qsfp_mac_rx_clk),
.qsfp_mac_rx_rst(qsfp_mac_rx_rst),
.qsfp_mac_rx_axis_tdata(qsfp_mac_rx_axis_tdata),
.qsfp_mac_rx_axis_tkeep(qsfp_mac_rx_axis_tkeep),
.qsfp_mac_rx_axis_tvalid(qsfp_mac_rx_axis_tvalid),
.qsfp_mac_rx_axis_tlast(qsfp_mac_rx_axis_tlast),
.qsfp_mac_rx_axis_tuser(qsfp_mac_rx_axis_tuser),
.qsfp_mac_rx_ptp_time(qsfp_mac_rx_ptp_time),
.qsfp_mac_rx_status(qsfp_mac_rx_status),
.qsfp_mac_rx_lfc_req(qsfp_mac_rx_lfc_req),
.qsfp_mac_rx_pfc_req(qsfp_mac_rx_pfc_req)
);
endmodule
`resetall

164
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/eth_mac_dual_wrapper.v
View File

@ -33,6 +33,7 @@ THE SOFTWARE.
*/
module eth_mac_dual_wrapper #
(
parameter N_CH = 2,
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 8,
parameter DATA_WIDTH = 512,
@ -50,70 +51,39 @@ module eth_mac_dual_wrapper #
input wire [7:0] rx_serial_data_n,
input wire ref_clk,
output wire mac_1_clk,
output wire mac_1_rst,
output wire [N_CH-1:0] mac_clk,
output wire [N_CH-1:0] mac_rst,
input wire [PTP_TS_WIDTH-1:0] mac_1_ptp_time,
input wire [N_CH*PTP_TS_WIDTH-1:0] mac_ptp_time,
output wire [PTP_TS_WIDTH-1:0] mac_1_tx_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] mac_1_tx_ptp_ts_tag,
output wire mac_1_tx_ptp_ts_valid,
output wire [N_CH*PTP_TS_WIDTH-1:0] mac_tx_ptp_ts,
output wire [N_CH*PTP_TAG_WIDTH-1:0] mac_tx_ptp_ts_tag,
output wire [N_CH-1:0] mac_tx_ptp_ts_valid,
input wire [DATA_WIDTH-1:0] mac_1_tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] mac_1_tx_axis_tkeep,
input wire mac_1_tx_axis_tvalid,
output wire mac_1_tx_axis_tready,
input wire mac_1_tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] mac_1_tx_axis_tuser,
input wire [N_CH*DATA_WIDTH-1:0] mac_tx_axis_tdata,
input wire [N_CH*KEEP_WIDTH-1:0] mac_tx_axis_tkeep,
input wire [N_CH-1:0] mac_tx_axis_tvalid,
output wire [N_CH-1:0] mac_tx_axis_tready,
input wire [N_CH-1:0] mac_tx_axis_tlast,
input wire [N_CH*TX_USER_WIDTH-1:0] mac_tx_axis_tuser,
output wire mac_1_tx_status,
input wire mac_1_tx_lfc_req,
input wire [7:0] mac_1_tx_pfc_req,
output wire [N_CH*1-1:0] mac_tx_status,
input wire [N_CH*1-1:0] mac_tx_lfc_req,
input wire [N_CH*8-1:0] mac_tx_pfc_req,
output wire [DATA_WIDTH-1:0] mac_1_rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] mac_1_rx_axis_tkeep,
output wire mac_1_rx_axis_tvalid,
output wire mac_1_rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] mac_1_rx_axis_tuser,
output wire [N_CH*DATA_WIDTH-1:0] mac_rx_axis_tdata,
output wire [N_CH*KEEP_WIDTH-1:0] mac_rx_axis_tkeep,
output wire [N_CH-1:0] mac_rx_axis_tvalid,
output wire [N_CH-1:0] mac_rx_axis_tlast,
output wire [N_CH*RX_USER_WIDTH-1:0] mac_rx_axis_tuser,
output wire mac_1_rx_status,
output wire mac_1_rx_lfc_req,
output wire [7:0] mac_1_rx_pfc_req,
output wire mac_2_clk,
output wire mac_2_rst,
input wire [PTP_TS_WIDTH-1:0] mac_2_ptp_time,
output wire [PTP_TS_WIDTH-1:0] mac_2_tx_ptp_ts,
output wire [PTP_TAG_WIDTH-1:0] mac_2_tx_ptp_ts_tag,
output wire mac_2_tx_ptp_ts_valid,
input wire [DATA_WIDTH-1:0] mac_2_tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] mac_2_tx_axis_tkeep,
input wire mac_2_tx_axis_tvalid,
output wire mac_2_tx_axis_tready,
input wire mac_2_tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] mac_2_tx_axis_tuser,
output wire mac_2_tx_status,
input wire mac_2_tx_lfc_req,
input wire [7:0] mac_2_tx_pfc_req,
output wire [DATA_WIDTH-1:0] mac_2_rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] mac_2_rx_axis_tkeep,
output wire mac_2_rx_axis_tvalid,
output wire mac_2_rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] mac_2_rx_axis_tuser,
output wire mac_2_rx_status,
output wire mac_2_rx_lfc_req,
output wire [7:0] mac_2_rx_pfc_req
output wire [N_CH*1-1:0] mac_rx_status,
output wire [N_CH*1-1:0] mac_rx_lfc_req,
output wire [N_CH*8-1:0] mac_rx_pfc_req
);
parameter N_CH = 2;
parameter XCVR_PER_MAC = 4;
parameter XCVR_CH = N_CH*XCVR_PER_MAC;
localparam XCVR_PER_MAC = 4;
localparam XCVR_CH = N_CH*XCVR_PER_MAC;
wire [N_CH*6-1:0] mac_pll_clk_d64;
wire [N_CH*6-1:0] mac_pll_clk_d66;
@ -122,9 +92,6 @@ wire [N_CH*6-1:0] mac_rec_clk_d66;
wire [N_CH-1:0] mac_tx_pll_locked;
wire [N_CH-1:0] mac_clk;
wire [N_CH-1:0] mac_rst;
wire [XCVR_CH*19-1:0] xcvr_reconfig_address;
wire [XCVR_CH-1:0] xcvr_reconfig_read;
wire [XCVR_CH-1:0] xcvr_reconfig_write;
@ -351,81 +318,22 @@ mac_13 mac_13_inst (
.o_rx_pause (mac_rx_pause[1*1 +: 1])
);
wire [N_CH*DATA_WIDTH-1:0] mac_rx_axis_tdata;
wire [N_CH*KEEP_WIDTH-1:0] mac_rx_axis_tkeep;
wire [N_CH-1:0] mac_rx_axis_tvalid;
wire [N_CH-1:0] mac_rx_axis_tlast;
wire [N_CH*RX_USER_WIDTH-1:0] mac_rx_axis_tuser;
wire [N_CH*DATA_WIDTH-1:0] mac_tx_axis_tdata;
wire [N_CH*KEEP_WIDTH-1:0] mac_tx_axis_tkeep;
wire [N_CH-1:0] mac_tx_axis_tvalid;
wire [N_CH-1:0] mac_tx_axis_tready;
wire [N_CH-1:0] mac_tx_axis_tlast;
wire [N_CH*TX_USER_WIDTH-1:0] mac_tx_axis_tuser;
assign mac_clk[0] = mac_pll_clk_d64[4];
assign mac_clk[1] = mac_pll_clk_d64[10];
assign mac_1_clk = mac_clk[0];
assign mac_1_rst = mac_rst[0];
assign mac_ptp_tod = mac_ptp_time;
assign mac_ptp_tod[0*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_1_ptp_time;
assign mac_tx_ptp_ts = mac_ptp_ets;
assign mac_tx_ptp_ts_tag = mac_ptp_ets_fp;
assign mac_tx_ptp_ts_valid = mac_ptp_ets_valid;
assign mac_1_tx_ptp_ts = mac_ptp_ets[0*PTP_TS_WIDTH +: PTP_TS_WIDTH];
assign mac_1_tx_ptp_ts_tag = mac_ptp_ets_fp[0*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
assign mac_1_tx_ptp_ts_valid = mac_ptp_ets_valid[0];
assign mac_tx_status = mac_tx_lanes_stable;
assign mac_tx_pause = mac_tx_lfc_req;
assign mac_tx_pfc = mac_tx_pfc_req;
assign mac_tx_axis_tdata[0*DATA_WIDTH +: DATA_WIDTH] = mac_1_tx_axis_tdata;
assign mac_tx_axis_tkeep[0*KEEP_WIDTH +: KEEP_WIDTH] = mac_1_tx_axis_tkeep;
assign mac_tx_axis_tvalid[0] = mac_1_tx_axis_tvalid;
assign mac_1_tx_axis_tready = mac_tx_axis_tready[0];
assign mac_tx_axis_tlast[0] = mac_1_tx_axis_tlast;
assign mac_tx_axis_tuser[0*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_1_tx_axis_tuser;
assign mac_1_tx_status = mac_tx_lanes_stable[0*1 +: 1];
assign mac_tx_pause[0*1 +: 1] = mac_1_tx_lfc_req;
assign mac_tx_pfc[0*8 +: 8] = mac_1_tx_pfc_req;
assign mac_1_rx_axis_tdata = mac_rx_axis_tdata[0*DATA_WIDTH +: DATA_WIDTH];
assign mac_1_rx_axis_tkeep = mac_rx_axis_tkeep[0*KEEP_WIDTH +: KEEP_WIDTH];
assign mac_1_rx_axis_tvalid = mac_rx_axis_tvalid[0];
assign mac_1_rx_axis_tlast = mac_rx_axis_tlast[0];
assign mac_1_rx_axis_tuser = mac_rx_axis_tuser[0*RX_USER_WIDTH +: RX_USER_WIDTH];
assign mac_1_rx_status = mac_rx_pcs_ready[0*1 +: 1];
assign mac_1_rx_lfc_req = mac_rx_pause[0*1 +: 1];
assign mac_1_rx_pfc_req = mac_rx_pfc[0*8 +: 8];
assign mac_2_clk = mac_clk[1];
assign mac_2_rst = mac_rst[1];
assign mac_ptp_tod[1*PTP_TS_WIDTH +: PTP_TS_WIDTH] = mac_2_ptp_time;
assign mac_2_tx_ptp_ts = mac_ptp_ets[1*PTP_TS_WIDTH +: PTP_TS_WIDTH];
assign mac_2_tx_ptp_ts_tag = mac_ptp_ets_fp[1*PTP_TAG_WIDTH +: PTP_TAG_WIDTH];
assign mac_2_tx_ptp_ts_valid = mac_ptp_ets_valid[1];
assign mac_tx_axis_tdata[1*DATA_WIDTH +: DATA_WIDTH] = mac_2_tx_axis_tdata;
assign mac_tx_axis_tkeep[1*KEEP_WIDTH +: KEEP_WIDTH] = mac_2_tx_axis_tkeep;
assign mac_tx_axis_tvalid[1] = mac_2_tx_axis_tvalid;
assign mac_2_tx_axis_tready = mac_tx_axis_tready[1];
assign mac_tx_axis_tlast[1] = mac_2_tx_axis_tlast;
assign mac_tx_axis_tuser[1*TX_USER_WIDTH +: TX_USER_WIDTH] = mac_2_tx_axis_tuser;
assign mac_2_tx_status = mac_tx_lanes_stable[1*1 +: 1];
assign mac_tx_pause[1*1 +: 1] = mac_2_tx_lfc_req;
assign mac_tx_pfc[1*8 +: 8] = mac_2_tx_pfc_req;
assign mac_2_rx_axis_tdata = mac_rx_axis_tdata[1*DATA_WIDTH +: DATA_WIDTH];
assign mac_2_rx_axis_tkeep = mac_rx_axis_tkeep[1*KEEP_WIDTH +: KEEP_WIDTH];
assign mac_2_rx_axis_tvalid = mac_rx_axis_tvalid[1];
assign mac_2_rx_axis_tlast = mac_rx_axis_tlast[1];
assign mac_2_rx_axis_tuser = mac_rx_axis_tuser[1*RX_USER_WIDTH +: RX_USER_WIDTH];
assign mac_2_rx_status = mac_rx_pcs_ready[1*1 +: 1];
assign mac_2_rx_lfc_req = mac_rx_pause[1*1 +: 1];
assign mac_2_rx_pfc_req = mac_rx_pfc[1*8 +: 8];
assign mac_rx_status = mac_rx_pcs_ready;
assign mac_rx_lfc_req = mac_rx_pause;
assign mac_rx_pfc_req = mac_rx_pfc;
generate

458
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v
View File

@ -443,68 +443,47 @@ pcie pcie_hip_inst (
.ninit_done(ninit_done)
);
// QSFP28 interfaces
// QSFP-DD interfaces
localparam QSFPDD_CNT = 2;
localparam CH_CNT = QSFPDD_CNT*2;
wire [CH_CNT-1:0] qsfpdd_mac_tx_clk;
wire [CH_CNT-1:0] qsfpdd_mac_tx_rst;
wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_tx_axis_tdata;
wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_tx_axis_tkeep;
wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tvalid;
wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tready;
wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tlast;
wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd_mac_tx_axis_tuser;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_time;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts;
wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts_tag;
wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_ts_valid;
wire [CH_CNT-1:0] qsfpdd_mac_tx_status;
wire [CH_CNT-1:0] qsfpdd_mac_tx_lfc_req;
wire [CH_CNT*8-1:0] qsfpdd_mac_tx_pfc_req;
wire [CH_CNT-1:0] qsfpdd_mac_rx_clk;
wire [CH_CNT-1:0] qsfpdd_mac_rx_rst;
wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_rx_axis_tdata;
wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_rx_axis_tkeep;
wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tvalid;
wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tlast;
wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd_mac_rx_axis_tuser;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_rx_ptp_time;
wire [CH_CNT-1:0] qsfpdd_mac_rx_status;
wire [CH_CNT-1:0] qsfpdd_mac_rx_lfc_req;
wire [CH_CNT*8-1:0] qsfpdd_mac_rx_pfc_req;
// QSFP-DD 0
wire qsfpdd0_mac_1_clk_int;
wire qsfpdd0_mac_1_rst_int;
wire [PTP_TS_WIDTH-1:0] qsfpdd0_mac_1_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfpdd0_mac_1_tx_ptp_ts_int;
wire [PTP_TAG_WIDTH-1:0] qsfpdd0_mac_1_tx_ptp_ts_tag_int;
wire qsfpdd0_mac_1_tx_ptp_ts_valid_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd0_mac_1_tx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd0_mac_1_tx_axis_tkeep_int;
wire qsfpdd0_mac_1_tx_axis_tvalid_int;
wire qsfpdd0_mac_1_tx_axis_tready_int;
wire qsfpdd0_mac_1_tx_axis_tlast_int;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd0_mac_1_tx_axis_tuser_int;
wire qsfpdd0_mac_1_tx_status_int;
wire qsfpdd0_mac_1_tx_lfc_req_int;
wire [7:0] qsfpdd0_mac_1_tx_pfc_req_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd0_mac_1_rx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd0_mac_1_rx_axis_tkeep_int;
wire qsfpdd0_mac_1_rx_axis_tvalid_int;
wire qsfpdd0_mac_1_rx_axis_tlast_int;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd0_mac_1_rx_axis_tuser_int;
wire qsfpdd0_mac_1_rx_status_int;
wire qsfpdd0_mac_1_rx_lfc_req_int;
wire [7:0] qsfpdd0_mac_1_rx_pfc_req_int;
wire qsfpdd0_mac_2_clk_int;
wire qsfpdd0_mac_2_rst_int;
wire [PTP_TS_WIDTH-1:0] qsfpdd0_mac_2_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfpdd0_mac_2_tx_ptp_ts_int;
wire [PTP_TAG_WIDTH-1:0] qsfpdd0_mac_2_tx_ptp_ts_tag_int;
wire qsfpdd0_mac_2_tx_ptp_ts_valid_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd0_mac_2_tx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd0_mac_2_tx_axis_tkeep_int;
wire qsfpdd0_mac_2_tx_axis_tvalid_int;
wire qsfpdd0_mac_2_tx_axis_tready_int;
wire qsfpdd0_mac_2_tx_axis_tlast_int;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd0_mac_2_tx_axis_tuser_int;
wire qsfpdd0_mac_2_tx_status_int;
wire qsfpdd0_mac_2_tx_lfc_req_int;
wire [7:0] qsfpdd0_mac_2_tx_pfc_req_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd0_mac_2_rx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd0_mac_2_rx_axis_tkeep_int;
wire qsfpdd0_mac_2_rx_axis_tvalid_int;
wire qsfpdd0_mac_2_rx_axis_tlast_int;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd0_mac_2_rx_axis_tuser_int;
wire qsfpdd0_mac_2_rx_status_int;
wire qsfpdd0_mac_2_rx_lfc_req_int;
wire [7:0] qsfpdd0_mac_2_rx_pfc_req_int;
assign qsfpdd_mac_rx_clk[0*2 +: 2] = qsfpdd_mac_tx_clk[0*2 +: 2];
assign qsfpdd_mac_rx_rst[0*2 +: 2] = qsfpdd_mac_tx_rst[0*2 +: 2];
eth_mac_dual_wrapper #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
@ -524,127 +503,40 @@ qsfpdd0_mac_inst (
// .rx_serial_data_n({qsfpdd0_rx_n[7], qsfpdd0_rx_n[5], qsfpdd0_rx_n[6], qsfpdd0_rx_n[4], qsfpdd0_rx_n[3], qsfpdd0_rx_n[1], qsfpdd0_rx_n[2], qsfpdd0_rx_n[0]}),
.ref_clk(refclk_156m_qsfpdd_p),
.mac_1_clk(qsfpdd0_mac_1_clk_int),
.mac_1_rst(qsfpdd0_mac_1_rst_int),
.mac_clk(qsfpdd_mac_tx_clk[0*2 +: 2*1]),
.mac_rst(qsfpdd_mac_tx_rst[0*2 +: 2*1]),
.mac_1_ptp_time(qsfpdd0_mac_1_ptp_time_int),
.mac_ptp_time(qsfpdd_mac_tx_ptp_time[0*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
.mac_1_tx_ptp_ts(qsfpdd0_mac_1_tx_ptp_ts_int),
.mac_1_tx_ptp_ts_tag(qsfpdd0_mac_1_tx_ptp_ts_tag_int),
.mac_1_tx_ptp_ts_valid(qsfpdd0_mac_1_tx_ptp_ts_valid_int),
.mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[0*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
.mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[0*2*TX_TAG_WIDTH +: 2*TX_TAG_WIDTH]),
.mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[0*2 +: 2*1]),
.mac_1_tx_axis_tdata(qsfpdd0_mac_1_tx_axis_tdata_int),
.mac_1_tx_axis_tkeep(qsfpdd0_mac_1_tx_axis_tkeep_int),
.mac_1_tx_axis_tvalid(qsfpdd0_mac_1_tx_axis_tvalid_int),
.mac_1_tx_axis_tready(qsfpdd0_mac_1_tx_axis_tready_int),
.mac_1_tx_axis_tlast(qsfpdd0_mac_1_tx_axis_tlast_int),
.mac_1_tx_axis_tuser(qsfpdd0_mac_1_tx_axis_tuser_int),
.mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[0*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
.mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[0*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
.mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[0*2 +: 2*1]),
.mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[0*2 +: 2*1]),
.mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[0*2 +: 2*1]),
.mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[0*2*AXIS_ETH_TX_USER_WIDTH +: 2*AXIS_ETH_TX_USER_WIDTH]),
.mac_1_tx_status(qsfpdd0_mac_1_tx_status_int),
.mac_1_tx_lfc_req(qsfpdd0_mac_1_tx_lfc_req_int),
.mac_1_tx_pfc_req(qsfpdd0_mac_1_tx_pfc_req_int),
.mac_tx_status(qsfpdd_mac_tx_status[0*2 +: 2*1]),
.mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[0*2 +: 2*1]),
.mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[0*2*8 +: 2*8]),
.mac_1_rx_axis_tdata(qsfpdd0_mac_1_rx_axis_tdata_int),
.mac_1_rx_axis_tkeep(qsfpdd0_mac_1_rx_axis_tkeep_int),
.mac_1_rx_axis_tvalid(qsfpdd0_mac_1_rx_axis_tvalid_int),
.mac_1_rx_axis_tlast(qsfpdd0_mac_1_rx_axis_tlast_int),
.mac_1_rx_axis_tuser(qsfpdd0_mac_1_rx_axis_tuser_int),
.mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[0*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
.mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[0*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
.mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[0*2 +: 2*1]),
.mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[0*2 +: 2*1]),
.mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[0*2*AXIS_ETH_RX_USER_WIDTH +: 2*AXIS_ETH_RX_USER_WIDTH]),
.mac_1_rx_status(qsfpdd0_mac_1_rx_status_int),
.mac_1_rx_lfc_req(qsfpdd0_mac_1_rx_lfc_req_int),
.mac_1_rx_pfc_req(qsfpdd0_mac_1_rx_pfc_req_int),
.mac_2_clk(qsfpdd0_mac_2_clk_int),
.mac_2_rst(qsfpdd0_mac_2_rst_int),
.mac_2_ptp_time(qsfpdd0_mac_2_ptp_time_int),
.mac_2_tx_ptp_ts(qsfpdd0_mac_2_tx_ptp_ts_int),
.mac_2_tx_ptp_ts_tag(qsfpdd0_mac_2_tx_ptp_ts_tag_int),
.mac_2_tx_ptp_ts_valid(qsfpdd0_mac_2_tx_ptp_ts_valid_int),
.mac_2_tx_axis_tdata(qsfpdd0_mac_2_tx_axis_tdata_int),
.mac_2_tx_axis_tkeep(qsfpdd0_mac_2_tx_axis_tkeep_int),
.mac_2_tx_axis_tvalid(qsfpdd0_mac_2_tx_axis_tvalid_int),
.mac_2_tx_axis_tready(qsfpdd0_mac_2_tx_axis_tready_int),
.mac_2_tx_axis_tlast(qsfpdd0_mac_2_tx_axis_tlast_int),
.mac_2_tx_axis_tuser(qsfpdd0_mac_2_tx_axis_tuser_int),
.mac_2_tx_status(qsfpdd0_mac_2_tx_status_int),
.mac_2_tx_lfc_req(qsfpdd0_mac_2_tx_lfc_req_int),
.mac_2_tx_pfc_req(qsfpdd0_mac_2_tx_pfc_req_int),
.mac_2_rx_axis_tdata(qsfpdd0_mac_2_rx_axis_tdata_int),
.mac_2_rx_axis_tkeep(qsfpdd0_mac_2_rx_axis_tkeep_int),
.mac_2_rx_axis_tvalid(qsfpdd0_mac_2_rx_axis_tvalid_int),
.mac_2_rx_axis_tlast(qsfpdd0_mac_2_rx_axis_tlast_int),
.mac_2_rx_axis_tuser(qsfpdd0_mac_2_rx_axis_tuser_int),
.mac_2_rx_status(qsfpdd0_mac_2_rx_status_int),
.mac_2_rx_lfc_req(qsfpdd0_mac_2_rx_lfc_req_int),
.mac_2_rx_pfc_req(qsfpdd0_mac_2_rx_pfc_req_int)
.mac_rx_status(qsfpdd_mac_rx_status[0*2 +: 2*1]),
.mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[0*2 +: 2*1]),
.mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[0*2*8 +: 2*8])
);
// QSFP-DD 1
wire qsfpdd1_mac_1_clk_int;
wire qsfpdd1_mac_1_rst_int;
wire [PTP_TS_WIDTH-1:0] qsfpdd1_mac_1_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfpdd1_mac_1_tx_ptp_ts_int;
wire [PTP_TAG_WIDTH-1:0] qsfpdd1_mac_1_tx_ptp_ts_tag_int;
wire qsfpdd1_mac_1_tx_ptp_ts_valid_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd1_mac_1_tx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd1_mac_1_tx_axis_tkeep_int;
wire qsfpdd1_mac_1_tx_axis_tvalid_int;
wire qsfpdd1_mac_1_tx_axis_tready_int;
wire qsfpdd1_mac_1_tx_axis_tlast_int;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd1_mac_1_tx_axis_tuser_int;
wire qsfpdd1_mac_1_tx_status_int;
wire qsfpdd1_mac_1_tx_lfc_req_int;
wire [7:0] qsfpdd1_mac_1_tx_pfc_req_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd1_mac_1_rx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd1_mac_1_rx_axis_tkeep_int;
wire qsfpdd1_mac_1_rx_axis_tvalid_int;
wire qsfpdd1_mac_1_rx_axis_tlast_int;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd1_mac_1_rx_axis_tuser_int;
wire qsfpdd1_mac_1_rx_status_int;
wire qsfpdd1_mac_1_rx_lfc_req_int;
wire [7:0] qsfpdd1_mac_1_rx_pfc_req_int;
wire qsfpdd1_mac_2_clk_int;
wire qsfpdd1_mac_2_rst_int;
wire [PTP_TS_WIDTH-1:0] qsfpdd1_mac_2_ptp_time_int;
wire [PTP_TS_WIDTH-1:0] qsfpdd1_mac_2_tx_ptp_ts_int;
wire [PTP_TAG_WIDTH-1:0] qsfpdd1_mac_2_tx_ptp_ts_tag_int;
wire qsfpdd1_mac_2_tx_ptp_ts_valid_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd1_mac_2_tx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd1_mac_2_tx_axis_tkeep_int;
wire qsfpdd1_mac_2_tx_axis_tvalid_int;
wire qsfpdd1_mac_2_tx_axis_tready_int;
wire qsfpdd1_mac_2_tx_axis_tlast_int;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd1_mac_2_tx_axis_tuser_int;
wire qsfpdd1_mac_2_tx_status_int;
wire qsfpdd1_mac_2_tx_lfc_req_int;
wire [7:0] qsfpdd1_mac_2_tx_pfc_req_int;
wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd1_mac_2_rx_axis_tdata_int;
wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd1_mac_2_rx_axis_tkeep_int;
wire qsfpdd1_mac_2_rx_axis_tvalid_int;
wire qsfpdd1_mac_2_rx_axis_tlast_int;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd1_mac_2_rx_axis_tuser_int;
wire qsfpdd1_mac_2_rx_status_int;
wire qsfpdd1_mac_2_rx_lfc_req_int;
wire [7:0] qsfpdd1_mac_2_rx_pfc_req_int;
assign qsfpdd_mac_rx_clk[1*2 +: 2] = qsfpdd_mac_tx_clk[1*2 +: 2];
assign qsfpdd_mac_rx_rst[1*2 +: 2] = qsfpdd_mac_tx_rst[1*2 +: 2];
eth_mac_dual_wrapper #(
.PTP_TS_WIDTH(PTP_TS_WIDTH),
@ -664,65 +556,35 @@ qsfpdd1_mac_inst (
// .rx_serial_data_n({qsfpdd1_rx_n[7], qsfpdd1_rx_n[5], qsfpdd1_rx_n[6], qsfpdd1_rx_n[4], qsfpdd1_rx_n[3], qsfpdd1_rx_n[1], qsfpdd1_rx_n[2], qsfpdd1_rx_n[0]}),
.ref_clk(refclk_156m_qsfpdd_p),
.mac_1_clk(qsfpdd1_mac_1_clk_int),
.mac_1_rst(qsfpdd1_mac_1_rst_int),
.mac_clk(qsfpdd_mac_tx_clk[1*2 +: 2*1]),
.mac_rst(qsfpdd_mac_tx_rst[1*2 +: 2*1]),
.mac_1_ptp_time(qsfpdd1_mac_1_ptp_time_int),
.mac_ptp_time(qsfpdd_mac_tx_ptp_time[1*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
.mac_1_tx_ptp_ts(qsfpdd1_mac_1_tx_ptp_ts_int),
.mac_1_tx_ptp_ts_tag(qsfpdd1_mac_1_tx_ptp_ts_tag_int),
.mac_1_tx_ptp_ts_valid(qsfpdd1_mac_1_tx_ptp_ts_valid_int),
.mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts[1*2*PTP_TS_WIDTH +: 2*PTP_TS_WIDTH]),
.mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag[1*2*TX_TAG_WIDTH +: 2*TX_TAG_WIDTH]),
.mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid[1*2 +: 2*1]),
.mac_1_tx_axis_tdata(qsfpdd1_mac_1_tx_axis_tdata_int),
.mac_1_tx_axis_tkeep(qsfpdd1_mac_1_tx_axis_tkeep_int),
.mac_1_tx_axis_tvalid(qsfpdd1_mac_1_tx_axis_tvalid_int),
.mac_1_tx_axis_tready(qsfpdd1_mac_1_tx_axis_tready_int),
.mac_1_tx_axis_tlast(qsfpdd1_mac_1_tx_axis_tlast_int),
.mac_1_tx_axis_tuser(qsfpdd1_mac_1_tx_axis_tuser_int),
.mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata[1*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
.mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep[1*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
.mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid[1*2 +: 2*1]),
.mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready[1*2 +: 2*1]),
.mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast[1*2 +: 2*1]),
.mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser[1*2*AXIS_ETH_TX_USER_WIDTH +: 2*AXIS_ETH_TX_USER_WIDTH]),
.mac_1_tx_status(qsfpdd1_mac_1_tx_status_int),
.mac_1_tx_lfc_req(qsfpdd1_mac_1_tx_lfc_req_int),
.mac_1_tx_pfc_req(qsfpdd1_mac_1_tx_pfc_req_int),
.mac_tx_status(qsfpdd_mac_tx_status[1*2 +: 2*1]),
.mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req[1*2 +: 2*1]),
.mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req[1*2*8 +: 2*8]),
.mac_1_rx_axis_tdata(qsfpdd1_mac_1_rx_axis_tdata_int),
.mac_1_rx_axis_tkeep(qsfpdd1_mac_1_rx_axis_tkeep_int),
.mac_1_rx_axis_tvalid(qsfpdd1_mac_1_rx_axis_tvalid_int),
.mac_1_rx_axis_tlast(qsfpdd1_mac_1_rx_axis_tlast_int),
.mac_1_rx_axis_tuser(qsfpdd1_mac_1_rx_axis_tuser_int),
.mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata[1*2*AXIS_ETH_DATA_WIDTH +: 2*AXIS_ETH_DATA_WIDTH]),
.mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep[1*2*AXIS_ETH_KEEP_WIDTH +: 2*AXIS_ETH_KEEP_WIDTH]),
.mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid[1*2 +: 2*1]),
.mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast[1*2 +: 2*1]),
.mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser[1*2*AXIS_ETH_RX_USER_WIDTH +: 2*AXIS_ETH_RX_USER_WIDTH]),
.mac_1_rx_status(qsfpdd1_mac_1_rx_status_int),
.mac_1_rx_lfc_req(qsfpdd1_mac_1_rx_lfc_req_int),
.mac_1_rx_pfc_req(qsfpdd1_mac_1_rx_pfc_req_int),
.mac_2_clk(qsfpdd1_mac_2_clk_int),
.mac_2_rst(qsfpdd1_mac_2_rst_int),
.mac_2_ptp_time(qsfpdd1_mac_2_ptp_time_int),
.mac_2_tx_ptp_ts(qsfpdd1_mac_2_tx_ptp_ts_int),
.mac_2_tx_ptp_ts_tag(qsfpdd1_mac_2_tx_ptp_ts_tag_int),
.mac_2_tx_ptp_ts_valid(qsfpdd1_mac_2_tx_ptp_ts_valid_int),
.mac_2_tx_axis_tdata(qsfpdd1_mac_2_tx_axis_tdata_int),
.mac_2_tx_axis_tkeep(qsfpdd1_mac_2_tx_axis_tkeep_int),
.mac_2_tx_axis_tvalid(qsfpdd1_mac_2_tx_axis_tvalid_int),
.mac_2_tx_axis_tready(qsfpdd1_mac_2_tx_axis_tready_int),
.mac_2_tx_axis_tlast(qsfpdd1_mac_2_tx_axis_tlast_int),
.mac_2_tx_axis_tuser(qsfpdd1_mac_2_tx_axis_tuser_int),
.mac_2_tx_status(qsfpdd1_mac_2_tx_status_int),
.mac_2_tx_lfc_req(qsfpdd1_mac_2_tx_lfc_req_int),
.mac_2_tx_pfc_req(qsfpdd1_mac_2_tx_pfc_req_int),
.mac_2_rx_axis_tdata(qsfpdd1_mac_2_rx_axis_tdata_int),
.mac_2_rx_axis_tkeep(qsfpdd1_mac_2_rx_axis_tkeep_int),
.mac_2_rx_axis_tvalid(qsfpdd1_mac_2_rx_axis_tvalid_int),
.mac_2_rx_axis_tlast(qsfpdd1_mac_2_rx_axis_tlast_int),
.mac_2_rx_axis_tuser(qsfpdd1_mac_2_rx_axis_tuser_int),
.mac_2_rx_status(qsfpdd1_mac_2_rx_status_int),
.mac_2_rx_lfc_req(qsfpdd1_mac_2_rx_lfc_req_int),
.mac_2_rx_pfc_req(qsfpdd1_mac_2_rx_pfc_req_int)
.mac_rx_status(qsfpdd_mac_rx_status[1*2 +: 2*1]),
.mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req[1*2 +: 2*1]),
.mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req[1*2*8 +: 2*8])
);
wire ptp_clk;
@ -731,8 +593,8 @@ wire ptp_sample_clk;
assign ptp_sample_clk = clk_100mhz;
assign ptp_clk = qsfpdd0_mac_1_clk_int;
assign ptp_rst = qsfpdd0_mac_1_rst_int;
assign ptp_clk = qsfpdd_mac_tx_clk[0];
assign ptp_rst = qsfpdd_mac_tx_rst[0];
fpga_core #(
// FW and board IDs
@ -745,6 +607,10 @@ fpga_core #(
.GIT_HASH(GIT_HASH),
.RELEASE_INFO(RELEASE_INFO),
// Board configuration
.QSFPDD_CNT(QSFPDD_CNT),
.CH_CNT(CH_CNT),
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
@ -939,125 +805,39 @@ core_inst (
/*
* Ethernet: QSFP-DD
*/
.qsfpdd0_mac_1_clk(qsfpdd0_mac_1_clk_int),
.qsfpdd0_mac_1_rst(qsfpdd0_mac_1_rst_int),
.qsfpdd_mac_tx_clk(qsfpdd_mac_tx_clk),
.qsfpdd_mac_tx_rst(qsfpdd_mac_tx_rst),
.qsfpdd0_mac_1_ptp_time(qsfpdd0_mac_1_ptp_time_int),
.qsfpdd_mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata),
.qsfpdd_mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep),
.qsfpdd_mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid),
.qsfpdd_mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready),
.qsfpdd_mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast),
.qsfpdd_mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser),
.qsfpdd0_mac_1_tx_ptp_ts(qsfpdd0_mac_1_tx_ptp_ts_int),
.qsfpdd0_mac_1_tx_ptp_ts_tag(qsfpdd0_mac_1_tx_ptp_ts_tag_int),
.qsfpdd0_mac_1_tx_ptp_ts_valid(qsfpdd0_mac_1_tx_ptp_ts_valid_int),
.qsfpdd_mac_tx_ptp_time(qsfpdd_mac_tx_ptp_time),
.qsfpdd_mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts),
.qsfpdd_mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag),
.qsfpdd_mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid),
.qsfpdd0_mac_1_tx_axis_tdata(qsfpdd0_mac_1_tx_axis_tdata_int),
.qsfpdd0_mac_1_tx_axis_tkeep(qsfpdd0_mac_1_tx_axis_tkeep_int),
.qsfpdd0_mac_1_tx_axis_tvalid(qsfpdd0_mac_1_tx_axis_tvalid_int),
.qsfpdd0_mac_1_tx_axis_tready(qsfpdd0_mac_1_tx_axis_tready_int),
.qsfpdd0_mac_1_tx_axis_tlast(qsfpdd0_mac_1_tx_axis_tlast_int),
.qsfpdd0_mac_1_tx_axis_tuser(qsfpdd0_mac_1_tx_axis_tuser_int),
.qsfpdd_mac_tx_status(qsfpdd_mac_tx_status),
.qsfpdd_mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req),
.qsfpdd_mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req),
.qsfpdd0_mac_1_tx_status(qsfpdd0_mac_1_tx_status_int),
.qsfpdd0_mac_1_tx_lfc_req(qsfpdd0_mac_1_tx_lfc_req_int),
.qsfpdd0_mac_1_tx_pfc_req(qsfpdd0_mac_1_tx_pfc_req_int),
.qsfpdd_mac_rx_clk(qsfpdd_mac_rx_clk),
.qsfpdd_mac_rx_rst(qsfpdd_mac_rx_rst),
.qsfpdd0_mac_1_rx_axis_tdata(qsfpdd0_mac_1_rx_axis_tdata_int),
.qsfpdd0_mac_1_rx_axis_tkeep(qsfpdd0_mac_1_rx_axis_tkeep_int),
.qsfpdd0_mac_1_rx_axis_tvalid(qsfpdd0_mac_1_rx_axis_tvalid_int),
.qsfpdd0_mac_1_rx_axis_tlast(qsfpdd0_mac_1_rx_axis_tlast_int),
.qsfpdd0_mac_1_rx_axis_tuser(qsfpdd0_mac_1_rx_axis_tuser_int),
.qsfpdd_mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata),
.qsfpdd_mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep),
.qsfpdd_mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid),
.qsfpdd_mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast),
.qsfpdd_mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser),
.qsfpdd0_mac_1_rx_status(qsfpdd0_mac_1_rx_status_int),
.qsfpdd0_mac_1_rx_lfc_req(qsfpdd0_mac_1_rx_lfc_req_int),
.qsfpdd0_mac_1_rx_pfc_req(qsfpdd0_mac_1_rx_pfc_req_int),
.qsfpdd_mac_rx_ptp_time(qsfpdd_mac_rx_ptp_time),
.qsfpdd0_mac_2_clk(qsfpdd0_mac_2_clk_int),
.qsfpdd0_mac_2_rst(qsfpdd0_mac_2_rst_int),
.qsfpdd0_mac_2_ptp_time(qsfpdd0_mac_2_ptp_time_int),
.qsfpdd0_mac_2_tx_ptp_ts(qsfpdd0_mac_2_tx_ptp_ts_int),
.qsfpdd0_mac_2_tx_ptp_ts_tag(qsfpdd0_mac_2_tx_ptp_ts_tag_int),
.qsfpdd0_mac_2_tx_ptp_ts_valid(qsfpdd0_mac_2_tx_ptp_ts_valid_int),
.qsfpdd0_mac_2_tx_axis_tdata(qsfpdd0_mac_2_tx_axis_tdata_int),
.qsfpdd0_mac_2_tx_axis_tkeep(qsfpdd0_mac_2_tx_axis_tkeep_int),
.qsfpdd0_mac_2_tx_axis_tvalid(qsfpdd0_mac_2_tx_axis_tvalid_int),
.qsfpdd0_mac_2_tx_axis_tready(qsfpdd0_mac_2_tx_axis_tready_int),
.qsfpdd0_mac_2_tx_axis_tlast(qsfpdd0_mac_2_tx_axis_tlast_int),
.qsfpdd0_mac_2_tx_axis_tuser(qsfpdd0_mac_2_tx_axis_tuser_int),
.qsfpdd0_mac_2_tx_status(qsfpdd0_mac_2_tx_status_int),
.qsfpdd0_mac_2_tx_lfc_req(qsfpdd0_mac_2_tx_lfc_req_int),
.qsfpdd0_mac_2_tx_pfc_req(qsfpdd0_mac_2_tx_pfc_req_int),
.qsfpdd0_mac_2_rx_axis_tdata(qsfpdd0_mac_2_rx_axis_tdata_int),
.qsfpdd0_mac_2_rx_axis_tkeep(qsfpdd0_mac_2_rx_axis_tkeep_int),
.qsfpdd0_mac_2_rx_axis_tvalid(qsfpdd0_mac_2_rx_axis_tvalid_int),
.qsfpdd0_mac_2_rx_axis_tlast(qsfpdd0_mac_2_rx_axis_tlast_int),
.qsfpdd0_mac_2_rx_axis_tuser(qsfpdd0_mac_2_rx_axis_tuser_int),
.qsfpdd0_mac_2_rx_status(qsfpdd0_mac_2_rx_status_int),
.qsfpdd0_mac_2_rx_lfc_req(qsfpdd0_mac_2_rx_lfc_req_int),
.qsfpdd0_mac_2_rx_pfc_req(qsfpdd0_mac_2_rx_pfc_req_int),
.qsfpdd1_mac_1_clk(qsfpdd1_mac_1_clk_int),
.qsfpdd1_mac_1_rst(qsfpdd1_mac_1_rst_int),
.qsfpdd1_mac_1_ptp_time(qsfpdd1_mac_1_ptp_time_int),
.qsfpdd1_mac_1_tx_ptp_ts(qsfpdd1_mac_1_tx_ptp_ts_int),
.qsfpdd1_mac_1_tx_ptp_ts_tag(qsfpdd1_mac_1_tx_ptp_ts_tag_int),
.qsfpdd1_mac_1_tx_ptp_ts_valid(qsfpdd1_mac_1_tx_ptp_ts_valid_int),
.qsfpdd1_mac_1_tx_axis_tdata(qsfpdd1_mac_1_tx_axis_tdata_int),
.qsfpdd1_mac_1_tx_axis_tkeep(qsfpdd1_mac_1_tx_axis_tkeep_int),
.qsfpdd1_mac_1_tx_axis_tvalid(qsfpdd1_mac_1_tx_axis_tvalid_int),
.qsfpdd1_mac_1_tx_axis_tready(qsfpdd1_mac_1_tx_axis_tready_int),
.qsfpdd1_mac_1_tx_axis_tlast(qsfpdd1_mac_1_tx_axis_tlast_int),
.qsfpdd1_mac_1_tx_axis_tuser(qsfpdd1_mac_1_tx_axis_tuser_int),
.qsfpdd1_mac_1_tx_status(qsfpdd1_mac_1_tx_status_int),
.qsfpdd1_mac_1_tx_lfc_req(qsfpdd1_mac_1_tx_lfc_req_int),
.qsfpdd1_mac_1_tx_pfc_req(qsfpdd1_mac_1_tx_pfc_req_int),
.qsfpdd1_mac_1_rx_axis_tdata(qsfpdd1_mac_1_rx_axis_tdata_int),
.qsfpdd1_mac_1_rx_axis_tkeep(qsfpdd1_mac_1_rx_axis_tkeep_int),
.qsfpdd1_mac_1_rx_axis_tvalid(qsfpdd1_mac_1_rx_axis_tvalid_int),
.qsfpdd1_mac_1_rx_axis_tlast(qsfpdd1_mac_1_rx_axis_tlast_int),
.qsfpdd1_mac_1_rx_axis_tuser(qsfpdd1_mac_1_rx_axis_tuser_int),
.qsfpdd1_mac_1_rx_status(qsfpdd1_mac_1_rx_status_int),
.qsfpdd1_mac_1_rx_lfc_req(qsfpdd1_mac_1_rx_lfc_req_int),
.qsfpdd1_mac_1_rx_pfc_req(qsfpdd1_mac_1_rx_pfc_req_int),
.qsfpdd1_mac_2_clk(qsfpdd1_mac_2_clk_int),
.qsfpdd1_mac_2_rst(qsfpdd1_mac_2_rst_int),
.qsfpdd1_mac_2_ptp_time(qsfpdd1_mac_2_ptp_time_int),
.qsfpdd1_mac_2_tx_ptp_ts(qsfpdd1_mac_2_tx_ptp_ts_int),
.qsfpdd1_mac_2_tx_ptp_ts_tag(qsfpdd1_mac_2_tx_ptp_ts_tag_int),
.qsfpdd1_mac_2_tx_ptp_ts_valid(qsfpdd1_mac_2_tx_ptp_ts_valid_int),
.qsfpdd1_mac_2_tx_axis_tdata(qsfpdd1_mac_2_tx_axis_tdata_int),
.qsfpdd1_mac_2_tx_axis_tkeep(qsfpdd1_mac_2_tx_axis_tkeep_int),
.qsfpdd1_mac_2_tx_axis_tvalid(qsfpdd1_mac_2_tx_axis_tvalid_int),
.qsfpdd1_mac_2_tx_axis_tready(qsfpdd1_mac_2_tx_axis_tready_int),
.qsfpdd1_mac_2_tx_axis_tlast(qsfpdd1_mac_2_tx_axis_tlast_int),
.qsfpdd1_mac_2_tx_axis_tuser(qsfpdd1_mac_2_tx_axis_tuser_int),
.qsfpdd1_mac_2_tx_status(qsfpdd1_mac_2_tx_status_int),
.qsfpdd1_mac_2_tx_lfc_req(qsfpdd1_mac_2_tx_lfc_req_int),
.qsfpdd1_mac_2_tx_pfc_req(qsfpdd1_mac_2_tx_pfc_req_int),
.qsfpdd1_mac_2_rx_axis_tdata(qsfpdd1_mac_2_rx_axis_tdata_int),
.qsfpdd1_mac_2_rx_axis_tkeep(qsfpdd1_mac_2_rx_axis_tkeep_int),
.qsfpdd1_mac_2_rx_axis_tvalid(qsfpdd1_mac_2_rx_axis_tvalid_int),
.qsfpdd1_mac_2_rx_axis_tlast(qsfpdd1_mac_2_rx_axis_tlast_int),
.qsfpdd1_mac_2_rx_axis_tuser(qsfpdd1_mac_2_rx_axis_tuser_int),
.qsfpdd1_mac_2_rx_status(qsfpdd1_mac_2_rx_status_int),
.qsfpdd1_mac_2_rx_lfc_req(qsfpdd1_mac_2_rx_lfc_req_int),
.qsfpdd1_mac_2_rx_pfc_req(qsfpdd1_mac_2_rx_pfc_req_int),
.qsfpdd_mac_rx_status(qsfpdd_mac_rx_status),
.qsfpdd_mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req),
.qsfpdd_mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req),
.qsfpdd0_modsel_l(qsfpdd0_modsel_l),
.qsfpdd0_reset_l(qsfpdd0_reset_l),

210
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga_core.v
View File

@ -24,6 +24,10 @@ module fpga_core #
parameter GIT_HASH = 32'hdce357bf,
parameter RELEASE_INFO = 32'h00000000,
// Board configuration
parameter QSFPDD_CNT = 2,
parameter CH_CNT = QSFPDD_CNT*2,
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
@ -218,125 +222,39 @@ module fpga_core #
/*
* Ethernet: QSFP-DD
*/
input wire qsfpdd0_mac_1_clk,
input wire qsfpdd0_mac_1_rst,
input wire [CH_CNT-1:0] qsfpdd_mac_tx_clk,
input wire [CH_CNT-1:0] qsfpdd_mac_tx_rst,
output wire [PTP_TS_WIDTH-1:0] qsfpdd0_mac_1_ptp_time,
output wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_tx_axis_tdata,
output wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_tx_axis_tkeep,
output wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tvalid,
input wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tready,
output wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tlast,
output wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd_mac_tx_axis_tuser,
input wire [PTP_TS_WIDTH-1:0] qsfpdd0_mac_1_tx_ptp_ts,
input wire [TX_TAG_WIDTH-1:0] qsfpdd0_mac_1_tx_ptp_ts_tag,
input wire qsfpdd0_mac_1_tx_ptp_ts_valid,
output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_time,
input wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts,
input wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts_tag,
input wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_ts_valid,
output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd0_mac_1_tx_axis_tdata,
output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd0_mac_1_tx_axis_tkeep,
output wire qsfpdd0_mac_1_tx_axis_tvalid,
input wire qsfpdd0_mac_1_tx_axis_tready,
output wire qsfpdd0_mac_1_tx_axis_tlast,
output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd0_mac_1_tx_axis_tuser,
input wire [CH_CNT-1:0] qsfpdd_mac_tx_status,
output wire [CH_CNT-1:0] qsfpdd_mac_tx_lfc_req,
output wire [CH_CNT*8-1:0] qsfpdd_mac_tx_pfc_req,
input wire qsfpdd0_mac_1_tx_status,
output wire qsfpdd0_mac_1_tx_lfc_req,
output wire [7:0] qsfpdd0_mac_1_tx_pfc_req,
input wire [CH_CNT-1:0] qsfpdd_mac_rx_clk,
input wire [CH_CNT-1:0] qsfpdd_mac_rx_rst,
input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd0_mac_1_rx_axis_tdata,
input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd0_mac_1_rx_axis_tkeep,
input wire qsfpdd0_mac_1_rx_axis_tvalid,
input wire qsfpdd0_mac_1_rx_axis_tlast,
input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd0_mac_1_rx_axis_tuser,
input wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_rx_axis_tdata,
input wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_rx_axis_tkeep,
input wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tvalid,
input wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tlast,
input wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd_mac_rx_axis_tuser,
input wire qsfpdd0_mac_1_rx_status,
input wire qsfpdd0_mac_1_rx_lfc_req,
input wire [7:0] qsfpdd0_mac_1_rx_pfc_req,
output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_rx_ptp_time,
input wire qsfpdd0_mac_2_clk,
input wire qsfpdd0_mac_2_rst,
output wire [PTP_TS_WIDTH-1:0] qsfpdd0_mac_2_ptp_time,
input wire [PTP_TS_WIDTH-1:0] qsfpdd0_mac_2_tx_ptp_ts,
input wire [TX_TAG_WIDTH-1:0] qsfpdd0_mac_2_tx_ptp_ts_tag,
input wire qsfpdd0_mac_2_tx_ptp_ts_valid,
output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd0_mac_2_tx_axis_tdata,
output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd0_mac_2_tx_axis_tkeep,
output wire qsfpdd0_mac_2_tx_axis_tvalid,
input wire qsfpdd0_mac_2_tx_axis_tready,
output wire qsfpdd0_mac_2_tx_axis_tlast,
output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd0_mac_2_tx_axis_tuser,
input wire qsfpdd0_mac_2_tx_status,
output wire qsfpdd0_mac_2_tx_lfc_req,
output wire [7:0] qsfpdd0_mac_2_tx_pfc_req,
input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd0_mac_2_rx_axis_tdata,
input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd0_mac_2_rx_axis_tkeep,
input wire qsfpdd0_mac_2_rx_axis_tvalid,
input wire qsfpdd0_mac_2_rx_axis_tlast,
input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd0_mac_2_rx_axis_tuser,
input wire qsfpdd0_mac_2_rx_status,
input wire qsfpdd0_mac_2_rx_lfc_req,
input wire [7:0] qsfpdd0_mac_2_rx_pfc_req,
input wire qsfpdd1_mac_1_clk,
input wire qsfpdd1_mac_1_rst,
output wire [PTP_TS_WIDTH-1:0] qsfpdd1_mac_1_ptp_time,
input wire [PTP_TS_WIDTH-1:0] qsfpdd1_mac_1_tx_ptp_ts,
input wire [TX_TAG_WIDTH-1:0] qsfpdd1_mac_1_tx_ptp_ts_tag,
input wire qsfpdd1_mac_1_tx_ptp_ts_valid,
output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd1_mac_1_tx_axis_tdata,
output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd1_mac_1_tx_axis_tkeep,
output wire qsfpdd1_mac_1_tx_axis_tvalid,
input wire qsfpdd1_mac_1_tx_axis_tready,
output wire qsfpdd1_mac_1_tx_axis_tlast,
output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd1_mac_1_tx_axis_tuser,
input wire qsfpdd1_mac_1_tx_status,
output wire qsfpdd1_mac_1_tx_lfc_req,
output wire [7:0] qsfpdd1_mac_1_tx_pfc_req,
input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd1_mac_1_rx_axis_tdata,
input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd1_mac_1_rx_axis_tkeep,
input wire qsfpdd1_mac_1_rx_axis_tvalid,
input wire qsfpdd1_mac_1_rx_axis_tlast,
input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd1_mac_1_rx_axis_tuser,
input wire qsfpdd1_mac_1_rx_status,
input wire qsfpdd1_mac_1_rx_lfc_req,
input wire [7:0] qsfpdd1_mac_1_rx_pfc_req,
input wire qsfpdd1_mac_2_clk,
input wire qsfpdd1_mac_2_rst,
output wire [PTP_TS_WIDTH-1:0] qsfpdd1_mac_2_ptp_time,
input wire [PTP_TS_WIDTH-1:0] qsfpdd1_mac_2_tx_ptp_ts,
input wire [TX_TAG_WIDTH-1:0] qsfpdd1_mac_2_tx_ptp_ts_tag,
input wire qsfpdd1_mac_2_tx_ptp_ts_valid,
output wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd1_mac_2_tx_axis_tdata,
output wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd1_mac_2_tx_axis_tkeep,
output wire qsfpdd1_mac_2_tx_axis_tvalid,
input wire qsfpdd1_mac_2_tx_axis_tready,
output wire qsfpdd1_mac_2_tx_axis_tlast,
output wire [AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd1_mac_2_tx_axis_tuser,
input wire qsfpdd1_mac_2_tx_status,
output wire qsfpdd1_mac_2_tx_lfc_req,
output wire [7:0] qsfpdd1_mac_2_tx_pfc_req,
input wire [AXIS_ETH_DATA_WIDTH-1:0] qsfpdd1_mac_2_rx_axis_tdata,
input wire [AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd1_mac_2_rx_axis_tkeep,
input wire qsfpdd1_mac_2_rx_axis_tvalid,
input wire qsfpdd1_mac_2_rx_axis_tlast,
input wire [AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd1_mac_2_rx_axis_tuser,
input wire qsfpdd1_mac_2_rx_status,
input wire qsfpdd1_mac_2_rx_lfc_req,
input wire [7:0] qsfpdd1_mac_2_rx_pfc_req,
input wire [CH_CNT-1:0] qsfpdd_mac_rx_status,
input wire [CH_CNT-1:0] qsfpdd_mac_rx_lfc_req,
input wire [CH_CNT*8-1:0] qsfpdd_mac_rx_pfc_req,
output wire qsfpdd0_modsel_l,
output wire qsfpdd0_reset_l,
@ -368,7 +286,7 @@ localparam RB_BASE_ADDR = 16'h1000;
localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}};
initial begin
if (PORT_COUNT > 4) begin
if (PORT_COUNT > CH_CNT) begin
$error("Error: Max port count exceeded (instance %m)");
$finish;
end
@ -610,11 +528,11 @@ assign fpga_led[1] = 1'b0;
assign fpga_led[2] = 1'b0;
assign fpga_led[3] = 1'b0;
assign qsfpdd0_led0 = qsfpdd0_mac_1_rx_status;
assign qsfpdd0_led0 = 1'b0;
assign qsfpdd0_led1_g = 1'b0;
assign qsfpdd0_led1_y = 1'b0;
assign qsfpdd1_led0 = qsfpdd1_mac_1_rx_status;
assign qsfpdd1_led0 = 1'b0;
assign qsfpdd1_led1_g = 1'b0;
assign qsfpdd1_led1_y = 1'b0;
@ -670,7 +588,7 @@ wire [PORT_COUNT*8-1:0] eth_rx_pfc_req;
wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack;
mqnic_port_map_mac_axis #(
.MAC_COUNT(4),
.MAC_COUNT(CH_CNT),
.PORT_MASK(PORT_MASK),
.PORT_GROUP_SIZE(2),
@ -688,55 +606,55 @@ mqnic_port_map_mac_axis #(
)
mqnic_port_map_mac_axis_inst (
// towards MAC
.mac_tx_clk({qsfpdd1_mac_2_clk, qsfpdd1_mac_1_clk, qsfpdd0_mac_2_clk, qsfpdd0_mac_1_clk}),
.mac_tx_rst({qsfpdd1_mac_2_rst, qsfpdd1_mac_1_rst, qsfpdd0_mac_2_rst, qsfpdd0_mac_1_rst}),
.mac_tx_clk(qsfpdd_mac_tx_clk),
.mac_tx_rst(qsfpdd_mac_tx_rst),
.mac_tx_ptp_clk({qsfpdd1_mac_2_clk, qsfpdd1_mac_1_clk, qsfpdd0_mac_2_clk, qsfpdd0_mac_1_clk}),
.mac_tx_ptp_rst({qsfpdd1_mac_2_rst, qsfpdd1_mac_1_rst, qsfpdd0_mac_2_rst, qsfpdd0_mac_1_rst}),
.mac_tx_ptp_ts_96({qsfpdd1_mac_2_ptp_time, qsfpdd1_mac_1_ptp_time, qsfpdd0_mac_2_ptp_time, qsfpdd0_mac_1_ptp_time}),
.mac_tx_ptp_clk(qsfpdd_mac_tx_clk),
.mac_tx_ptp_rst(qsfpdd_mac_tx_rst),
.mac_tx_ptp_ts_96(qsfpdd_mac_tx_ptp_time),
.mac_tx_ptp_ts_step(),
.m_axis_mac_tx_tdata({qsfpdd1_mac_2_tx_axis_tdata, qsfpdd1_mac_1_tx_axis_tdata, qsfpdd0_mac_2_tx_axis_tdata, qsfpdd0_mac_1_tx_axis_tdata}),
.m_axis_mac_tx_tkeep({qsfpdd1_mac_2_tx_axis_tkeep, qsfpdd1_mac_1_tx_axis_tkeep, qsfpdd0_mac_2_tx_axis_tkeep, qsfpdd0_mac_1_tx_axis_tkeep}),
.m_axis_mac_tx_tvalid({qsfpdd1_mac_2_tx_axis_tvalid, qsfpdd1_mac_1_tx_axis_tvalid, qsfpdd0_mac_2_tx_axis_tvalid, qsfpdd0_mac_1_tx_axis_tvalid}),
.m_axis_mac_tx_tready({qsfpdd1_mac_2_tx_axis_tready, qsfpdd1_mac_1_tx_axis_tready, qsfpdd0_mac_2_tx_axis_tready, qsfpdd0_mac_1_tx_axis_tready}),
.m_axis_mac_tx_tlast({qsfpdd1_mac_2_tx_axis_tlast, qsfpdd1_mac_1_tx_axis_tlast, qsfpdd0_mac_2_tx_axis_tlast, qsfpdd0_mac_1_tx_axis_tlast}),
.m_axis_mac_tx_tuser({qsfpdd1_mac_2_tx_axis_tuser, qsfpdd1_mac_1_tx_axis_tuser, qsfpdd0_mac_2_tx_axis_tuser, qsfpdd0_mac_1_tx_axis_tuser}),
.m_axis_mac_tx_tdata(qsfpdd_mac_tx_axis_tdata),
.m_axis_mac_tx_tkeep(qsfpdd_mac_tx_axis_tkeep),
.m_axis_mac_tx_tvalid(qsfpdd_mac_tx_axis_tvalid),
.m_axis_mac_tx_tready(qsfpdd_mac_tx_axis_tready),
.m_axis_mac_tx_tlast(qsfpdd_mac_tx_axis_tlast),
.m_axis_mac_tx_tuser(qsfpdd_mac_tx_axis_tuser),
.s_axis_mac_tx_ptp_ts({qsfpdd1_mac_2_tx_ptp_ts, qsfpdd1_mac_1_tx_ptp_ts, qsfpdd0_mac_2_tx_ptp_ts, qsfpdd0_mac_1_tx_ptp_ts}),
.s_axis_mac_tx_ptp_ts_tag({qsfpdd1_mac_2_tx_ptp_ts_tag, qsfpdd1_mac_1_tx_ptp_ts_tag, qsfpdd0_mac_2_tx_ptp_ts_tag, qsfpdd0_mac_1_tx_ptp_ts_tag}),
.s_axis_mac_tx_ptp_ts_valid({qsfpdd1_mac_2_tx_ptp_ts_valid, qsfpdd1_mac_1_tx_ptp_ts_valid, qsfpdd0_mac_2_tx_ptp_ts_valid, qsfpdd0_mac_1_tx_ptp_ts_valid}),
.s_axis_mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts),
.s_axis_mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag),
.s_axis_mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid),
.s_axis_mac_tx_ptp_ts_ready(),
.mac_tx_enable(),
.mac_tx_status({qsfpdd1_mac_2_tx_status, qsfpdd1_mac_1_tx_status, qsfpdd0_mac_2_tx_status, qsfpdd0_mac_1_tx_status}),
.mac_tx_status(qsfpdd_mac_tx_status),
.mac_tx_lfc_en(),
.mac_tx_lfc_req({qsfpdd1_mac_2_tx_lfc_req, qsfpdd1_mac_1_tx_lfc_req, qsfpdd0_mac_2_tx_lfc_req, qsfpdd0_mac_1_tx_lfc_req}),
.mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req),
.mac_tx_pfc_en(),
.mac_tx_pfc_req({qsfpdd1_mac_2_tx_pfc_req, qsfpdd1_mac_1_tx_pfc_req, qsfpdd0_mac_2_tx_pfc_req, qsfpdd0_mac_1_tx_pfc_req}),
.mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req),
.mac_rx_clk({qsfpdd1_mac_2_clk, qsfpdd1_mac_1_clk, qsfpdd0_mac_2_clk, qsfpdd0_mac_1_clk}),
.mac_rx_rst({qsfpdd1_mac_2_rst, qsfpdd1_mac_1_rst, qsfpdd0_mac_2_rst, qsfpdd0_mac_1_rst}),
.mac_rx_clk(qsfpdd_mac_rx_clk),
.mac_rx_rst(qsfpdd_mac_rx_rst),
.mac_rx_ptp_clk({qsfpdd1_mac_2_clk, qsfpdd1_mac_1_clk, qsfpdd0_mac_2_clk, qsfpdd0_mac_1_clk}),
.mac_rx_ptp_rst({qsfpdd1_mac_2_rst, qsfpdd1_mac_1_rst, qsfpdd0_mac_2_rst, qsfpdd0_mac_1_rst}),
.mac_rx_ptp_ts_96(),
.mac_rx_ptp_clk(qsfpdd_mac_rx_clk),
.mac_rx_ptp_rst(qsfpdd_mac_rx_rst),
.mac_rx_ptp_ts_96(qsfpdd_mac_rx_ptp_time),
.mac_rx_ptp_ts_step(),
.s_axis_mac_rx_tdata({qsfpdd1_mac_2_rx_axis_tdata, qsfpdd1_mac_1_rx_axis_tdata, qsfpdd0_mac_2_rx_axis_tdata, qsfpdd0_mac_1_rx_axis_tdata}),
.s_axis_mac_rx_tkeep({qsfpdd1_mac_2_rx_axis_tkeep, qsfpdd1_mac_1_rx_axis_tkeep, qsfpdd0_mac_2_rx_axis_tkeep, qsfpdd0_mac_1_rx_axis_tkeep}),
.s_axis_mac_rx_tvalid({qsfpdd1_mac_2_rx_axis_tvalid, qsfpdd1_mac_1_rx_axis_tvalid, qsfpdd0_mac_2_rx_axis_tvalid, qsfpdd0_mac_1_rx_axis_tvalid}),
.s_axis_mac_rx_tdata(qsfpdd_mac_rx_axis_tdata),
.s_axis_mac_rx_tkeep(qsfpdd_mac_rx_axis_tkeep),
.s_axis_mac_rx_tvalid(qsfpdd_mac_rx_axis_tvalid),
.s_axis_mac_rx_tready(),
.s_axis_mac_rx_tlast({qsfpdd1_mac_2_rx_axis_tlast, qsfpdd1_mac_1_rx_axis_tlast, qsfpdd0_mac_2_rx_axis_tlast, qsfpdd0_mac_1_rx_axis_tlast}),
.s_axis_mac_rx_tuser({qsfpdd1_mac_2_rx_axis_tuser, qsfpdd1_mac_1_rx_axis_tuser, qsfpdd0_mac_2_rx_axis_tuser, qsfpdd0_mac_1_rx_axis_tuser}),
.s_axis_mac_rx_tlast(qsfpdd_mac_rx_axis_tlast),
.s_axis_mac_rx_tuser(qsfpdd_mac_rx_axis_tuser),
.mac_rx_enable(),
.mac_rx_status({qsfpdd1_mac_2_rx_status, qsfpdd1_mac_1_rx_status, qsfpdd0_mac_2_rx_status, qsfpdd0_mac_1_rx_status}),
.mac_rx_status(qsfpdd_mac_rx_status),
.mac_rx_lfc_en(),
.mac_rx_lfc_req({qsfpdd1_mac_2_rx_lfc_req, qsfpdd1_mac_1_rx_lfc_req, qsfpdd0_mac_2_rx_lfc_req, qsfpdd0_mac_1_rx_lfc_req}),
.mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req),
.mac_rx_lfc_ack(),
.mac_rx_pfc_en(),
.mac_rx_pfc_req({qsfpdd1_mac_2_rx_pfc_req, qsfpdd1_mac_1_rx_pfc_req, qsfpdd0_mac_2_rx_pfc_req, qsfpdd0_mac_1_rx_pfc_req}),
.mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req),
.mac_rx_pfc_ack(),
// towards datapath

3
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/Makefile
View File

@ -10,8 +10,9 @@ COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
DUT = fpga_core
TOPLEVEL = $(DUT)
TOPLEVEL = test_$(DUT)
MODULE = test_$(DUT)
VERILOG_SOURCES += $(TOPLEVEL).v
VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_ptile.v
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v

88
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -245,9 +245,9 @@ class TB(object):
self.driver = mqnic.Driver()
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
self.dev.functions[0].configure_bar(0, 2**len(dut.uut.core_inst.core_pcie_inst.axil_ctrl_araddr), ext=True, prefetch=True)
if hasattr(dut.uut.core_inst.core_pcie_inst, 'pcie_app_ctrl'):
self.dev.functions[0].configure_bar(2, 2**len(dut.uut.core_inst.core_pcie_inst.axil_app_ctrl_araddr), ext=True, prefetch=True)
cocotb.start_soon(Clock(dut.ptp_clk, 2.482, units="ns").start())
dut.ptp_rst.setimmediatevalue(0)
@ -256,36 +256,36 @@ class TB(object):
# Ethernet
self.qsfpdd_mac = []
for x in range(2):
macs = []
for y in range(1, 3):
cocotb.start_soon(Clock(getattr(dut, f"qsfpdd{x}_mac_{y}_clk"), 2.482, units="ns").start())
for ch in self.dut.ch:
cocotb.start_soon(Clock(ch.ch_mac_tx_clk, 2.482, units="ns").start())
cocotb.start_soon(Clock(ch.ch_mac_rx_clk, 2.482, units="ns").start())
mac = EthMac(
tx_clk=getattr(dut, f"qsfpdd{x}_mac_{y}_clk"),
tx_rst=getattr(dut, f"qsfpdd{x}_mac_{y}_rst"),
tx_bus=AxiStreamBus.from_prefix(dut, f"qsfpdd{x}_mac_{y}_tx_axis"),
tx_ptp_time=getattr(dut, f"qsfpdd{x}_mac_{y}_ptp_time"),
tx_ptp_ts=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_ptp_ts"),
tx_ptp_ts_tag=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_ptp_ts_tag"),
tx_ptp_ts_valid=getattr(dut, f"qsfpdd{x}_mac_{y}_tx_ptp_ts_valid"),
rx_clk=getattr(dut, f"qsfpdd{x}_mac_{y}_clk"),
rx_rst=getattr(dut, f"qsfpdd{x}_mac_{y}_rst"),
rx_bus=AxiStreamBus.from_prefix(dut, f"qsfpdd{x}_mac_{y}_rx_axis"),
rx_ptp_time=getattr(dut, f"qsfpdd{x}_mac_{y}_ptp_time"),
tx_clk=ch.ch_mac_tx_clk,
tx_rst=ch.ch_mac_tx_rst,
tx_bus=AxiStreamBus.from_prefix(ch, "ch_mac_tx_axis"),
tx_ptp_time=ch.ch_mac_tx_ptp_time,
tx_ptp_ts=ch.ch_mac_tx_ptp_ts,
tx_ptp_ts_tag=ch.ch_mac_tx_ptp_ts_tag,
tx_ptp_ts_valid=ch.ch_mac_tx_ptp_ts_valid,
rx_clk=ch.ch_mac_rx_clk,
rx_rst=ch.ch_mac_rx_rst,
rx_bus=AxiStreamBus.from_prefix(ch, "ch_mac_rx_axis"),
rx_ptp_time=ch.ch_mac_rx_ptp_time,
ifg=12, speed=100e9
)
macs.append(mac)
ch.ch_mac_rx_status.setimmediatevalue(1)
ch.ch_mac_rx_lfc_req.setimmediatevalue(0)
ch.ch_mac_rx_pfc_req.setimmediatevalue(0)
getattr(dut, f"qsfpdd{x}_mac_{y}_rx_status").setimmediatevalue(1)
getattr(dut, f"qsfpdd{x}_mac_{y}_rx_lfc_req").setimmediatevalue(0)
getattr(dut, f"qsfpdd{x}_mac_{y}_rx_pfc_req").setimmediatevalue(0)
self.qsfpdd_mac.append(mac)
self.qsfpdd_mac.append(macs)
dut.qsfpdd0_modprs_l.setimmediatevalue(0)
dut.qsfpdd0_int_l.setimmediatevalue(1)
getattr(dut, f"qsfpdd{x}_modprs_l").setimmediatevalue(0)
getattr(dut, f"qsfpdd{x}_int_l").setimmediatevalue(1)
dut.qsfpdd1_modprs_l.setimmediatevalue(0)
dut.qsfpdd1_int_l.setimmediatevalue(1)
dut.fpga_i2c_scl_i.setimmediatevalue(1)
dut.fpga_i2c_sda_i.setimmediatevalue(1)
@ -299,17 +299,17 @@ class TB(object):
async def init(self):
self.dut.ptp_rst.setimmediatevalue(0)
for x in range(2):
for y in range(1, 3):
getattr(self.dut, f"qsfpdd{x}_mac_{y}_rst").setimmediatevalue(0)
for ch in self.dut.ch:
ch.ch_mac_tx_rst.setimmediatevalue(0)
ch.ch_mac_rx_rst.setimmediatevalue(0)
await RisingEdge(self.dut.clk_250mhz)
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(1)
for x in range(2):
for y in range(1, 3):
getattr(self.dut, f"qsfpdd{x}_mac_{y}_rst").setimmediatevalue(1)
for ch in self.dut.ch:
ch.ch_mac_tx_rst.setimmediatevalue(1)
ch.ch_mac_rx_rst.setimmediatevalue(1)
await FallingEdge(self.dut.rst_250mhz)
await Timer(100, 'ns')
@ -318,9 +318,9 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
self.dut.ptp_rst.setimmediatevalue(0)
for x in range(2):
for y in range(1, 3):
getattr(self.dut, f"qsfpdd{x}_mac_{y}_rst").setimmediatevalue(0)
for ch in self.dut.ch:
ch.ch_mac_tx_rst.setimmediatevalue(0)
ch.ch_mac_rx_rst.setimmediatevalue(0)
await self.rc.enumerate()
@ -329,8 +329,7 @@ class TB(object):
await RisingEdge(self.dut.clk_250mhz)
if self.loopback_enable:
for macs in self.qsfpdd_mac:
for mac in macs:
for mac in self.qsfpdd_mac:
if not mac.tx.empty():
await mac.rx.send(await mac.tx.recv())
@ -338,7 +337,7 @@ class TB(object):
@cocotb.test()
async def run_test_nic(dut):
tb = TB(dut, msix_count=2**len(dut.core_inst.core_pcie_inst.irq_index))
tb = TB(dut, msix_count=2**len(dut.uut.core_inst.core_pcie_inst.irq_index))
await tb.init()
@ -363,10 +362,10 @@ async def run_test_nic(dut):
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.qsfpdd_mac[0][0].tx.recv()
pkt = await tb.qsfpdd_mac[0].tx.recv()
tb.log.info("Packet: %s", pkt)
await tb.qsfpdd_mac[0][0].rx.send(pkt)
await tb.qsfpdd_mac[0].rx.send(pkt)
pkt = await tb.driver.interfaces[0].recv()
@ -375,10 +374,10 @@ async def run_test_nic(dut):
# await tb.driver.interfaces[1].start_xmit(data, 0)
# pkt = await tb.qsfpdd_mac[1][0].tx.recv()
# pkt = await tb.qsfpdd_mac[2].tx.recv()
# tb.log.info("Packet: %s", pkt)
# await tb.qsfpdd_mac[1][0].rx.send(pkt)
# await tb.qsfpdd_mac[2].rx.send(pkt)
# pkt = await tb.driver.interfaces[1].recv()
@ -398,10 +397,10 @@ async def run_test_nic(dut):
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
pkt = await tb.qsfpdd_mac[0][0].tx.recv()
pkt = await tb.qsfpdd_mac[0].tx.recv()
tb.log.info("Packet: %s", pkt)
await tb.qsfpdd_mac[0][0].rx.send(pkt)
await tb.qsfpdd_mac[0].rx.send(pkt)
pkt = await tb.driver.interfaces[0].recv()
@ -546,9 +545,10 @@ pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
def test_fpga_core(request):
dut = "fpga_core"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
toplevel = f"test_{dut}"
verilog_sources = [
os.path.join(tests_dir, f"{toplevel}.v"),
os.path.join(rtl_dir, f"{dut}.v"),
os.path.join(rtl_dir, "common", "mqnic_core_pcie_ptile.v"),
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),

671
fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/tb/fpga_core/test_fpga_core.v Normal file
View File

@ -0,0 +1,671 @@
/*
Copyright (c) 2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Testbench top-level module
*/
module test_fpga_core #
(
// FW and board IDs
parameter FPGA_ID = 32'hC341A0DD,
parameter FW_ID = 32'h00000000,
parameter FW_VER = 32'h00_00_01_00,
parameter BOARD_ID = 32'h1172_B00E,
parameter BOARD_VER = 32'h01_00_00_00,
parameter BUILD_DATE = 32'd1563227611,
parameter GIT_HASH = 32'hdce357bf,
parameter RELEASE_INFO = 32'h00000000,
// Board configuration
parameter QSFPDD_CNT = 2,
parameter CH_CNT = QSFPDD_CNT*2,
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
parameter PORT_MASK = 0,
// Clock configuration
parameter CLK_PERIOD_NS_NUM = 4,
parameter CLK_PERIOD_NS_DENOM = 1,
// PTP configuration
parameter PTP_CLK_PERIOD_NS_NUM = 2048,
parameter PTP_CLK_PERIOD_NS_DENOM = 825,
parameter PTP_TS_WIDTH = 96,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_CLOCK_CDC_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter CQ_OP_TABLE_SIZE = 32,
parameter EQN_WIDTH = 5,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter CQN_WIDTH = (TX_QUEUE_INDEX_WIDTH > RX_QUEUE_INDEX_WIDTH ? TX_QUEUE_INDEX_WIDTH : RX_QUEUE_INDEX_WIDTH) + 1,
parameter EQ_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter CQ_PIPELINE = 3+(CQN_WIDTH > 12 ? CQN_WIDTH-12 : 0),
// TX and RX engine configuration
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
parameter RX_INDIR_TBL_ADDR_WIDTH = RX_QUEUE_INDEX_WIDTH > 8 ? 8 : RX_QUEUE_INDEX_WIDTH,
// Scheduler configuration
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Interface configuration
parameter PTP_TS_ENABLE = 1,
parameter TX_CPL_FIFO_DEPTH = 32,
parameter TX_TAG_WIDTH = 8,
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter PFC_ENABLE = 1,
parameter LFC_ENABLE = PFC_ENABLE,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 131072,
parameter MAX_TX_SIZE = 9214,
parameter MAX_RX_SIZE = 9214,
parameter TX_RAM_SIZE = 131072,
parameter RX_RAM_SIZE = 131072,
// Application block configuration
parameter APP_ID = 32'h00000000,
parameter APP_ENABLE = 0,
parameter APP_CTRL_ENABLE = 1,
parameter APP_DMA_ENABLE = 1,
parameter APP_AXIS_DIRECT_ENABLE = 1,
parameter APP_AXIS_SYNC_ENABLE = 1,
parameter APP_AXIS_IF_ENABLE = 1,
parameter APP_STAT_ENABLE = 1,
// DMA interface configuration
parameter DMA_IMM_ENABLE = 0,
parameter DMA_IMM_WIDTH = 32,
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
parameter RAM_PIPELINE = 2,
// PCIe interface configuration
parameter SEG_COUNT = 2,
parameter SEG_DATA_WIDTH = 256,
parameter SEG_EMPTY_WIDTH = $clog2(SEG_DATA_WIDTH/32),
parameter SEG_HDR_WIDTH = 128,
parameter SEG_PRFX_WIDTH = 32,
parameter TX_SEQ_NUM_WIDTH = 6,
parameter PF_COUNT = 1,
parameter VF_COUNT = 0,
parameter PCIE_TAG_COUNT = 256,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EQN_WIDTH,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24,
// AXI lite interface configuration (application control)
parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH,
parameter AXIL_APP_CTRL_ADDR_WIDTH = 24,
// Ethernet interface configuration
parameter AXIS_ETH_DATA_WIDTH = 512,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 0,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 2,
parameter AXIS_ETH_TX_TS_PIPELINE = 0,
parameter AXIS_ETH_RX_PIPELINE = 0,
parameter AXIS_ETH_RX_FIFO_PIPELINE = 2,
// Statistics counter subsystem
parameter STAT_ENABLE = 1,
parameter STAT_DMA_ENABLE = 1,
parameter STAT_PCIE_ENABLE = 1,
parameter STAT_INC_WIDTH = 24,
parameter STAT_ID_WIDTH = 12
)
(
/*
* Clock: 250 MHz
* Synchronous reset
*/
input wire clk_250mhz,
input wire rst_250mhz,
/*
* PTP clock
*/
input wire ptp_clk,
input wire ptp_rst,
input wire ptp_sample_clk,
/*
* GPIO
*/
output wire [3:0] fpga_led,
output wire qsfpdd0_led0,
output wire qsfpdd0_led1_g,
output wire qsfpdd0_led1_y,
output wire qsfpdd1_led0,
output wire qsfpdd1_led1_g,
output wire qsfpdd1_led1_y,
/*
* I2C
*/
input wire fpga_i2c_scl_i,
output wire fpga_i2c_scl_o,
output wire fpga_i2c_scl_t,
input wire fpga_i2c_sda_i,
output wire fpga_i2c_sda_o,
output wire fpga_i2c_sda_t,
/*
* P-Tile interface
*/
input wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] rx_st_data,
input wire [SEG_COUNT*SEG_EMPTY_WIDTH-1:0] rx_st_empty,
input wire [SEG_COUNT-1:0] rx_st_sop,
input wire [SEG_COUNT-1:0] rx_st_eop,
input wire [SEG_COUNT-1:0] rx_st_valid,
output wire rx_st_ready,
input wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] rx_st_hdr,
input wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] rx_st_tlp_prfx,
input wire [SEG_COUNT-1:0] rx_st_vf_active,
input wire [SEG_COUNT*3-1:0] rx_st_func_num,
input wire [SEG_COUNT*11-1:0] rx_st_vf_num,
input wire [SEG_COUNT*3-1:0] rx_st_bar_range,
input wire [SEG_COUNT-1:0] rx_st_tlp_abort,
output wire [SEG_COUNT*SEG_DATA_WIDTH-1:0] tx_st_data,
output wire [SEG_COUNT-1:0] tx_st_sop,
output wire [SEG_COUNT-1:0] tx_st_eop,
output wire [SEG_COUNT-1:0] tx_st_valid,
input wire tx_st_ready,
output wire [SEG_COUNT-1:0] tx_st_err,
output wire [SEG_COUNT*SEG_HDR_WIDTH-1:0] tx_st_hdr,
output wire [SEG_COUNT*SEG_PRFX_WIDTH-1:0] tx_st_tlp_prfx,
output wire [11:0] rx_buffer_limit,
output wire [1:0] rx_buffer_limit_tdm_idx,
input wire [15:0] tx_cdts_limit,
input wire [2:0] tx_cdts_limit_tdm_idx,
input wire [15:0] tl_cfg_ctl,
input wire [4:0] tl_cfg_add,
input wire [2:0] tl_cfg_func,
/*
* Ethernet: QSFP-DD
*/
// input wire [CH_CNT-1:0] qsfpdd_mac_tx_clk,
// input wire [CH_CNT-1:0] qsfpdd_mac_tx_rst,
// output wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_tx_axis_tdata,
// output wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_tx_axis_tkeep,
// output wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tvalid,
// input wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tready,
// output wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tlast,
// output wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd_mac_tx_axis_tuser,
// output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_time,
// input wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts,
// input wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts_tag,
// input wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_ts_valid,
// input wire [CH_CNT-1:0] qsfpdd_mac_tx_status,
// output wire [CH_CNT-1:0] qsfpdd_mac_tx_lfc_req,
// output wire [CH_CNT*8-1:0] qsfpdd_mac_tx_pfc_req,
// input wire [CH_CNT-1:0] qsfpdd_mac_rx_clk,
// input wire [CH_CNT-1:0] qsfpdd_mac_rx_rst,
// input wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_rx_axis_tdata,
// input wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_rx_axis_tkeep,
// input wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tvalid,
// input wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tlast,
// input wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd_mac_rx_axis_tuser,
// output wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_rx_ptp_time,
// input wire [CH_CNT-1:0] qsfpdd_mac_rx_status,
// input wire [CH_CNT-1:0] qsfpdd_mac_rx_lfc_req,
// input wire [CH_CNT*8-1:0] qsfpdd_mac_rx_pfc_req,
output wire qsfpdd0_modsel_l,
output wire qsfpdd0_reset_l,
input wire qsfpdd0_modprs_l,
output wire qsfpdd0_lpmode,
input wire qsfpdd0_int_l,
output wire qsfpdd1_modsel_l,
output wire qsfpdd1_reset_l,
input wire qsfpdd1_modprs_l,
output wire qsfpdd1_lpmode,
input wire qsfpdd1_int_l,
input wire qsfpdd_i2c_scl_i,
output wire qsfpdd_i2c_scl_o,
output wire qsfpdd_i2c_scl_t,
input wire qsfpdd_i2c_sda_i,
output wire qsfpdd_i2c_sda_o,
output wire qsfpdd_i2c_sda_t
);
genvar n;
wire [CH_CNT-1:0] qsfpdd_mac_tx_clk;
wire [CH_CNT-1:0] qsfpdd_mac_tx_rst;
wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_tx_axis_tdata;
wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_tx_axis_tkeep;
wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tvalid;
wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tready;
wire [CH_CNT-1:0] qsfpdd_mac_tx_axis_tlast;
wire [CH_CNT*AXIS_ETH_TX_USER_WIDTH-1:0] qsfpdd_mac_tx_axis_tuser;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_time;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts;
wire [CH_CNT*TX_TAG_WIDTH-1:0] qsfpdd_mac_tx_ptp_ts_tag;
wire [CH_CNT-1:0] qsfpdd_mac_tx_ptp_ts_valid;
wire [CH_CNT-1:0] qsfpdd_mac_tx_status;
wire [CH_CNT-1:0] qsfpdd_mac_tx_lfc_req;
wire [CH_CNT*8-1:0] qsfpdd_mac_tx_pfc_req;
wire [CH_CNT-1:0] qsfpdd_mac_rx_clk;
wire [CH_CNT-1:0] qsfpdd_mac_rx_rst;
wire [CH_CNT*AXIS_ETH_DATA_WIDTH-1:0] qsfpdd_mac_rx_axis_tdata;
wire [CH_CNT*AXIS_ETH_KEEP_WIDTH-1:0] qsfpdd_mac_rx_axis_tkeep;
wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tvalid;
wire [CH_CNT-1:0] qsfpdd_mac_rx_axis_tlast;
wire [CH_CNT*AXIS_ETH_RX_USER_WIDTH-1:0] qsfpdd_mac_rx_axis_tuser;
wire [CH_CNT*PTP_TS_WIDTH-1:0] qsfpdd_mac_rx_ptp_time;
wire [CH_CNT-1:0] qsfpdd_mac_rx_status;
wire [CH_CNT-1:0] qsfpdd_mac_rx_lfc_req;
wire [CH_CNT*8-1:0] qsfpdd_mac_rx_pfc_req;
generate
for (n = 0; n < QSFPDD_CNT; n = n + 1) begin : ch
wire ch_mac_tx_clk;
wire ch_mac_tx_rst;
wire [AXIS_ETH_DATA_WIDTH-1:0] ch_mac_tx_axis_tdata;
wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_mac_tx_axis_tkeep;
wire ch_mac_tx_axis_tvalid;
wire ch_mac_tx_axis_tready;
wire ch_mac_tx_axis_tlast;
wire [AXIS_ETH_TX_USER_WIDTH-1:0] ch_mac_tx_axis_tuser;
wire [PTP_TS_WIDTH-1:0] ch_mac_tx_ptp_time;
wire [PTP_TS_WIDTH-1:0] ch_mac_tx_ptp_ts;
wire [TX_TAG_WIDTH-1:0] ch_mac_tx_ptp_ts_tag;
wire ch_mac_tx_ptp_ts_valid;
wire ch_mac_tx_status;
wire ch_mac_tx_lfc_req;
wire [7:0] ch_mac_tx_pfc_req;
wire ch_mac_rx_clk;
wire ch_mac_rx_rst;
wire [AXIS_ETH_DATA_WIDTH-1:0] ch_mac_rx_axis_tdata;
wire [AXIS_ETH_KEEP_WIDTH-1:0] ch_mac_rx_axis_tkeep;
wire ch_mac_rx_axis_tvalid;
wire ch_mac_rx_axis_tlast;
wire [AXIS_ETH_RX_USER_WIDTH-1:0] ch_mac_rx_axis_tuser;
wire [PTP_TS_WIDTH-1:0] ch_mac_rx_ptp_time;
wire ch_mac_rx_status;
wire ch_mac_rx_lfc_req;
wire [7:0] ch_mac_rx_pfc_req;
assign qsfpdd_mac_tx_clk[n +: 1] = ch_mac_tx_clk;
assign qsfpdd_mac_tx_rst[n +: 1] = ch_mac_tx_rst;
assign ch_mac_tx_axis_tdata = qsfpdd_mac_tx_axis_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH];
assign ch_mac_tx_axis_tkeep = qsfpdd_mac_tx_axis_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH];
assign ch_mac_tx_axis_tvalid = qsfpdd_mac_tx_axis_tvalid[n +: 1];
assign qsfpdd_mac_tx_axis_tready[n +: 1] = ch_mac_tx_axis_tready;
assign ch_mac_tx_axis_tlast = qsfpdd_mac_tx_axis_tlast[n +: 1];
assign ch_mac_tx_axis_tuser = qsfpdd_mac_tx_axis_tuser[n*AXIS_ETH_TX_USER_WIDTH +: AXIS_ETH_TX_USER_WIDTH];
assign ch_mac_tx_ptp_time = qsfpdd_mac_tx_ptp_time[n*PTP_TS_WIDTH +: PTP_TS_WIDTH];
assign qsfpdd_mac_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH] = ch_mac_tx_ptp_ts;
assign qsfpdd_mac_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH] = ch_mac_tx_ptp_ts_tag;
assign qsfpdd_mac_tx_ptp_ts_valid[n +: 1] = ch_mac_tx_ptp_ts_valid;
assign qsfpdd_mac_tx_status[n +: 1] = ch_mac_tx_status;
assign ch_mac_tx_lfc_req = qsfpdd_mac_tx_lfc_req[n +: 1];
assign ch_mac_tx_pfc_req = qsfpdd_mac_tx_pfc_req[n*8 +: 8];
assign qsfpdd_mac_rx_clk[n +: 1] = ch_mac_rx_clk;
assign qsfpdd_mac_rx_rst[n +: 1] = ch_mac_rx_rst;
assign qsfpdd_mac_rx_axis_tdata[n*AXIS_ETH_DATA_WIDTH +: AXIS_ETH_DATA_WIDTH] = ch_mac_rx_axis_tdata;
assign qsfpdd_mac_rx_axis_tkeep[n*AXIS_ETH_KEEP_WIDTH +: AXIS_ETH_KEEP_WIDTH] = ch_mac_rx_axis_tkeep;
assign qsfpdd_mac_rx_axis_tvalid[n +: 1] = ch_mac_rx_axis_tvalid;
assign qsfpdd_mac_rx_axis_tlast[n +: 1] = ch_mac_rx_axis_tlast;
assign qsfpdd_mac_rx_axis_tuser[n*AXIS_ETH_RX_USER_WIDTH +: AXIS_ETH_RX_USER_WIDTH] = ch_mac_rx_axis_tuser;
assign ch_mac_rx_ptp_time = qsfpdd_mac_rx_ptp_time[n*PTP_TS_WIDTH +: PTP_TS_WIDTH];
assign qsfpdd_mac_rx_status[n +: 1] = ch_mac_rx_status;
assign qsfpdd_mac_rx_lfc_req[n +: 1] = ch_mac_rx_lfc_req;
assign qsfpdd_mac_rx_pfc_req[n*8 +: 8] = ch_mac_rx_pfc_req;
end
endgenerate
fpga_core #(
// FW and board IDs
.FPGA_ID(FPGA_ID),
.FW_ID(FW_ID),
.FW_VER(FW_VER),
.BOARD_ID(BOARD_ID),
.BOARD_VER(BOARD_VER),
.BUILD_DATE(BUILD_DATE),
.GIT_HASH(GIT_HASH),
.RELEASE_INFO(RELEASE_INFO),
// Board configuration
.QSFPDD_CNT(QSFPDD_CNT),
.CH_CNT(CH_CNT),
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_MASK(PORT_MASK),
// Clock configuration
.CLK_PERIOD_NS_NUM(CLK_PERIOD_NS_NUM),
.CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM),
// PTP configuration
.PTP_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM),
.PTP_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_CLOCK_CDC_PIPELINE(PTP_CLOCK_CDC_PIPELINE),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.CQ_OP_TABLE_SIZE(CQ_OP_TABLE_SIZE),
.EQN_WIDTH(EQN_WIDTH),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.CQN_WIDTH(CQN_WIDTH),
.EQ_PIPELINE(EQ_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.CQ_PIPELINE(CQ_PIPELINE),
// TX and RX engine configuration
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
.RX_INDIR_TBL_ADDR_WIDTH(RX_INDIR_TBL_ADDR_WIDTH),
// Scheduler configuration
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Interface configuration
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_CPL_FIFO_DEPTH(TX_CPL_FIFO_DEPTH),
.TX_TAG_WIDTH(TX_TAG_WIDTH),
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.PFC_ENABLE(PFC_ENABLE),
.LFC_ENABLE(LFC_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE),
// Application block configuration
.APP_ID(APP_ID),
.APP_ENABLE(APP_ENABLE),
.APP_CTRL_ENABLE(APP_CTRL_ENABLE),
.APP_DMA_ENABLE(APP_DMA_ENABLE),
.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
.APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE),
.APP_STAT_ENABLE(APP_STAT_ENABLE),
// DMA interface configuration
.DMA_IMM_ENABLE(DMA_IMM_ENABLE),
.DMA_IMM_WIDTH(DMA_IMM_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
// PCIe interface configuration
.SEG_COUNT(SEG_COUNT),
.SEG_DATA_WIDTH(SEG_DATA_WIDTH),
.SEG_EMPTY_WIDTH(SEG_EMPTY_WIDTH),
.SEG_HDR_WIDTH(SEG_HDR_WIDTH),
.SEG_PRFX_WIDTH(SEG_PRFX_WIDTH),
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
.PF_COUNT(PF_COUNT),
.VF_COUNT(VF_COUNT),
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
// Interrupt configuration
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
// AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
// AXI lite interface configuration (application control)
.AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH),
.AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH),
// Ethernet interface configuration
.AXIS_ETH_DATA_WIDTH(AXIS_ETH_DATA_WIDTH),
.AXIS_ETH_KEEP_WIDTH(AXIS_ETH_KEEP_WIDTH),
.AXIS_ETH_SYNC_DATA_WIDTH(AXIS_ETH_SYNC_DATA_WIDTH),
.AXIS_ETH_TX_USER_WIDTH(AXIS_ETH_TX_USER_WIDTH),
.AXIS_ETH_RX_USER_WIDTH(AXIS_ETH_RX_USER_WIDTH),
.AXIS_ETH_TX_PIPELINE(AXIS_ETH_TX_PIPELINE),
.AXIS_ETH_TX_FIFO_PIPELINE(AXIS_ETH_TX_FIFO_PIPELINE),
.AXIS_ETH_TX_TS_PIPELINE(AXIS_ETH_TX_TS_PIPELINE),
.AXIS_ETH_RX_PIPELINE(AXIS_ETH_RX_PIPELINE),
.AXIS_ETH_RX_FIFO_PIPELINE(AXIS_ETH_RX_FIFO_PIPELINE),
// Statistics counter subsystem
.STAT_ENABLE(STAT_ENABLE),
.STAT_DMA_ENABLE(STAT_DMA_ENABLE),
.STAT_PCIE_ENABLE(STAT_PCIE_ENABLE),
.STAT_INC_WIDTH(STAT_INC_WIDTH),
.STAT_ID_WIDTH(STAT_ID_WIDTH)
)
uut (
/*
* Clock: 250 MHz
* Synchronous reset
*/
.clk_250mhz(clk_250mhz),
.rst_250mhz(rst_250mhz),
/*
* PTP clock
*/
.ptp_clk(ptp_clk),
.ptp_rst(ptp_rst),
.ptp_sample_clk(ptp_sample_clk),
/*
* GPIO
*/
.fpga_led(fpga_led),
.qsfpdd0_led0(qsfpdd0_led0),
.qsfpdd0_led1_g(qsfpdd0_led1_g),
.qsfpdd0_led1_y(qsfpdd0_led1_y),
.qsfpdd1_led0(qsfpdd1_led0),
.qsfpdd1_led1_g(qsfpdd1_led1_g),
.qsfpdd1_led1_y(qsfpdd1_led1_y),
/*
* I2C
*/
.fpga_i2c_scl_i(fpga_i2c_scl_i),
.fpga_i2c_scl_o(fpga_i2c_scl_o),
.fpga_i2c_scl_t(fpga_i2c_scl_t),
.fpga_i2c_sda_i(fpga_i2c_sda_i),
.fpga_i2c_sda_o(fpga_i2c_sda_o),
.fpga_i2c_sda_t(fpga_i2c_sda_t),
/*
* P-Tile interface
*/
.rx_st_data(rx_st_data),
.rx_st_empty(rx_st_empty),
.rx_st_sop(rx_st_sop),
.rx_st_eop(rx_st_eop),
.rx_st_valid(rx_st_valid),
.rx_st_ready(rx_st_ready),
.rx_st_hdr(rx_st_hdr),
.rx_st_tlp_prfx(rx_st_tlp_prfx),
.rx_st_vf_active(rx_st_vf_active),
.rx_st_func_num(rx_st_func_num),
.rx_st_vf_num(rx_st_vf_num),
.rx_st_bar_range(rx_st_bar_range),
.rx_st_tlp_abort(rx_st_tlp_abort),
.tx_st_data(tx_st_data),
.tx_st_sop(tx_st_sop),
.tx_st_eop(tx_st_eop),
.tx_st_valid(tx_st_valid),
.tx_st_ready(tx_st_ready),
.tx_st_err(tx_st_err),
.tx_st_hdr(tx_st_hdr),
.tx_st_tlp_prfx(tx_st_tlp_prfx),
.rx_buffer_limit(rx_buffer_limit),
.rx_buffer_limit_tdm_idx(rx_buffer_limit_tdm_idx),
.tx_cdts_limit(tx_cdts_limit),
.tx_cdts_limit_tdm_idx(tx_cdts_limit_tdm_idx),
.tl_cfg_ctl(tl_cfg_ctl),
.tl_cfg_add(tl_cfg_add),
.tl_cfg_func(tl_cfg_func),
/*
* Ethernet: QSFP-DD
*/
.qsfpdd_mac_tx_clk(qsfpdd_mac_tx_clk),
.qsfpdd_mac_tx_rst(qsfpdd_mac_tx_rst),
.qsfpdd_mac_tx_axis_tdata(qsfpdd_mac_tx_axis_tdata),
.qsfpdd_mac_tx_axis_tkeep(qsfpdd_mac_tx_axis_tkeep),
.qsfpdd_mac_tx_axis_tvalid(qsfpdd_mac_tx_axis_tvalid),
.qsfpdd_mac_tx_axis_tready(qsfpdd_mac_tx_axis_tready),
.qsfpdd_mac_tx_axis_tlast(qsfpdd_mac_tx_axis_tlast),
.qsfpdd_mac_tx_axis_tuser(qsfpdd_mac_tx_axis_tuser),
.qsfpdd_mac_tx_ptp_time(qsfpdd_mac_tx_ptp_time),
.qsfpdd_mac_tx_ptp_ts(qsfpdd_mac_tx_ptp_ts),
.qsfpdd_mac_tx_ptp_ts_tag(qsfpdd_mac_tx_ptp_ts_tag),
.qsfpdd_mac_tx_ptp_ts_valid(qsfpdd_mac_tx_ptp_ts_valid),
.qsfpdd_mac_tx_status(qsfpdd_mac_tx_status),
.qsfpdd_mac_tx_lfc_req(qsfpdd_mac_tx_lfc_req),
.qsfpdd_mac_tx_pfc_req(qsfpdd_mac_tx_pfc_req),
.qsfpdd_mac_rx_clk(qsfpdd_mac_rx_clk),
.qsfpdd_mac_rx_rst(qsfpdd_mac_rx_rst),
.qsfpdd_mac_rx_axis_tdata(qsfpdd_mac_rx_axis_tdata),
.qsfpdd_mac_rx_axis_tkeep(qsfpdd_mac_rx_axis_tkeep),
.qsfpdd_mac_rx_axis_tvalid(qsfpdd_mac_rx_axis_tvalid),
.qsfpdd_mac_rx_axis_tlast(qsfpdd_mac_rx_axis_tlast),
.qsfpdd_mac_rx_axis_tuser(qsfpdd_mac_rx_axis_tuser),
.qsfpdd_mac_rx_ptp_time(qsfpdd_mac_rx_ptp_time),
.qsfpdd_mac_rx_status(qsfpdd_mac_rx_status),
.qsfpdd_mac_rx_lfc_req(qsfpdd_mac_rx_lfc_req),
.qsfpdd_mac_rx_pfc_req(qsfpdd_mac_rx_pfc_req),
.qsfpdd0_modsel_l(qsfpdd0_modsel_l),
.qsfpdd0_reset_l(qsfpdd0_reset_l),
.qsfpdd0_modprs_l(qsfpdd0_modprs_l),
.qsfpdd0_lpmode(qsfpdd0_lpmode),
.qsfpdd0_int_l(qsfpdd0_int_l),
.qsfpdd1_modsel_l(qsfpdd1_modsel_l),
.qsfpdd1_reset_l(qsfpdd1_reset_l),
.qsfpdd1_modprs_l(qsfpdd1_modprs_l),
.qsfpdd1_lpmode(qsfpdd1_lpmode),
.qsfpdd1_int_l(qsfpdd1_int_l),
.qsfpdd_i2c_scl_i(qsfpdd_i2c_scl_i),
.qsfpdd_i2c_scl_o(qsfpdd_i2c_scl_o),
.qsfpdd_i2c_scl_t(qsfpdd_i2c_scl_t),
.qsfpdd_i2c_sda_i(qsfpdd_i2c_sda_i),
.qsfpdd_i2c_sda_o(qsfpdd_i2c_sda_o),
.qsfpdd_i2c_sda_t(qsfpdd_i2c_sda_t)
);
endmodule
`resetall