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fpga: Add DRAM bandwidth test to DMA benchmark application

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-03-29 14:27:46 -07:00
parent d6bac395f3
commit 3d06b34679
38 changed files with 813 additions and 124 deletions
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138
fpga/app/dma_bench/modules/mqnic_app_dma_bench/main.c
View File

@ -391,6 +391,7 @@ static int mqnic_app_dma_bench_probe(struct auxiliary_device *adev,
int mismatch = 0;
int k;
int rb_index;
dev_info(dev, "%s() called", __func__);
@ -448,6 +449,8 @@ static int mqnic_app_dma_bench_probe(struct auxiliary_device *adev,
print_counters(app);
// DMA test
dev_info(dev, "Run DMA benchmark");
dev_info(dev, "Write test data");
for (k = 0; k < 256; k++)
((char *)app->dma_region)[k] = k;
@ -546,6 +549,141 @@ static int mqnic_app_dma_bench_probe(struct auxiliary_device *adev,
dev_info(dev, "Statistics counters");
print_counters(app);
// DRAM test
rb_index = 0;
while ((rb = mqnic_find_reg_block(app->rb_list, 0x12348102, 0x00000100, rb_index))) {
u32 data_width;
u32 lane_count;
u64 size;
u64 base_addr;
u64 size_mask;
u64 cycles, time;
dev_info(dev, "Run DRAM benchmark (channel %d)", rb_index);
data_width = ioread32(rb->regs + 0x14);
lane_count = ioread32(rb->regs + 0x18);
dev_info(dev, "Address width: %d", ioread32(rb->regs + 0x10));
dev_info(dev, "Data width: %d", data_width);
base_addr = ioread32(rb->regs + 0x30);
base_addr |= ((u64)ioread32(rb->regs + 0x34)) << 32;
dev_info(dev, "Base address: 0x%016llx", base_addr);
size_mask = ioread32(rb->regs + 0x38);
size_mask |= ((u64)ioread32(rb->regs + 0x3C)) << 32;
dev_info(dev, "Size mask: 0x%016llx", size_mask);
// reset FIFO and data generator/checker
iowrite32(0x00000002, rb->regs + 0x20);
iowrite32(0x00000202, rb->regs + 0x24);
// enable FIFO
iowrite32(0x00000001, rb->regs + 0x20);
size = 1024*1024;
dev_info(dev, "Write test, size %lld", size);
// clear cycle count
iowrite32(0, rb->regs + 0x60);
// set up and start transfer
iowrite32(size, rb->regs + 0x68);
iowrite32(0, rb->regs + 0x6C);
iowrite32(0x00000001, rb->regs + 0x24);
// wait for transfer to complete
for (k = 0; k < 10; k++) {
udelay(10000);
if (ioread32(rb->regs + 0x24) == 0)
break;
}
dev_info(dev, "Status: %d", ioread32(rb->regs + 0x24));
dev_info(dev, "Occupancy: %d", ioread32(rb->regs + 0x50));
cycles = ioread32(rb->regs + 0x60);
time = mqnic_core_clk_cycles_to_ns(app->mdev, cycles);
dev_info(dev, "Time: %lld ns (%lld cycles)", time, cycles);
dev_info(dev, "Bandwidth: %lld Mbps", size*data_width*1000/time);
dev_info(dev, "Read+write test with offset, size %lld", size);
// clear cycle count
iowrite32(0, rb->regs + 0x60);
// set up and start transfer
iowrite32(size, rb->regs + 0x68);
iowrite32(size, rb->regs + 0x6C);
iowrite32(0x00000101, rb->regs + 0x24);
// wait for transfer to complete
for (k = 0; k < 10; k++) {
udelay(10000);
if (ioread32(rb->regs + 0x24) == 0)
break;
}
dev_info(dev, "Status: %d", ioread32(rb->regs + 0x24));
dev_info(dev, "Occupancy: %d", ioread32(rb->regs + 0x50));
cycles = ioread32(rb->regs + 0x60);
time = mqnic_core_clk_cycles_to_ns(app->mdev, cycles);
dev_info(dev, "Time: %lld ns (%lld cycles)", time, cycles);
dev_info(dev, "Bandwidth: %lld Mbps", size*data_width*1000/time);
dev_info(dev, "Read test, size %lld", size);
// clear cycle count
iowrite32(0, rb->regs + 0x60);
// set up and start transfer
iowrite32(0, rb->regs + 0x68);
iowrite32(size, rb->regs + 0x6C);
iowrite32(0x00000100, rb->regs + 0x24);
// wait for transfer to complete
for (k = 0; k < 10; k++) {
udelay(10000);
if (ioread32(rb->regs + 0x24) == 0)
break;
}
dev_info(dev, "Status: %d", ioread32(rb->regs + 0x24));
dev_info(dev, "Occupancy: %d", ioread32(rb->regs + 0x50));
cycles = ioread32(rb->regs + 0x60);
time = mqnic_core_clk_cycles_to_ns(app->mdev, cycles);
dev_info(dev, "Time: %lld ns (%lld cycles)", time, cycles);
dev_info(dev, "Bandwidth: %lld Mbps", size*data_width*1000/time);
dev_info(dev, "Read+write test, size %lld", size);
// clear cycle count
iowrite32(0, rb->regs + 0x60);
// set up and start transfer
iowrite32(size, rb->regs + 0x68);
iowrite32(size, rb->regs + 0x6C);
iowrite32(0x00000101, rb->regs + 0x24);
// wait for transfer to complete
for (k = 0; k < 10; k++) {
udelay(10000);
if (ioread32(rb->regs + 0x24) == 0)
break;
}
dev_info(dev, "Status: %d", ioread32(rb->regs + 0x24));
dev_info(dev, "Occupancy: %d", ioread32(rb->regs + 0x50));
cycles = ioread32(rb->regs + 0x60);
time = mqnic_core_clk_cycles_to_ns(app->mdev, cycles);
dev_info(dev, "Time: %lld ns (%lld cycles)", time, cycles);
dev_info(dev, "Bandwidth: %lld Mbps", size*data_width*1000/time);
for (k = 0; k < lane_count; k++) {
dev_info(dev, "Lane %d error count: %d", k, ioread32(rb->regs + 0x80 + k*4));
}
rb_index++;
}
return 0;
fail_dma_alloc:

507
fpga/app/dma_bench/rtl/mqnic_app_block_dma_bench.v
View File

@ -625,6 +625,13 @@ localparam RBB = RB_BASE_ADDR & {AXIL_APP_CTRL_ADDR_WIDTH{1'b1}};
localparam DMA_BENCH_RB_BASE_ADDR = RB_BASE_ADDR;
localparam DRAM_CH_RB_BASE_ADDR = DMA_BENCH_RB_BASE_ADDR + 16'h1000;
localparam DRAM_CH_RB_STRIDE = 16'h0100;
localparam DDR_CH_OFFSET = 0;
localparam HBM_CH_OFFSET = DDR_CH_OFFSET + (DDR_ENABLE ? DDR_CH : 0);
localparam DRAM_CH_COUNT = HBM_CH_OFFSET + (HBM_ENABLE ? HBM_CH : 0);
// check configuration
initial begin
if (APP_ID != 32'h12348001) begin
@ -749,72 +756,6 @@ assign m_axis_if_rx_tid = s_axis_if_rx_tid;
assign m_axis_if_rx_tdest = s_axis_if_rx_tdest;
assign m_axis_if_rx_tuser = s_axis_if_rx_tuser;
/*
* DDR
*/
assign m_axi_ddr_awid = 0;
assign m_axi_ddr_awaddr = 0;
assign m_axi_ddr_awlen = 0;
assign m_axi_ddr_awsize = 0;
assign m_axi_ddr_awburst = 0;
assign m_axi_ddr_awlock = 0;
assign m_axi_ddr_awcache = 0;
assign m_axi_ddr_awprot = 0;
assign m_axi_ddr_awqos = 0;
assign m_axi_ddr_awuser = 0;
assign m_axi_ddr_awvalid = 0;
assign m_axi_ddr_wdata = 0;
assign m_axi_ddr_wstrb = 0;
assign m_axi_ddr_wlast = 0;
assign m_axi_ddr_wuser = 0;
assign m_axi_ddr_wvalid = 0;
assign m_axi_ddr_bready = 0;
assign m_axi_ddr_arid = 0;
assign m_axi_ddr_araddr = 0;
assign m_axi_ddr_arlen = 0;
assign m_axi_ddr_arsize = 0;
assign m_axi_ddr_arburst = 0;
assign m_axi_ddr_arlock = 0;
assign m_axi_ddr_arcache = 0;
assign m_axi_ddr_arprot = 0;
assign m_axi_ddr_arqos = 0;
assign m_axi_ddr_aruser = 0;
assign m_axi_ddr_arvalid = 0;
assign m_axi_ddr_rready = 0;
/*
* HBM
*/
assign m_axi_hbm_awid = 0;
assign m_axi_hbm_awaddr = 0;
assign m_axi_hbm_awlen = 0;
assign m_axi_hbm_awsize = 0;
assign m_axi_hbm_awburst = 0;
assign m_axi_hbm_awlock = 0;
assign m_axi_hbm_awcache = 0;
assign m_axi_hbm_awprot = 0;
assign m_axi_hbm_awqos = 0;
assign m_axi_hbm_awuser = 0;
assign m_axi_hbm_awvalid = 0;
assign m_axi_hbm_wdata = 0;
assign m_axi_hbm_wstrb = 0;
assign m_axi_hbm_wlast = 0;
assign m_axi_hbm_wuser = 0;
assign m_axi_hbm_wvalid = 0;
assign m_axi_hbm_bready = 0;
assign m_axi_hbm_arid = 0;
assign m_axi_hbm_araddr = 0;
assign m_axi_hbm_arlen = 0;
assign m_axi_hbm_arsize = 0;
assign m_axi_hbm_arburst = 0;
assign m_axi_hbm_arlock = 0;
assign m_axi_hbm_arcache = 0;
assign m_axi_hbm_arprot = 0;
assign m_axi_hbm_arqos = 0;
assign m_axi_hbm_aruser = 0;
assign m_axi_hbm_arvalid = 0;
assign m_axi_hbm_rready = 0;
/*
* Statistics increment output
*/
@ -850,7 +791,7 @@ axil_reg_if #(
.DATA_WIDTH(REG_DATA_WIDTH),
.ADDR_WIDTH(REG_ADDR_WIDTH),
.STRB_WIDTH(REG_STRB_WIDTH),
.TIMEOUT(4)
.TIMEOUT(8)
)
axil_reg_if_inst (
.clk(clk),
@ -895,6 +836,49 @@ axil_reg_if_inst (
.reg_rd_ack(ctrl_reg_rd_ack)
);
wire dma_bench_ctrl_reg_wr_wait;
wire dma_bench_ctrl_reg_wr_ack;
wire [REG_DATA_WIDTH-1:0] dma_bench_ctrl_reg_rd_data;
wire dma_bench_ctrl_reg_rd_wait;
wire dma_bench_ctrl_reg_rd_ack;
wire ch_ctrl_reg_wr_wait[DRAM_CH_COUNT-1:0];
wire ch_ctrl_reg_wr_ack[DRAM_CH_COUNT-1:0];
wire [REG_DATA_WIDTH-1:0] ch_ctrl_reg_rd_data[DRAM_CH_COUNT-1:0];
wire ch_ctrl_reg_rd_wait[DRAM_CH_COUNT-1:0];
wire ch_ctrl_reg_rd_ack[DRAM_CH_COUNT-1:0];
reg ctrl_reg_wr_wait_cmb;
reg ctrl_reg_wr_ack_cmb;
reg [REG_DATA_WIDTH-1:0] ctrl_reg_rd_data_cmb;
reg ctrl_reg_rd_wait_cmb;
reg ctrl_reg_rd_ack_cmb;
assign ctrl_reg_wr_wait = ctrl_reg_wr_wait_cmb;
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_cmb;
assign ctrl_reg_rd_data = ctrl_reg_rd_data_cmb;
assign ctrl_reg_rd_wait = ctrl_reg_rd_wait_cmb;
assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_cmb;
integer k;
always @* begin
ctrl_reg_wr_wait_cmb = dma_bench_ctrl_reg_wr_wait;
ctrl_reg_wr_ack_cmb = dma_bench_ctrl_reg_wr_ack;
ctrl_reg_rd_data_cmb = dma_bench_ctrl_reg_rd_data;
ctrl_reg_rd_wait_cmb = dma_bench_ctrl_reg_rd_wait;
ctrl_reg_rd_ack_cmb = dma_bench_ctrl_reg_rd_ack;
for (k = 0; k < DRAM_CH_COUNT; k = k + 1) begin
ctrl_reg_wr_wait_cmb = ctrl_reg_wr_wait_cmb | ch_ctrl_reg_wr_wait[k];
ctrl_reg_wr_ack_cmb = ctrl_reg_wr_ack_cmb | ch_ctrl_reg_wr_ack[k];
ctrl_reg_rd_data_cmb = ctrl_reg_rd_data_cmb | ch_ctrl_reg_rd_data[k];
ctrl_reg_rd_wait_cmb = ctrl_reg_rd_wait_cmb | ch_ctrl_reg_rd_wait[k];
ctrl_reg_rd_ack_cmb = ctrl_reg_rd_ack_cmb | ch_ctrl_reg_rd_ack[k];
end
end
// DMA benchmark
dma_bench #(
// DMA interface configuration
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
@ -915,7 +899,7 @@ dma_bench #(
.REG_DATA_WIDTH(REG_DATA_WIDTH),
.REG_STRB_WIDTH(REG_STRB_WIDTH),
.RB_BASE_ADDR(DMA_BENCH_RB_BASE_ADDR),
.RB_NEXT_PTR(0)
.RB_NEXT_PTR((DDR_ENABLE || HBM_ENABLE) ? DRAM_CH_RB_BASE_ADDR : 0)
)
dma_bench_inst (
.clk(clk),
@ -928,13 +912,13 @@ dma_bench_inst (
.reg_wr_data(ctrl_reg_wr_data),
.reg_wr_strb(ctrl_reg_wr_strb),
.reg_wr_en(ctrl_reg_wr_en),
.reg_wr_wait(ctrl_reg_wr_wait),
.reg_wr_ack(ctrl_reg_wr_ack),
.reg_wr_wait(dma_bench_ctrl_reg_wr_wait),
.reg_wr_ack(dma_bench_ctrl_reg_wr_ack),
.reg_rd_addr(ctrl_reg_rd_addr),
.reg_rd_en(ctrl_reg_rd_en),
.reg_rd_data(ctrl_reg_rd_data),
.reg_rd_wait(ctrl_reg_rd_wait),
.reg_rd_ack(ctrl_reg_rd_ack),
.reg_rd_data(dma_bench_ctrl_reg_rd_data),
.reg_rd_wait(dma_bench_ctrl_reg_rd_wait),
.reg_rd_ack(dma_bench_ctrl_reg_rd_ack),
/*
* DMA read descriptor output
@ -993,6 +977,383 @@ dma_bench_inst (
.dma_ram_rd_resp_ready(data_dma_ram_rd_resp_ready)
);
// DRAM test
generate
genvar n;
if (DDR_ENABLE) begin : ddr
for (n = 0; n < DDR_CH; n = n + 1) begin : ddr_ch
localparam GROUP_INDEX = n % DDR_GROUP_SIZE;
localparam GROUP_ADDR_WIDTH = AXI_DDR_ADDR_WIDTH - $clog2(DDR_GROUP_SIZE);
localparam BASE_ADDR = ({AXI_DDR_ADDR_WIDTH{1'b0}} | GROUP_INDEX) << GROUP_ADDR_WIDTH;
localparam SIZE_MASK = {GROUP_ADDR_WIDTH{1'b1}};
(* shreg_extract = "no" *)
reg [REG_ADDR_WIDTH-1:0] ch_reg_wr_addr_reg = 0;
(* shreg_extract = "no" *)
reg [REG_DATA_WIDTH-1:0] ch_reg_wr_data_reg = 0;
(* shreg_extract = "no" *)
reg [REG_STRB_WIDTH-1:0] ch_reg_wr_strb_reg = 0;
(* shreg_extract = "no" *)
reg ch_reg_wr_en_reg = 1'b0;
(* shreg_extract = "no" *)
reg ch_reg_wr_wait_reg = 1'b0;
(* shreg_extract = "no" *)
reg ch_reg_wr_ack_reg = 1'b0;
(* shreg_extract = "no" *)
reg [REG_ADDR_WIDTH-1:0] ch_reg_rd_addr_reg = 0;
(* shreg_extract = "no" *)
reg ch_reg_rd_en_reg = 1'b0;
(* shreg_extract = "no" *)
reg [REG_DATA_WIDTH-1:0] ch_reg_rd_data_reg = 0;
(* shreg_extract = "no" *)
reg ch_reg_rd_wait_reg = 1'b0;
(* shreg_extract = "no" *)
reg ch_reg_rd_ack_reg = 1'b0;
wire ch_reg_wr_wait;
wire ch_reg_wr_ack;
wire [REG_DATA_WIDTH-1:0] ch_reg_rd_data;
wire ch_reg_rd_wait;
wire ch_reg_rd_ack;
always @(posedge clk) begin
ch_reg_wr_addr_reg <= ctrl_reg_wr_addr;
ch_reg_wr_data_reg <= ctrl_reg_wr_data;
ch_reg_wr_strb_reg <= ctrl_reg_wr_strb;
ch_reg_wr_en_reg <= ctrl_reg_wr_en;
ch_reg_wr_wait_reg <= ch_reg_wr_wait;
ch_reg_wr_ack_reg <= ch_reg_wr_ack;
ch_reg_rd_addr_reg <= ctrl_reg_rd_addr;
ch_reg_rd_en_reg <= ctrl_reg_rd_en;
ch_reg_rd_data_reg <= ch_reg_rd_data;
ch_reg_rd_wait_reg <= ch_reg_rd_wait;
ch_reg_rd_ack_reg <= ch_reg_rd_ack;
if (rst) begin
ch_reg_wr_en_reg <= 1'b0;
ch_reg_wr_wait_reg <= 1'b0;
ch_reg_wr_ack_reg <= 1'b0;
ch_reg_rd_en_reg <= 1'b0;
ch_reg_rd_wait_reg <= 1'b0;
ch_reg_rd_ack_reg <= 1'b0;
end
end
assign ch_ctrl_reg_wr_wait[DDR_CH_OFFSET+n] = ch_reg_wr_wait;
assign ch_ctrl_reg_wr_ack[DDR_CH_OFFSET+n] = ch_reg_wr_ack;
assign ch_ctrl_reg_rd_data[DDR_CH_OFFSET+n] = ch_reg_rd_data;
assign ch_ctrl_reg_rd_wait[DDR_CH_OFFSET+n] = ch_reg_rd_wait;
assign ch_ctrl_reg_rd_ack[DDR_CH_OFFSET+n] = ch_reg_rd_ack;
dram_test_ch #(
// AXI configuration
.AXI_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_DDR_ID_WIDTH),
.AXI_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
// FIFO config
.FIFO_BASE_ADDR(BASE_ADDR),
.FIFO_SIZE_MASK(SIZE_MASK),
// Register interface
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.REG_DATA_WIDTH(REG_DATA_WIDTH),
.REG_STRB_WIDTH(REG_STRB_WIDTH),
.RB_BASE_ADDR(DRAM_CH_RB_BASE_ADDR + (DDR_CH_OFFSET+n)*DRAM_CH_RB_STRIDE),
.RB_NEXT_PTR(DDR_CH_OFFSET+n < DRAM_CH_COUNT-1 ? DRAM_CH_RB_BASE_ADDR + (DDR_CH_OFFSET+n+1)*DRAM_CH_RB_STRIDE : 0)
)
dram_test_ch_inst (
.clk(clk),
.rst(rst),
/*
* Register interface
*/
.reg_wr_addr(ch_reg_wr_addr_reg),
.reg_wr_data(ch_reg_wr_data_reg),
.reg_wr_strb(ch_reg_wr_strb_reg),
.reg_wr_en(ch_reg_wr_en_reg),
.reg_wr_wait(ch_reg_wr_wait),
.reg_wr_ack(ch_reg_wr_ack),
.reg_rd_addr(ch_reg_rd_addr_reg),
.reg_rd_en(ch_reg_rd_en_reg),
.reg_rd_data(ch_reg_rd_data),
.reg_rd_wait(ch_reg_rd_wait),
.reg_rd_ack(ch_reg_rd_ack),
/*
* AXI master interface
*/
.m_axi_clk(ddr_clk[n]),
.m_axi_rst(ddr_rst[n]),
.m_axi_awid(m_axi_ddr_awid[n*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
.m_axi_awaddr(m_axi_ddr_awaddr[n*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
.m_axi_awlen(m_axi_ddr_awlen[n*8 +: 8]),
.m_axi_awsize(m_axi_ddr_awsize[n*3 +: 3]),
.m_axi_awburst(m_axi_ddr_awburst[n*2 +: 2]),
.m_axi_awlock(m_axi_ddr_awlock[n +: 1]),
.m_axi_awcache(m_axi_ddr_awcache[n*4 +: 4]),
.m_axi_awprot(m_axi_ddr_awprot[n*3 +: 3]),
.m_axi_awvalid(m_axi_ddr_awvalid[n +: 1]),
.m_axi_awready(m_axi_ddr_awready[n +: 1]),
.m_axi_wdata(m_axi_ddr_wdata[n*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
.m_axi_wstrb(m_axi_ddr_wstrb[n*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
.m_axi_wlast(m_axi_ddr_wlast[n +: 1]),
.m_axi_wvalid(m_axi_ddr_wvalid[n +: 1]),
.m_axi_wready(m_axi_ddr_wready[n +: 1]),
.m_axi_bid(m_axi_ddr_bid[n*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
.m_axi_bresp(m_axi_ddr_bresp[n*2 +: 2]),
.m_axi_bvalid(m_axi_ddr_bvalid[n +: 1]),
.m_axi_bready(m_axi_ddr_bready[n +: 1]),
.m_axi_arid(m_axi_ddr_arid[n*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
.m_axi_araddr(m_axi_ddr_araddr[n*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
.m_axi_arlen(m_axi_ddr_arlen[n*8 +: 8]),
.m_axi_arsize(m_axi_ddr_arsize[n*3 +: 3]),
.m_axi_arburst(m_axi_ddr_arburst[n*2 +: 2]),
.m_axi_arlock(m_axi_ddr_arlock[n +: 1]),
.m_axi_arcache(m_axi_ddr_arcache[n*4 +: 4]),
.m_axi_arprot(m_axi_ddr_arprot[n*3 +: 3]),
.m_axi_arvalid(m_axi_ddr_arvalid[n +: 1]),
.m_axi_arready(m_axi_ddr_arready[n +: 1]),
.m_axi_rid(m_axi_ddr_rid[n*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
.m_axi_rdata(m_axi_ddr_rdata[n*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
.m_axi_rresp(m_axi_ddr_rresp[n*2 +: 2]),
.m_axi_rlast(m_axi_ddr_rlast[n +: 1]),
.m_axi_rvalid(m_axi_ddr_rvalid[n +: 1]),
.m_axi_rready(m_axi_ddr_rready[n +: 1])
);
end
end else begin
assign m_axi_ddr_awid = 0;
assign m_axi_ddr_awaddr = 0;
assign m_axi_ddr_awlen = 0;
assign m_axi_ddr_awsize = 0;
assign m_axi_ddr_awburst = 0;
assign m_axi_ddr_awlock = 0;
assign m_axi_ddr_awcache = 0;
assign m_axi_ddr_awprot = 0;
assign m_axi_ddr_awvalid = 0;
assign m_axi_ddr_wdata = 0;
assign m_axi_ddr_wstrb = 0;
assign m_axi_ddr_wlast = 0;
assign m_axi_ddr_wvalid = 0;
assign m_axi_ddr_bready = 0;
assign m_axi_ddr_arid = 0;
assign m_axi_ddr_araddr = 0;
assign m_axi_ddr_arlen = 0;
assign m_axi_ddr_arsize = 0;
assign m_axi_ddr_arburst = 0;
assign m_axi_ddr_arlock = 0;
assign m_axi_ddr_arcache = 0;
assign m_axi_ddr_arprot = 0;
assign m_axi_ddr_arvalid = 0;
assign m_axi_ddr_rready = 0;
end
assign m_axi_ddr_awqos = 0;
assign m_axi_ddr_awuser = 0;
assign m_axi_ddr_wuser = 0;
assign m_axi_ddr_arqos = 0;
assign m_axi_ddr_aruser = 0;
if (HBM_ENABLE) begin : hbm
for (n = 0; n < HBM_CH; n = n + 1) begin : hbm_ch
localparam GROUP_INDEX = n % HBM_GROUP_SIZE;
localparam GROUP_ADDR_WIDTH = AXI_HBM_ADDR_WIDTH - $clog2(HBM_GROUP_SIZE);
localparam BASE_ADDR = ({AXI_HBM_ADDR_WIDTH{1'b0}} | GROUP_INDEX) << GROUP_ADDR_WIDTH;
localparam SIZE_MASK = {GROUP_ADDR_WIDTH{1'b1}};
(* shreg_extract = "no" *)
reg [REG_ADDR_WIDTH-1:0] ch_reg_wr_addr_reg = 0;
(* shreg_extract = "no" *)
reg [REG_DATA_WIDTH-1:0] ch_reg_wr_data_reg = 0;
(* shreg_extract = "no" *)
reg [REG_STRB_WIDTH-1:0] ch_reg_wr_strb_reg = 0;
(* shreg_extract = "no" *)
reg ch_reg_wr_en_reg = 1'b0;
(* shreg_extract = "no" *)
reg ch_reg_wr_wait_reg = 1'b0;
(* shreg_extract = "no" *)
reg ch_reg_wr_ack_reg = 1'b0;
(* shreg_extract = "no" *)
reg [REG_ADDR_WIDTH-1:0] ch_reg_rd_addr_reg = 0;
(* shreg_extract = "no" *)
reg ch_reg_rd_en_reg = 1'b0;
(* shreg_extract = "no" *)
reg [REG_DATA_WIDTH-1:0] ch_reg_rd_data_reg = 0;
(* shreg_extract = "no" *)
reg ch_reg_rd_wait_reg = 1'b0;
(* shreg_extract = "no" *)
reg ch_reg_rd_ack_reg = 1'b0;
wire ch_reg_wr_wait;
wire ch_reg_wr_ack;
wire [REG_DATA_WIDTH-1:0] ch_reg_rd_data;
wire ch_reg_rd_wait;
wire ch_reg_rd_ack;
always @(posedge clk) begin
ch_reg_wr_addr_reg <= ctrl_reg_wr_addr;
ch_reg_wr_data_reg <= ctrl_reg_wr_data;
ch_reg_wr_strb_reg <= ctrl_reg_wr_strb;
ch_reg_wr_en_reg <= ctrl_reg_wr_en;
ch_reg_wr_wait_reg <= ch_reg_wr_wait;
ch_reg_wr_ack_reg <= ch_reg_wr_ack;
ch_reg_rd_addr_reg <= ctrl_reg_rd_addr;
ch_reg_rd_en_reg <= ctrl_reg_rd_en;
ch_reg_rd_data_reg <= ch_reg_rd_data;
ch_reg_rd_wait_reg <= ch_reg_rd_wait;
ch_reg_rd_ack_reg <= ch_reg_rd_ack;
if (rst) begin
ch_reg_wr_en_reg <= 1'b0;
ch_reg_wr_wait_reg <= 1'b0;
ch_reg_wr_ack_reg <= 1'b0;
ch_reg_rd_en_reg <= 1'b0;
ch_reg_rd_wait_reg <= 1'b0;
ch_reg_rd_ack_reg <= 1'b0;
end
end
assign ch_ctrl_reg_wr_wait[HBM_CH_OFFSET+n] = ch_reg_wr_wait;
assign ch_ctrl_reg_wr_ack[HBM_CH_OFFSET+n] = ch_reg_wr_ack;
assign ch_ctrl_reg_rd_data[HBM_CH_OFFSET+n] = ch_reg_rd_data;
assign ch_ctrl_reg_rd_wait[HBM_CH_OFFSET+n] = ch_reg_rd_wait;
assign ch_ctrl_reg_rd_ack[HBM_CH_OFFSET+n] = ch_reg_rd_ack;
dram_test_ch #(
// AXI configuration
.AXI_DATA_WIDTH(AXI_HBM_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_HBM_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_HBM_ID_WIDTH),
.AXI_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN),
// FIFO config
.FIFO_BASE_ADDR(BASE_ADDR),
.FIFO_SIZE_MASK(SIZE_MASK),
// Register interface
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.REG_DATA_WIDTH(REG_DATA_WIDTH),
.REG_STRB_WIDTH(REG_STRB_WIDTH),
.RB_BASE_ADDR(DRAM_CH_RB_BASE_ADDR + (HBM_CH_OFFSET+n)*DRAM_CH_RB_STRIDE),
.RB_NEXT_PTR(HBM_CH_OFFSET+n < DRAM_CH_COUNT-1 ? DRAM_CH_RB_BASE_ADDR + (HBM_CH_OFFSET+n+1)*DRAM_CH_RB_STRIDE : 0)
)
dram_test_ch_inst (
.clk(clk),
.rst(rst),
/*
* Register interface
*/
.reg_wr_addr(ch_reg_wr_addr_reg),
.reg_wr_data(ch_reg_wr_data_reg),
.reg_wr_strb(ch_reg_wr_strb_reg),
.reg_wr_en(ch_reg_wr_en_reg),
.reg_wr_wait(ch_reg_wr_wait),
.reg_wr_ack(ch_reg_wr_ack),
.reg_rd_addr(ch_reg_rd_addr_reg),
.reg_rd_en(ch_reg_rd_en_reg),
.reg_rd_data(ch_reg_rd_data),
.reg_rd_wait(ch_reg_rd_wait),
.reg_rd_ack(ch_reg_rd_ack),
/*
* AXI master interface
*/
.m_axi_clk(hbm_clk[n]),
.m_axi_rst(hbm_rst[n]),
.m_axi_awid(m_axi_hbm_awid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]),
.m_axi_awaddr(m_axi_hbm_awaddr[n*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]),
.m_axi_awlen(m_axi_hbm_awlen[n*8 +: 8]),
.m_axi_awsize(m_axi_hbm_awsize[n*3 +: 3]),
.m_axi_awburst(m_axi_hbm_awburst[n*2 +: 2]),
.m_axi_awlock(m_axi_hbm_awlock[n +: 1]),
.m_axi_awcache(m_axi_hbm_awcache[n*4 +: 4]),
.m_axi_awprot(m_axi_hbm_awprot[n*3 +: 3]),
.m_axi_awvalid(m_axi_hbm_awvalid[n +: 1]),
.m_axi_awready(m_axi_hbm_awready[n +: 1]),
.m_axi_wdata(m_axi_hbm_wdata[n*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]),
.m_axi_wstrb(m_axi_hbm_wstrb[n*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]),
.m_axi_wlast(m_axi_hbm_wlast[n +: 1]),
.m_axi_wvalid(m_axi_hbm_wvalid[n +: 1]),
.m_axi_wready(m_axi_hbm_wready[n +: 1]),
.m_axi_bid(m_axi_hbm_bid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]),
.m_axi_bresp(m_axi_hbm_bresp[n*2 +: 2]),
.m_axi_bvalid(m_axi_hbm_bvalid[n +: 1]),
.m_axi_bready(m_axi_hbm_bready[n +: 1]),
.m_axi_arid(m_axi_hbm_arid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]),
.m_axi_araddr(m_axi_hbm_araddr[n*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]),
.m_axi_arlen(m_axi_hbm_arlen[n*8 +: 8]),
.m_axi_arsize(m_axi_hbm_arsize[n*3 +: 3]),
.m_axi_arburst(m_axi_hbm_arburst[n*2 +: 2]),
.m_axi_arlock(m_axi_hbm_arlock[n +: 1]),
.m_axi_arcache(m_axi_hbm_arcache[n*4 +: 4]),
.m_axi_arprot(m_axi_hbm_arprot[n*3 +: 3]),
.m_axi_arvalid(m_axi_hbm_arvalid[n +: 1]),
.m_axi_arready(m_axi_hbm_arready[n +: 1]),
.m_axi_rid(m_axi_hbm_rid[n*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]),
.m_axi_rdata(m_axi_hbm_rdata[n*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]),
.m_axi_rresp(m_axi_hbm_rresp[n*2 +: 2]),
.m_axi_rlast(m_axi_hbm_rlast[n +: 1]),
.m_axi_rvalid(m_axi_hbm_rvalid[n +: 1]),
.m_axi_rready(m_axi_hbm_rready[n +: 1])
);
end
end else begin
assign m_axi_hbm_awid = 0;
assign m_axi_hbm_awaddr = 0;
assign m_axi_hbm_awlen = 0;
assign m_axi_hbm_awsize = 0;
assign m_axi_hbm_awburst = 0;
assign m_axi_hbm_awlock = 0;
assign m_axi_hbm_awcache = 0;
assign m_axi_hbm_awprot = 0;
assign m_axi_hbm_awvalid = 0;
assign m_axi_hbm_wdata = 0;
assign m_axi_hbm_wstrb = 0;
assign m_axi_hbm_wlast = 0;
assign m_axi_hbm_wvalid = 0;
assign m_axi_hbm_bready = 0;
assign m_axi_hbm_arid = 0;
assign m_axi_hbm_araddr = 0;
assign m_axi_hbm_arlen = 0;
assign m_axi_hbm_arsize = 0;
assign m_axi_hbm_arburst = 0;
assign m_axi_hbm_arlock = 0;
assign m_axi_hbm_arcache = 0;
assign m_axi_hbm_arprot = 0;
assign m_axi_hbm_arvalid = 0;
assign m_axi_hbm_rready = 0;
end
assign m_axi_hbm_awqos = 0;
assign m_axi_hbm_awuser = 0;
assign m_axi_hbm_wuser = 0;
assign m_axi_hbm_arqos = 0;
assign m_axi_hbm_aruser = 0;
endgenerate
endmodule
`resetall

20
fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile
View File

@ -82,10 +82,14 @@ VERILOG_SOURCES += ../../rtl/common/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/common/tx_scheduler_rr.v
VERILOG_SOURCES += ../../rtl/mqnic_app_block_dma_bench.v
VERILOG_SOURCES += ../../rtl/dma_bench.v
VERILOG_SOURCES += ../../rtl/dram_test_ch.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_ts_extract.v
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axi_vfifo_raw.v
VERILOG_SOURCES += ../../lib/axi/rtl/axi_vfifo_raw_rd.v
VERILOG_SOURCES += ../../lib/axi/rtl/axi_vfifo_raw_wr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v
@ -200,18 +204,18 @@ export PARAM_TX_RAM_SIZE := 131072
export PARAM_RX_RAM_SIZE := 131072
# RAM configuration
export PARAM_DDR_CH := 1
export PARAM_DDR_ENABLE := 0
export PARAM_DDR_CH := 2
export PARAM_DDR_ENABLE := 1
export PARAM_DDR_GROUP_SIZE := 1
export PARAM_AXI_DDR_DATA_WIDTH := 256
export PARAM_AXI_DDR_ADDR_WIDTH := 32
export PARAM_AXI_DDR_DATA_WIDTH := 512
export PARAM_AXI_DDR_ADDR_WIDTH := 34
export PARAM_AXI_DDR_ID_WIDTH := 8
export PARAM_AXI_DDR_MAX_BURST_LEN := 256
export PARAM_HBM_CH := 1
export PARAM_HBM_ENABLE := 0
export PARAM_HBM_CH := 2
export PARAM_HBM_ENABLE := 1
export PARAM_HBM_GROUP_SIZE := $(PARAM_HBM_CH)
export PARAM_AXI_HBM_DATA_WIDTH := 256
export PARAM_AXI_HBM_ADDR_WIDTH := 32
export PARAM_AXI_HBM_ADDR_WIDTH := 33
export PARAM_AXI_HBM_ID_WIDTH := 6
export PARAM_AXI_HBM_MAX_BURST_LEN := 16

56
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -861,6 +861,42 @@ async def run_test_nic(dut):
assert mem[src_offset:src_offset+region_len] == mem[dest_offset:dest_offset+region_len]
tb.log.info("Test DRAM channels")
index = 0
while True:
dram_test_rb = app_reg_blocks.find(0x12348102, 0x00000100, index)
index = index+1
if not dram_test_rb:
break
# configure FIFO
await dram_test_rb.write_dword(0x48, (16*2**20)-1)
await dram_test_rb.write_dword(0x4C, 0x00000000)
# reset FIFO and data generator/checker
await dram_test_rb.write_dword(0x20, 0x00000002)
await dram_test_rb.write_dword(0x20, 0x00000202)
await Timer(100, 'ns')
# enable FIFO
await dram_test_rb.write_dword(0x20, 0x00000001)
# enable data generation and checking
await dram_test_rb.write_dword(0x68, 1024)
await dram_test_rb.write_dword(0x6C, 1024)
await dram_test_rb.write_dword(0x24, 0x00000101)
# wait for transfer to complete
while True:
val = await dram_test_rb.read_dword(0x24)
if val == 0:
break
await Timer(1000, 'ns')
tb.log.info("Read statistics counters")
await Timer(2000, 'ns')
@ -949,10 +985,14 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
os.path.join(rtl_dir, "common", "tx_scheduler_rr.v"),
os.path.join(rtl_dir, "mqnic_app_block_dma_bench.v"),
os.path.join(rtl_dir, "dma_bench.v"),
os.path.join(rtl_dir, "dram_test_ch.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(eth_rtl_dir, "ptp_ts_extract.v"),
os.path.join(eth_rtl_dir, "lfsr.v"),
os.path.join(axi_rtl_dir, "axi_vfifo_raw.v"),
os.path.join(axi_rtl_dir, "axi_vfifo_raw_rd.v"),
os.path.join(axi_rtl_dir, "axi_vfifo_raw_wr.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"),
@ -1067,18 +1107,18 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt
parameters['RX_RAM_SIZE'] = 131072
# RAM configuration
parameters['DDR_CH'] = 1
parameters['DDR_ENABLE'] = 0
parameters['DDR_CH'] = 2
parameters['DDR_ENABLE'] = 1
parameters['DDR_GROUP_SIZE'] = 1
parameters['AXI_DDR_DATA_WIDTH'] = 256
parameters['AXI_DDR_ADDR_WIDTH'] = 32
parameters['AXI_DDR_DATA_WIDTH'] = 512
parameters['AXI_DDR_ADDR_WIDTH'] = 34
parameters['AXI_DDR_ID_WIDTH'] = 8
parameters['AXI_DDR_MAX_BURST_LEN'] = 256
parameters['HBM_CH'] = 1
parameters['HBM_ENABLE'] = 0
parameters['HBM_CH'] = 2
parameters['HBM_ENABLE'] = 1
parameters['HBM_GROUP_SIZE'] = parameters['HBM_CH']
parameters['AXI_HBM_DATA_WIDTH'] = 256
parameters['AXI_HBM_ADDR_WIDTH'] = 32
parameters['AXI_HBM_ADDR_WIDTH'] = 33
parameters['AXI_HBM_ID_WIDTH'] = 6
parameters['AXI_HBM_MAX_BURST_LEN'] = 16

9
fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -58,9 +58,14 @@ SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
@ -114,6 +119,9 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += placement.xdc
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -123,6 +131,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

4
fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -191,8 +191,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

9
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -59,9 +59,14 @@ SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
@ -116,6 +121,9 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
XDC_FILES = fpga.xdc
XDC_FILES += placement.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -125,6 +133,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

4
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -194,8 +194,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

9
fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -59,9 +59,14 @@ SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
SYN_FILES += lib/axi/rtl/axil_cdc_wr.v
@ -121,6 +126,9 @@ XDC_FILES += placement.xdc
XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -130,6 +138,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

4
fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -191,8 +191,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

9
fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -59,9 +59,14 @@ SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
SYN_FILES += lib/axi/rtl/axil_cdc_wr.v
@ -121,6 +126,9 @@ XDC_FILES += placement.xdc
XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -130,6 +138,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

4
fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -191,8 +191,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

9
fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -58,9 +58,14 @@ SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
SYN_FILES += lib/axi/rtl/axil_cdc_wr.v
@ -119,6 +124,9 @@ XDC_FILES = fpga.xdc
XDC_FILES += placement.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -129,6 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
XDC_FILES += hbm.xdc
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl

8
fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -141,8 +141,8 @@ dict set params DDR_CH "2"
dict set params DDR_ENABLE "1"
dict set params AXI_DDR_ID_WIDTH "8"
dict set params AXI_DDR_MAX_BURST_LEN "256"
dict set params HBM_CH "32"
dict set params HBM_ENABLE "1"
dict set params HBM_CH "16"
dict set params HBM_ENABLE "0"
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_MAX_BURST_LEN "16"
@ -195,8 +195,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

9
fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -58,9 +58,14 @@ SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_cdc.v
SYN_FILES += lib/axi/rtl/axil_cdc_rd.v
SYN_FILES += lib/axi/rtl/axil_cdc_wr.v
@ -119,6 +124,9 @@ XDC_FILES = fpga.xdc
XDC_FILES += placement.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axil_cdc.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -129,6 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
XDC_FILES += hbm.xdc
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl

2
fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -137,7 +137,7 @@ dict set params TX_RAM_SIZE "131072"
dict set params RX_RAM_SIZE "131072"
# RAM configuration
dict set params HBM_CH "32"
dict set params HBM_CH "16"
dict set params HBM_ENABLE "1"
dict set params HBM_GROUP_SIZE [dict get $params HBM_CH]
dict set params AXI_HBM_MAX_BURST_LEN "16"

8
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile
View File

@ -59,6 +59,7 @@ SYN_FILES += rtl/common/tdma_ber.v
SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
@ -76,6 +77,9 @@ SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
@ -129,6 +133,9 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -138,6 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl

4
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/config.tcl
View File

@ -194,8 +194,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

8
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile
View File

@ -59,6 +59,7 @@ SYN_FILES += rtl/common/tdma_ber.v
SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
@ -76,6 +77,9 @@ SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
@ -129,6 +133,9 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -138,6 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl

4
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/config.tcl
View File

@ -194,8 +194,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

8
fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile
View File

@ -59,6 +59,7 @@ SYN_FILES += rtl/common/tdma_ber.v
SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
@ -76,6 +77,9 @@ SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
@ -129,6 +133,9 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -138,6 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

4
fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/config.tcl
View File

@ -204,8 +204,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

8
fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile
View File

@ -60,6 +60,7 @@ SYN_FILES += rtl/common/tdma_ber.v
SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
@ -77,6 +78,9 @@ SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
@ -131,6 +135,9 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
XDC_FILES = fpga.xdc
XDC_FILES += placement.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -140,6 +147,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl

4
fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/config.tcl
View File

@ -204,8 +204,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

9
fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -59,9 +59,14 @@ SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
@ -116,6 +121,9 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
XDC_FILES = fpga.xdc
XDC_FILES += placement.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -125,6 +133,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

4
fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -191,8 +191,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

9
fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -59,9 +59,14 @@ SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
@ -117,6 +122,9 @@ XDC_FILES = fpga.xdc
XDC_FILES += placement.xdc
XDC_FILES += cfgmclk.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -126,6 +134,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

4
fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -191,8 +191,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

9
fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -58,9 +58,14 @@ SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
@ -115,6 +120,9 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
XDC_FILES = fpga.xdc
XDC_FILES += placement.xdc
XDC_FILES += boot.xdc
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -124,6 +132,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

4
fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -191,8 +191,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

8
fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile
View File

@ -56,6 +56,7 @@ SYN_FILES += rtl/common/tdma_ber.v
SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
@ -73,6 +74,9 @@ SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
@ -111,6 +115,9 @@ SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -120,6 +127,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/zynq_ps.tcl

4
fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/config.tcl
View File

@ -204,8 +204,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

8
fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile
View File

@ -60,6 +60,7 @@ SYN_FILES += rtl/common/tdma_ber.v
SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
@ -77,6 +78,9 @@ SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
@ -129,6 +133,9 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -138,6 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

4
fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/config.tcl
View File

@ -194,8 +194,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

8
fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile
View File

@ -56,6 +56,7 @@ SYN_FILES += rtl/common/tdma_ber.v
SYN_FILES += rtl/common/tdma_ber_ch.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
@ -73,6 +74,9 @@ SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
@ -111,6 +115,9 @@ SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
# XDC files
XDC_FILES = fpga.xdc
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -120,6 +127,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/zynq_ps.tcl

4
fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/config.tcl
View File

@ -204,8 +204,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4

9
fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile
View File

@ -60,9 +60,14 @@ SYN_FILES += rtl/common/cmac_pad.v
SYN_FILES += rtl/common/mac_ts_insert.v
SYN_FILES += app/dma_bench/rtl/mqnic_app_block_dma_bench.v
SYN_FILES += app/dma_bench/rtl/dma_bench.v
SYN_FILES += app/dma_bench/rtl/dram_test_ch.v
SYN_FILES += lib/eth/rtl/ptp_clock.v
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
SYN_FILES += lib/eth/rtl/ptp_perout.v
SYN_FILES += lib/eth/rtl/lfsr.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_rd.v
SYN_FILES += lib/axi/rtl/axi_vfifo_raw_wr.v
SYN_FILES += lib/axi/rtl/axil_interconnect.v
SYN_FILES += lib/axi/rtl/axil_crossbar.v
SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
@ -118,6 +123,9 @@ XDC_FILES = fpga.xdc
XDC_FILES += placement.xdc
XDC_FILES += boot.xdc
XDC_FILES += led.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
@ -127,6 +135,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
# IP
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl

4
fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -191,8 +191,8 @@ if {[dict get $params DDR_ENABLE]} {
# performance-related configuration
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {false} $ddr4
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK} $ddr4
# set AXI ID width
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4