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fpga/common: Fix MTU register write addresses

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-04-12 14:10:47 -07:00
parent 57905a5ef9
commit 3d5dc74e01
1 changed files with 2 additions and 2 deletions
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4
fpga/common/rtl/mqnic_interface.v
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@ -942,8 +942,8 @@ always @(posedge clk) begin
ctrl_reg_wr_ack_reg <= 1'b1;
case ({ctrl_reg_wr_addr >> 2, 2'b00})
// Interface control
RBB+8'h18: tx_mtu_reg <= ctrl_reg_wr_data; // IF ctrl: TX MTU
RBB+8'h1C: rx_mtu_reg <= ctrl_reg_wr_data; // IF ctrl: RX MTU
RBB+8'h28: tx_mtu_reg <= ctrl_reg_wr_data; // IF ctrl: TX MTU
RBB+8'h2C: rx_mtu_reg <= ctrl_reg_wr_data; // IF ctrl: RX MTU
RBB+8'h30: rss_mask_reg <= ctrl_reg_wr_data; // IF ctrl: RSS mask
default: ctrl_reg_wr_ack_reg <= 1'b0;
endcase