From 3e03b20bc78368958933703a41e8acf613169050 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 24 Jul 2021 01:13:25 -0700 Subject: [PATCH] Properly handle zero-length PCIe read and write operations --- rtl/pcie_us_axi_master_rd.v | 2 +- rtl/pcie_us_axil_master.v | 2 +- tb/pcie_us_axi_master/test_pcie_us_axi_master.py | 4 ++-- .../test_pcie_us_axi_master_rd.py | 2 +- .../test_pcie_us_axi_master_wr.py | 2 +- tb/pcie_us_axil_master/test_pcie_us_axil_master.py | 12 +++++++++--- 6 files changed, 15 insertions(+), 9 deletions(-) diff --git a/rtl/pcie_us_axi_master_rd.v b/rtl/pcie_us_axi_master_rd.v index 046bcb804..a2d1f6387 100644 --- a/rtl/pcie_us_axi_master_rd.v +++ b/rtl/pcie_us_axi_master_rd.v @@ -306,7 +306,7 @@ assign status_error_uncor = status_error_uncor_reg; always @* begin casez (first_be_next) - 4'b0000: single_dword_len = 3'd0; + 4'b0000: single_dword_len = 3'd1; 4'b0001: single_dword_len = 3'd1; 4'b0010: single_dword_len = 3'd1; 4'b0100: single_dword_len = 3'd1; diff --git a/rtl/pcie_us_axil_master.v b/rtl/pcie_us_axil_master.v index df543f3b6..ae3b5b28d 100644 --- a/rtl/pcie_us_axil_master.v +++ b/rtl/pcie_us_axil_master.v @@ -272,7 +272,7 @@ always @* begin endcase m_axis_cc_tdata_int[9:8] = at_reg; casez (first_be_reg) - 4'b0000: m_axis_cc_tdata_int[28:16] = 13'd0; // Byte count + 4'b0000: m_axis_cc_tdata_int[28:16] = 13'd1; // Byte count 4'b0001: m_axis_cc_tdata_int[28:16] = 13'd1; // Byte count 4'b0010: m_axis_cc_tdata_int[28:16] = 13'd1; // Byte count 4'b0100: m_axis_cc_tdata_int[28:16] = 13'd1; // Byte count diff --git a/tb/pcie_us_axi_master/test_pcie_us_axi_master.py b/tb/pcie_us_axi_master/test_pcie_us_axi_master.py index 7058e5c44..b8a0a84e4 100644 --- a/tb/pcie_us_axi_master/test_pcie_us_axi_master.py +++ b/tb/pcie_us_axi_master/test_pcie_us_axi_master.py @@ -157,7 +157,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None): dev_bar0 = tb.rc.tree[0][0].bar_addr[0] - for length in list(range(1, byte_lanes*2))+[1024]: + for length in list(range(0, byte_lanes*2))+[1024]: for pcie_offset in range(byte_lanes): tb.log.info("length %d, pcie_offset %d", length, pcie_offset) pcie_addr = pcie_offset+0x1000 @@ -196,7 +196,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None): dev_bar0 = tb.rc.tree[0][0].bar_addr[0] - for length in list(range(1, byte_lanes*2))+[1024]: + for length in list(range(0, byte_lanes*2))+[1024]: for pcie_offset in range(byte_lanes): tb.log.info("length %d, pcie_offset %d", length, pcie_offset) pcie_addr = pcie_offset+0x1000 diff --git a/tb/pcie_us_axi_master_rd/test_pcie_us_axi_master_rd.py b/tb/pcie_us_axi_master_rd/test_pcie_us_axi_master_rd.py index f995d2d68..84834c079 100644 --- a/tb/pcie_us_axi_master_rd/test_pcie_us_axi_master_rd.py +++ b/tb/pcie_us_axi_master_rd/test_pcie_us_axi_master_rd.py @@ -154,7 +154,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None): dev_bar0 = tb.rc.tree[0][0].bar_addr[0] - for length in list(range(1, byte_lanes*2))+[1024]: + for length in list(range(0, byte_lanes*2))+[1024]: for pcie_offset in list(range(byte_lanes))+list(range(4096-byte_lanes, 4096)): tb.log.info("length %d, pcie_offset %d", length, pcie_offset) pcie_addr = pcie_offset+0x1000 diff --git a/tb/pcie_us_axi_master_wr/test_pcie_us_axi_master_wr.py b/tb/pcie_us_axi_master_wr/test_pcie_us_axi_master_wr.py index 629394588..88d689275 100644 --- a/tb/pcie_us_axi_master_wr/test_pcie_us_axi_master_wr.py +++ b/tb/pcie_us_axi_master_wr/test_pcie_us_axi_master_wr.py @@ -139,7 +139,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None): dev_bar0 = tb.rc.tree[0][0].bar_addr[0] - for length in list(range(1, byte_lanes*2))+[1024]: + for length in list(range(0, byte_lanes*2))+[1024]: for pcie_offset in list(range(byte_lanes))+list(range(4096-byte_lanes, 4096)): tb.log.info("length %d, pcie_offset %d", length, pcie_offset) pcie_addr = pcie_offset+0x1000 diff --git a/tb/pcie_us_axil_master/test_pcie_us_axil_master.py b/tb/pcie_us_axil_master/test_pcie_us_axil_master.py index a87e3ad3c..5def3e5be 100644 --- a/tb/pcie_us_axil_master/test_pcie_us_axil_master.py +++ b/tb/pcie_us_axil_master/test_pcie_us_axil_master.py @@ -154,7 +154,7 @@ async def run_test_write(dut, idle_inserter=None, backpressure_inserter=None): dev_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_bar1 = tb.rc.tree[0][0].bar_addr[1] - for length in range(1, 5): + for length in range(0, 5): for pcie_offset in range(4-length+1): tb.log.info("length %d, pcie_offset %d", length, pcie_offset) pcie_addr = pcie_offset+0x1000 @@ -192,7 +192,7 @@ async def run_test_read(dut, idle_inserter=None, backpressure_inserter=None): dev_bar0 = tb.rc.tree[0][0].bar_addr[0] dev_bar1 = tb.rc.tree[0][0].bar_addr[1] - for length in range(1, 5): + for length in range(0, 5): for pcie_offset in range(4-length+1): tb.log.info("length %d, pcie_offset %d", length, pcie_offset) pcie_addr = pcie_offset+0x1000 @@ -355,7 +355,13 @@ def cycle_pause(): if cocotb.SIM_NAME: - for test in [run_test_write, run_test_read, run_test_io_write, run_test_io_read, run_test_bad_ops]: + for test in [ + run_test_write, + run_test_read, + run_test_io_write, + run_test_io_read, + run_test_bad_ops + ]: factory = TestFactory(test) factory.add_option("idle_inserter", [None, cycle_pause])