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https://github.com/corundum/corundum.git
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Use MSI-X in example designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
e2588cd995
commit
3f334dbbbb
@ -17,7 +17,6 @@ SYN_FILES += lib/pcie/rtl/pcie_s10_if.v
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SYN_FILES += lib/pcie/rtl/pcie_s10_if_rx.v
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SYN_FILES += lib/pcie/rtl/pcie_s10_if_tx.v
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SYN_FILES += lib/pcie/rtl/pcie_s10_cfg.v
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SYN_FILES += lib/pcie/rtl/pcie_s10_msi.v
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SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
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SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
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SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
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@ -28,11 +27,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
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SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
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SYN_FILES += lib/pcie/rtl/pcie_msix.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
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SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
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SYN_FILES += lib/pcie/rtl/dma_psdpram.v
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SYN_FILES += lib/pcie/rtl/arbiter.v
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SYN_FILES += lib/pcie/rtl/priority_encoder.v
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SYN_FILES += lib/pcie/rtl/pulse_merge.v
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@ -6,7 +6,7 @@ proc do_create_pcie {} {
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create_system pcie
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set_project_property DEVICE {1SM21CHU2F53E2VG}
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set_project_property DEVICE_FAMILY {Stratix 10}
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set_project_property HIDE_FROM_IP_CATALOG {true}
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set_project_property HIDE_FROM_IP_CATALOG {false}
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set_use_testbench_naming_pattern 0 {}
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# add HDL parameters
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@ -54,20 +54,20 @@ proc do_create_pcie {} {
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar2_type_hwtcl} {64-bit prefetchable memory}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar3_address_width_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar3_type_hwtcl} {Disabled}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar4_address_width_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar4_type_hwtcl} {Disabled}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar4_address_width_hwtcl} {16}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar4_type_hwtcl} {64-bit prefetchable memory}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar5_address_width_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar5_type_hwtcl} {Disabled}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_class_code_hwtcl} {16711680}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_eq_eieos_cnt_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_expansion_base_address_register_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_loopback_enable_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msi_multiple_msg_cap_hwtcl} {32}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_bir_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_pba_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_pba_offset_hwtcl} {0.0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msi_multiple_msg_cap_hwtcl} {1}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_bir_hwtcl} {4}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_pba_hwtcl} {4}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_pba_offset_hwtcl} {8192.0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_offset_hwtcl} {0.0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_size_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_size_hwtcl} {31}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_type0_device_id_hwtcl} {1}
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set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_type0_vendor_id_hwtcl} {4660}
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@ -276,8 +276,8 @@ proc do_create_pcie {} {
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set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_ep_native_hwtcl} {Native}
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set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_maxpayload_size_hwtcl} {1024}
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set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_ats_cap_enable_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_msi_enable_hwtcl} {1}
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set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_msix_enable_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_msi_enable_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_msix_enable_hwtcl} {1}
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set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_tph_cap_enable_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_ats_cap_enable_hwtcl} {0}
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set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_msi_enable_hwtcl} {0}
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@ -62,6 +62,7 @@ parameter TX_SEQ_NUM_WIDTH = 6;
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parameter PCIE_TAG_COUNT = 256;
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parameter BAR0_APERTURE = 24;
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parameter BAR2_APERTURE = 24;
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parameter BAR4_APERTURE = 16;
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// Clock and reset
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@ -118,12 +119,6 @@ wire [SEG_COUNT-1:0] tx_data_cdts_consumed;
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wire [SEG_COUNT*2-1:0] tx_cdts_type;
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wire [SEG_COUNT*1-1:0] tx_cdts_data_value;
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wire app_msi_req;
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wire app_msi_ack;
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wire [2:0] app_msi_tc;
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wire [4:0] app_msi_num;
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wire [1:0] app_msi_func_num;
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wire [31:0] tl_cfg_ctl;
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wire [4:0] tl_cfg_add;
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wire [1:0] tl_cfg_func;
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@ -163,12 +158,12 @@ pcie pcie_hip_inst (
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.tx_cplh_cdts (tx_cplh_cdts),
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.tx_ph_cdts (tx_ph_cdts),
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.tx_nph_cdts (tx_nph_cdts),
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.app_msi_req (app_msi_req),
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.app_msi_ack (app_msi_ack),
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.app_msi_tc (app_msi_tc),
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.app_msi_num (app_msi_num),
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.app_msi_req (1'b0),
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.app_msi_ack (),
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.app_msi_tc (3'd0),
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.app_msi_num (5'd0),
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.app_int_sts (4'd0),
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.app_msi_func_num (app_msi_func_num),
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.app_msi_func_num (2'd0),
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.int_status (),
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.int_status_common (),
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.derr_cor_ext_rpl (),
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@ -476,7 +471,8 @@ fpga_core #(
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.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
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.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
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.BAR0_APERTURE(BAR0_APERTURE),
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.BAR2_APERTURE(BAR2_APERTURE)
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.BAR2_APERTURE(BAR2_APERTURE),
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.BAR4_APERTURE(BAR4_APERTURE)
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)
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fpga_core_inst (
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.clk(clk),
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@ -527,15 +523,6 @@ fpga_core_inst (
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.tx_cdts_type(tx_cdts_type),
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.tx_cdts_data_value(tx_cdts_data_value),
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/*
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* H-tile MSI interrupt interface
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*/
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.app_msi_req(app_msi_req),
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.app_msi_ack(app_msi_ack),
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.app_msi_tc(app_msi_tc),
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.app_msi_num(app_msi_num),
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.app_msi_func_num(app_msi_func_num),
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/*
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* H-tile configuration interface
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*/
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@ -39,7 +39,8 @@ module fpga_core #
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parameter TX_SEQ_NUM_WIDTH = 6,
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parameter PCIE_TAG_COUNT = 256,
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parameter BAR0_APERTURE = 24,
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parameter BAR2_APERTURE = 24
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parameter BAR2_APERTURE = 24,
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parameter BAR4_APERTURE = 16
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)
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(
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input wire clk,
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@ -84,12 +85,6 @@ module fpga_core #
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input wire [SEG_COUNT*2-1:0] tx_cdts_type,
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input wire [SEG_COUNT*1-1:0] tx_cdts_data_value,
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output wire app_msi_req,
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input wire app_msi_ack,
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output wire [2:0] app_msi_tc,
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output wire [4:0] app_msi_num,
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output wire [1:0] app_msi_func_num,
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input wire [31:0] tl_cfg_ctl,
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input wire [4:0] tl_cfg_add,
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input wire [1:0] tl_cfg_func
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@ -114,7 +109,8 @@ example_core_pcie_s10 #(
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.WRITE_TX_LIMIT(2**TX_SEQ_NUM_WIDTH),
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.WRITE_TX_FC_ENABLE(1),
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.BAR0_APERTURE(BAR0_APERTURE),
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.BAR2_APERTURE(BAR2_APERTURE)
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.BAR2_APERTURE(BAR2_APERTURE),
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.BAR4_APERTURE(BAR4_APERTURE)
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)
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example_core_pcie_s10_inst (
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.clk(clk),
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@ -158,15 +154,6 @@ example_core_pcie_s10_inst (
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.tx_cdts_type(tx_cdts_type),
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.tx_cdts_data_value(tx_cdts_data_value),
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/*
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* H-tile MSI interrupt interface
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*/
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.app_msi_req(app_msi_req),
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.app_msi_ack(app_msi_ack),
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.app_msi_tc(app_msi_tc),
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.app_msi_num(app_msi_num),
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.app_msi_func_num(app_msi_func_num),
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/*
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* H-tile configuration interface
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*/
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@ -38,7 +38,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if_rx.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if_tx.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_cfg.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_msi.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
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@ -49,11 +48,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
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VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
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@ -65,6 +64,7 @@ export PARAM_TX_SEQ_NUM_WIDTH ?= 6
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export PARAM_PCIE_TAG_COUNT ?= 64
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export PARAM_BAR0_APERTURE ?= 24
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export PARAM_BAR2_APERTURE ?= 24
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export PARAM_BAR4_APERTURE ?= 16
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ifeq ($(SIM), icarus)
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PLUSARGS += -fst
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@ -76,6 +76,7 @@ ifeq ($(SIM), icarus)
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COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
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COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
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COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
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COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
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ifeq ($(WAVES), 1)
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VERILOG_SOURCES += iverilog_dump.v
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@ -91,6 +92,7 @@ else ifeq ($(SIM), verilator)
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COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
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COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
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COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
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COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
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ifeq ($(WAVES), 1)
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COMPILE_ARGS += --trace-fst
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@ -55,20 +55,20 @@ class TB(object):
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max_payload_size=1024,
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enable_extended_tag=True,
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pf0_msi_enable=True,
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pf0_msi_count=32,
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pf0_msi_enable=False,
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pf0_msi_count=1,
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pf1_msi_enable=False,
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pf1_msi_count=1,
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pf2_msi_enable=False,
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pf2_msi_count=1,
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pf3_msi_enable=False,
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pf3_msi_count=1,
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pf0_msix_enable=False,
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pf0_msix_table_size=0,
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pf0_msix_table_bir=0,
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pf0_msix_enable=True,
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pf0_msix_table_size=31,
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pf0_msix_table_bir=4,
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pf0_msix_table_offset=0x00000000,
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pf0_msix_pba_bir=0,
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pf0_msix_pba_offset=0x00000000,
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pf0_msix_pba_bir=4,
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pf0_msix_pba_offset=0x00008000,
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pf1_msix_enable=False,
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pf1_msix_table_size=0,
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pf1_msix_table_bir=0,
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@ -144,11 +144,11 @@ class TB(object):
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# app_xfer_pending=dut.app_xfer_pending,
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# Interrupt interface
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app_msi_req=dut.app_msi_req,
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app_msi_ack=dut.app_msi_ack,
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app_msi_tc=dut.app_msi_tc,
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app_msi_num=dut.app_msi_num,
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app_msi_func_num=dut.app_msi_func_num,
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# app_msi_req=dut.app_msi_req,
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# app_msi_ack=dut.app_msi_ack,
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# app_msi_tc=dut.app_msi_tc,
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# app_msi_num=dut.app_msi_num,
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# app_msi_func_num=dut.app_msi_func_num,
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# app_int_sts=dut.app_int_sts,
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# Error interface
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@ -191,6 +191,7 @@ class TB(object):
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self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_s10_inst.core_pcie_inst.axil_ctrl_awaddr))
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self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_s10_inst.core_pcie_inst.axi_ram_awaddr))
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self.dev.functions[0].configure_bar(4, 2**len(dut.example_core_pcie_s10_inst.core_pcie_inst.axil_msix_awaddr))
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async def init(self):
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@ -428,7 +429,6 @@ def test_fpga_core(request):
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os.path.join(pcie_rtl_dir, "pcie_s10_if_rx.v"),
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os.path.join(pcie_rtl_dir, "pcie_s10_if_tx.v"),
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os.path.join(pcie_rtl_dir, "pcie_s10_cfg.v"),
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os.path.join(pcie_rtl_dir, "pcie_s10_msi.v"),
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os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
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os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
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os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
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@ -439,11 +439,11 @@ def test_fpga_core(request):
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os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
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os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
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os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"),
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os.path.join(pcie_rtl_dir, "pcie_msix.v"),
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os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
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os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
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os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
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os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
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os.path.join(pcie_rtl_dir, "arbiter.v"),
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os.path.join(pcie_rtl_dir, "priority_encoder.v"),
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os.path.join(pcie_rtl_dir, "pulse_merge.v"),
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]
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@ -457,6 +457,7 @@ def test_fpga_core(request):
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parameters['PCIE_TAG_COUNT'] = 64
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parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -20,7 +20,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -30,11 +29,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
|
||||
@ -26,8 +26,19 @@ set_property -dict [list \
|
||||
CONFIG.pf0_bar2_type {Memory} \
|
||||
CONFIG.pf0_bar2_scale {Megabytes} \
|
||||
CONFIG.pf0_bar2_size {16} \
|
||||
CONFIG.pf0_msi_enabled {true} \
|
||||
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||
CONFIG.pf0_bar4_64bit {true} \
|
||||
CONFIG.pf0_bar4_prefetchable {true} \
|
||||
CONFIG.pf0_bar4_enabled {true} \
|
||||
CONFIG.pf0_bar4_type {Memory} \
|
||||
CONFIG.pf0_bar4_scale {Kilobytes} \
|
||||
CONFIG.pf0_bar4_size {64} \
|
||||
CONFIG.pf0_msi_enabled {false} \
|
||||
CONFIG.pf0_msix_enabled {true} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \
|
||||
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
CONFIG.en_msi_per_vec_masking {true} \
|
||||
] [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
@ -68,6 +68,7 @@ parameter RQ_SEQ_NUM_ENABLE = 1;
|
||||
parameter PCIE_TAG_COUNT = 256;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
parameter BAR2_APERTURE = 24;
|
||||
parameter BAR4_APERTURE = 16;
|
||||
|
||||
// PCIe
|
||||
wire pcie_user_clk;
|
||||
@ -160,22 +161,18 @@ wire [7:0] cfg_fc_cplh;
|
||||
wire [11:0] cfg_fc_cpld;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
wire [3:0] cfg_interrupt_msix_enable;
|
||||
wire [3:0] cfg_interrupt_msix_mask;
|
||||
wire [251:0] cfg_interrupt_msix_vf_enable;
|
||||
wire [251:0] cfg_interrupt_msix_vf_mask;
|
||||
wire [63:0] cfg_interrupt_msix_address;
|
||||
wire [31:0] cfg_interrupt_msix_data;
|
||||
wire cfg_interrupt_msix_int;
|
||||
wire [1:0] cfg_interrupt_msix_vec_pending;
|
||||
wire cfg_interrupt_msix_vec_pending_status;
|
||||
wire cfg_interrupt_msix_sent;
|
||||
wire cfg_interrupt_msix_fail;
|
||||
wire [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
@ -308,21 +305,17 @@ pcie4_uscale_plus_inst (
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_pm_aspm_l1_entry_reject(1'b0),
|
||||
@ -360,7 +353,8 @@ fpga_core #(
|
||||
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
@ -431,21 +425,17 @@ core_inst (
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.status_error_cor(status_error_cor),
|
||||
|
||||
@ -47,7 +47,8 @@ module fpga_core #
|
||||
parameter RQ_SEQ_NUM_ENABLE = 1,
|
||||
parameter PCIE_TAG_COUNT = 256,
|
||||
parameter BAR0_APERTURE = 24,
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
/*
|
||||
@ -120,22 +121,18 @@ module fpga_core #
|
||||
input wire [11:0] cfg_fc_cpld,
|
||||
output wire [2:0] cfg_fc_sel,
|
||||
|
||||
input wire [3:0] cfg_interrupt_msi_enable,
|
||||
input wire [11:0] cfg_interrupt_msi_mmenable,
|
||||
input wire cfg_interrupt_msi_mask_update,
|
||||
input wire [31:0] cfg_interrupt_msi_data,
|
||||
output wire [3:0] cfg_interrupt_msi_select,
|
||||
output wire [31:0] cfg_interrupt_msi_int,
|
||||
output wire [31:0] cfg_interrupt_msi_pending_status,
|
||||
output wire cfg_interrupt_msi_pending_status_data_enable,
|
||||
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
|
||||
input wire cfg_interrupt_msi_sent,
|
||||
input wire cfg_interrupt_msi_fail,
|
||||
output wire [2:0] cfg_interrupt_msi_attr,
|
||||
output wire cfg_interrupt_msi_tph_present,
|
||||
output wire [1:0] cfg_interrupt_msi_tph_type,
|
||||
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
|
||||
output wire [3:0] cfg_interrupt_msi_function_number,
|
||||
input wire [3:0] cfg_interrupt_msix_enable,
|
||||
input wire [3:0] cfg_interrupt_msix_mask,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_enable,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_mask,
|
||||
output wire [63:0] cfg_interrupt_msix_address,
|
||||
output wire [31:0] cfg_interrupt_msix_data,
|
||||
output wire cfg_interrupt_msix_int,
|
||||
output wire [1:0] cfg_interrupt_msix_vec_pending,
|
||||
input wire cfg_interrupt_msix_vec_pending_status,
|
||||
input wire cfg_interrupt_msix_sent,
|
||||
input wire cfg_interrupt_msix_fail,
|
||||
output wire [7:0] cfg_interrupt_msi_function_number,
|
||||
|
||||
output wire status_error_cor,
|
||||
output wire status_error_uncor
|
||||
@ -166,7 +163,8 @@ example_core_pcie_us #(
|
||||
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
|
||||
.WRITE_TX_FC_ENABLE(1),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
example_core_pcie_us_inst (
|
||||
.clk(clk),
|
||||
@ -246,22 +244,17 @@ example_core_pcie_us_inst (
|
||||
/*
|
||||
* Interrupt interface
|
||||
*/
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(8'd0),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
|
||||
@ -40,7 +40,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -50,11 +49,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
@ -74,6 +73,7 @@ export PARAM_RQ_SEQ_NUM_ENABLE ?= 1
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -93,6 +93,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -116,6 +117,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -66,20 +66,20 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -223,33 +223,33 @@ class TB(object):
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||
# cfg_interrupt_msix_enable
|
||||
# cfg_interrupt_msix_mask
|
||||
# cfg_interrupt_msix_vf_enable
|
||||
# cfg_interrupt_msix_vf_mask
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
|
||||
cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
@ -268,6 +268,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
async def init(self):
|
||||
|
||||
@ -507,7 +508,6 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -517,11 +517,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -543,6 +543,7 @@ def test_fpga_core(request):
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -20,7 +20,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -30,11 +29,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
|
||||
@ -26,8 +26,19 @@ set_property -dict [list \
|
||||
CONFIG.pf0_bar2_type {Memory} \
|
||||
CONFIG.pf0_bar2_scale {Megabytes} \
|
||||
CONFIG.pf0_bar2_size {16} \
|
||||
CONFIG.pf0_msi_enabled {true} \
|
||||
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||
CONFIG.pf0_bar4_64bit {true} \
|
||||
CONFIG.pf0_bar4_prefetchable {true} \
|
||||
CONFIG.pf0_bar4_enabled {true} \
|
||||
CONFIG.pf0_bar4_type {Memory} \
|
||||
CONFIG.pf0_bar4_scale {Kilobytes} \
|
||||
CONFIG.pf0_bar4_size {64} \
|
||||
CONFIG.pf0_msi_enabled {false} \
|
||||
CONFIG.pf0_msix_enabled {true} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \
|
||||
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
CONFIG.en_msi_per_vec_masking {true} \
|
||||
] [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
@ -67,6 +67,7 @@ parameter RQ_SEQ_NUM_ENABLE = 1;
|
||||
parameter PCIE_TAG_COUNT = 256;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
parameter BAR2_APERTURE = 24;
|
||||
parameter BAR4_APERTURE = 16;
|
||||
|
||||
// Clock and reset
|
||||
wire pcie_user_clk;
|
||||
@ -175,22 +176,18 @@ wire [7:0] cfg_fc_cplh;
|
||||
wire [11:0] cfg_fc_cpld;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
wire [3:0] cfg_interrupt_msix_enable;
|
||||
wire [3:0] cfg_interrupt_msix_mask;
|
||||
wire [251:0] cfg_interrupt_msix_vf_enable;
|
||||
wire [251:0] cfg_interrupt_msix_vf_mask;
|
||||
wire [63:0] cfg_interrupt_msix_address;
|
||||
wire [31:0] cfg_interrupt_msix_data;
|
||||
wire cfg_interrupt_msix_int;
|
||||
wire [1:0] cfg_interrupt_msix_vec_pending;
|
||||
wire cfg_interrupt_msix_vec_pending_status;
|
||||
wire cfg_interrupt_msix_sent;
|
||||
wire cfg_interrupt_msix_fail;
|
||||
wire [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
@ -323,21 +320,17 @@ pcie4_uscale_plus_inst (
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_pm_aspm_l1_entry_reject(1'b0),
|
||||
@ -375,7 +368,8 @@ fpga_core #(
|
||||
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
@ -445,21 +439,17 @@ core_inst (
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.status_error_cor(status_error_cor),
|
||||
|
||||
@ -47,7 +47,8 @@ module fpga_core #
|
||||
parameter RQ_SEQ_NUM_ENABLE = 1,
|
||||
parameter PCIE_TAG_COUNT = 256,
|
||||
parameter BAR0_APERTURE = 24,
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
/*
|
||||
@ -119,22 +120,18 @@ module fpga_core #
|
||||
input wire [11:0] cfg_fc_cpld,
|
||||
output wire [2:0] cfg_fc_sel,
|
||||
|
||||
input wire [3:0] cfg_interrupt_msi_enable,
|
||||
input wire [11:0] cfg_interrupt_msi_mmenable,
|
||||
input wire cfg_interrupt_msi_mask_update,
|
||||
input wire [31:0] cfg_interrupt_msi_data,
|
||||
output wire [3:0] cfg_interrupt_msi_select,
|
||||
output wire [31:0] cfg_interrupt_msi_int,
|
||||
output wire [31:0] cfg_interrupt_msi_pending_status,
|
||||
output wire cfg_interrupt_msi_pending_status_data_enable,
|
||||
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
|
||||
input wire cfg_interrupt_msi_sent,
|
||||
input wire cfg_interrupt_msi_fail,
|
||||
output wire [2:0] cfg_interrupt_msi_attr,
|
||||
output wire cfg_interrupt_msi_tph_present,
|
||||
output wire [1:0] cfg_interrupt_msi_tph_type,
|
||||
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
|
||||
output wire [3:0] cfg_interrupt_msi_function_number,
|
||||
input wire [3:0] cfg_interrupt_msix_enable,
|
||||
input wire [3:0] cfg_interrupt_msix_mask,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_enable,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_mask,
|
||||
output wire [63:0] cfg_interrupt_msix_address,
|
||||
output wire [31:0] cfg_interrupt_msix_data,
|
||||
output wire cfg_interrupt_msix_int,
|
||||
output wire [1:0] cfg_interrupt_msix_vec_pending,
|
||||
input wire cfg_interrupt_msix_vec_pending_status,
|
||||
input wire cfg_interrupt_msix_sent,
|
||||
input wire cfg_interrupt_msix_fail,
|
||||
output wire [7:0] cfg_interrupt_msi_function_number,
|
||||
|
||||
output wire status_error_cor,
|
||||
output wire status_error_uncor
|
||||
@ -163,7 +160,8 @@ example_core_pcie_us #(
|
||||
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
|
||||
.WRITE_TX_FC_ENABLE(1),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
example_core_pcie_us_inst (
|
||||
.clk(clk),
|
||||
@ -243,22 +241,17 @@ example_core_pcie_us_inst (
|
||||
/*
|
||||
* Interrupt interface
|
||||
*/
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(8'd0),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
|
||||
@ -40,7 +40,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -50,11 +49,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
@ -74,6 +73,7 @@ export PARAM_RQ_SEQ_NUM_ENABLE ?= 1
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -93,6 +93,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -116,6 +117,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -66,20 +66,20 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -223,33 +223,33 @@ class TB(object):
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||
# cfg_interrupt_msix_enable
|
||||
# cfg_interrupt_msix_mask
|
||||
# cfg_interrupt_msix_vf_enable
|
||||
# cfg_interrupt_msix_vf_mask
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
|
||||
cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
@ -268,6 +268,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
dut.sw.setimmediatevalue(0)
|
||||
|
||||
@ -509,7 +510,6 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -519,11 +519,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -545,6 +545,7 @@ def test_fpga_core(request):
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -20,7 +20,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -30,11 +29,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
|
||||
@ -26,8 +26,19 @@ set_property -dict [list \
|
||||
CONFIG.pf0_bar2_type {Memory} \
|
||||
CONFIG.pf0_bar2_scale {Megabytes} \
|
||||
CONFIG.pf0_bar2_size {16} \
|
||||
CONFIG.pf0_msi_enabled {true} \
|
||||
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||
CONFIG.pf0_bar4_64bit {true} \
|
||||
CONFIG.pf0_bar4_prefetchable {true} \
|
||||
CONFIG.pf0_bar4_enabled {true} \
|
||||
CONFIG.pf0_bar4_type {Memory} \
|
||||
CONFIG.pf0_bar4_scale {Kilobytes} \
|
||||
CONFIG.pf0_bar4_size {64} \
|
||||
CONFIG.pf0_msi_enabled {false} \
|
||||
CONFIG.pf0_msix_enabled {true} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \
|
||||
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
CONFIG.en_msi_per_vec_masking {true} \
|
||||
] [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
@ -67,6 +67,7 @@ parameter RQ_SEQ_NUM_ENABLE = 1;
|
||||
parameter PCIE_TAG_COUNT = 256;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
parameter BAR2_APERTURE = 24;
|
||||
parameter BAR4_APERTURE = 16;
|
||||
|
||||
// Clock and reset
|
||||
wire pcie_user_clk;
|
||||
@ -175,22 +176,18 @@ wire [7:0] cfg_fc_cplh;
|
||||
wire [11:0] cfg_fc_cpld;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
wire [3:0] cfg_interrupt_msix_enable;
|
||||
wire [3:0] cfg_interrupt_msix_mask;
|
||||
wire [251:0] cfg_interrupt_msix_vf_enable;
|
||||
wire [251:0] cfg_interrupt_msix_vf_mask;
|
||||
wire [63:0] cfg_interrupt_msix_address;
|
||||
wire [31:0] cfg_interrupt_msix_data;
|
||||
wire cfg_interrupt_msix_int;
|
||||
wire [1:0] cfg_interrupt_msix_vec_pending;
|
||||
wire cfg_interrupt_msix_vec_pending_status;
|
||||
wire cfg_interrupt_msix_sent;
|
||||
wire cfg_interrupt_msix_fail;
|
||||
wire [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
@ -323,21 +320,17 @@ pcie4_uscale_plus_inst (
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_pm_aspm_l1_entry_reject(1'b0),
|
||||
@ -375,7 +368,8 @@ fpga_core #(
|
||||
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
@ -445,21 +439,17 @@ core_inst (
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.status_error_cor(status_error_cor),
|
||||
|
||||
@ -47,7 +47,8 @@ module fpga_core #
|
||||
parameter RQ_SEQ_NUM_ENABLE = 1,
|
||||
parameter PCIE_TAG_COUNT = 256,
|
||||
parameter BAR0_APERTURE = 24,
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
/*
|
||||
@ -119,22 +120,18 @@ module fpga_core #
|
||||
input wire [11:0] cfg_fc_cpld,
|
||||
output wire [2:0] cfg_fc_sel,
|
||||
|
||||
input wire [3:0] cfg_interrupt_msi_enable,
|
||||
input wire [11:0] cfg_interrupt_msi_mmenable,
|
||||
input wire cfg_interrupt_msi_mask_update,
|
||||
input wire [31:0] cfg_interrupt_msi_data,
|
||||
output wire [3:0] cfg_interrupt_msi_select,
|
||||
output wire [31:0] cfg_interrupt_msi_int,
|
||||
output wire [31:0] cfg_interrupt_msi_pending_status,
|
||||
output wire cfg_interrupt_msi_pending_status_data_enable,
|
||||
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
|
||||
input wire cfg_interrupt_msi_sent,
|
||||
input wire cfg_interrupt_msi_fail,
|
||||
output wire [2:0] cfg_interrupt_msi_attr,
|
||||
output wire cfg_interrupt_msi_tph_present,
|
||||
output wire [1:0] cfg_interrupt_msi_tph_type,
|
||||
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
|
||||
output wire [3:0] cfg_interrupt_msi_function_number,
|
||||
input wire [3:0] cfg_interrupt_msix_enable,
|
||||
input wire [3:0] cfg_interrupt_msix_mask,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_enable,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_mask,
|
||||
output wire [63:0] cfg_interrupt_msix_address,
|
||||
output wire [31:0] cfg_interrupt_msix_data,
|
||||
output wire cfg_interrupt_msix_int,
|
||||
output wire [1:0] cfg_interrupt_msix_vec_pending,
|
||||
input wire cfg_interrupt_msix_vec_pending_status,
|
||||
input wire cfg_interrupt_msix_sent,
|
||||
input wire cfg_interrupt_msix_fail,
|
||||
output wire [7:0] cfg_interrupt_msi_function_number,
|
||||
|
||||
output wire status_error_cor,
|
||||
output wire status_error_uncor
|
||||
@ -163,7 +160,8 @@ example_core_pcie_us #(
|
||||
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
|
||||
.WRITE_TX_FC_ENABLE(1),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
example_core_pcie_us_inst (
|
||||
.clk(clk),
|
||||
@ -243,22 +241,17 @@ example_core_pcie_us_inst (
|
||||
/*
|
||||
* Interrupt interface
|
||||
*/
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(8'd0),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
|
||||
@ -40,7 +40,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -50,11 +49,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
@ -74,6 +73,7 @@ export PARAM_RQ_SEQ_NUM_ENABLE ?= 1
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -93,6 +93,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -116,6 +117,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -66,20 +66,20 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -223,33 +223,33 @@ class TB(object):
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||
# cfg_interrupt_msix_enable
|
||||
# cfg_interrupt_msix_mask
|
||||
# cfg_interrupt_msix_vf_enable
|
||||
# cfg_interrupt_msix_vf_mask
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
|
||||
cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
@ -268,6 +268,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
dut.sw.setimmediatevalue(0)
|
||||
|
||||
@ -509,7 +510,6 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -519,11 +519,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -545,6 +545,7 @@ def test_fpga_core(request):
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -19,7 +19,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -29,11 +28,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
|
||||
@ -26,8 +26,19 @@ set_property -dict [list \
|
||||
CONFIG.pf0_bar2_type {Memory} \
|
||||
CONFIG.pf0_bar2_scale {Megabytes} \
|
||||
CONFIG.pf0_bar2_size {16} \
|
||||
CONFIG.pf0_msi_enabled {true} \
|
||||
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||
CONFIG.pf0_bar4_64bit {true} \
|
||||
CONFIG.pf0_bar4_prefetchable {true} \
|
||||
CONFIG.pf0_bar4_enabled {true} \
|
||||
CONFIG.pf0_bar4_type {Memory} \
|
||||
CONFIG.pf0_bar4_scale {Kilobytes} \
|
||||
CONFIG.pf0_bar4_size {64} \
|
||||
CONFIG.pf0_msi_enabled {false} \
|
||||
CONFIG.pf0_msix_enabled {true} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \
|
||||
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
CONFIG.en_msi_per_vec_masking {true} \
|
||||
] [get_ips pcie4c_uscale_plus_0]
|
||||
|
||||
@ -66,6 +66,7 @@ parameter RQ_SEQ_NUM_ENABLE = 1;
|
||||
parameter PCIE_TAG_COUNT = 256;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
parameter BAR2_APERTURE = 24;
|
||||
parameter BAR4_APERTURE = 16;
|
||||
|
||||
// Clock and reset
|
||||
wire pcie_user_clk;
|
||||
@ -162,22 +163,18 @@ wire [7:0] cfg_fc_cplh;
|
||||
wire [11:0] cfg_fc_cpld;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
wire [3:0] cfg_interrupt_msix_enable;
|
||||
wire [3:0] cfg_interrupt_msix_mask;
|
||||
wire [251:0] cfg_interrupt_msix_vf_enable;
|
||||
wire [251:0] cfg_interrupt_msix_vf_mask;
|
||||
wire [63:0] cfg_interrupt_msix_address;
|
||||
wire [31:0] cfg_interrupt_msix_data;
|
||||
wire cfg_interrupt_msix_int;
|
||||
wire [1:0] cfg_interrupt_msix_vec_pending;
|
||||
wire cfg_interrupt_msix_vec_pending_status;
|
||||
wire cfg_interrupt_msix_sent;
|
||||
wire cfg_interrupt_msix_fail;
|
||||
wire [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
@ -310,21 +307,17 @@ pcie4c_uscale_plus_inst (
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_pm_aspm_l1_entry_reject(1'b0),
|
||||
@ -362,7 +355,8 @@ fpga_core #(
|
||||
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
@ -427,21 +421,17 @@ core_inst (
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.status_error_cor(status_error_cor),
|
||||
|
||||
@ -47,7 +47,8 @@ module fpga_core #
|
||||
parameter RQ_SEQ_NUM_ENABLE = 1,
|
||||
parameter PCIE_TAG_COUNT = 256,
|
||||
parameter BAR0_APERTURE = 24,
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
/*
|
||||
@ -113,22 +114,18 @@ module fpga_core #
|
||||
input wire [11:0] cfg_fc_cpld,
|
||||
output wire [2:0] cfg_fc_sel,
|
||||
|
||||
input wire [3:0] cfg_interrupt_msi_enable,
|
||||
input wire [11:0] cfg_interrupt_msi_mmenable,
|
||||
input wire cfg_interrupt_msi_mask_update,
|
||||
input wire [31:0] cfg_interrupt_msi_data,
|
||||
output wire [3:0] cfg_interrupt_msi_select,
|
||||
output wire [31:0] cfg_interrupt_msi_int,
|
||||
output wire [31:0] cfg_interrupt_msi_pending_status,
|
||||
output wire cfg_interrupt_msi_pending_status_data_enable,
|
||||
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
|
||||
input wire cfg_interrupt_msi_sent,
|
||||
input wire cfg_interrupt_msi_fail,
|
||||
output wire [2:0] cfg_interrupt_msi_attr,
|
||||
output wire cfg_interrupt_msi_tph_present,
|
||||
output wire [1:0] cfg_interrupt_msi_tph_type,
|
||||
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
|
||||
output wire [3:0] cfg_interrupt_msi_function_number,
|
||||
input wire [3:0] cfg_interrupt_msix_enable,
|
||||
input wire [3:0] cfg_interrupt_msix_mask,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_enable,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_mask,
|
||||
output wire [63:0] cfg_interrupt_msix_address,
|
||||
output wire [31:0] cfg_interrupt_msix_data,
|
||||
output wire cfg_interrupt_msix_int,
|
||||
output wire [1:0] cfg_interrupt_msix_vec_pending,
|
||||
input wire cfg_interrupt_msix_vec_pending_status,
|
||||
input wire cfg_interrupt_msix_sent,
|
||||
input wire cfg_interrupt_msix_fail,
|
||||
output wire [7:0] cfg_interrupt_msi_function_number,
|
||||
|
||||
output wire status_error_cor,
|
||||
output wire status_error_uncor
|
||||
@ -155,7 +152,8 @@ example_core_pcie_us #(
|
||||
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
|
||||
.WRITE_TX_FC_ENABLE(1),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
example_core_pcie_us_inst (
|
||||
.clk(clk),
|
||||
@ -235,22 +233,17 @@ example_core_pcie_us_inst (
|
||||
/*
|
||||
* Interrupt interface
|
||||
*/
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(8'd0),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
|
||||
@ -40,7 +40,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -50,11 +49,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
@ -74,6 +73,7 @@ export PARAM_RQ_SEQ_NUM_ENABLE ?= 1
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -93,6 +93,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -116,6 +117,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -66,20 +66,20 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -223,33 +223,33 @@ class TB(object):
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||
# cfg_interrupt_msix_enable
|
||||
# cfg_interrupt_msix_mask
|
||||
# cfg_interrupt_msix_vf_enable
|
||||
# cfg_interrupt_msix_vf_mask
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
|
||||
cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
@ -268,6 +268,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
async def init(self):
|
||||
|
||||
@ -507,7 +508,6 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -517,11 +517,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -543,6 +543,7 @@ def test_fpga_core(request):
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -19,7 +19,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -29,11 +28,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
|
||||
@ -26,8 +26,19 @@ set_property -dict [list \
|
||||
CONFIG.pf0_bar2_type {Memory} \
|
||||
CONFIG.pf0_bar2_scale {Megabytes} \
|
||||
CONFIG.pf0_bar2_size {16} \
|
||||
CONFIG.pf0_msi_enabled {true} \
|
||||
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||
CONFIG.pf0_bar4_64bit {true} \
|
||||
CONFIG.pf0_bar4_prefetchable {true} \
|
||||
CONFIG.pf0_bar4_enabled {true} \
|
||||
CONFIG.pf0_bar4_type {Memory} \
|
||||
CONFIG.pf0_bar4_scale {Kilobytes} \
|
||||
CONFIG.pf0_bar4_size {64} \
|
||||
CONFIG.pf0_msi_enabled {false} \
|
||||
CONFIG.pf0_msix_enabled {true} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \
|
||||
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
CONFIG.en_msi_per_vec_masking {true} \
|
||||
] [get_ips pcie4c_uscale_plus_0]
|
||||
|
||||
@ -69,6 +69,7 @@ parameter RQ_SEQ_NUM_ENABLE = 1;
|
||||
parameter PCIE_TAG_COUNT = 256;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
parameter BAR2_APERTURE = 24;
|
||||
parameter BAR4_APERTURE = 16;
|
||||
|
||||
// Clock and reset
|
||||
wire pcie_user_clk;
|
||||
@ -165,22 +166,18 @@ wire [7:0] cfg_fc_cplh;
|
||||
wire [11:0] cfg_fc_cpld;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
wire [3:0] cfg_interrupt_msix_enable;
|
||||
wire [3:0] cfg_interrupt_msix_mask;
|
||||
wire [251:0] cfg_interrupt_msix_vf_enable;
|
||||
wire [251:0] cfg_interrupt_msix_vf_mask;
|
||||
wire [63:0] cfg_interrupt_msix_address;
|
||||
wire [31:0] cfg_interrupt_msix_data;
|
||||
wire cfg_interrupt_msix_int;
|
||||
wire [1:0] cfg_interrupt_msix_vec_pending;
|
||||
wire cfg_interrupt_msix_vec_pending_status;
|
||||
wire cfg_interrupt_msix_sent;
|
||||
wire cfg_interrupt_msix_fail;
|
||||
wire [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
@ -313,21 +310,17 @@ pcie4c_uscale_plus_inst (
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_pm_aspm_l1_entry_reject(1'b0),
|
||||
@ -365,7 +358,8 @@ fpga_core #(
|
||||
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
@ -436,21 +430,17 @@ core_inst (
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.status_error_cor(status_error_cor),
|
||||
|
||||
@ -47,7 +47,8 @@ module fpga_core #
|
||||
parameter RQ_SEQ_NUM_ENABLE = 1,
|
||||
parameter PCIE_TAG_COUNT = 256,
|
||||
parameter BAR0_APERTURE = 24,
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
/*
|
||||
@ -120,22 +121,18 @@ module fpga_core #
|
||||
input wire [11:0] cfg_fc_cpld,
|
||||
output wire [2:0] cfg_fc_sel,
|
||||
|
||||
input wire [3:0] cfg_interrupt_msi_enable,
|
||||
input wire [11:0] cfg_interrupt_msi_mmenable,
|
||||
input wire cfg_interrupt_msi_mask_update,
|
||||
input wire [31:0] cfg_interrupt_msi_data,
|
||||
output wire [3:0] cfg_interrupt_msi_select,
|
||||
output wire [31:0] cfg_interrupt_msi_int,
|
||||
output wire [31:0] cfg_interrupt_msi_pending_status,
|
||||
output wire cfg_interrupt_msi_pending_status_data_enable,
|
||||
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
|
||||
input wire cfg_interrupt_msi_sent,
|
||||
input wire cfg_interrupt_msi_fail,
|
||||
output wire [2:0] cfg_interrupt_msi_attr,
|
||||
output wire cfg_interrupt_msi_tph_present,
|
||||
output wire [1:0] cfg_interrupt_msi_tph_type,
|
||||
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
|
||||
output wire [3:0] cfg_interrupt_msi_function_number,
|
||||
input wire [3:0] cfg_interrupt_msix_enable,
|
||||
input wire [3:0] cfg_interrupt_msix_mask,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_enable,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_mask,
|
||||
output wire [63:0] cfg_interrupt_msix_address,
|
||||
output wire [31:0] cfg_interrupt_msix_data,
|
||||
output wire cfg_interrupt_msix_int,
|
||||
output wire [1:0] cfg_interrupt_msix_vec_pending,
|
||||
input wire cfg_interrupt_msix_vec_pending_status,
|
||||
input wire cfg_interrupt_msix_sent,
|
||||
input wire cfg_interrupt_msix_fail,
|
||||
output wire [7:0] cfg_interrupt_msi_function_number,
|
||||
|
||||
output wire status_error_cor,
|
||||
output wire status_error_uncor
|
||||
@ -166,7 +163,8 @@ example_core_pcie_us #(
|
||||
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
|
||||
.WRITE_TX_FC_ENABLE(1),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
example_core_pcie_us_inst (
|
||||
.clk(clk),
|
||||
@ -246,22 +244,17 @@ example_core_pcie_us_inst (
|
||||
/*
|
||||
* Interrupt interface
|
||||
*/
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(8'd0),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
|
||||
@ -40,7 +40,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -50,11 +49,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
@ -74,6 +73,7 @@ export PARAM_RQ_SEQ_NUM_ENABLE ?= 1
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -93,6 +93,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -116,6 +117,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -66,20 +66,20 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -223,33 +223,33 @@ class TB(object):
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||
# cfg_interrupt_msix_enable
|
||||
# cfg_interrupt_msix_mask
|
||||
# cfg_interrupt_msix_vf_enable
|
||||
# cfg_interrupt_msix_vf_mask
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
|
||||
cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
@ -268,6 +268,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
async def init(self):
|
||||
|
||||
@ -507,7 +508,6 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -517,11 +517,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -543,6 +543,7 @@ def test_fpga_core(request):
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -19,7 +19,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -29,11 +28,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
|
||||
@ -24,8 +24,18 @@ set_property -dict [list \
|
||||
CONFIG.pf0_bar2_type {Memory} \
|
||||
CONFIG.pf0_bar2_scale {Megabytes} \
|
||||
CONFIG.pf0_bar2_size {16} \
|
||||
CONFIG.pf0_msi_enabled {true} \
|
||||
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||
CONFIG.pf0_bar4_64bit {true} \
|
||||
CONFIG.pf0_bar4_prefetchable {true} \
|
||||
CONFIG.pf0_bar4_enabled {true} \
|
||||
CONFIG.pf0_bar4_type {Memory} \
|
||||
CONFIG.pf0_bar4_scale {Kilobytes} \
|
||||
CONFIG.pf0_bar4_size {64} \
|
||||
CONFIG.pf0_msi_enabled {false} \
|
||||
CONFIG.pf0_msix_enabled {true} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
CONFIG.en_msi_per_vec_masking {true} \
|
||||
] [get_ips pcie3_ultrascale_0]
|
||||
|
||||
@ -68,6 +68,7 @@ parameter RQ_SEQ_NUM_ENABLE = 1;
|
||||
parameter PCIE_TAG_COUNT = 64;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
parameter BAR2_APERTURE = 24;
|
||||
parameter BAR4_APERTURE = 16;
|
||||
|
||||
// PCIe
|
||||
wire pcie_user_clk;
|
||||
@ -157,22 +158,15 @@ wire [7:0] cfg_fc_cplh;
|
||||
wire [11:0] cfg_fc_cpld;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [7:0] cfg_interrupt_msi_vf_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [1:0] cfg_interrupt_msix_enable;
|
||||
wire [1:0] cfg_interrupt_msix_mask;
|
||||
wire [7:0] cfg_interrupt_msix_vf_enable;
|
||||
wire [7:0] cfg_interrupt_msix_vf_mask;
|
||||
wire [63:0] cfg_interrupt_msix_address;
|
||||
wire [31:0] cfg_interrupt_msix_data;
|
||||
wire cfg_interrupt_msix_int;
|
||||
wire cfg_interrupt_msix_sent;
|
||||
wire cfg_interrupt_msix_fail;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire status_error_cor;
|
||||
@ -303,22 +297,15 @@ pcie3_ultrascale_inst (
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_hot_reset_out(),
|
||||
@ -362,7 +349,8 @@ fpga_core #(
|
||||
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
@ -430,22 +418,15 @@ core_inst (
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.status_error_cor(status_error_cor),
|
||||
|
||||
@ -47,7 +47,8 @@ module fpga_core #
|
||||
parameter RQ_SEQ_NUM_ENABLE = 1,
|
||||
parameter PCIE_TAG_COUNT = 64,
|
||||
parameter BAR0_APERTURE = 24,
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
/*
|
||||
@ -117,22 +118,15 @@ module fpga_core #
|
||||
input wire [11:0] cfg_fc_cpld,
|
||||
output wire [2:0] cfg_fc_sel,
|
||||
|
||||
input wire [3:0] cfg_interrupt_msi_enable,
|
||||
input wire [7:0] cfg_interrupt_msi_vf_enable,
|
||||
input wire [11:0] cfg_interrupt_msi_mmenable,
|
||||
input wire cfg_interrupt_msi_mask_update,
|
||||
input wire [31:0] cfg_interrupt_msi_data,
|
||||
output wire [3:0] cfg_interrupt_msi_select,
|
||||
output wire [31:0] cfg_interrupt_msi_int,
|
||||
output wire [31:0] cfg_interrupt_msi_pending_status,
|
||||
output wire cfg_interrupt_msi_pending_status_data_enable,
|
||||
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
|
||||
input wire cfg_interrupt_msi_sent,
|
||||
input wire cfg_interrupt_msi_fail,
|
||||
output wire [2:0] cfg_interrupt_msi_attr,
|
||||
output wire cfg_interrupt_msi_tph_present,
|
||||
output wire [1:0] cfg_interrupt_msi_tph_type,
|
||||
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
|
||||
input wire [1:0] cfg_interrupt_msix_enable,
|
||||
input wire [1:0] cfg_interrupt_msix_mask,
|
||||
input wire [7:0] cfg_interrupt_msix_vf_enable,
|
||||
input wire [7:0] cfg_interrupt_msix_vf_mask,
|
||||
output wire [63:0] cfg_interrupt_msix_address,
|
||||
output wire [31:0] cfg_interrupt_msix_data,
|
||||
output wire cfg_interrupt_msix_int,
|
||||
input wire cfg_interrupt_msix_sent,
|
||||
input wire cfg_interrupt_msix_fail,
|
||||
output wire [3:0] cfg_interrupt_msi_function_number,
|
||||
|
||||
output wire status_error_cor,
|
||||
@ -164,7 +158,8 @@ example_core_pcie_us #(
|
||||
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
|
||||
.WRITE_TX_FC_ENABLE(1),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
example_core_pcie_us_inst (
|
||||
.clk(clk),
|
||||
@ -244,22 +239,17 @@ example_core_pcie_us_inst (
|
||||
/*
|
||||
* Interrupt interface
|
||||
*/
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(),
|
||||
.cfg_interrupt_msix_vec_pending_status(1'b0),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
|
||||
@ -40,7 +40,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -50,11 +49,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
@ -74,6 +73,7 @@ export PARAM_RQ_SEQ_NUM_ENABLE ?= 1
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -93,6 +93,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -116,6 +117,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -62,16 +62,16 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -198,32 +198,32 @@ class TB(object):
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_vf_enable=dut.cfg_interrupt_msi_vf_enable,
|
||||
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||
cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||
cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||
# cfg_interrupt_msix_enable
|
||||
# cfg_interrupt_msix_mask
|
||||
# cfg_interrupt_msix_vf_enable
|
||||
# cfg_interrupt_msix_vf_mask
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_vf_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
@ -242,6 +242,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
async def init(self):
|
||||
|
||||
@ -481,7 +482,6 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -491,11 +491,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -517,6 +517,7 @@ def test_fpga_core(request):
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -20,7 +20,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -30,11 +29,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
|
||||
@ -24,10 +24,21 @@ set_property -dict [list \
|
||||
CONFIG.pf0_bar2_type {Memory} \
|
||||
CONFIG.pf0_bar2_scale {Megabytes} \
|
||||
CONFIG.pf0_bar2_size {16} \
|
||||
CONFIG.pf0_msi_enabled {true} \
|
||||
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||
CONFIG.pf0_bar4_64bit {true} \
|
||||
CONFIG.pf0_bar4_prefetchable {true} \
|
||||
CONFIG.pf0_bar4_enabled {true} \
|
||||
CONFIG.pf0_bar4_type {Memory} \
|
||||
CONFIG.pf0_bar4_scale {Kilobytes} \
|
||||
CONFIG.pf0_bar4_size {64} \
|
||||
CONFIG.pf0_msi_enabled {false} \
|
||||
CONFIG.pf0_msix_enabled {true} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \
|
||||
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
CONFIG.en_msi_per_vec_masking {true} \
|
||||
CONFIG.mode_selection {Advanced} \
|
||||
CONFIG.en_gt_selection {true} \
|
||||
CONFIG.MASTER_GT {GTYE4_CHANNEL_X0Y7} \
|
||||
|
||||
@ -68,6 +68,7 @@ parameter RQ_SEQ_NUM_ENABLE = 1;
|
||||
parameter PCIE_TAG_COUNT = 256;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
parameter BAR2_APERTURE = 24;
|
||||
parameter BAR4_APERTURE = 16;
|
||||
|
||||
// PCIe
|
||||
wire pcie_user_clk;
|
||||
@ -160,22 +161,18 @@ wire [7:0] cfg_fc_cplh;
|
||||
wire [11:0] cfg_fc_cpld;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
wire [3:0] cfg_interrupt_msix_enable;
|
||||
wire [3:0] cfg_interrupt_msix_mask;
|
||||
wire [251:0] cfg_interrupt_msix_vf_enable;
|
||||
wire [251:0] cfg_interrupt_msix_vf_mask;
|
||||
wire [63:0] cfg_interrupt_msix_address;
|
||||
wire [31:0] cfg_interrupt_msix_data;
|
||||
wire cfg_interrupt_msix_int;
|
||||
wire [1:0] cfg_interrupt_msix_vec_pending;
|
||||
wire cfg_interrupt_msix_vec_pending_status;
|
||||
wire cfg_interrupt_msix_sent;
|
||||
wire cfg_interrupt_msix_fail;
|
||||
wire [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
@ -308,21 +305,17 @@ pcie4_uscale_plus_inst (
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_pm_aspm_l1_entry_reject(1'b0),
|
||||
@ -360,7 +353,8 @@ fpga_core #(
|
||||
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
@ -431,21 +425,17 @@ core_inst (
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.status_error_cor(status_error_cor),
|
||||
|
||||
@ -47,7 +47,8 @@ module fpga_core #
|
||||
parameter RQ_SEQ_NUM_ENABLE = 1,
|
||||
parameter PCIE_TAG_COUNT = 256,
|
||||
parameter BAR0_APERTURE = 24,
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
/*
|
||||
@ -120,22 +121,18 @@ module fpga_core #
|
||||
input wire [11:0] cfg_fc_cpld,
|
||||
output wire [2:0] cfg_fc_sel,
|
||||
|
||||
input wire [3:0] cfg_interrupt_msi_enable,
|
||||
input wire [11:0] cfg_interrupt_msi_mmenable,
|
||||
input wire cfg_interrupt_msi_mask_update,
|
||||
input wire [31:0] cfg_interrupt_msi_data,
|
||||
output wire [3:0] cfg_interrupt_msi_select,
|
||||
output wire [31:0] cfg_interrupt_msi_int,
|
||||
output wire [31:0] cfg_interrupt_msi_pending_status,
|
||||
output wire cfg_interrupt_msi_pending_status_data_enable,
|
||||
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
|
||||
input wire cfg_interrupt_msi_sent,
|
||||
input wire cfg_interrupt_msi_fail,
|
||||
output wire [2:0] cfg_interrupt_msi_attr,
|
||||
output wire cfg_interrupt_msi_tph_present,
|
||||
output wire [1:0] cfg_interrupt_msi_tph_type,
|
||||
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
|
||||
output wire [3:0] cfg_interrupt_msi_function_number,
|
||||
input wire [3:0] cfg_interrupt_msix_enable,
|
||||
input wire [3:0] cfg_interrupt_msix_mask,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_enable,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_mask,
|
||||
output wire [63:0] cfg_interrupt_msix_address,
|
||||
output wire [31:0] cfg_interrupt_msix_data,
|
||||
output wire cfg_interrupt_msix_int,
|
||||
output wire [1:0] cfg_interrupt_msix_vec_pending,
|
||||
input wire cfg_interrupt_msix_vec_pending_status,
|
||||
input wire cfg_interrupt_msix_sent,
|
||||
input wire cfg_interrupt_msix_fail,
|
||||
output wire [7:0] cfg_interrupt_msi_function_number,
|
||||
|
||||
output wire status_error_cor,
|
||||
output wire status_error_uncor
|
||||
@ -166,7 +163,8 @@ example_core_pcie_us #(
|
||||
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
|
||||
.WRITE_TX_FC_ENABLE(1),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
example_core_pcie_us_inst (
|
||||
.clk(clk),
|
||||
@ -246,22 +244,17 @@ example_core_pcie_us_inst (
|
||||
/*
|
||||
* Interrupt interface
|
||||
*/
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(8'd0),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
|
||||
@ -40,7 +40,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -50,11 +49,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
@ -74,6 +73,7 @@ export PARAM_RQ_SEQ_NUM_ENABLE ?= 1
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -93,6 +93,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -116,6 +117,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -66,20 +66,20 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -223,33 +223,33 @@ class TB(object):
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||
# cfg_interrupt_msix_enable
|
||||
# cfg_interrupt_msix_mask
|
||||
# cfg_interrupt_msix_vf_enable
|
||||
# cfg_interrupt_msix_vf_mask
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
|
||||
cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
@ -268,6 +268,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
async def init(self):
|
||||
|
||||
@ -507,7 +508,6 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -517,11 +517,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -543,6 +543,7 @@ def test_fpga_core(request):
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -17,7 +17,6 @@ SYN_FILES += lib/pcie/rtl/pcie_s10_if.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_if_rx.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_if_tx.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -28,11 +27,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
|
||||
@ -17,7 +17,6 @@ SYN_FILES += lib/pcie/rtl/pcie_s10_if.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_if_rx.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_if_tx.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_s10_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -28,11 +27,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
|
||||
@ -6,7 +6,7 @@ proc do_create_pcie {} {
|
||||
create_system pcie
|
||||
set_project_property DEVICE {1SM21CHU1F53E1VG}
|
||||
set_project_property DEVICE_FAMILY {Stratix 10}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {true}
|
||||
set_project_property HIDE_FROM_IP_CATALOG {false}
|
||||
set_use_testbench_naming_pattern 0 {}
|
||||
|
||||
# add HDL parameters
|
||||
@ -54,20 +54,20 @@ proc do_create_pcie {} {
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar2_type_hwtcl} {64-bit prefetchable memory}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar3_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar3_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar4_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar4_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar4_address_width_hwtcl} {16}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar4_type_hwtcl} {64-bit prefetchable memory}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar5_address_width_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_bar5_type_hwtcl} {Disabled}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_class_code_hwtcl} {16711680}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_eq_eieos_cnt_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_expansion_base_address_register_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_loopback_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msi_multiple_msg_cap_hwtcl} {32}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_bir_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_pba_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_pba_offset_hwtcl} {0.0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msi_multiple_msg_cap_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_bir_hwtcl} {4}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_pba_hwtcl} {4}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_pba_offset_hwtcl} {8192.0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_offset_hwtcl} {0.0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_size_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_size_hwtcl} {31}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_msix_table_size_vfcomm_cs2_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_type0_device_id_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {pf0_pci_type0_vendor_id_hwtcl} {4660}
|
||||
@ -276,8 +276,8 @@ proc do_create_pcie {} {
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_ep_native_hwtcl} {Native}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_maxpayload_size_hwtcl} {1024}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_ats_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_msi_enable_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_msix_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_msi_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_msix_enable_hwtcl} {1}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf0_tph_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_ats_cap_enable_hwtcl} {0}
|
||||
set_instance_parameter_value pcie_s10_hip_ast_0 {virtual_pf1_msi_enable_hwtcl} {0}
|
||||
|
||||
@ -62,6 +62,7 @@ parameter TX_SEQ_NUM_WIDTH = 6;
|
||||
parameter PCIE_TAG_COUNT = 256;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
parameter BAR2_APERTURE = 24;
|
||||
parameter BAR4_APERTURE = 16;
|
||||
|
||||
// Clock and reset
|
||||
|
||||
@ -118,12 +119,6 @@ wire [SEG_COUNT-1:0] tx_data_cdts_consumed;
|
||||
wire [SEG_COUNT*2-1:0] tx_cdts_type;
|
||||
wire [SEG_COUNT*1-1:0] tx_cdts_data_value;
|
||||
|
||||
wire app_msi_req;
|
||||
wire app_msi_ack;
|
||||
wire [2:0] app_msi_tc;
|
||||
wire [4:0] app_msi_num;
|
||||
wire [1:0] app_msi_func_num;
|
||||
|
||||
wire [31:0] tl_cfg_ctl;
|
||||
wire [4:0] tl_cfg_add;
|
||||
wire [1:0] tl_cfg_func;
|
||||
@ -163,12 +158,12 @@ pcie pcie_hip_inst (
|
||||
.tx_cplh_cdts (tx_cplh_cdts),
|
||||
.tx_ph_cdts (tx_ph_cdts),
|
||||
.tx_nph_cdts (tx_nph_cdts),
|
||||
.app_msi_req (app_msi_req),
|
||||
.app_msi_ack (app_msi_ack),
|
||||
.app_msi_tc (app_msi_tc),
|
||||
.app_msi_num (app_msi_num),
|
||||
.app_msi_req (1'b0),
|
||||
.app_msi_ack (),
|
||||
.app_msi_tc (3'd0),
|
||||
.app_msi_num (5'd0),
|
||||
.app_int_sts (4'd0),
|
||||
.app_msi_func_num (app_msi_func_num),
|
||||
.app_msi_func_num (2'd0),
|
||||
.int_status (),
|
||||
.int_status_common (),
|
||||
.derr_cor_ext_rpl (),
|
||||
@ -476,7 +471,8 @@ fpga_core #(
|
||||
.TX_SEQ_NUM_WIDTH(TX_SEQ_NUM_WIDTH),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
fpga_core_inst (
|
||||
.clk(clk),
|
||||
@ -519,12 +515,6 @@ fpga_core_inst (
|
||||
.tx_cdts_type(tx_cdts_type),
|
||||
.tx_cdts_data_value(tx_cdts_data_value),
|
||||
|
||||
.app_msi_req(app_msi_req),
|
||||
.app_msi_ack(app_msi_ack),
|
||||
.app_msi_tc(app_msi_tc),
|
||||
.app_msi_num(app_msi_num),
|
||||
.app_msi_func_num(app_msi_func_num),
|
||||
|
||||
.tl_cfg_ctl(tl_cfg_ctl),
|
||||
.tl_cfg_add(tl_cfg_add),
|
||||
.tl_cfg_func(tl_cfg_func)
|
||||
|
||||
@ -39,7 +39,8 @@ module fpga_core #
|
||||
parameter TX_SEQ_NUM_WIDTH = 6,
|
||||
parameter PCIE_TAG_COUNT = 256,
|
||||
parameter BAR0_APERTURE = 24,
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
@ -82,12 +83,6 @@ module fpga_core #
|
||||
input wire [SEG_COUNT*2-1:0] tx_cdts_type,
|
||||
input wire [SEG_COUNT*1-1:0] tx_cdts_data_value,
|
||||
|
||||
output wire app_msi_req,
|
||||
input wire app_msi_ack,
|
||||
output wire [2:0] app_msi_tc,
|
||||
output wire [4:0] app_msi_num,
|
||||
output wire [1:0] app_msi_func_num,
|
||||
|
||||
input wire [31:0] tl_cfg_ctl,
|
||||
input wire [4:0] tl_cfg_add,
|
||||
input wire [1:0] tl_cfg_func
|
||||
@ -110,7 +105,8 @@ example_core_pcie_s10 #(
|
||||
.WRITE_TX_LIMIT(2**TX_SEQ_NUM_WIDTH),
|
||||
.WRITE_TX_FC_ENABLE(1),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
example_core_pcie_s10_inst (
|
||||
.clk(clk),
|
||||
@ -154,15 +150,6 @@ example_core_pcie_s10_inst (
|
||||
.tx_cdts_type(tx_cdts_type),
|
||||
.tx_cdts_data_value(tx_cdts_data_value),
|
||||
|
||||
/*
|
||||
* H-tile MSI interrupt interface
|
||||
*/
|
||||
.app_msi_req(app_msi_req),
|
||||
.app_msi_ack(app_msi_ack),
|
||||
.app_msi_tc(app_msi_tc),
|
||||
.app_msi_num(app_msi_num),
|
||||
.app_msi_func_num(app_msi_func_num),
|
||||
|
||||
/*
|
||||
* H-tile configuration interface
|
||||
*/
|
||||
|
||||
@ -38,7 +38,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if_rx.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_if_tx.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_s10_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -49,11 +48,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
@ -65,6 +64,7 @@ export PARAM_TX_SEQ_NUM_WIDTH ?= 6
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -76,6 +76,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -91,6 +92,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -55,20 +55,20 @@ class TB(object):
|
||||
max_payload_size=1024,
|
||||
enable_extended_tag=True,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -144,11 +144,11 @@ class TB(object):
|
||||
# app_xfer_pending=dut.app_xfer_pending,
|
||||
|
||||
# Interrupt interface
|
||||
app_msi_req=dut.app_msi_req,
|
||||
app_msi_ack=dut.app_msi_ack,
|
||||
app_msi_tc=dut.app_msi_tc,
|
||||
app_msi_num=dut.app_msi_num,
|
||||
app_msi_func_num=dut.app_msi_func_num,
|
||||
# app_msi_req=dut.app_msi_req,
|
||||
# app_msi_ack=dut.app_msi_ack,
|
||||
# app_msi_tc=dut.app_msi_tc,
|
||||
# app_msi_num=dut.app_msi_num,
|
||||
# app_msi_func_num=dut.app_msi_func_num,
|
||||
# app_int_sts=dut.app_int_sts,
|
||||
|
||||
# Error interface
|
||||
@ -191,6 +191,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_s10_inst.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_s10_inst.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.example_core_pcie_s10_inst.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
async def init(self):
|
||||
|
||||
@ -428,7 +429,6 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_s10_if_rx.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_s10_if_tx.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_s10_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_s10_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -439,11 +439,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -457,6 +457,7 @@ def test_fpga_core(request):
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -20,7 +20,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -30,11 +29,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
|
||||
@ -24,8 +24,18 @@ set_property -dict [list \
|
||||
CONFIG.pf0_bar2_type {Memory} \
|
||||
CONFIG.pf0_bar2_scale {Megabytes} \
|
||||
CONFIG.pf0_bar2_size {16} \
|
||||
CONFIG.pf0_msi_enabled {true} \
|
||||
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||
CONFIG.pf0_bar4_64bit {true} \
|
||||
CONFIG.pf0_bar4_prefetchable {true} \
|
||||
CONFIG.pf0_bar4_enabled {true} \
|
||||
CONFIG.pf0_bar4_type {Memory} \
|
||||
CONFIG.pf0_bar4_scale {Kilobytes} \
|
||||
CONFIG.pf0_bar4_size {64} \
|
||||
CONFIG.pf0_msi_enabled {false} \
|
||||
CONFIG.pf0_msix_enabled {true} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
CONFIG.en_msi_per_vec_masking {true} \
|
||||
] [get_ips pcie3_ultrascale_0]
|
||||
|
||||
@ -72,6 +72,7 @@ parameter RQ_SEQ_NUM_ENABLE = 1;
|
||||
parameter PCIE_TAG_COUNT = 64;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
parameter BAR2_APERTURE = 24;
|
||||
parameter BAR4_APERTURE = 16;
|
||||
|
||||
// Clock and reset
|
||||
wire pcie_user_clk;
|
||||
@ -192,22 +193,15 @@ wire [7:0] cfg_fc_cplh;
|
||||
wire [11:0] cfg_fc_cpld;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [7:0] cfg_interrupt_msi_vf_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [1:0] cfg_interrupt_msix_enable;
|
||||
wire [1:0] cfg_interrupt_msix_mask;
|
||||
wire [7:0] cfg_interrupt_msix_vf_enable;
|
||||
wire [7:0] cfg_interrupt_msix_vf_mask;
|
||||
wire [63:0] cfg_interrupt_msix_address;
|
||||
wire [31:0] cfg_interrupt_msix_data;
|
||||
wire cfg_interrupt_msix_int;
|
||||
wire cfg_interrupt_msix_sent;
|
||||
wire cfg_interrupt_msix_fail;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire status_error_cor;
|
||||
@ -338,22 +332,15 @@ pcie3_ultrascale_inst (
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_hot_reset_out(),
|
||||
@ -397,7 +384,8 @@ fpga_core #(
|
||||
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
@ -469,22 +457,15 @@ core_inst (
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.status_error_cor(status_error_cor),
|
||||
|
||||
@ -47,7 +47,8 @@ module fpga_core #
|
||||
parameter RQ_SEQ_NUM_ENABLE = 1,
|
||||
parameter PCIE_TAG_COUNT = 64,
|
||||
parameter BAR0_APERTURE = 24,
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
/*
|
||||
@ -121,22 +122,15 @@ module fpga_core #
|
||||
input wire [11:0] cfg_fc_cpld,
|
||||
output wire [2:0] cfg_fc_sel,
|
||||
|
||||
input wire [3:0] cfg_interrupt_msi_enable,
|
||||
input wire [7:0] cfg_interrupt_msi_vf_enable,
|
||||
input wire [11:0] cfg_interrupt_msi_mmenable,
|
||||
input wire cfg_interrupt_msi_mask_update,
|
||||
input wire [31:0] cfg_interrupt_msi_data,
|
||||
output wire [3:0] cfg_interrupt_msi_select,
|
||||
output wire [31:0] cfg_interrupt_msi_int,
|
||||
output wire [31:0] cfg_interrupt_msi_pending_status,
|
||||
output wire cfg_interrupt_msi_pending_status_data_enable,
|
||||
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
|
||||
input wire cfg_interrupt_msi_sent,
|
||||
input wire cfg_interrupt_msi_fail,
|
||||
output wire [2:0] cfg_interrupt_msi_attr,
|
||||
output wire cfg_interrupt_msi_tph_present,
|
||||
output wire [1:0] cfg_interrupt_msi_tph_type,
|
||||
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
|
||||
input wire [1:0] cfg_interrupt_msix_enable,
|
||||
input wire [1:0] cfg_interrupt_msix_mask,
|
||||
input wire [7:0] cfg_interrupt_msix_vf_enable,
|
||||
input wire [7:0] cfg_interrupt_msix_vf_mask,
|
||||
output wire [63:0] cfg_interrupt_msix_address,
|
||||
output wire [31:0] cfg_interrupt_msix_data,
|
||||
output wire cfg_interrupt_msix_int,
|
||||
input wire cfg_interrupt_msix_sent,
|
||||
input wire cfg_interrupt_msix_fail,
|
||||
output wire [3:0] cfg_interrupt_msi_function_number,
|
||||
|
||||
output wire status_error_cor,
|
||||
@ -166,7 +160,8 @@ example_core_pcie_us #(
|
||||
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
|
||||
.WRITE_TX_FC_ENABLE(1),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
example_core_pcie_us_inst (
|
||||
.clk(clk),
|
||||
@ -246,22 +241,17 @@ example_core_pcie_us_inst (
|
||||
/*
|
||||
* Interrupt interface
|
||||
*/
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(),
|
||||
.cfg_interrupt_msix_vec_pending_status(1'b0),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
|
||||
@ -40,7 +40,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -50,11 +49,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
@ -74,6 +73,7 @@ export PARAM_RQ_SEQ_NUM_ENABLE ?= 1
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -93,6 +93,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -116,6 +117,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -62,16 +62,16 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -198,32 +198,32 @@ class TB(object):
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_vf_enable=dut.cfg_interrupt_msi_vf_enable,
|
||||
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||
cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||
cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||
# cfg_interrupt_msix_enable
|
||||
# cfg_interrupt_msix_mask
|
||||
# cfg_interrupt_msix_vf_enable
|
||||
# cfg_interrupt_msix_vf_mask
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_vf_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
@ -242,6 +242,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
dut.btnu.setimmediatevalue(0)
|
||||
dut.btnl.setimmediatevalue(0)
|
||||
@ -488,7 +489,6 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -498,11 +498,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -524,6 +524,7 @@ def test_fpga_core(request):
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -20,7 +20,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -30,11 +29,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
|
||||
@ -26,8 +26,19 @@ set_property -dict [list \
|
||||
CONFIG.pf0_bar2_type {Memory} \
|
||||
CONFIG.pf0_bar2_scale {Megabytes} \
|
||||
CONFIG.pf0_bar2_size {16} \
|
||||
CONFIG.pf0_msi_enabled {true} \
|
||||
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||
CONFIG.pf0_bar4_64bit {true} \
|
||||
CONFIG.pf0_bar4_prefetchable {true} \
|
||||
CONFIG.pf0_bar4_enabled {true} \
|
||||
CONFIG.pf0_bar4_type {Memory} \
|
||||
CONFIG.pf0_bar4_scale {Kilobytes} \
|
||||
CONFIG.pf0_bar4_size {64} \
|
||||
CONFIG.pf0_msi_enabled {false} \
|
||||
CONFIG.pf0_msix_enabled {true} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \
|
||||
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
CONFIG.en_msi_per_vec_masking {true} \
|
||||
] [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
@ -72,6 +72,7 @@ parameter RQ_SEQ_NUM_ENABLE = 1;
|
||||
parameter PCIE_TAG_COUNT = 256;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
parameter BAR2_APERTURE = 24;
|
||||
parameter BAR4_APERTURE = 16;
|
||||
|
||||
// Clock and reset
|
||||
wire pcie_user_clk;
|
||||
@ -195,22 +196,18 @@ wire [7:0] cfg_fc_cplh;
|
||||
wire [11:0] cfg_fc_cpld;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
wire [3:0] cfg_interrupt_msix_enable;
|
||||
wire [3:0] cfg_interrupt_msix_mask;
|
||||
wire [251:0] cfg_interrupt_msix_vf_enable;
|
||||
wire [251:0] cfg_interrupt_msix_vf_mask;
|
||||
wire [63:0] cfg_interrupt_msix_address;
|
||||
wire [31:0] cfg_interrupt_msix_data;
|
||||
wire cfg_interrupt_msix_int;
|
||||
wire [1:0] cfg_interrupt_msix_vec_pending;
|
||||
wire cfg_interrupt_msix_vec_pending_status;
|
||||
wire cfg_interrupt_msix_sent;
|
||||
wire cfg_interrupt_msix_fail;
|
||||
wire [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
@ -343,21 +340,17 @@ pcie4_uscale_plus_inst (
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_pm_aspm_l1_entry_reject(1'b0),
|
||||
@ -395,7 +388,8 @@ fpga_core #(
|
||||
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
@ -470,21 +464,17 @@ core_inst (
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.status_error_cor(status_error_cor),
|
||||
|
||||
@ -47,7 +47,8 @@ module fpga_core #
|
||||
parameter RQ_SEQ_NUM_ENABLE = 1,
|
||||
parameter PCIE_TAG_COUNT = 256,
|
||||
parameter BAR0_APERTURE = 24,
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
/*
|
||||
@ -124,22 +125,18 @@ module fpga_core #
|
||||
input wire [11:0] cfg_fc_cpld,
|
||||
output wire [2:0] cfg_fc_sel,
|
||||
|
||||
input wire [3:0] cfg_interrupt_msi_enable,
|
||||
input wire [11:0] cfg_interrupt_msi_mmenable,
|
||||
input wire cfg_interrupt_msi_mask_update,
|
||||
input wire [31:0] cfg_interrupt_msi_data,
|
||||
output wire [3:0] cfg_interrupt_msi_select,
|
||||
output wire [31:0] cfg_interrupt_msi_int,
|
||||
output wire [31:0] cfg_interrupt_msi_pending_status,
|
||||
output wire cfg_interrupt_msi_pending_status_data_enable,
|
||||
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
|
||||
input wire cfg_interrupt_msi_sent,
|
||||
input wire cfg_interrupt_msi_fail,
|
||||
output wire [2:0] cfg_interrupt_msi_attr,
|
||||
output wire cfg_interrupt_msi_tph_present,
|
||||
output wire [1:0] cfg_interrupt_msi_tph_type,
|
||||
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
|
||||
output wire [3:0] cfg_interrupt_msi_function_number,
|
||||
input wire [3:0] cfg_interrupt_msix_enable,
|
||||
input wire [3:0] cfg_interrupt_msix_mask,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_enable,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_mask,
|
||||
output wire [63:0] cfg_interrupt_msix_address,
|
||||
output wire [31:0] cfg_interrupt_msix_data,
|
||||
output wire cfg_interrupt_msix_int,
|
||||
output wire [1:0] cfg_interrupt_msix_vec_pending,
|
||||
input wire cfg_interrupt_msix_vec_pending_status,
|
||||
input wire cfg_interrupt_msix_sent,
|
||||
input wire cfg_interrupt_msix_fail,
|
||||
output wire [7:0] cfg_interrupt_msi_function_number,
|
||||
|
||||
output wire status_error_cor,
|
||||
output wire status_error_uncor
|
||||
@ -168,7 +165,8 @@ example_core_pcie_us #(
|
||||
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
|
||||
.WRITE_TX_FC_ENABLE(1),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
example_core_pcie_us_inst (
|
||||
.clk(clk),
|
||||
@ -248,22 +246,17 @@ example_core_pcie_us_inst (
|
||||
/*
|
||||
* Interrupt interface
|
||||
*/
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(8'd0),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
|
||||
@ -40,7 +40,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -50,11 +49,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
@ -74,6 +73,7 @@ export PARAM_RQ_SEQ_NUM_ENABLE ?= 1
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -93,6 +93,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -116,6 +117,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -66,20 +66,20 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -223,33 +223,33 @@ class TB(object):
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||
# cfg_interrupt_msix_enable
|
||||
# cfg_interrupt_msix_mask
|
||||
# cfg_interrupt_msix_vf_enable
|
||||
# cfg_interrupt_msix_vf_mask
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
|
||||
cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
@ -268,6 +268,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
dut.btnu.setimmediatevalue(0)
|
||||
dut.btnl.setimmediatevalue(0)
|
||||
@ -514,7 +515,6 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -524,11 +524,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -550,6 +550,7 @@ def test_fpga_core(request):
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -20,7 +20,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -30,11 +29,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
|
||||
@ -26,8 +26,19 @@ set_property -dict [list \
|
||||
CONFIG.pf0_bar2_type {Memory} \
|
||||
CONFIG.pf0_bar2_scale {Megabytes} \
|
||||
CONFIG.pf0_bar2_size {16} \
|
||||
CONFIG.pf0_msi_enabled {true} \
|
||||
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||
CONFIG.pf0_bar4_64bit {true} \
|
||||
CONFIG.pf0_bar4_prefetchable {true} \
|
||||
CONFIG.pf0_bar4_enabled {true} \
|
||||
CONFIG.pf0_bar4_type {Memory} \
|
||||
CONFIG.pf0_bar4_scale {Kilobytes} \
|
||||
CONFIG.pf0_bar4_size {64} \
|
||||
CONFIG.pf0_msi_enabled {false} \
|
||||
CONFIG.pf0_msix_enabled {true} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \
|
||||
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
CONFIG.en_msi_per_vec_masking {true} \
|
||||
] [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
@ -67,6 +67,7 @@ parameter RQ_SEQ_NUM_ENABLE = 1;
|
||||
parameter PCIE_TAG_COUNT = 256;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
parameter BAR2_APERTURE = 24;
|
||||
parameter BAR4_APERTURE = 16;
|
||||
|
||||
// Clock and reset
|
||||
wire pcie_user_clk;
|
||||
@ -175,22 +176,18 @@ wire [7:0] cfg_fc_cplh;
|
||||
wire [11:0] cfg_fc_cpld;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
wire [3:0] cfg_interrupt_msix_enable;
|
||||
wire [3:0] cfg_interrupt_msix_mask;
|
||||
wire [251:0] cfg_interrupt_msix_vf_enable;
|
||||
wire [251:0] cfg_interrupt_msix_vf_mask;
|
||||
wire [63:0] cfg_interrupt_msix_address;
|
||||
wire [31:0] cfg_interrupt_msix_data;
|
||||
wire cfg_interrupt_msix_int;
|
||||
wire [1:0] cfg_interrupt_msix_vec_pending;
|
||||
wire cfg_interrupt_msix_vec_pending_status;
|
||||
wire cfg_interrupt_msix_sent;
|
||||
wire cfg_interrupt_msix_fail;
|
||||
wire [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
@ -323,21 +320,17 @@ pcie4_uscale_plus_inst (
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_pm_aspm_l1_entry_reject(1'b0),
|
||||
@ -375,7 +368,8 @@ fpga_core #(
|
||||
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
@ -445,21 +439,17 @@ core_inst (
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.status_error_cor(status_error_cor),
|
||||
|
||||
@ -47,7 +47,8 @@ module fpga_core #
|
||||
parameter RQ_SEQ_NUM_ENABLE = 1,
|
||||
parameter PCIE_TAG_COUNT = 256,
|
||||
parameter BAR0_APERTURE = 24,
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
/*
|
||||
@ -119,22 +120,18 @@ module fpga_core #
|
||||
input wire [11:0] cfg_fc_cpld,
|
||||
output wire [2:0] cfg_fc_sel,
|
||||
|
||||
input wire [3:0] cfg_interrupt_msi_enable,
|
||||
input wire [11:0] cfg_interrupt_msi_mmenable,
|
||||
input wire cfg_interrupt_msi_mask_update,
|
||||
input wire [31:0] cfg_interrupt_msi_data,
|
||||
output wire [3:0] cfg_interrupt_msi_select,
|
||||
output wire [31:0] cfg_interrupt_msi_int,
|
||||
output wire [31:0] cfg_interrupt_msi_pending_status,
|
||||
output wire cfg_interrupt_msi_pending_status_data_enable,
|
||||
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
|
||||
input wire cfg_interrupt_msi_sent,
|
||||
input wire cfg_interrupt_msi_fail,
|
||||
output wire [2:0] cfg_interrupt_msi_attr,
|
||||
output wire cfg_interrupt_msi_tph_present,
|
||||
output wire [1:0] cfg_interrupt_msi_tph_type,
|
||||
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
|
||||
output wire [3:0] cfg_interrupt_msi_function_number,
|
||||
input wire [3:0] cfg_interrupt_msix_enable,
|
||||
input wire [3:0] cfg_interrupt_msix_mask,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_enable,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_mask,
|
||||
output wire [63:0] cfg_interrupt_msix_address,
|
||||
output wire [31:0] cfg_interrupt_msix_data,
|
||||
output wire cfg_interrupt_msix_int,
|
||||
output wire [1:0] cfg_interrupt_msix_vec_pending,
|
||||
input wire cfg_interrupt_msix_vec_pending_status,
|
||||
input wire cfg_interrupt_msix_sent,
|
||||
input wire cfg_interrupt_msix_fail,
|
||||
output wire [7:0] cfg_interrupt_msi_function_number,
|
||||
|
||||
output wire status_error_cor,
|
||||
output wire status_error_uncor
|
||||
@ -163,7 +160,8 @@ example_core_pcie_us #(
|
||||
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
|
||||
.WRITE_TX_FC_ENABLE(1),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
example_core_pcie_us_inst (
|
||||
.clk(clk),
|
||||
@ -243,22 +241,17 @@ example_core_pcie_us_inst (
|
||||
/*
|
||||
* Interrupt interface
|
||||
*/
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(8'd0),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
|
||||
@ -40,7 +40,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -50,11 +49,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
@ -74,6 +73,7 @@ export PARAM_RQ_SEQ_NUM_ENABLE ?= 1
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -93,6 +93,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -116,6 +117,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -66,20 +66,20 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -223,33 +223,33 @@ class TB(object):
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||
# cfg_interrupt_msix_enable
|
||||
# cfg_interrupt_msix_mask
|
||||
# cfg_interrupt_msix_vf_enable
|
||||
# cfg_interrupt_msix_vf_mask
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
|
||||
cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
@ -268,6 +268,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
dut.sw.setimmediatevalue(0)
|
||||
|
||||
@ -509,7 +510,6 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -519,11 +519,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -545,6 +545,7 @@ def test_fpga_core(request):
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -20,7 +20,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -30,11 +29,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
|
||||
@ -24,8 +24,19 @@ set_property -dict [list \
|
||||
CONFIG.pf0_bar2_type {Memory} \
|
||||
CONFIG.pf0_bar2_scale {Megabytes} \
|
||||
CONFIG.pf0_bar2_size {16} \
|
||||
CONFIG.pf0_msi_enabled {true} \
|
||||
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||
CONFIG.pf0_bar4_64bit {true} \
|
||||
CONFIG.pf0_bar4_prefetchable {true} \
|
||||
CONFIG.pf0_bar4_enabled {true} \
|
||||
CONFIG.pf0_bar4_type {Memory} \
|
||||
CONFIG.pf0_bar4_scale {Kilobytes} \
|
||||
CONFIG.pf0_bar4_size {64} \
|
||||
CONFIG.pf0_msi_enabled {false} \
|
||||
CONFIG.pf0_msix_enabled {true} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \
|
||||
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
CONFIG.en_msi_per_vec_masking {true} \
|
||||
] [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
@ -72,6 +72,7 @@ parameter RQ_SEQ_NUM_ENABLE = 1;
|
||||
parameter PCIE_TAG_COUNT = 256;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
parameter BAR2_APERTURE = 24;
|
||||
parameter BAR4_APERTURE = 16;
|
||||
|
||||
// Clock and reset
|
||||
wire pcie_user_clk;
|
||||
@ -195,22 +196,18 @@ wire [7:0] cfg_fc_cplh;
|
||||
wire [11:0] cfg_fc_cpld;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
wire [3:0] cfg_interrupt_msix_enable;
|
||||
wire [3:0] cfg_interrupt_msix_mask;
|
||||
wire [251:0] cfg_interrupt_msix_vf_enable;
|
||||
wire [251:0] cfg_interrupt_msix_vf_mask;
|
||||
wire [63:0] cfg_interrupt_msix_address;
|
||||
wire [31:0] cfg_interrupt_msix_data;
|
||||
wire cfg_interrupt_msix_int;
|
||||
wire [1:0] cfg_interrupt_msix_vec_pending;
|
||||
wire cfg_interrupt_msix_vec_pending_status;
|
||||
wire cfg_interrupt_msix_sent;
|
||||
wire cfg_interrupt_msix_fail;
|
||||
wire [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
@ -343,21 +340,17 @@ pcie4_uscale_plus_inst (
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_pm_aspm_l1_entry_reject(1'b0),
|
||||
@ -395,7 +388,8 @@ fpga_core #(
|
||||
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
@ -470,21 +464,17 @@ core_inst (
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.status_error_cor(status_error_cor),
|
||||
|
||||
@ -47,7 +47,8 @@ module fpga_core #
|
||||
parameter RQ_SEQ_NUM_ENABLE = 1,
|
||||
parameter PCIE_TAG_COUNT = 256,
|
||||
parameter BAR0_APERTURE = 24,
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
/*
|
||||
@ -124,22 +125,18 @@ module fpga_core #
|
||||
input wire [11:0] cfg_fc_cpld,
|
||||
output wire [2:0] cfg_fc_sel,
|
||||
|
||||
input wire [3:0] cfg_interrupt_msi_enable,
|
||||
input wire [11:0] cfg_interrupt_msi_mmenable,
|
||||
input wire cfg_interrupt_msi_mask_update,
|
||||
input wire [31:0] cfg_interrupt_msi_data,
|
||||
output wire [3:0] cfg_interrupt_msi_select,
|
||||
output wire [31:0] cfg_interrupt_msi_int,
|
||||
output wire [31:0] cfg_interrupt_msi_pending_status,
|
||||
output wire cfg_interrupt_msi_pending_status_data_enable,
|
||||
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
|
||||
input wire cfg_interrupt_msi_sent,
|
||||
input wire cfg_interrupt_msi_fail,
|
||||
output wire [2:0] cfg_interrupt_msi_attr,
|
||||
output wire cfg_interrupt_msi_tph_present,
|
||||
output wire [1:0] cfg_interrupt_msi_tph_type,
|
||||
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
|
||||
output wire [3:0] cfg_interrupt_msi_function_number,
|
||||
input wire [3:0] cfg_interrupt_msix_enable,
|
||||
input wire [3:0] cfg_interrupt_msix_mask,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_enable,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_mask,
|
||||
output wire [63:0] cfg_interrupt_msix_address,
|
||||
output wire [31:0] cfg_interrupt_msix_data,
|
||||
output wire cfg_interrupt_msix_int,
|
||||
output wire [1:0] cfg_interrupt_msix_vec_pending,
|
||||
input wire cfg_interrupt_msix_vec_pending_status,
|
||||
input wire cfg_interrupt_msix_sent,
|
||||
input wire cfg_interrupt_msix_fail,
|
||||
output wire [7:0] cfg_interrupt_msi_function_number,
|
||||
|
||||
output wire status_error_cor,
|
||||
output wire status_error_uncor
|
||||
@ -168,7 +165,8 @@ example_core_pcie_us #(
|
||||
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
|
||||
.WRITE_TX_FC_ENABLE(1),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
example_core_pcie_us_inst (
|
||||
.clk(clk),
|
||||
@ -248,22 +246,17 @@ example_core_pcie_us_inst (
|
||||
/*
|
||||
* Interrupt interface
|
||||
*/
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(8'd0),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
|
||||
@ -40,7 +40,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -50,11 +49,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
@ -74,6 +73,7 @@ export PARAM_RQ_SEQ_NUM_ENABLE ?= 1
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -93,6 +93,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -116,6 +117,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -66,20 +66,20 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -223,33 +223,33 @@ class TB(object):
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||
# cfg_interrupt_msix_enable
|
||||
# cfg_interrupt_msix_mask
|
||||
# cfg_interrupt_msix_vf_enable
|
||||
# cfg_interrupt_msix_vf_mask
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
|
||||
cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
@ -268,6 +268,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
dut.btnu.setimmediatevalue(0)
|
||||
dut.btnl.setimmediatevalue(0)
|
||||
@ -514,7 +515,6 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -524,11 +524,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -550,6 +550,7 @@ def test_fpga_core(request):
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -309,7 +309,7 @@ static int edev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
}
|
||||
|
||||
// Allocate MSI IRQs
|
||||
ret = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
|
||||
ret = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI | PCI_IRQ_MSIX);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "Failed to allocate IRQs");
|
||||
goto fail_map_bars;
|
||||
|
||||
@ -60,7 +60,9 @@ module example_core #
|
||||
// RAM segment byte enable width
|
||||
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8,
|
||||
// RAM segment address width
|
||||
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH)
|
||||
parameter RAM_SEG_ADDR_WIDTH = RAM_ADDR_WIDTH-$clog2(RAM_SEG_COUNT*RAM_SEG_BE_WIDTH),
|
||||
// Interrupt configuration
|
||||
parameter IRQ_INDEX_WIDTH = 5
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
@ -146,9 +148,11 @@ module example_core #
|
||||
output wire [RAM_SEG_COUNT-1:0] ram_wr_done,
|
||||
|
||||
/*
|
||||
* MSI request outputs
|
||||
* Interrupt request output
|
||||
*/
|
||||
output wire [31:0] msi_irq
|
||||
output wire [IRQ_INDEX_WIDTH-1:0] irq_index,
|
||||
output wire irq_valid,
|
||||
input wire irq_ready
|
||||
);
|
||||
|
||||
localparam RAM_ADDR_IMM_WIDTH = (DMA_IMM_ENABLE && (DMA_IMM_WIDTH > RAM_ADDR_WIDTH)) ? DMA_IMM_WIDTH : RAM_ADDR_WIDTH;
|
||||
@ -224,6 +228,7 @@ reg dma_write_desc_status_valid_reg = 0, dma_write_desc_status_valid_next;
|
||||
reg dma_enable_reg = 0, dma_enable_next;
|
||||
reg dma_rd_int_en_reg = 0, dma_rd_int_en_next;
|
||||
reg dma_wr_int_en_reg = 0, dma_wr_int_en_next;
|
||||
reg irq_valid_reg = 1'b0, irq_valid_next;
|
||||
|
||||
reg dma_read_block_run_reg = 1'b0, dma_read_block_run_next;
|
||||
reg [DMA_LEN_WIDTH-1:0] dma_read_block_len_reg = 0, dma_read_block_len_next;
|
||||
@ -276,8 +281,8 @@ assign m_axis_dma_write_desc_len = dma_write_desc_len_reg;
|
||||
assign m_axis_dma_write_desc_tag = dma_write_desc_tag_reg;
|
||||
assign m_axis_dma_write_desc_valid = dma_write_desc_valid_reg;
|
||||
|
||||
assign msi_irq[0] = (s_axis_dma_read_desc_status_valid && dma_rd_int_en_reg) || (s_axis_dma_write_desc_status_valid && dma_wr_int_en_reg);
|
||||
assign msi_irq[31:1] = 31'd0;
|
||||
assign irq_index = 0;
|
||||
assign irq_valid = irq_valid_reg;
|
||||
|
||||
always @* begin
|
||||
axil_ctrl_awready_next = 1'b0;
|
||||
@ -315,6 +320,8 @@ always @* begin
|
||||
dma_rd_int_en_next = dma_rd_int_en_reg;
|
||||
dma_wr_int_en_next = dma_wr_int_en_reg;
|
||||
|
||||
irq_valid_next = irq_valid_reg && !irq_ready;
|
||||
|
||||
dma_read_block_run_next = dma_read_block_run_reg;
|
||||
dma_read_block_len_next = dma_read_block_len_reg;
|
||||
dma_read_block_count_next = dma_read_block_count_reg;
|
||||
@ -526,6 +533,10 @@ always @* begin
|
||||
dma_read_desc_status_tag_next = s_axis_dma_read_desc_status_tag;
|
||||
dma_read_desc_status_error_next = s_axis_dma_read_desc_status_error;
|
||||
dma_read_desc_status_valid_next = s_axis_dma_read_desc_status_valid;
|
||||
|
||||
if (dma_rd_int_en_reg) begin
|
||||
irq_valid_next = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// store write response
|
||||
@ -533,6 +544,10 @@ always @* begin
|
||||
dma_write_desc_status_tag_next = s_axis_dma_write_desc_status_tag;
|
||||
dma_write_desc_status_error_next = s_axis_dma_write_desc_status_error;
|
||||
dma_write_desc_status_valid_next = s_axis_dma_write_desc_status_valid;
|
||||
|
||||
if (dma_wr_int_en_reg) begin
|
||||
irq_valid_next = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
// block read
|
||||
@ -626,6 +641,8 @@ always @(posedge clk) begin
|
||||
dma_rd_int_en_reg <= dma_rd_int_en_next;
|
||||
dma_wr_int_en_reg <= dma_wr_int_en_next;
|
||||
|
||||
irq_valid_reg <= irq_valid_next;
|
||||
|
||||
dma_read_block_run_reg <= dma_read_block_run_next;
|
||||
dma_read_block_len_reg <= dma_read_block_len_next;
|
||||
dma_read_block_count_reg <= dma_read_block_count_next;
|
||||
@ -670,6 +687,7 @@ always @(posedge clk) begin
|
||||
dma_enable_reg <= 1'b0;
|
||||
dma_rd_int_en_reg <= 1'b0;
|
||||
dma_wr_int_en_reg <= 1'b0;
|
||||
irq_valid_reg <= 1'b0;
|
||||
dma_read_block_run_reg <= 1'b0;
|
||||
dma_write_block_run_reg <= 1'b0;
|
||||
end
|
||||
|
||||
@ -72,7 +72,9 @@ module example_core_pcie #
|
||||
// BAR0 aperture (log2 size)
|
||||
parameter BAR0_APERTURE = 24,
|
||||
// BAR2 aperture (log2 size)
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
// BAR4 aperture (log2 size)
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
@ -144,6 +146,17 @@ module example_core_pcie #
|
||||
input wire [TX_SEQ_NUM_COUNT*TX_SEQ_NUM_WIDTH-1:0] s_axis_wr_req_tx_seq_num,
|
||||
input wire [TX_SEQ_NUM_COUNT-1:0] s_axis_wr_req_tx_seq_num_valid,
|
||||
|
||||
/*
|
||||
* TLP output (MSI-X write request)
|
||||
*/
|
||||
output wire [31:0] tx_msix_wr_req_tlp_data,
|
||||
output wire tx_msix_wr_req_tlp_strb,
|
||||
output wire [TLP_HDR_WIDTH-1:0] tx_msix_wr_req_tlp_hdr,
|
||||
output wire tx_msix_wr_req_tlp_valid,
|
||||
output wire tx_msix_wr_req_tlp_sop,
|
||||
output wire tx_msix_wr_req_tlp_eop,
|
||||
input wire tx_msix_wr_req_tlp_ready,
|
||||
|
||||
/*
|
||||
* Transmit flow control
|
||||
*/
|
||||
@ -158,28 +171,29 @@ module example_core_pcie #
|
||||
input wire ext_tag_enable,
|
||||
input wire [2:0] max_read_request_size,
|
||||
input wire [2:0] max_payload_size,
|
||||
input wire msix_enable,
|
||||
input wire msix_mask,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire status_error_cor,
|
||||
output wire status_error_uncor,
|
||||
|
||||
/*
|
||||
* MSI request outputs
|
||||
*/
|
||||
output wire [31:0] msi_irq
|
||||
output wire status_error_uncor
|
||||
);
|
||||
|
||||
parameter AXIL_DATA_WIDTH = 32;
|
||||
parameter AXIL_ADDR_WIDTH = BAR0_APERTURE;
|
||||
parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
|
||||
parameter AXIL_CTRL_DATA_WIDTH = 32;
|
||||
parameter AXIL_CTRL_ADDR_WIDTH = BAR0_APERTURE;
|
||||
parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8);
|
||||
|
||||
parameter AXI_DATA_WIDTH = TLP_DATA_WIDTH;
|
||||
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
|
||||
parameter AXI_ADDR_WIDTH = BAR2_APERTURE;
|
||||
parameter AXI_ID_WIDTH = 8;
|
||||
|
||||
parameter AXIL_MSIX_DATA_WIDTH = 32;
|
||||
parameter AXIL_MSIX_ADDR_WIDTH = BAR4_APERTURE;
|
||||
parameter AXIL_MSIX_STRB_WIDTH = (AXIL_MSIX_DATA_WIDTH/8);
|
||||
|
||||
parameter RAM_SEL_WIDTH = 2;
|
||||
parameter RAM_ADDR_WIDTH = 16;
|
||||
parameter RAM_SEG_COUNT = TLP_SEG_COUNT*2;
|
||||
@ -191,25 +205,47 @@ parameter PCIE_ADDR_WIDTH = 64;
|
||||
parameter DMA_LEN_WIDTH = 16;
|
||||
parameter DMA_TAG_WIDTH = 8;
|
||||
|
||||
wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_awaddr;
|
||||
wire [2:0] axil_ctrl_awprot;
|
||||
wire axil_ctrl_awvalid;
|
||||
wire axil_ctrl_awready;
|
||||
wire [AXIL_DATA_WIDTH-1:0] axil_ctrl_wdata;
|
||||
wire [AXIL_STRB_WIDTH-1:0] axil_ctrl_wstrb;
|
||||
wire axil_ctrl_wvalid;
|
||||
wire axil_ctrl_wready;
|
||||
wire [1:0] axil_ctrl_bresp;
|
||||
wire axil_ctrl_bvalid;
|
||||
wire axil_ctrl_bready;
|
||||
wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_araddr;
|
||||
wire [2:0] axil_ctrl_arprot;
|
||||
wire axil_ctrl_arvalid;
|
||||
wire axil_ctrl_arready;
|
||||
wire [AXIL_DATA_WIDTH-1:0] axil_ctrl_rdata;
|
||||
wire [1:0] axil_ctrl_rresp;
|
||||
wire axil_ctrl_rvalid;
|
||||
wire axil_ctrl_rready;
|
||||
parameter IRQ_INDEX_WIDTH = 5;
|
||||
|
||||
wire [AXIL_CTRL_ADDR_WIDTH-1:0] axil_ctrl_awaddr;
|
||||
wire [2:0] axil_ctrl_awprot;
|
||||
wire axil_ctrl_awvalid;
|
||||
wire axil_ctrl_awready;
|
||||
wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_ctrl_wdata;
|
||||
wire [AXIL_CTRL_STRB_WIDTH-1:0] axil_ctrl_wstrb;
|
||||
wire axil_ctrl_wvalid;
|
||||
wire axil_ctrl_wready;
|
||||
wire [1:0] axil_ctrl_bresp;
|
||||
wire axil_ctrl_bvalid;
|
||||
wire axil_ctrl_bready;
|
||||
wire [AXIL_CTRL_ADDR_WIDTH-1:0] axil_ctrl_araddr;
|
||||
wire [2:0] axil_ctrl_arprot;
|
||||
wire axil_ctrl_arvalid;
|
||||
wire axil_ctrl_arready;
|
||||
wire [AXIL_CTRL_DATA_WIDTH-1:0] axil_ctrl_rdata;
|
||||
wire [1:0] axil_ctrl_rresp;
|
||||
wire axil_ctrl_rvalid;
|
||||
wire axil_ctrl_rready;
|
||||
|
||||
wire [AXIL_MSIX_ADDR_WIDTH-1:0] axil_msix_awaddr;
|
||||
wire [2:0] axil_msix_awprot;
|
||||
wire axil_msix_awvalid;
|
||||
wire axil_msix_awready;
|
||||
wire [AXIL_MSIX_DATA_WIDTH-1:0] axil_msix_wdata;
|
||||
wire [AXIL_MSIX_STRB_WIDTH-1:0] axil_msix_wstrb;
|
||||
wire axil_msix_wvalid;
|
||||
wire axil_msix_wready;
|
||||
wire [1:0] axil_msix_bresp;
|
||||
wire axil_msix_bvalid;
|
||||
wire axil_msix_bready;
|
||||
wire [AXIL_MSIX_ADDR_WIDTH-1:0] axil_msix_araddr;
|
||||
wire [2:0] axil_msix_arprot;
|
||||
wire axil_msix_arvalid;
|
||||
wire axil_msix_arready;
|
||||
wire [AXIL_MSIX_DATA_WIDTH-1:0] axil_msix_rdata;
|
||||
wire [1:0] axil_msix_rresp;
|
||||
wire axil_msix_rvalid;
|
||||
wire axil_msix_rready;
|
||||
|
||||
wire [PCIE_ADDR_WIDTH-1:0] axis_dma_read_desc_dma_addr;
|
||||
wire [RAM_SEL_WIDTH-1:0] axis_dma_read_desc_ram_sel;
|
||||
@ -252,8 +288,8 @@ wire [RAM_SEG_COUNT-1:0] ram_wr_cmd_valid;
|
||||
wire [RAM_SEG_COUNT-1:0] ram_wr_cmd_ready;
|
||||
wire [RAM_SEG_COUNT-1:0] ram_wr_done;
|
||||
|
||||
wire [2:0] status_error_cor_int;
|
||||
wire [2:0] status_error_uncor_int;
|
||||
wire [3:0] status_error_cor_int;
|
||||
wire [3:0] status_error_uncor_int;
|
||||
|
||||
// PCIe connections
|
||||
wire [TLP_DATA_WIDTH-1:0] ctrl_rx_req_tlp_data;
|
||||
@ -292,8 +328,31 @@ wire [TLP_SEG_COUNT-1:0] ram_tx_cpl_tlp_sop;
|
||||
wire [TLP_SEG_COUNT-1:0] ram_tx_cpl_tlp_eop;
|
||||
wire ram_tx_cpl_tlp_ready;
|
||||
|
||||
wire [TLP_DATA_WIDTH-1:0] msix_rx_req_tlp_data;
|
||||
wire [TLP_STRB_WIDTH-1:0] msix_rx_req_tlp_strb;
|
||||
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] msix_rx_req_tlp_hdr;
|
||||
wire [TLP_SEG_COUNT*3-1:0] msix_rx_req_tlp_bar_id;
|
||||
wire [TLP_SEG_COUNT*8-1:0] msix_rx_req_tlp_func_num;
|
||||
wire [TLP_SEG_COUNT-1:0] msix_rx_req_tlp_valid;
|
||||
wire [TLP_SEG_COUNT-1:0] msix_rx_req_tlp_sop;
|
||||
wire [TLP_SEG_COUNT-1:0] msix_rx_req_tlp_eop;
|
||||
wire msix_rx_req_tlp_ready;
|
||||
|
||||
wire [TLP_DATA_WIDTH-1:0] msix_tx_cpl_tlp_data;
|
||||
wire [TLP_STRB_WIDTH-1:0] msix_tx_cpl_tlp_strb;
|
||||
wire [TLP_SEG_COUNT*TLP_HDR_WIDTH-1:0] msix_tx_cpl_tlp_hdr;
|
||||
wire [TLP_SEG_COUNT-1:0] msix_tx_cpl_tlp_valid;
|
||||
wire [TLP_SEG_COUNT-1:0] msix_tx_cpl_tlp_sop;
|
||||
wire [TLP_SEG_COUNT-1:0] msix_tx_cpl_tlp_eop;
|
||||
wire msix_tx_cpl_tlp_ready;
|
||||
|
||||
// Interrupts
|
||||
wire [IRQ_INDEX_WIDTH-1:0] irq_index;
|
||||
wire irq_valid;
|
||||
wire irq_ready;
|
||||
|
||||
pcie_tlp_demux_bar #(
|
||||
.PORTS(2),
|
||||
.PORTS(3),
|
||||
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
|
||||
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
|
||||
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
|
||||
@ -325,16 +384,16 @@ pcie_tlp_demux_inst (
|
||||
/*
|
||||
* TLP output
|
||||
*/
|
||||
.out_tlp_data( {ram_rx_req_tlp_data, ctrl_rx_req_tlp_data }),
|
||||
.out_tlp_strb( {ram_rx_req_tlp_strb, ctrl_rx_req_tlp_strb }),
|
||||
.out_tlp_hdr( {ram_rx_req_tlp_hdr, ctrl_rx_req_tlp_hdr }),
|
||||
.out_tlp_bar_id( {ram_rx_req_tlp_bar_id, ctrl_rx_req_tlp_bar_id }),
|
||||
.out_tlp_func_num({ram_rx_req_tlp_func_num, ctrl_rx_req_tlp_func_num}),
|
||||
.out_tlp_data( {msix_rx_req_tlp_data, ram_rx_req_tlp_data, ctrl_rx_req_tlp_data }),
|
||||
.out_tlp_strb( {msix_rx_req_tlp_strb, ram_rx_req_tlp_strb, ctrl_rx_req_tlp_strb }),
|
||||
.out_tlp_hdr( {msix_rx_req_tlp_hdr, ram_rx_req_tlp_hdr, ctrl_rx_req_tlp_hdr }),
|
||||
.out_tlp_bar_id( {msix_rx_req_tlp_bar_id, ram_rx_req_tlp_bar_id, ctrl_rx_req_tlp_bar_id }),
|
||||
.out_tlp_func_num({msix_rx_req_tlp_func_num, ram_rx_req_tlp_func_num, ctrl_rx_req_tlp_func_num}),
|
||||
.out_tlp_error(),
|
||||
.out_tlp_valid( {ram_rx_req_tlp_valid, ctrl_rx_req_tlp_valid }),
|
||||
.out_tlp_sop( {ram_rx_req_tlp_sop, ctrl_rx_req_tlp_sop }),
|
||||
.out_tlp_eop( {ram_rx_req_tlp_eop, ctrl_rx_req_tlp_eop }),
|
||||
.out_tlp_ready( {ram_rx_req_tlp_ready, ctrl_rx_req_tlp_ready }),
|
||||
.out_tlp_valid( {msix_rx_req_tlp_valid, ram_rx_req_tlp_valid, ctrl_rx_req_tlp_valid }),
|
||||
.out_tlp_sop( {msix_rx_req_tlp_sop, ram_rx_req_tlp_sop, ctrl_rx_req_tlp_sop }),
|
||||
.out_tlp_eop( {msix_rx_req_tlp_eop, ram_rx_req_tlp_eop, ctrl_rx_req_tlp_eop }),
|
||||
.out_tlp_ready( {msix_rx_req_tlp_ready, ram_rx_req_tlp_ready, ctrl_rx_req_tlp_ready }),
|
||||
|
||||
/*
|
||||
* Control
|
||||
@ -349,7 +408,7 @@ pcie_tlp_demux_inst (
|
||||
);
|
||||
|
||||
pcie_tlp_mux #(
|
||||
.PORTS(2),
|
||||
.PORTS(3),
|
||||
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
|
||||
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
|
||||
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
|
||||
@ -364,17 +423,17 @@ pcie_tlp_mux_inst (
|
||||
/*
|
||||
* TLP input
|
||||
*/
|
||||
.in_tlp_data( {ram_tx_cpl_tlp_data, ctrl_tx_cpl_tlp_data }),
|
||||
.in_tlp_strb( {ram_tx_cpl_tlp_strb, ctrl_tx_cpl_tlp_strb }),
|
||||
.in_tlp_hdr( {ram_tx_cpl_tlp_hdr, ctrl_tx_cpl_tlp_hdr }),
|
||||
.in_tlp_data( {msix_tx_cpl_tlp_data, ram_tx_cpl_tlp_data, ctrl_tx_cpl_tlp_data }),
|
||||
.in_tlp_strb( {msix_tx_cpl_tlp_strb, ram_tx_cpl_tlp_strb, ctrl_tx_cpl_tlp_strb }),
|
||||
.in_tlp_hdr( {msix_tx_cpl_tlp_hdr, ram_tx_cpl_tlp_hdr, ctrl_tx_cpl_tlp_hdr }),
|
||||
.in_tlp_seq(0),
|
||||
.in_tlp_bar_id(0),
|
||||
.in_tlp_func_num(0),
|
||||
.in_tlp_error(0),
|
||||
.in_tlp_valid({ram_tx_cpl_tlp_valid, ctrl_tx_cpl_tlp_valid}),
|
||||
.in_tlp_sop( {ram_tx_cpl_tlp_sop, ctrl_tx_cpl_tlp_sop }),
|
||||
.in_tlp_eop( {ram_tx_cpl_tlp_eop, ctrl_tx_cpl_tlp_eop }),
|
||||
.in_tlp_ready({ram_tx_cpl_tlp_ready, ctrl_tx_cpl_tlp_ready}),
|
||||
.in_tlp_valid({msix_tx_cpl_tlp_valid, ram_tx_cpl_tlp_valid, ctrl_tx_cpl_tlp_valid}),
|
||||
.in_tlp_sop( {msix_tx_cpl_tlp_sop, ram_tx_cpl_tlp_sop, ctrl_tx_cpl_tlp_sop }),
|
||||
.in_tlp_eop( {msix_tx_cpl_tlp_eop, ram_tx_cpl_tlp_eop, ctrl_tx_cpl_tlp_eop }),
|
||||
.in_tlp_ready({msix_tx_cpl_tlp_ready, ram_tx_cpl_tlp_ready, ctrl_tx_cpl_tlp_ready}),
|
||||
|
||||
/*
|
||||
* TLP output
|
||||
@ -403,9 +462,9 @@ pcie_axil_master #(
|
||||
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
|
||||
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
|
||||
.TLP_SEG_COUNT(TLP_SEG_COUNT),
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
|
||||
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
|
||||
.AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
|
||||
.AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
|
||||
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR)
|
||||
)
|
||||
pcie_axil_master_inst (
|
||||
@ -639,6 +698,76 @@ axi_ram_inst (
|
||||
.s_axi_rready(axi_ram_rready)
|
||||
);
|
||||
|
||||
pcie_axil_master #(
|
||||
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
|
||||
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
|
||||
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
|
||||
.TLP_SEG_COUNT(TLP_SEG_COUNT),
|
||||
.AXIL_DATA_WIDTH(AXIL_MSIX_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(AXIL_MSIX_ADDR_WIDTH),
|
||||
.AXIL_STRB_WIDTH(AXIL_MSIX_STRB_WIDTH),
|
||||
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR)
|
||||
)
|
||||
msix_pcie_axil_master_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* TLP input (request)
|
||||
*/
|
||||
.rx_req_tlp_data(msix_rx_req_tlp_data),
|
||||
.rx_req_tlp_hdr(msix_rx_req_tlp_hdr),
|
||||
.rx_req_tlp_valid(msix_rx_req_tlp_valid),
|
||||
.rx_req_tlp_sop(msix_rx_req_tlp_sop),
|
||||
.rx_req_tlp_eop(msix_rx_req_tlp_eop),
|
||||
.rx_req_tlp_ready(msix_rx_req_tlp_ready),
|
||||
|
||||
/*
|
||||
* TLP output (completion)
|
||||
*/
|
||||
.tx_cpl_tlp_data(msix_tx_cpl_tlp_data),
|
||||
.tx_cpl_tlp_strb(msix_tx_cpl_tlp_strb),
|
||||
.tx_cpl_tlp_hdr(msix_tx_cpl_tlp_hdr),
|
||||
.tx_cpl_tlp_valid(msix_tx_cpl_tlp_valid),
|
||||
.tx_cpl_tlp_sop(msix_tx_cpl_tlp_sop),
|
||||
.tx_cpl_tlp_eop(msix_tx_cpl_tlp_eop),
|
||||
.tx_cpl_tlp_ready(msix_tx_cpl_tlp_ready),
|
||||
|
||||
/*
|
||||
* AXI Lite Master output
|
||||
*/
|
||||
.m_axil_awaddr(axil_msix_awaddr),
|
||||
.m_axil_awprot(axil_msix_awprot),
|
||||
.m_axil_awvalid(axil_msix_awvalid),
|
||||
.m_axil_awready(axil_msix_awready),
|
||||
.m_axil_wdata(axil_msix_wdata),
|
||||
.m_axil_wstrb(axil_msix_wstrb),
|
||||
.m_axil_wvalid(axil_msix_wvalid),
|
||||
.m_axil_wready(axil_msix_wready),
|
||||
.m_axil_bresp(axil_msix_bresp),
|
||||
.m_axil_bvalid(axil_msix_bvalid),
|
||||
.m_axil_bready(axil_msix_bready),
|
||||
.m_axil_araddr(axil_msix_araddr),
|
||||
.m_axil_arprot(axil_msix_arprot),
|
||||
.m_axil_arvalid(axil_msix_arvalid),
|
||||
.m_axil_arready(axil_msix_arready),
|
||||
.m_axil_rdata(axil_msix_rdata),
|
||||
.m_axil_rresp(axil_msix_rresp),
|
||||
.m_axil_rvalid(axil_msix_rvalid),
|
||||
.m_axil_rready(axil_msix_rready),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.completer_id({bus_num, 5'd0, 3'd0}),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.status_error_cor(status_error_cor_int[2]),
|
||||
.status_error_uncor(status_error_uncor_int[2])
|
||||
);
|
||||
|
||||
dma_if_pcie #(
|
||||
.TLP_DATA_WIDTH(TLP_DATA_WIDTH),
|
||||
.TLP_STRB_WIDTH(TLP_STRB_WIDTH),
|
||||
@ -789,12 +918,73 @@ dma_if_pcie_inst (
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.status_error_cor(status_error_cor_int[2]),
|
||||
.status_error_uncor(status_error_uncor_int[2])
|
||||
.status_error_cor(status_error_cor_int[3]),
|
||||
.status_error_uncor(status_error_uncor_int[3])
|
||||
);
|
||||
|
||||
pcie_msix #(
|
||||
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH),
|
||||
.AXIL_DATA_WIDTH(AXIL_MSIX_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(AXIL_MSIX_ADDR_WIDTH),
|
||||
.AXIL_STRB_WIDTH(AXIL_MSIX_STRB_WIDTH),
|
||||
.TLP_HDR_WIDTH(TLP_HDR_WIDTH),
|
||||
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR)
|
||||
)
|
||||
pcie_msix_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
/*
|
||||
* AXI lite interface for MSI-X tables
|
||||
*/
|
||||
.s_axil_awaddr(axil_msix_awaddr),
|
||||
.s_axil_awprot(axil_msix_awprot),
|
||||
.s_axil_awvalid(axil_msix_awvalid),
|
||||
.s_axil_awready(axil_msix_awready),
|
||||
.s_axil_wdata(axil_msix_wdata),
|
||||
.s_axil_wstrb(axil_msix_wstrb),
|
||||
.s_axil_wvalid(axil_msix_wvalid),
|
||||
.s_axil_wready(axil_msix_wready),
|
||||
.s_axil_bresp(axil_msix_bresp),
|
||||
.s_axil_bvalid(axil_msix_bvalid),
|
||||
.s_axil_bready(axil_msix_bready),
|
||||
.s_axil_araddr(axil_msix_araddr),
|
||||
.s_axil_arprot(axil_msix_arprot),
|
||||
.s_axil_arvalid(axil_msix_arvalid),
|
||||
.s_axil_arready(axil_msix_arready),
|
||||
.s_axil_rdata(axil_msix_rdata),
|
||||
.s_axil_rresp(axil_msix_rresp),
|
||||
.s_axil_rvalid(axil_msix_rvalid),
|
||||
.s_axil_rready(axil_msix_rready),
|
||||
|
||||
/*
|
||||
* Interrupt request input
|
||||
*/
|
||||
.irq_index(irq_index),
|
||||
.irq_valid(irq_valid),
|
||||
.irq_ready(irq_ready),
|
||||
|
||||
/*
|
||||
* Memory write TLP output
|
||||
*/
|
||||
.tx_wr_req_tlp_data(tx_msix_wr_req_tlp_data),
|
||||
.tx_wr_req_tlp_strb(tx_msix_wr_req_tlp_strb),
|
||||
.tx_wr_req_tlp_hdr(tx_msix_wr_req_tlp_hdr),
|
||||
.tx_wr_req_tlp_valid(tx_msix_wr_req_tlp_valid),
|
||||
.tx_wr_req_tlp_sop(tx_msix_wr_req_tlp_sop),
|
||||
.tx_wr_req_tlp_eop(tx_msix_wr_req_tlp_eop),
|
||||
.tx_wr_req_tlp_ready(tx_msix_wr_req_tlp_ready),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
.requester_id({bus_num, 5'd0, 3'd0}),
|
||||
.msix_enable(msix_enable),
|
||||
.msix_mask(msix_mask)
|
||||
);
|
||||
|
||||
pulse_merge #(
|
||||
.INPUT_WIDTH(3),
|
||||
.INPUT_WIDTH(4),
|
||||
.COUNT_WIDTH(4)
|
||||
)
|
||||
status_error_cor_pm_inst (
|
||||
@ -807,7 +997,7 @@ status_error_cor_pm_inst (
|
||||
);
|
||||
|
||||
pulse_merge #(
|
||||
.INPUT_WIDTH(3),
|
||||
.INPUT_WIDTH(4),
|
||||
.COUNT_WIDTH(4)
|
||||
)
|
||||
status_error_uncor_pm_inst (
|
||||
@ -820,9 +1010,9 @@ status_error_uncor_pm_inst (
|
||||
);
|
||||
|
||||
example_core #(
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(AXIL_ADDR_WIDTH),
|
||||
.AXIL_STRB_WIDTH(AXIL_STRB_WIDTH),
|
||||
.AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
|
||||
.AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
|
||||
.DMA_ADDR_WIDTH(PCIE_ADDR_WIDTH),
|
||||
.DMA_IMM_ENABLE(IMM_ENABLE),
|
||||
.DMA_IMM_WIDTH(IMM_WIDTH),
|
||||
@ -833,7 +1023,8 @@ example_core #(
|
||||
.RAM_SEG_COUNT(RAM_SEG_COUNT),
|
||||
.RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
|
||||
.RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
|
||||
.RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH)
|
||||
.RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
|
||||
.IRQ_INDEX_WIDTH(IRQ_INDEX_WIDTH)
|
||||
)
|
||||
core_inst (
|
||||
.clk(clk),
|
||||
@ -919,9 +1110,11 @@ core_inst (
|
||||
.ram_wr_done(ram_wr_done),
|
||||
|
||||
/*
|
||||
* MSI request outputs
|
||||
* Interrupt request output
|
||||
*/
|
||||
.msi_irq(msi_irq)
|
||||
.irq_index(irq_index),
|
||||
.irq_valid(irq_valid),
|
||||
.irq_ready(irq_ready)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -66,7 +66,9 @@ module example_core_pcie_s10 #
|
||||
// BAR0 aperture (log2 size)
|
||||
parameter BAR0_APERTURE = 24,
|
||||
// BAR2 aperture (log2 size)
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
// BAR4 aperture (log2 size)
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
@ -110,15 +112,6 @@ module example_core_pcie_s10 #
|
||||
input wire [SEG_COUNT*2-1:0] tx_cdts_type,
|
||||
input wire [SEG_COUNT*1-1:0] tx_cdts_data_value,
|
||||
|
||||
/*
|
||||
* H-Tile/L-Tile MSI interrupt interface
|
||||
*/
|
||||
output wire app_msi_req,
|
||||
input wire app_msi_ack,
|
||||
output wire [2:0] app_msi_tc,
|
||||
output wire [4:0] app_msi_num,
|
||||
output wire [1:0] app_msi_func_num,
|
||||
|
||||
/*
|
||||
* H-Tile/L-Tile configuration interface
|
||||
*/
|
||||
@ -135,7 +128,6 @@ parameter TX_SEQ_NUM_COUNT = SEG_COUNT;
|
||||
parameter PF_COUNT = 1;
|
||||
parameter VF_COUNT = 0;
|
||||
parameter F_COUNT = PF_COUNT+VF_COUNT;
|
||||
parameter MSI_COUNT = 32;
|
||||
|
||||
wire [TLP_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
|
||||
wire [TLP_STRB_WIDTH-1:0] pcie_rx_req_tlp_strb;
|
||||
@ -186,6 +178,14 @@ wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
|
||||
wire pcie_tx_cpl_tlp_ready;
|
||||
|
||||
wire [31:0] pcie_tx_msix_wr_req_tlp_data;
|
||||
wire pcie_tx_msix_wr_req_tlp_strb;
|
||||
wire [TLP_HDR_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_hdr;
|
||||
wire pcie_tx_msix_wr_req_tlp_valid;
|
||||
wire pcie_tx_msix_wr_req_tlp_sop;
|
||||
wire pcie_tx_msix_wr_req_tlp_eop;
|
||||
wire pcie_tx_msix_wr_req_tlp_ready;
|
||||
|
||||
wire [7:0] pcie_tx_fc_ph_av;
|
||||
wire [11:0] pcie_tx_fc_pd_av;
|
||||
wire [7:0] pcie_tx_fc_nph_av;
|
||||
@ -194,8 +194,8 @@ wire ext_tag_enable;
|
||||
wire [7:0] bus_num;
|
||||
wire [2:0] max_read_request_size;
|
||||
wire [2:0] max_payload_size;
|
||||
|
||||
wire [MSI_COUNT-1:0] msi_irq;
|
||||
wire msix_enable;
|
||||
wire msix_mask;
|
||||
|
||||
pcie_s10_if #(
|
||||
.SEG_COUNT(SEG_COUNT),
|
||||
@ -211,8 +211,7 @@ pcie_s10_if #(
|
||||
.VF_COUNT(0),
|
||||
.F_COUNT(PF_COUNT+VF_COUNT),
|
||||
.IO_BAR_INDEX(5),
|
||||
.MSI_ENABLE(1),
|
||||
.MSI_COUNT(MSI_COUNT)
|
||||
.MSI_ENABLE(0)
|
||||
)
|
||||
pcie_s10_if_inst (
|
||||
.clk(clk),
|
||||
@ -259,11 +258,11 @@ pcie_s10_if_inst (
|
||||
/*
|
||||
* H-Tile/L-Tile MSI interrupt interface
|
||||
*/
|
||||
.app_msi_req(app_msi_req),
|
||||
.app_msi_ack(app_msi_ack),
|
||||
.app_msi_tc(app_msi_tc),
|
||||
.app_msi_num(app_msi_num),
|
||||
.app_msi_func_num(app_msi_func_num),
|
||||
.app_msi_req(),
|
||||
.app_msi_ack(1'b0),
|
||||
.app_msi_tc(),
|
||||
.app_msi_num(),
|
||||
.app_msi_func_num(),
|
||||
|
||||
/*
|
||||
* H-Tile/L-Tile configuration interface
|
||||
@ -345,13 +344,13 @@ pcie_s10_if_inst (
|
||||
/*
|
||||
* TLP input (write request from MSI)
|
||||
*/
|
||||
.tx_msi_wr_req_tlp_data(0),
|
||||
.tx_msi_wr_req_tlp_strb(0),
|
||||
.tx_msi_wr_req_tlp_hdr(0),
|
||||
.tx_msi_wr_req_tlp_valid(0),
|
||||
.tx_msi_wr_req_tlp_sop(0),
|
||||
.tx_msi_wr_req_tlp_eop(0),
|
||||
.tx_msi_wr_req_tlp_ready(),
|
||||
.tx_msi_wr_req_tlp_data(pcie_tx_msix_wr_req_tlp_data),
|
||||
.tx_msi_wr_req_tlp_strb(pcie_tx_msix_wr_req_tlp_strb),
|
||||
.tx_msi_wr_req_tlp_hdr(pcie_tx_msix_wr_req_tlp_hdr),
|
||||
.tx_msi_wr_req_tlp_valid(pcie_tx_msix_wr_req_tlp_valid),
|
||||
.tx_msi_wr_req_tlp_sop(pcie_tx_msix_wr_req_tlp_sop),
|
||||
.tx_msi_wr_req_tlp_eop(pcie_tx_msix_wr_req_tlp_eop),
|
||||
.tx_msi_wr_req_tlp_ready(pcie_tx_msix_wr_req_tlp_ready),
|
||||
|
||||
/*
|
||||
* Flow control
|
||||
@ -370,13 +369,13 @@ pcie_s10_if_inst (
|
||||
.bus_num(bus_num),
|
||||
.max_read_request_size(max_read_request_size),
|
||||
.max_payload_size(max_payload_size),
|
||||
.msix_enable(),
|
||||
.msix_mask(),
|
||||
.msix_enable(msix_enable),
|
||||
.msix_mask(msix_mask),
|
||||
|
||||
/*
|
||||
* MSI request inputs
|
||||
*/
|
||||
.msi_irq(msi_irq)
|
||||
.msi_irq(0)
|
||||
);
|
||||
|
||||
example_core_pcie #(
|
||||
@ -399,7 +398,8 @@ example_core_pcie #(
|
||||
.TLP_FORCE_64_BIT_ADDR(0),
|
||||
.CHECK_BUS_NUMBER(1),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
core_pcie_inst (
|
||||
.clk(clk),
|
||||
@ -478,6 +478,17 @@ core_pcie_inst (
|
||||
.pcie_tx_fc_pd_av(pcie_tx_fc_pd_av),
|
||||
.pcie_tx_fc_nph_av(pcie_tx_fc_nph_av),
|
||||
|
||||
/*
|
||||
* TLP output (MSI-X write request)
|
||||
*/
|
||||
.tx_msix_wr_req_tlp_data(pcie_tx_msix_wr_req_tlp_data),
|
||||
.tx_msix_wr_req_tlp_strb(pcie_tx_msix_wr_req_tlp_strb),
|
||||
.tx_msix_wr_req_tlp_hdr(pcie_tx_msix_wr_req_tlp_hdr),
|
||||
.tx_msix_wr_req_tlp_valid(pcie_tx_msix_wr_req_tlp_valid),
|
||||
.tx_msix_wr_req_tlp_sop(pcie_tx_msix_wr_req_tlp_sop),
|
||||
.tx_msix_wr_req_tlp_eop(pcie_tx_msix_wr_req_tlp_eop),
|
||||
.tx_msix_wr_req_tlp_ready(pcie_tx_msix_wr_req_tlp_ready),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
@ -485,17 +496,14 @@ core_pcie_inst (
|
||||
.ext_tag_enable(ext_tag_enable),
|
||||
.max_read_request_size(max_read_request_size),
|
||||
.max_payload_size(max_payload_size),
|
||||
.msix_enable(msix_enable),
|
||||
.msix_mask(msix_mask),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.status_error_cor(),
|
||||
.status_error_uncor(),
|
||||
|
||||
/*
|
||||
* MSI request outputs
|
||||
*/
|
||||
.msi_irq(msi_irq)
|
||||
.status_error_uncor()
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -78,7 +78,9 @@ module example_core_pcie_us #
|
||||
// BAR0 aperture (log2 size)
|
||||
parameter BAR0_APERTURE = 24,
|
||||
// BAR2 aperture (log2 size)
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
// BAR4 aperture (log2 size)
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
@ -158,22 +160,17 @@ module example_core_pcie_us #
|
||||
/*
|
||||
* Interrupt interface
|
||||
*/
|
||||
input wire [3:0] cfg_interrupt_msi_enable,
|
||||
input wire [7:0] cfg_interrupt_msi_vf_enable,
|
||||
input wire [11:0] cfg_interrupt_msi_mmenable,
|
||||
input wire cfg_interrupt_msi_mask_update,
|
||||
input wire [31:0] cfg_interrupt_msi_data,
|
||||
output wire [3:0] cfg_interrupt_msi_select,
|
||||
output wire [31:0] cfg_interrupt_msi_int,
|
||||
output wire [31:0] cfg_interrupt_msi_pending_status,
|
||||
output wire cfg_interrupt_msi_pending_status_data_enable,
|
||||
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
|
||||
input wire cfg_interrupt_msi_sent,
|
||||
input wire cfg_interrupt_msi_fail,
|
||||
output wire [2:0] cfg_interrupt_msi_attr,
|
||||
output wire cfg_interrupt_msi_tph_present,
|
||||
output wire [1:0] cfg_interrupt_msi_tph_type,
|
||||
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
|
||||
input wire [3:0] cfg_interrupt_msix_enable,
|
||||
input wire [3:0] cfg_interrupt_msix_mask,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_enable,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_mask,
|
||||
output wire [63:0] cfg_interrupt_msix_address,
|
||||
output wire [31:0] cfg_interrupt_msix_data,
|
||||
output wire cfg_interrupt_msix_int,
|
||||
output wire [1:0] cfg_interrupt_msix_vec_pending,
|
||||
input wire cfg_interrupt_msix_vec_pending_status,
|
||||
input wire cfg_interrupt_msix_sent,
|
||||
input wire cfg_interrupt_msix_fail,
|
||||
output wire [7:0] cfg_interrupt_msi_function_number,
|
||||
|
||||
/*
|
||||
@ -199,7 +196,6 @@ parameter TX_SEQ_NUM_ENABLE = RQ_SEQ_NUM_ENABLE;
|
||||
parameter PF_COUNT = 1;
|
||||
parameter VF_COUNT = 0;
|
||||
parameter F_COUNT = PF_COUNT+VF_COUNT;
|
||||
parameter MSI_COUNT = 32;
|
||||
|
||||
wire [TLP_DATA_WIDTH-1:0] pcie_rx_req_tlp_data;
|
||||
wire [TLP_STRB_WIDTH-1:0] pcie_rx_req_tlp_strb;
|
||||
@ -250,12 +246,21 @@ wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_sop;
|
||||
wire [TLP_SEG_COUNT-1:0] pcie_tx_cpl_tlp_eop;
|
||||
wire pcie_tx_cpl_tlp_ready;
|
||||
|
||||
wire [31:0] pcie_tx_msix_wr_req_tlp_data;
|
||||
wire pcie_tx_msix_wr_req_tlp_strb;
|
||||
wire [TLP_HDR_WIDTH-1:0] pcie_tx_msix_wr_req_tlp_hdr;
|
||||
wire pcie_tx_msix_wr_req_tlp_valid;
|
||||
wire pcie_tx_msix_wr_req_tlp_sop;
|
||||
wire pcie_tx_msix_wr_req_tlp_eop;
|
||||
wire pcie_tx_msix_wr_req_tlp_ready;
|
||||
|
||||
wire [7:0] pcie_tx_fc_ph_av;
|
||||
wire [11:0] pcie_tx_fc_pd_av;
|
||||
wire [7:0] pcie_tx_fc_nph_av;
|
||||
|
||||
wire ext_tag_enable;
|
||||
wire [MSI_COUNT-1:0] msi_irq;
|
||||
wire msix_enable;
|
||||
wire msix_mask;
|
||||
|
||||
pcie_us_if #(
|
||||
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
|
||||
@ -281,9 +286,8 @@ pcie_us_if #(
|
||||
.READ_EXT_TAG_ENABLE(1),
|
||||
.READ_MAX_READ_REQ_SIZE(1),
|
||||
.READ_MAX_PAYLOAD_SIZE(1),
|
||||
.MSIX_ENABLE(0),
|
||||
.MSI_ENABLE(1),
|
||||
.MSI_COUNT(MSI_COUNT)
|
||||
.MSIX_ENABLE(1),
|
||||
.MSI_ENABLE(0)
|
||||
)
|
||||
pcie_us_if_inst (
|
||||
.clk(clk),
|
||||
@ -363,22 +367,33 @@ pcie_us_if_inst (
|
||||
/*
|
||||
* Interrupt interface
|
||||
*/
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(cfg_interrupt_msi_vf_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_enable(),
|
||||
.cfg_interrupt_msi_vf_enable(),
|
||||
.cfg_interrupt_msi_mmenable(),
|
||||
.cfg_interrupt_msi_mask_update(),
|
||||
.cfg_interrupt_msi_data(),
|
||||
.cfg_interrupt_msi_select(),
|
||||
.cfg_interrupt_msi_int(),
|
||||
.cfg_interrupt_msi_pending_status(),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(),
|
||||
.cfg_interrupt_msi_pending_status_function_num(),
|
||||
.cfg_interrupt_msi_sent(),
|
||||
.cfg_interrupt_msi_fail(),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_attr(),
|
||||
.cfg_interrupt_msi_tph_present(),
|
||||
.cfg_interrupt_msi_tph_type(),
|
||||
.cfg_interrupt_msi_tph_st_tag(),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
@ -454,13 +469,13 @@ pcie_us_if_inst (
|
||||
/*
|
||||
* TLP input (write request from MSI-X)
|
||||
*/
|
||||
.tx_msix_wr_req_tlp_data(0),
|
||||
.tx_msix_wr_req_tlp_strb(0),
|
||||
.tx_msix_wr_req_tlp_hdr(0),
|
||||
.tx_msix_wr_req_tlp_valid(0),
|
||||
.tx_msix_wr_req_tlp_sop(0),
|
||||
.tx_msix_wr_req_tlp_eop(0),
|
||||
.tx_msix_wr_req_tlp_ready(),
|
||||
.tx_msix_wr_req_tlp_data(pcie_tx_msix_wr_req_tlp_data),
|
||||
.tx_msix_wr_req_tlp_strb(pcie_tx_msix_wr_req_tlp_strb),
|
||||
.tx_msix_wr_req_tlp_hdr(pcie_tx_msix_wr_req_tlp_hdr),
|
||||
.tx_msix_wr_req_tlp_valid(pcie_tx_msix_wr_req_tlp_valid),
|
||||
.tx_msix_wr_req_tlp_sop(pcie_tx_msix_wr_req_tlp_sop),
|
||||
.tx_msix_wr_req_tlp_eop(pcie_tx_msix_wr_req_tlp_eop),
|
||||
.tx_msix_wr_req_tlp_ready(pcie_tx_msix_wr_req_tlp_ready),
|
||||
|
||||
/*
|
||||
* Flow control
|
||||
@ -478,11 +493,13 @@ pcie_us_if_inst (
|
||||
.ext_tag_enable(ext_tag_enable),
|
||||
.max_read_request_size(),
|
||||
.max_payload_size(),
|
||||
.msix_enable(msix_enable),
|
||||
.msix_mask(msix_mask),
|
||||
|
||||
/*
|
||||
* MSI request inputs
|
||||
*/
|
||||
.msi_irq(msi_irq)
|
||||
.msi_irq(0)
|
||||
);
|
||||
|
||||
example_core_pcie #(
|
||||
@ -505,7 +522,8 @@ example_core_pcie #(
|
||||
.TLP_FORCE_64_BIT_ADDR(1),
|
||||
.CHECK_BUS_NUMBER(0),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
core_pcie_inst (
|
||||
.clk(clk),
|
||||
@ -584,6 +602,17 @@ core_pcie_inst (
|
||||
.pcie_tx_fc_pd_av(pcie_tx_fc_pd_av),
|
||||
.pcie_tx_fc_nph_av(pcie_tx_fc_nph_av),
|
||||
|
||||
/*
|
||||
* TLP output (MSI-X write request)
|
||||
*/
|
||||
.tx_msix_wr_req_tlp_data(pcie_tx_msix_wr_req_tlp_data),
|
||||
.tx_msix_wr_req_tlp_strb(pcie_tx_msix_wr_req_tlp_strb),
|
||||
.tx_msix_wr_req_tlp_hdr(pcie_tx_msix_wr_req_tlp_hdr),
|
||||
.tx_msix_wr_req_tlp_valid(pcie_tx_msix_wr_req_tlp_valid),
|
||||
.tx_msix_wr_req_tlp_sop(pcie_tx_msix_wr_req_tlp_sop),
|
||||
.tx_msix_wr_req_tlp_eop(pcie_tx_msix_wr_req_tlp_eop),
|
||||
.tx_msix_wr_req_tlp_ready(pcie_tx_msix_wr_req_tlp_ready),
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
@ -591,17 +620,14 @@ core_pcie_inst (
|
||||
.ext_tag_enable(ext_tag_enable),
|
||||
.max_read_request_size(cfg_max_read_req),
|
||||
.max_payload_size(cfg_max_payload),
|
||||
.msix_enable(msix_enable),
|
||||
.msix_mask(msix_mask),
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
.status_error_cor(status_error_cor),
|
||||
.status_error_uncor(status_error_uncor),
|
||||
|
||||
/*
|
||||
* MSI request outputs
|
||||
*/
|
||||
.msi_irq(msi_irq)
|
||||
.status_error_uncor(status_error_uncor)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -39,11 +39,11 @@ VERILOG_SOURCES += ../../../../rtl/pcie_axi_master_wr.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_tlp_demux_bar.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../../../rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../../../rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../../../rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../../../rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../../../rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../../../rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pulse_merge.v
|
||||
|
||||
@ -68,6 +68,7 @@ export PARAM_TLP_FORCE_64_BIT_ADDR ?= 0
|
||||
export PARAM_CHECK_BUS_NUMBER ?= 1
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -92,6 +93,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).CHECK_BUS_NUMBER=$(PARAM_CHECK_BUS_NUMBER)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -120,6 +122,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GCHECK_BUS_NUMBER=$(PARAM_CHECK_BUS_NUMBER)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -60,6 +60,45 @@ class TB(object):
|
||||
self.rc = RootComplex()
|
||||
|
||||
self.dev = PcieIfDevice(
|
||||
# configuration options
|
||||
force_64bit_addr=False,
|
||||
pf_count=1,
|
||||
max_payload_size=512,
|
||||
enable_extended_tag=True,
|
||||
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
pf1_msix_table_offset=0x00000000,
|
||||
pf1_msix_pba_bir=0,
|
||||
pf1_msix_pba_offset=0x00000000,
|
||||
pf2_msix_enable=False,
|
||||
pf2_msix_table_size=0,
|
||||
pf2_msix_table_bir=0,
|
||||
pf2_msix_table_offset=0x00000000,
|
||||
pf2_msix_pba_bir=0,
|
||||
pf2_msix_pba_offset=0x00000000,
|
||||
pf3_msix_enable=False,
|
||||
pf3_msix_table_size=0,
|
||||
pf3_msix_table_bir=0,
|
||||
pf3_msix_table_offset=0x00000000,
|
||||
pf3_msix_pba_bir=0,
|
||||
pf3_msix_pba_offset=0x00000000,
|
||||
|
||||
clk=dut.clk,
|
||||
rst=dut.rst,
|
||||
|
||||
@ -77,6 +116,8 @@ class TB(object):
|
||||
|
||||
rx_cpl_tlp_bus=PcieIfRxBus.from_prefix(dut, "rx_cpl_tlp"),
|
||||
|
||||
tx_msi_wr_req_tlp_bus=PcieIfTxBus.from_prefix(dut, "tx_msix_wr_req_tlp"),
|
||||
|
||||
cfg_max_payload=dut.max_payload_size,
|
||||
cfg_max_read_req=dut.max_read_request_size,
|
||||
cfg_ext_tag_enable=dut.ext_tag_enable,
|
||||
@ -90,13 +131,15 @@ class TB(object):
|
||||
|
||||
self.rc.make_port().connect(self.dev)
|
||||
|
||||
self.dev.functions[0].msi_multiple_message_capable = 5
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.axil_msix_awaddr))
|
||||
|
||||
dut.bus_num.setimmediatevalue(0)
|
||||
|
||||
dut.msix_enable.setimmediatevalue(0)
|
||||
dut.msix_mask.setimmediatevalue(0)
|
||||
|
||||
# monitor error outputs
|
||||
self.status_error_cor_asserted = False
|
||||
self.status_error_uncor_asserted = False
|
||||
@ -142,11 +185,14 @@ async def run_test(dut):
|
||||
dev = tb.rc.find_device(tb.dev.functions[0].pcie_id)
|
||||
await dev.enable_device()
|
||||
await dev.set_master()
|
||||
await dev.alloc_irq_vectors(32, 32)
|
||||
|
||||
dev_pf0_bar0 = dev.bar_window[0]
|
||||
dev_pf0_bar2 = dev.bar_window[2]
|
||||
|
||||
tb.dut.bus_num.value = tb.dev.bus_num
|
||||
tb.dut.msix_enable.value = tb.dev.functions[0].msix_cap.msix_enable
|
||||
tb.dut.msix_mask.value = tb.dev.functions[0].msix_cap.msix_function_mask
|
||||
|
||||
tb.log.info("Test memory write to BAR 2")
|
||||
|
||||
@ -357,11 +403,11 @@ def test_example_core_pcie(request, pcie_data_width):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -388,6 +434,7 @@ def test_example_core_pcie(request, pcie_data_width):
|
||||
parameters['CHECK_BUS_NUMBER'] = 1
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -37,7 +37,6 @@ VERILOG_SOURCES += ../../../../rtl/pcie_s10_if.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_s10_if_rx.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_s10_if_tx.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_s10_cfg.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_s10_msi.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_axi_master_rd.v
|
||||
@ -48,11 +47,11 @@ VERILOG_SOURCES += ../../../../rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_tlp_fifo_mux.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../../../rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../../../rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../../../rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../../../rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../../../rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../../../rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pulse_merge.v
|
||||
|
||||
@ -74,6 +73,7 @@ export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << $(PARAM_TX_SEQ_NUM_WIDTH)
|
||||
export PARAM_WRITE_TX_FC_ENABLE ?= 1
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -95,6 +95,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_TX_FC_ENABLE=$(PARAM_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -120,6 +121,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GWRITE_TX_FC_ENABLE=$(PARAM_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -56,20 +56,20 @@ class TB(object):
|
||||
max_payload_size=1024,
|
||||
enable_extended_tag=True,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -145,11 +145,11 @@ class TB(object):
|
||||
# app_xfer_pending=dut.app_xfer_pending,
|
||||
|
||||
# Interrupt interface
|
||||
app_msi_req=dut.app_msi_req,
|
||||
app_msi_ack=dut.app_msi_ack,
|
||||
app_msi_tc=dut.app_msi_tc,
|
||||
app_msi_num=dut.app_msi_num,
|
||||
app_msi_func_num=dut.app_msi_func_num,
|
||||
# app_msi_req=dut.app_msi_req,
|
||||
# app_msi_ack=dut.app_msi_ack,
|
||||
# app_msi_tc=dut.app_msi_tc,
|
||||
# app_msi_num=dut.app_msi_num,
|
||||
# app_msi_func_num=dut.app_msi_func_num,
|
||||
# app_int_sts=dut.app_int_sts,
|
||||
|
||||
# Error interface
|
||||
@ -196,6 +196,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
async def init(self):
|
||||
|
||||
@ -218,6 +219,7 @@ async def run_test(dut):
|
||||
dev = tb.rc.find_device(tb.dev.functions[0].pcie_id)
|
||||
await dev.enable_device()
|
||||
await dev.set_master()
|
||||
await dev.alloc_irq_vectors(32, 32)
|
||||
|
||||
dev_pf0_bar0 = dev.bar_window[0]
|
||||
dev_pf0_bar2 = dev.bar_window[2]
|
||||
@ -430,7 +432,6 @@ def test_example_core_pcie_s10(request, data_width, l_tile):
|
||||
os.path.join(pcie_rtl_dir, "pcie_s10_if_rx.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_s10_if_tx.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_s10_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_s10_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -441,11 +442,11 @@ def test_example_core_pcie_s10(request, data_width, l_tile):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -469,6 +470,7 @@ def test_example_core_pcie_s10(request, data_width, l_tile):
|
||||
parameters['WRITE_TX_FC_ENABLE'] = 1
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -39,7 +39,6 @@ VERILOG_SOURCES += ../../../../rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_axi_master_rd.v
|
||||
@ -49,11 +48,11 @@ VERILOG_SOURCES += ../../../../rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../../../rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../../../rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../../../rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../../../rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../../../rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../../../rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../../../rtl/pulse_merge.v
|
||||
|
||||
@ -81,6 +80,7 @@ export PARAM_WRITE_TX_LIMIT ?= $(shell echo "$$(( 1 << ($(PARAM_RQ_SEQ_NUM_WIDTH
|
||||
export PARAM_WRITE_TX_FC_ENABLE ?= 1
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -108,6 +108,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_TX_FC_ENABLE=$(PARAM_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -139,6 +140,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GWRITE_TX_FC_ENABLE=$(PARAM_WRITE_TX_FC_ENABLE)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -67,20 +67,20 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -224,32 +224,32 @@ class TB(object):
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||
# cfg_interrupt_msix_enable
|
||||
# cfg_interrupt_msix_mask
|
||||
# cfg_interrupt_msix_vf_enable
|
||||
# cfg_interrupt_msix_vf_mask
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
|
||||
cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
@ -271,6 +271,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
# monitor error outputs
|
||||
self.status_error_cor_asserted = False
|
||||
@ -311,6 +312,7 @@ async def run_test(dut):
|
||||
dev = tb.rc.find_device(tb.dev.functions[0].pcie_id)
|
||||
await dev.enable_device()
|
||||
await dev.set_master()
|
||||
await dev.alloc_irq_vectors(32, 32)
|
||||
|
||||
dev_pf0_bar0 = dev.bar_window[0]
|
||||
dev_pf0_bar2 = dev.bar_window[2]
|
||||
@ -527,7 +529,6 @@ def test_example_core_pcie_us(request, axis_pcie_data_width, straddle):
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -537,11 +538,11 @@ def test_example_core_pcie_us(request, axis_pcie_data_width, straddle):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -571,6 +572,7 @@ def test_example_core_pcie_us(request, axis_pcie_data_width, straddle):
|
||||
parameters['WRITE_TX_FC_ENABLE'] = 1
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
@ -20,7 +20,6 @@ SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -30,11 +29,11 @@ SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_msix.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/arbiter.v
|
||||
SYN_FILES += lib/pcie/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
|
||||
@ -26,8 +26,19 @@ set_property -dict [list \
|
||||
CONFIG.pf0_bar2_type {Memory} \
|
||||
CONFIG.pf0_bar2_scale {Megabytes} \
|
||||
CONFIG.pf0_bar2_size {16} \
|
||||
CONFIG.pf0_msi_enabled {true} \
|
||||
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||
CONFIG.pf0_bar4_64bit {true} \
|
||||
CONFIG.pf0_bar4_prefetchable {true} \
|
||||
CONFIG.pf0_bar4_enabled {true} \
|
||||
CONFIG.pf0_bar4_type {Memory} \
|
||||
CONFIG.pf0_bar4_scale {Kilobytes} \
|
||||
CONFIG.pf0_bar4_size {64} \
|
||||
CONFIG.pf0_msi_enabled {false} \
|
||||
CONFIG.pf0_msix_enabled {true} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_SIZE {01F} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_TABLE_OFFSET {00000000} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_5:4} \
|
||||
CONFIG.PF0_MSIX_CAP_PBA_OFFSET {00008000} \
|
||||
CONFIG.MSI_X_OPTIONS {MSI-X_External} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
CONFIG.en_msi_per_vec_masking {true} \
|
||||
] [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
@ -70,6 +70,7 @@ parameter RQ_SEQ_NUM_ENABLE = 1;
|
||||
parameter PCIE_TAG_COUNT = 256;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
parameter BAR2_APERTURE = 24;
|
||||
parameter BAR4_APERTURE = 16;
|
||||
|
||||
// PCIe
|
||||
wire pcie_user_clk;
|
||||
@ -162,22 +163,18 @@ wire [7:0] cfg_fc_cplh;
|
||||
wire [11:0] cfg_fc_cpld;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
|
||||
wire [3:0] cfg_interrupt_msi_enable;
|
||||
wire [11:0] cfg_interrupt_msi_mmenable;
|
||||
wire cfg_interrupt_msi_mask_update;
|
||||
wire [31:0] cfg_interrupt_msi_data;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire cfg_interrupt_msi_sent;
|
||||
wire cfg_interrupt_msi_fail;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
wire [3:0] cfg_interrupt_msix_enable;
|
||||
wire [3:0] cfg_interrupt_msix_mask;
|
||||
wire [251:0] cfg_interrupt_msix_vf_enable;
|
||||
wire [251:0] cfg_interrupt_msix_vf_mask;
|
||||
wire [63:0] cfg_interrupt_msix_address;
|
||||
wire [31:0] cfg_interrupt_msix_data;
|
||||
wire cfg_interrupt_msix_int;
|
||||
wire [1:0] cfg_interrupt_msix_vec_pending;
|
||||
wire cfg_interrupt_msix_vec_pending_status;
|
||||
wire cfg_interrupt_msix_sent;
|
||||
wire cfg_interrupt_msix_fail;
|
||||
wire [7:0] cfg_interrupt_msi_function_number;
|
||||
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
@ -310,21 +307,17 @@ pcie4_uscale_plus_inst (
|
||||
.cfg_interrupt_int(4'd0),
|
||||
.cfg_interrupt_pending(4'd0),
|
||||
.cfg_interrupt_sent(),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.cfg_pm_aspm_l1_entry_reject(1'b0),
|
||||
@ -400,7 +393,8 @@ fpga_core #(
|
||||
.RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
|
||||
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
core_inst (
|
||||
/*
|
||||
@ -472,21 +466,17 @@ core_inst (
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
.status_error_cor(status_error_cor),
|
||||
|
||||
@ -47,7 +47,8 @@ module fpga_core #
|
||||
parameter RQ_SEQ_NUM_ENABLE = 1,
|
||||
parameter PCIE_TAG_COUNT = 256,
|
||||
parameter BAR0_APERTURE = 24,
|
||||
parameter BAR2_APERTURE = 24
|
||||
parameter BAR2_APERTURE = 24,
|
||||
parameter BAR4_APERTURE = 16
|
||||
)
|
||||
(
|
||||
/*
|
||||
@ -121,22 +122,18 @@ module fpga_core #
|
||||
input wire [11:0] cfg_fc_cpld,
|
||||
output wire [2:0] cfg_fc_sel,
|
||||
|
||||
input wire [3:0] cfg_interrupt_msi_enable,
|
||||
input wire [11:0] cfg_interrupt_msi_mmenable,
|
||||
input wire cfg_interrupt_msi_mask_update,
|
||||
input wire [31:0] cfg_interrupt_msi_data,
|
||||
output wire [3:0] cfg_interrupt_msi_select,
|
||||
output wire [31:0] cfg_interrupt_msi_int,
|
||||
output wire [31:0] cfg_interrupt_msi_pending_status,
|
||||
output wire cfg_interrupt_msi_pending_status_data_enable,
|
||||
output wire [3:0] cfg_interrupt_msi_pending_status_function_num,
|
||||
input wire cfg_interrupt_msi_sent,
|
||||
input wire cfg_interrupt_msi_fail,
|
||||
output wire [2:0] cfg_interrupt_msi_attr,
|
||||
output wire cfg_interrupt_msi_tph_present,
|
||||
output wire [1:0] cfg_interrupt_msi_tph_type,
|
||||
output wire [8:0] cfg_interrupt_msi_tph_st_tag,
|
||||
output wire [3:0] cfg_interrupt_msi_function_number,
|
||||
input wire [3:0] cfg_interrupt_msix_enable,
|
||||
input wire [3:0] cfg_interrupt_msix_mask,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_enable,
|
||||
input wire [251:0] cfg_interrupt_msix_vf_mask,
|
||||
output wire [63:0] cfg_interrupt_msix_address,
|
||||
output wire [31:0] cfg_interrupt_msix_data,
|
||||
output wire cfg_interrupt_msix_int,
|
||||
output wire [1:0] cfg_interrupt_msix_vec_pending,
|
||||
input wire cfg_interrupt_msix_vec_pending_status,
|
||||
input wire cfg_interrupt_msix_sent,
|
||||
input wire cfg_interrupt_msix_fail,
|
||||
output wire [7:0] cfg_interrupt_msi_function_number,
|
||||
|
||||
output wire status_error_cor,
|
||||
output wire status_error_uncor
|
||||
@ -168,7 +165,8 @@ example_core_pcie_us #(
|
||||
.WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
|
||||
.WRITE_TX_FC_ENABLE(1),
|
||||
.BAR0_APERTURE(BAR0_APERTURE),
|
||||
.BAR2_APERTURE(BAR2_APERTURE)
|
||||
.BAR2_APERTURE(BAR2_APERTURE),
|
||||
.BAR4_APERTURE(BAR4_APERTURE)
|
||||
)
|
||||
example_core_pcie_us_inst (
|
||||
.clk(clk),
|
||||
@ -248,22 +246,17 @@ example_core_pcie_us_inst (
|
||||
/*
|
||||
* Interrupt interface
|
||||
*/
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_vf_enable(8'd0),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msix_enable(cfg_interrupt_msix_enable),
|
||||
.cfg_interrupt_msix_mask(cfg_interrupt_msix_mask),
|
||||
.cfg_interrupt_msix_vf_enable(cfg_interrupt_msix_vf_enable),
|
||||
.cfg_interrupt_msix_vf_mask(cfg_interrupt_msix_vf_mask),
|
||||
.cfg_interrupt_msix_address(cfg_interrupt_msix_address),
|
||||
.cfg_interrupt_msix_data(cfg_interrupt_msix_data),
|
||||
.cfg_interrupt_msix_int(cfg_interrupt_msix_int),
|
||||
.cfg_interrupt_msix_vec_pending(cfg_interrupt_msix_vec_pending),
|
||||
.cfg_interrupt_msix_vec_pending_status(cfg_interrupt_msix_vec_pending_status),
|
||||
.cfg_interrupt_msix_sent(cfg_interrupt_msix_sent),
|
||||
.cfg_interrupt_msix_fail(cfg_interrupt_msix_fail),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
|
||||
/*
|
||||
|
||||
@ -40,7 +40,6 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
|
||||
@ -50,11 +49,11 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_fifo_raw.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_msix.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
@ -74,6 +73,7 @@ export PARAM_RQ_SEQ_NUM_ENABLE ?= 1
|
||||
export PARAM_PCIE_TAG_COUNT ?= 64
|
||||
export PARAM_BAR0_APERTURE ?= 24
|
||||
export PARAM_BAR2_APERTURE ?= 24
|
||||
export PARAM_BAR4_APERTURE ?= 16
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
@ -93,6 +93,7 @@ ifeq ($(SIM), icarus)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -P $(TOPLEVEL).BAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
@ -116,6 +117,7 @@ else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
|
||||
COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
|
||||
COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
|
||||
COMPILE_ARGS += -GBAR4_APERTURE=$(PARAM_BAR4_APERTURE)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
|
||||
@ -66,20 +66,20 @@ class TB(object):
|
||||
enable_sriov=False,
|
||||
enable_extended_configuration=False,
|
||||
|
||||
pf0_msi_enable=True,
|
||||
pf0_msi_count=32,
|
||||
pf0_msi_enable=False,
|
||||
pf0_msi_count=1,
|
||||
pf1_msi_enable=False,
|
||||
pf1_msi_count=1,
|
||||
pf2_msi_enable=False,
|
||||
pf2_msi_count=1,
|
||||
pf3_msi_enable=False,
|
||||
pf3_msi_count=1,
|
||||
pf0_msix_enable=False,
|
||||
pf0_msix_table_size=0,
|
||||
pf0_msix_table_bir=0,
|
||||
pf0_msix_enable=True,
|
||||
pf0_msix_table_size=31,
|
||||
pf0_msix_table_bir=4,
|
||||
pf0_msix_table_offset=0x00000000,
|
||||
pf0_msix_pba_bir=0,
|
||||
pf0_msix_pba_offset=0x00000000,
|
||||
pf0_msix_pba_bir=4,
|
||||
pf0_msix_pba_offset=0x00008000,
|
||||
pf1_msix_enable=False,
|
||||
pf1_msix_table_size=0,
|
||||
pf1_msix_table_bir=0,
|
||||
@ -223,33 +223,33 @@ class TB(object):
|
||||
# cfg_interrupt_int
|
||||
# cfg_interrupt_sent
|
||||
# cfg_interrupt_pending
|
||||
cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
|
||||
# cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
|
||||
# cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
|
||||
# cfg_interrupt_msix_enable
|
||||
# cfg_interrupt_msix_mask
|
||||
# cfg_interrupt_msix_vf_enable
|
||||
# cfg_interrupt_msix_vf_mask
|
||||
# cfg_interrupt_msix_address
|
||||
# cfg_interrupt_msix_data
|
||||
# cfg_interrupt_msix_int
|
||||
# cfg_interrupt_msix_vec_pending
|
||||
# cfg_interrupt_msix_vec_pending_status
|
||||
# cfg_interrupt_msix_sent
|
||||
# cfg_interrupt_msix_fail
|
||||
cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
|
||||
# cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
|
||||
# cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
# cfg_interrupt_msi_enable
|
||||
# cfg_interrupt_msi_mmenable
|
||||
# cfg_interrupt_msi_mask_update
|
||||
# cfg_interrupt_msi_data
|
||||
# cfg_interrupt_msi_select
|
||||
# cfg_interrupt_msi_int
|
||||
# cfg_interrupt_msi_pending_status
|
||||
# cfg_interrupt_msi_pending_status_data_enable
|
||||
# cfg_interrupt_msi_pending_status_function_num
|
||||
# cfg_interrupt_msi_sent
|
||||
# cfg_interrupt_msi_fail
|
||||
cfg_interrupt_msix_enable=dut.cfg_interrupt_msix_enable,
|
||||
cfg_interrupt_msix_mask=dut.cfg_interrupt_msix_mask,
|
||||
cfg_interrupt_msix_vf_enable=dut.cfg_interrupt_msix_vf_enable,
|
||||
cfg_interrupt_msix_vf_mask=dut.cfg_interrupt_msix_vf_mask,
|
||||
cfg_interrupt_msix_address=dut.cfg_interrupt_msix_address,
|
||||
cfg_interrupt_msix_data=dut.cfg_interrupt_msix_data,
|
||||
cfg_interrupt_msix_int=dut.cfg_interrupt_msix_int,
|
||||
cfg_interrupt_msix_vec_pending=dut.cfg_interrupt_msix_vec_pending,
|
||||
cfg_interrupt_msix_vec_pending_status=dut.cfg_interrupt_msix_vec_pending_status,
|
||||
cfg_interrupt_msix_sent=dut.cfg_interrupt_msix_sent,
|
||||
cfg_interrupt_msix_fail=dut.cfg_interrupt_msix_fail,
|
||||
# cfg_interrupt_msi_attr
|
||||
# cfg_interrupt_msi_tph_present
|
||||
# cfg_interrupt_msi_tph_type
|
||||
# cfg_interrupt_msi_tph_st_tag
|
||||
cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
# cfg_ext_read_received
|
||||
@ -268,6 +268,7 @@ class TB(object):
|
||||
|
||||
self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr))
|
||||
self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr))
|
||||
self.dev.functions[0].configure_bar(4, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_msix_awaddr))
|
||||
|
||||
async def init(self):
|
||||
|
||||
@ -507,7 +508,6 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
|
||||
@ -517,11 +517,11 @@ def test_fpga_core(request):
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_tlp_fifo_raw.v"),
|
||||
os.path.join(pcie_rtl_dir, "pcie_msix.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
|
||||
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
|
||||
os.path.join(pcie_rtl_dir, "arbiter.v"),
|
||||
os.path.join(pcie_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
|
||||
]
|
||||
@ -543,6 +543,7 @@ def test_fpga_core(request):
|
||||
parameters['PCIE_TAG_COUNT'] = 64
|
||||
parameters['BAR0_APERTURE'] = 24
|
||||
parameters['BAR2_APERTURE'] = 24
|
||||
parameters['BAR4_APERTURE'] = 16
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user