From 3f7a4cee27ce3a419b33fa36c466b63ce6e2e775 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 13 Nov 2023 21:39:42 -0800 Subject: [PATCH] fpga/mqnic: Fix datapath width parameter for 25G Signed-off-by: Alex Forencich --- fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v | 3 ++- fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v | 3 ++- fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v index 86ffff5fa..d1edbd1f0 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga.v @@ -120,6 +120,7 @@ module fpga # parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, // Ethernet interface configuration + parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = MAC_100G ? 0 : (MAC_RSFEC ? 1 : 0), parameter AXIS_ETH_TX_PIPELINE = 0, parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, parameter AXIS_ETH_TX_TS_PIPELINE = 0, @@ -210,7 +211,7 @@ parameter PCIE_TAG_COUNT = 256; // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH; +parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE && !MAC_100G ? 2 : 1); parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; diff --git a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v index c9bfcf588..29b89a662 100644 --- a/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/rtl/fpga.v @@ -120,6 +120,7 @@ module fpga # parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, // Ethernet interface configuration + parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = MAC_100G ? 0 : (MAC_RSFEC ? 1 : 0), parameter AXIS_ETH_TX_PIPELINE = 0, parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, parameter AXIS_ETH_TX_TS_PIPELINE = 0, @@ -203,7 +204,7 @@ parameter PCIE_TAG_COUNT = 256; // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH; +parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE && !MAC_100G ? 2 : 1); parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1; diff --git a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v index 99ae2f127..011ba2c8f 100644 --- a/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/DK_DEV_AGF014EA/fpga_100g/rtl/fpga.v @@ -120,6 +120,7 @@ module fpga # parameter AXIL_APP_CTRL_ADDR_WIDTH = 24, // Ethernet interface configuration + parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = MAC_100G ? 0 : (MAC_RSFEC ? 1 : 0), parameter AXIS_ETH_TX_PIPELINE = 0, parameter AXIS_ETH_TX_FIFO_PIPELINE = 2, parameter AXIS_ETH_TX_TS_PIPELINE = 0, @@ -217,7 +218,7 @@ parameter PCIE_TAG_COUNT = 256; // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; -parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH; +parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE && !MAC_100G ? 2 : 1); parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1; parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;