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Fix clock name

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This commit is contained in:
Alex Forencich 2018-06-11 16:37:34 -07:00
parent fea477db09
commit 415f723edc
2 changed files with 2 additions and 2 deletions
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2
example/VCU108/fpga_10g/fpga.xdc
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@ -9,7 +9,7 @@ set_property CONFIG_VOLTAGE 1.8 [current_design]
# 300 MHz
#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p]
#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n]
#create_clock -period 3.333 -name clk_300_mhz_1 [get_ports clk_300mhz_1_p]
#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]
#set_clock_groups -asynchronous -group [get_clocks clk_300mhz_1 -include_generated_clocks]
#set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p]

2
example/VCU108/fpga_1g/fpga.xdc
View File

@ -9,7 +9,7 @@ set_property CONFIG_VOLTAGE 1.8 [current_design]
# 300 MHz
#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p]
#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n]
#create_clock -period 3.333 -name clk_300_mhz_1 [get_ports clk_300mhz_1_p]
#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]
#set_clock_groups -asynchronous -group [get_clocks clk_300mhz_1 -include_generated_clocks]
#set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p]