From 415f723edc7c9dfc5de82f5822122b2d014a645a Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Mon, 11 Jun 2018 16:37:34 -0700 Subject: [PATCH] Fix clock name --- example/VCU108/fpga_10g/fpga.xdc | 2 +- example/VCU108/fpga_1g/fpga.xdc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/example/VCU108/fpga_10g/fpga.xdc b/example/VCU108/fpga_10g/fpga.xdc index 4ad1c74f3..be8bed33b 100644 --- a/example/VCU108/fpga_10g/fpga.xdc +++ b/example/VCU108/fpga_10g/fpga.xdc @@ -9,7 +9,7 @@ set_property CONFIG_VOLTAGE 1.8 [current_design] # 300 MHz #set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p] #set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n] -#create_clock -period 3.333 -name clk_300_mhz_1 [get_ports clk_300mhz_1_p] +#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] #set_clock_groups -asynchronous -group [get_clocks clk_300mhz_1 -include_generated_clocks] #set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p] diff --git a/example/VCU108/fpga_1g/fpga.xdc b/example/VCU108/fpga_1g/fpga.xdc index b7cc5658a..48a01e1c3 100644 --- a/example/VCU108/fpga_1g/fpga.xdc +++ b/example/VCU108/fpga_1g/fpga.xdc @@ -9,7 +9,7 @@ set_property CONFIG_VOLTAGE 1.8 [current_design] # 300 MHz #set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p] #set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n] -#create_clock -period 3.333 -name clk_300_mhz_1 [get_ports clk_300mhz_1_p] +#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] #set_clock_groups -asynchronous -group [get_clocks clk_300mhz_1 -include_generated_clocks] #set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p]