diff --git a/fpga/lib/eth/rtl/eth_axis_tx.v b/fpga/lib/eth/rtl/eth_axis_tx.v index 55ddca1eb..d6dac7e52 100644 --- a/fpga/lib/eth/rtl/eth_axis_tx.v +++ b/fpga/lib/eth/rtl/eth_axis_tx.v @@ -207,14 +207,15 @@ always @* begin if (send_eth_payload_reg) begin s_eth_payload_axis_tready_next = m_axis_tready_int_early && shift_eth_payload_axis_input_tready; + m_axis_tdata_int = shift_eth_payload_axis_tdata; + m_axis_tkeep_int = shift_eth_payload_axis_tkeep; + m_axis_tlast_int = shift_eth_payload_axis_tlast; + m_axis_tuser_int = shift_eth_payload_axis_tuser; + if ((s_eth_payload_axis_tready && s_eth_payload_axis_tvalid) || (m_axis_tready_int_reg && shift_eth_payload_axis_extra_cycle_reg)) begin transfer_in_save = 1'b1; - m_axis_tdata_int = shift_eth_payload_axis_tdata; - m_axis_tkeep_int = shift_eth_payload_axis_tkeep; m_axis_tvalid_int = 1'b1; - m_axis_tlast_int = shift_eth_payload_axis_tlast; - m_axis_tuser_int = shift_eth_payload_axis_tuser; if (shift_eth_payload_axis_tlast) begin flush_save = 1'b1; diff --git a/fpga/lib/eth/rtl/ip_eth_rx.v b/fpga/lib/eth/rtl/ip_eth_rx.v index 5dd99676f..c8bad790f 100644 --- a/fpga/lib/eth/rtl/ip_eth_rx.v +++ b/fpga/lib/eth/rtl/ip_eth_rx.v @@ -361,13 +361,13 @@ always @* begin s_eth_payload_axis_tready_next = m_ip_payload_axis_tready_int_early; m_ip_payload_axis_tdata_int = s_eth_payload_axis_tdata; - m_ip_payload_axis_tvalid_int = s_eth_payload_axis_tvalid; m_ip_payload_axis_tlast_int = s_eth_payload_axis_tlast; m_ip_payload_axis_tuser_int = s_eth_payload_axis_tuser; if (s_eth_payload_axis_tready && s_eth_payload_axis_tvalid) begin // word transfer through word_count_next = word_count_reg - 16'd1; + m_ip_payload_axis_tvalid_int = 1'b1; if (s_eth_payload_axis_tlast) begin if (word_count_reg > 16'd1) begin // end of frame, but length does not match @@ -395,7 +395,6 @@ always @* begin s_eth_payload_axis_tready_next = m_ip_payload_axis_tready_int_early; m_ip_payload_axis_tdata_int = last_word_data_reg; - m_ip_payload_axis_tvalid_int = s_eth_payload_axis_tvalid && s_eth_payload_axis_tlast; m_ip_payload_axis_tlast_int = s_eth_payload_axis_tlast; m_ip_payload_axis_tuser_int = s_eth_payload_axis_tuser; @@ -403,6 +402,7 @@ always @* begin if (s_eth_payload_axis_tlast) begin s_eth_hdr_ready_next = !m_ip_hdr_valid_next; s_eth_payload_axis_tready_next = 1'b0; + m_ip_payload_axis_tvalid_int = 1'b1; state_next = STATE_IDLE; end else begin state_next = STATE_READ_PAYLOAD_LAST; diff --git a/fpga/lib/eth/rtl/ip_eth_rx_64.v b/fpga/lib/eth/rtl/ip_eth_rx_64.v index 8f0e33425..b33dd67d8 100644 --- a/fpga/lib/eth/rtl/ip_eth_rx_64.v +++ b/fpga/lib/eth/rtl/ip_eth_rx_64.v @@ -388,7 +388,6 @@ always @* begin m_ip_payload_axis_tdata_int = shift_eth_payload_axis_tdata; m_ip_payload_axis_tkeep_int = shift_eth_payload_axis_tkeep; - m_ip_payload_axis_tvalid_int = shift_eth_payload_axis_tvalid; m_ip_payload_axis_tlast_int = shift_eth_payload_axis_tlast; m_ip_payload_axis_tuser_int = shift_eth_payload_axis_tuser; @@ -398,6 +397,7 @@ always @* begin // word transfer through word_count_next = word_count_reg - 16'd8; transfer_in_save = 1'b1; + m_ip_payload_axis_tvalid_int = 1'b1; if (word_count_reg <= 8) begin // have entire payload m_ip_payload_axis_tkeep_int = shift_eth_payload_axis_tkeep & count2keep(word_count_reg); @@ -462,7 +462,6 @@ always @* begin m_ip_payload_axis_tdata_int = last_word_data_reg; m_ip_payload_axis_tkeep_int = last_word_keep_reg; - m_ip_payload_axis_tvalid_int = shift_eth_payload_axis_tvalid && shift_eth_payload_axis_tlast; m_ip_payload_axis_tlast_int = shift_eth_payload_axis_tlast; m_ip_payload_axis_tuser_int = shift_eth_payload_axis_tuser; @@ -472,6 +471,7 @@ always @* begin s_eth_payload_axis_tready_next = 1'b0; flush_save = 1'b1; s_eth_hdr_ready_next = !m_ip_hdr_valid_next; + m_ip_payload_axis_tvalid_int = 1'b1; state_next = STATE_IDLE; end else begin state_next = STATE_READ_PAYLOAD_LAST; diff --git a/fpga/lib/eth/rtl/ip_eth_tx.v b/fpga/lib/eth/rtl/ip_eth_tx.v index 4b52dd49e..bfe0c705c 100644 --- a/fpga/lib/eth/rtl/ip_eth_tx.v +++ b/fpga/lib/eth/rtl/ip_eth_tx.v @@ -298,13 +298,13 @@ always @* begin s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early; m_eth_payload_axis_tdata_int = s_ip_payload_axis_tdata; - m_eth_payload_axis_tvalid_int = s_ip_payload_axis_tvalid; m_eth_payload_axis_tlast_int = s_ip_payload_axis_tlast; m_eth_payload_axis_tuser_int = s_ip_payload_axis_tuser; if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin // word transfer through word_count_next = word_count_reg - 6'd1; + m_eth_payload_axis_tvalid_int = 1'b1; if (s_ip_payload_axis_tlast) begin if (word_count_reg != 16'd1) begin // end of frame, but length does not match @@ -332,7 +332,6 @@ always @* begin s_ip_payload_axis_tready_next = m_eth_payload_axis_tready_int_early; m_eth_payload_axis_tdata_int = last_word_data_reg; - m_eth_payload_axis_tvalid_int = s_ip_payload_axis_tvalid && s_ip_payload_axis_tlast; m_eth_payload_axis_tlast_int = s_ip_payload_axis_tlast; m_eth_payload_axis_tuser_int = s_ip_payload_axis_tuser; @@ -340,6 +339,7 @@ always @* begin if (s_ip_payload_axis_tlast) begin s_ip_hdr_ready_next = !m_eth_hdr_valid_next; s_ip_payload_axis_tready_next = 1'b0; + m_eth_payload_axis_tvalid_int = 1'b1; state_next = STATE_IDLE; end else begin state_next = STATE_WRITE_PAYLOAD_LAST; diff --git a/fpga/lib/eth/rtl/ip_eth_tx_64.v b/fpga/lib/eth/rtl/ip_eth_tx_64.v index f8caa3b41..412447100 100644 --- a/fpga/lib/eth/rtl/ip_eth_tx_64.v +++ b/fpga/lib/eth/rtl/ip_eth_tx_64.v @@ -408,7 +408,6 @@ always @* begin m_eth_payload_axis_tdata_int = shift_ip_payload_axis_tdata; m_eth_payload_axis_tkeep_int = shift_ip_payload_axis_tkeep; - m_eth_payload_axis_tvalid_int = shift_ip_payload_axis_tvalid; m_eth_payload_axis_tlast_int = shift_ip_payload_axis_tlast; m_eth_payload_axis_tuser_int = shift_ip_payload_axis_tuser; @@ -418,6 +417,7 @@ always @* begin // word transfer through word_count_next = word_count_reg - 16'd8; transfer_in_save = 1'b1; + m_eth_payload_axis_tvalid_int = 1'b1; if (word_count_reg <= 8) begin // have entire payload m_eth_payload_axis_tkeep_int = count2keep(word_count_reg); @@ -458,7 +458,6 @@ always @* begin m_eth_payload_axis_tdata_int = last_word_data_reg; m_eth_payload_axis_tkeep_int = last_word_keep_reg; - m_eth_payload_axis_tvalid_int = shift_ip_payload_axis_tvalid && shift_ip_payload_axis_tlast; m_eth_payload_axis_tlast_int = shift_ip_payload_axis_tlast; m_eth_payload_axis_tuser_int = shift_ip_payload_axis_tuser; @@ -467,6 +466,7 @@ always @* begin if (shift_ip_payload_axis_tlast) begin s_ip_hdr_ready_next = !m_eth_hdr_valid_next; s_ip_payload_axis_tready_next = 1'b0; + m_eth_payload_axis_tvalid_int = 1'b1; state_next = STATE_IDLE; end else begin state_next = STATE_WRITE_PAYLOAD_LAST; diff --git a/fpga/lib/eth/rtl/udp_ip_rx.v b/fpga/lib/eth/rtl/udp_ip_rx.v index 9b1a68467..7096e5d4c 100644 --- a/fpga/lib/eth/rtl/udp_ip_rx.v +++ b/fpga/lib/eth/rtl/udp_ip_rx.v @@ -320,13 +320,13 @@ always @* begin s_ip_payload_axis_tready_next = m_udp_payload_axis_tready_int_early; m_udp_payload_axis_tdata_int = s_ip_payload_axis_tdata; - m_udp_payload_axis_tvalid_int = s_ip_payload_axis_tvalid; m_udp_payload_axis_tlast_int = s_ip_payload_axis_tlast; m_udp_payload_axis_tuser_int = s_ip_payload_axis_tuser; if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin // word transfer through word_count_next = word_count_reg - 16'd1; + m_udp_payload_axis_tvalid_int = 1'b1; if (s_ip_payload_axis_tlast) begin if (word_count_reg != 16'd1) begin // end of frame, but length does not match @@ -354,7 +354,6 @@ always @* begin s_ip_payload_axis_tready_next = m_udp_payload_axis_tready_int_early; m_udp_payload_axis_tdata_int = last_word_data_reg; - m_udp_payload_axis_tvalid_int = s_ip_payload_axis_tvalid && s_ip_payload_axis_tlast; m_udp_payload_axis_tlast_int = s_ip_payload_axis_tlast; m_udp_payload_axis_tuser_int = s_ip_payload_axis_tuser; @@ -362,6 +361,7 @@ always @* begin if (s_ip_payload_axis_tlast) begin s_ip_hdr_ready_next = !m_udp_hdr_valid_next; s_ip_payload_axis_tready_next = 1'b0; + m_udp_payload_axis_tvalid_int = 1'b1; state_next = STATE_IDLE; end else begin state_next = STATE_READ_PAYLOAD_LAST; diff --git a/fpga/lib/eth/rtl/udp_ip_rx_64.v b/fpga/lib/eth/rtl/udp_ip_rx_64.v index 65bbc4183..352e91ce7 100644 --- a/fpga/lib/eth/rtl/udp_ip_rx_64.v +++ b/fpga/lib/eth/rtl/udp_ip_rx_64.v @@ -328,7 +328,6 @@ always @* begin m_udp_payload_axis_tdata_int = s_ip_payload_axis_tdata; m_udp_payload_axis_tkeep_int = s_ip_payload_axis_tkeep; - m_udp_payload_axis_tvalid_int = s_ip_payload_axis_tvalid; m_udp_payload_axis_tlast_int = s_ip_payload_axis_tlast; m_udp_payload_axis_tuser_int = s_ip_payload_axis_tuser; @@ -337,6 +336,7 @@ always @* begin if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin // word transfer through word_count_next = word_count_reg - 16'd8; + m_udp_payload_axis_tvalid_int = 1'b1; if (word_count_reg <= 8) begin // have entire payload m_udp_payload_axis_tkeep_int = s_ip_payload_axis_tkeep & count2keep(word_count_reg); @@ -375,7 +375,6 @@ always @* begin m_udp_payload_axis_tdata_int = last_word_data_reg; m_udp_payload_axis_tkeep_int = last_word_keep_reg; - m_udp_payload_axis_tvalid_int = s_ip_payload_axis_tvalid && s_ip_payload_axis_tlast; m_udp_payload_axis_tlast_int = s_ip_payload_axis_tlast; m_udp_payload_axis_tuser_int = s_ip_payload_axis_tuser; @@ -383,6 +382,7 @@ always @* begin if (s_ip_payload_axis_tlast) begin s_ip_hdr_ready_next = !m_udp_hdr_valid_next; s_ip_payload_axis_tready_next = 1'b0; + m_udp_payload_axis_tvalid_int = 1'b1; state_next = STATE_IDLE; end else begin state_next = STATE_READ_PAYLOAD_LAST; diff --git a/fpga/lib/eth/rtl/udp_ip_tx.v b/fpga/lib/eth/rtl/udp_ip_tx.v index 25398e7c2..8224cd831 100644 --- a/fpga/lib/eth/rtl/udp_ip_tx.v +++ b/fpga/lib/eth/rtl/udp_ip_tx.v @@ -289,13 +289,13 @@ always @* begin s_udp_payload_axis_tready_next = m_ip_payload_axis_tready_int_early; m_ip_payload_axis_tdata_int = s_udp_payload_axis_tdata; - m_ip_payload_axis_tvalid_int = s_udp_payload_axis_tvalid; m_ip_payload_axis_tlast_int = s_udp_payload_axis_tlast; m_ip_payload_axis_tuser_int = s_udp_payload_axis_tuser; if (s_udp_payload_axis_tready && s_udp_payload_axis_tvalid) begin // word transfer through word_count_next = word_count_reg - 16'd1; + m_ip_payload_axis_tvalid_int = 1'b1; if (s_udp_payload_axis_tlast) begin if (word_count_reg != 16'd1) begin // end of frame, but length does not match @@ -323,7 +323,6 @@ always @* begin s_udp_payload_axis_tready_next = m_ip_payload_axis_tready_int_early; m_ip_payload_axis_tdata_int = last_word_data_reg; - m_ip_payload_axis_tvalid_int = s_udp_payload_axis_tvalid && s_udp_payload_axis_tlast; m_ip_payload_axis_tlast_int = s_udp_payload_axis_tlast; m_ip_payload_axis_tuser_int = s_udp_payload_axis_tuser; @@ -331,6 +330,7 @@ always @* begin if (s_udp_payload_axis_tlast) begin s_udp_hdr_ready_next = !m_ip_hdr_valid_next; s_udp_payload_axis_tready_next = 1'b0; + m_ip_payload_axis_tvalid_int = 1'b1; state_next = STATE_IDLE; end else begin state_next = STATE_WRITE_PAYLOAD_LAST; diff --git a/fpga/lib/eth/rtl/udp_ip_tx_64.v b/fpga/lib/eth/rtl/udp_ip_tx_64.v index b027e3e7c..c3faa1c07 100644 --- a/fpga/lib/eth/rtl/udp_ip_tx_64.v +++ b/fpga/lib/eth/rtl/udp_ip_tx_64.v @@ -325,7 +325,6 @@ always @* begin m_ip_payload_axis_tdata_int = s_udp_payload_axis_tdata; m_ip_payload_axis_tkeep_int = s_udp_payload_axis_tkeep; - m_ip_payload_axis_tvalid_int = s_udp_payload_axis_tvalid; m_ip_payload_axis_tlast_int = s_udp_payload_axis_tlast; m_ip_payload_axis_tuser_int = s_udp_payload_axis_tuser; @@ -334,6 +333,7 @@ always @* begin if (m_ip_payload_axis_tready_int_reg && s_udp_payload_axis_tvalid) begin // word transfer through word_count_next = word_count_reg - 16'd8; + m_ip_payload_axis_tvalid_int = 1'b1; if (word_count_reg <= 8) begin // have entire payload m_ip_payload_axis_tkeep_int = count2keep(word_count_reg); @@ -372,7 +372,6 @@ always @* begin m_ip_payload_axis_tdata_int = last_word_data_reg; m_ip_payload_axis_tkeep_int = last_word_keep_reg; - m_ip_payload_axis_tvalid_int = s_udp_payload_axis_tvalid && s_udp_payload_axis_tlast; m_ip_payload_axis_tlast_int = s_udp_payload_axis_tlast; m_ip_payload_axis_tuser_int = s_udp_payload_axis_tuser; @@ -380,6 +379,7 @@ always @* begin if (s_udp_payload_axis_tlast) begin s_udp_hdr_ready_next = !m_ip_hdr_valid_next; s_udp_payload_axis_tready_next = 1'b0; + m_ip_payload_axis_tvalid_int = 1'b1; state_next = STATE_IDLE; end else begin state_next = STATE_WRITE_PAYLOAD_LAST; diff --git a/fpga/lib/eth/tox.ini b/fpga/lib/eth/tox.ini index d60284378..cf35010ab 100644 --- a/fpga/lib/eth/tox.ini +++ b/fpga/lib/eth/tox.ini @@ -1,23 +1,25 @@ # tox configuration [tox] -envlist = py39 +envlist = py3 skipsdist = True +minversion = 3.2.0 +requires = virtualenv >= 16.1 [gh-actions] python = - 3.9: py39 + 3.9: py3 [testenv] deps = - pytest - pytest-xdist - pytest-split - cocotb - cocotb-test - cocotbext-axi - cocotbext-eth - scapy - jinja2 + pytest == 6.2.5 + pytest-xdist == 2.4.0 + pytest-split == 0.4.0 + cocotb == 1.6.1 + cocotb-test == 0.2.1 + cocotbext-axi == 0.1.16 + cocotbext-eth == 0.1.18 + scapy == 2.4.5 + jinja2 == 3.0.3 commands = pytest -n auto {posargs}