FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

Update lfsr.v

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-01-15 12:36:03 -08:00
parent cb1dc8fb15
commit 450765187e
1 changed files with 172 additions and 171 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

173
rtl/lfsr.v
View File

@ -1,6 +1,6 @@
/* /*
Copyright (c) 2016-2018 Alex Forencich Copyright (c) 2016-2023 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal of this software and associated documentation files (the "Software"), to deal
@ -184,6 +184,7 @@ Name Configuration Length Polynomial Initial value Note
CRC16-IBM Galois, bit-reverse 16 16'h8005 16'hffff CRC16-IBM Galois, bit-reverse 16 16'h8005 16'hffff
CRC16-CCITT Galois 16 16'h1021 16'h1d0f CRC16-CCITT Galois 16 16'h1021 16'h1d0f
CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output CRC32 Galois, bit-reverse 32 32'h04c11db7 32'hffffffff Ethernet FCS; invert final output
CRC32C Galois, bit-reverse 32 32'h1edc6f41 32'hffffffff iSCSI, Intel CRC32 instruction; invert final output
PRBS6 Fibonacci 6 6'h21 any PRBS6 Fibonacci 6 6'h21 any
PRBS7 Fibonacci 7 7'h41 any PRBS7 Fibonacci 7 7'h41 any
PRBS9 Fibonacci 9 9'h021 any ITU V.52 PRBS9 Fibonacci 9 9'h021 any ITU V.52
@ -200,44 +201,47 @@ PRBS31 Fibonacci, inverted 31 31'h10000001 any
*/ */
reg [LFSR_WIDTH-1:0] lfsr_mask_state[LFSR_WIDTH-1:0]; function [LFSR_WIDTH+DATA_WIDTH-1:0] lfsr_mask(input [31:0] index);
reg [DATA_WIDTH-1:0] lfsr_mask_data[LFSR_WIDTH-1:0]; reg [LFSR_WIDTH-1:0] lfsr_mask_state[LFSR_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] output_mask_state[DATA_WIDTH-1:0]; reg [DATA_WIDTH-1:0] lfsr_mask_data[LFSR_WIDTH-1:0];
reg [DATA_WIDTH-1:0] output_mask_data[DATA_WIDTH-1:0]; reg [LFSR_WIDTH-1:0] output_mask_state[DATA_WIDTH-1:0];
reg [DATA_WIDTH-1:0] output_mask_data[DATA_WIDTH-1:0];
reg [LFSR_WIDTH-1:0] state_val = 0; reg [LFSR_WIDTH-1:0] state_val;
reg [DATA_WIDTH-1:0] data_val = 0; reg [DATA_WIDTH-1:0] data_val;
integer i, j, k; reg [DATA_WIDTH-1:0] data_mask;
initial begin integer i, j;
begin
// init bit masks // init bit masks
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
lfsr_mask_state[i] = {LFSR_WIDTH{1'b0}}; lfsr_mask_state[i] = 0;
lfsr_mask_state[i][i] = 1'b1; lfsr_mask_state[i][i] = 1'b1;
lfsr_mask_data[i] = {DATA_WIDTH{1'b0}}; lfsr_mask_data[i] = 0;
end end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin for (i = 0; i < DATA_WIDTH; i = i + 1) begin
output_mask_state[i] = {LFSR_WIDTH{1'b0}}; output_mask_state[i] = 0;
if (i < LFSR_WIDTH) begin if (i < LFSR_WIDTH) begin
output_mask_state[i][i] = 1'b1; output_mask_state[i][i] = 1'b1;
end end
output_mask_data[i] = {DATA_WIDTH{1'b0}}; output_mask_data[i] = 0;
end end
// simulate shift register // simulate shift register
if (LFSR_CONFIG == "FIBONACCI") begin if (LFSR_CONFIG == "FIBONACCI") begin
// Fibonacci configuration // Fibonacci configuration
for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin for (data_mask = {1'b1, {DATA_WIDTH-1{1'b0}}}; data_mask != 0; data_mask = data_mask >> 1) begin
// determine shift in value // determine shift in value
// current value in last FF, XOR with input data bit (MSB first) // current value in last FF, XOR with input data bit (MSB first)
state_val = lfsr_mask_state[LFSR_WIDTH-1]; state_val = lfsr_mask_state[LFSR_WIDTH-1];
data_val = lfsr_mask_data[LFSR_WIDTH-1]; data_val = lfsr_mask_data[LFSR_WIDTH-1];
data_val = data_val ^ (1 << i); data_val = data_val ^ data_mask;
// add XOR inputs from correct indicies // add XOR inputs from correct indicies
for (j = 1; j < LFSR_WIDTH; j = j + 1) begin for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
if (LFSR_POLY & (1 << j)) begin if ((LFSR_POLY >> j) & 1) begin
state_val = lfsr_mask_state[j-1] ^ state_val; state_val = lfsr_mask_state[j-1] ^ state_val;
data_val = lfsr_mask_data[j-1] ^ data_val; data_val = lfsr_mask_data[j-1] ^ data_val;
end end
@ -257,19 +261,19 @@ initial begin
if (LFSR_FEED_FORWARD) begin if (LFSR_FEED_FORWARD) begin
// only shift in new input data // only shift in new input data
state_val = {LFSR_WIDTH{1'b0}}; state_val = {LFSR_WIDTH{1'b0}};
data_val = 1 << i; data_val = data_mask;
end end
lfsr_mask_state[0] = state_val; lfsr_mask_state[0] = state_val;
lfsr_mask_data[0] = data_val; lfsr_mask_data[0] = data_val;
end end
end else if (LFSR_CONFIG == "GALOIS") begin end else if (LFSR_CONFIG == "GALOIS") begin
// Galois configuration // Galois configuration
for (i = DATA_WIDTH-1; i >= 0; i = i - 1) begin for (data_mask = {1'b1, {DATA_WIDTH-1{1'b0}}}; data_mask != 0; data_mask = data_mask >> 1) begin
// determine shift in value // determine shift in value
// current value in last FF, XOR with input data bit (MSB first) // current value in last FF, XOR with input data bit (MSB first)
state_val = lfsr_mask_state[LFSR_WIDTH-1]; state_val = lfsr_mask_state[LFSR_WIDTH-1];
data_val = lfsr_mask_data[LFSR_WIDTH-1]; data_val = lfsr_mask_data[LFSR_WIDTH-1];
data_val = data_val ^ (1 << i); data_val = data_val ^ data_mask;
// shift // shift
for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin for (j = LFSR_WIDTH-1; j > 0; j = j - 1) begin
@ -285,14 +289,14 @@ initial begin
if (LFSR_FEED_FORWARD) begin if (LFSR_FEED_FORWARD) begin
// only shift in new input data // only shift in new input data
state_val = {LFSR_WIDTH{1'b0}}; state_val = {LFSR_WIDTH{1'b0}};
data_val = 1 << i; data_val = data_mask;
end end
lfsr_mask_state[0] = state_val; lfsr_mask_state[0] = state_val;
lfsr_mask_data[0] = data_val; lfsr_mask_data[0] = data_val;
// add XOR inputs at correct indicies // add XOR inputs at correct indicies
for (j = 1; j < LFSR_WIDTH; j = j + 1) begin for (j = 1; j < LFSR_WIDTH; j = j + 1) begin
if (LFSR_POLY & (1 << j)) begin if ((LFSR_POLY >> j) & 1) begin
lfsr_mask_state[j] = lfsr_mask_state[j] ^ state_val; lfsr_mask_state[j] = lfsr_mask_state[j] ^ state_val;
lfsr_mask_data[j] = lfsr_mask_data[j] ^ data_val; lfsr_mask_data[j] = lfsr_mask_data[j] ^ data_val;
end end
@ -305,56 +309,39 @@ initial begin
// reverse bits if selected // reverse bits if selected
if (REVERSE) begin if (REVERSE) begin
// reverse order if (index < LFSR_WIDTH) begin
for (i = 0; i < LFSR_WIDTH/2; i = i + 1) begin state_val = 0;
state_val = lfsr_mask_state[i];
data_val = lfsr_mask_data[i];
lfsr_mask_state[i] = lfsr_mask_state[LFSR_WIDTH-i-1];
lfsr_mask_data[i] = lfsr_mask_data[LFSR_WIDTH-i-1];
lfsr_mask_state[LFSR_WIDTH-i-1] = state_val;
lfsr_mask_data[LFSR_WIDTH-i-1] = data_val;
end
for (i = 0; i < DATA_WIDTH/2; i = i + 1) begin
state_val = output_mask_state[i];
data_val = output_mask_data[i];
output_mask_state[i] = output_mask_state[DATA_WIDTH-i-1];
output_mask_data[i] = output_mask_data[DATA_WIDTH-i-1];
output_mask_state[DATA_WIDTH-i-1] = state_val;
output_mask_data[DATA_WIDTH-i-1] = data_val;
end
// reverse bits
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_val = 0; state_val[i] = lfsr_mask_state[LFSR_WIDTH-index-1][LFSR_WIDTH-i-1];
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin
state_val[j] = lfsr_mask_state[i][LFSR_WIDTH-j-1];
end end
lfsr_mask_state[i] = state_val;
data_val = 0; data_val = 0;
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
data_val[j] = lfsr_mask_data[i][DATA_WIDTH-j-1];
end
lfsr_mask_data[i] = data_val;
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin for (i = 0; i < DATA_WIDTH; i = i + 1) begin
state_val = 0; data_val[i] = lfsr_mask_data[LFSR_WIDTH-index-1][DATA_WIDTH-i-1];
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin end
state_val[j] = output_mask_state[i][LFSR_WIDTH-j-1]; end else begin
state_val = 0;
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_val[i] = output_mask_state[DATA_WIDTH-(index-LFSR_WIDTH)-1][LFSR_WIDTH-i-1];
end end
output_mask_state[i] = state_val;
data_val = 0; data_val = 0;
for (j = 0; j < DATA_WIDTH; j = j + 1) begin for (i = 0; i < DATA_WIDTH; i = i + 1) begin
data_val[j] = output_mask_data[i][DATA_WIDTH-j-1]; data_val[i] = output_mask_data[DATA_WIDTH-(index-LFSR_WIDTH)-1][DATA_WIDTH-i-1];
end
output_mask_data[i] = data_val;
end end
end end
end else begin
// for (i = 0; i < LFSR_WIDTH; i = i + 1) begin if (index < LFSR_WIDTH) begin
// $display("%b %b", lfsr_mask_state[i], lfsr_mask_data[i]); state_val = lfsr_mask_state[index];
// end data_val = lfsr_mask_data[index];
end end else begin
state_val = output_mask_state[index-LFSR_WIDTH];
data_val = output_mask_data[index-LFSR_WIDTH];
end
end
lfsr_mask = {data_val, state_val};
end
endfunction
// synthesis translate_off // synthesis translate_off
`define SIMULATION `define SIMULATION
@ -380,11 +367,13 @@ if (STYLE_INT == "REDUCTION") begin
// slightly smaller than generated code with Quartus // slightly smaller than generated code with Quartus
// --> better for simulation // --> better for simulation
for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : loop1 for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : lfsr_state
assign state_out[n] = ^{(state_in & lfsr_mask_state[n]), (data_in & lfsr_mask_data[n])}; wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n);
assign state_out[n] = ^({data_in, state_in} & mask);
end end
for (n = 0; n < DATA_WIDTH; n = n + 1) begin : loop2 for (n = 0; n < DATA_WIDTH; n = n + 1) begin : lfsr_data
assign data_out[n] = ^{(state_in & output_mask_state[n]), (data_in & output_mask_data[n])}; wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n+LFSR_WIDTH);
assign data_out[n] = ^({data_in, state_in} & mask);
end end
end else if (STYLE_INT == "LOOP") begin end else if (STYLE_INT == "LOOP") begin
@ -395,36 +384,48 @@ end else if (STYLE_INT == "LOOP") begin
// same size as generated code with Quartus // same size as generated code with Quartus
// --> better for synthesis // --> better for synthesis
reg [LFSR_WIDTH-1:0] state_out_reg = 0; for (n = 0; n < LFSR_WIDTH; n = n + 1) begin : lfsr_state
reg [DATA_WIDTH-1:0] data_out_reg = 0; wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n);
assign state_out = state_out_reg; reg state_reg;
assign data_out = data_out_reg;
assign state_out[n] = state_reg;
integer i;
always @* begin always @* begin
state_reg = 1'b0;
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
state_out_reg[i] = 0; if (mask[i]) begin
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin state_reg = state_reg ^ state_in[i];
if (lfsr_mask_state[i][j]) begin
state_out_reg[i] = state_out_reg[i] ^ state_in[j];
end
end
for (j = 0; j < DATA_WIDTH; j = j + 1) begin
if (lfsr_mask_data[i][j]) begin
state_out_reg[i] = state_out_reg[i] ^ data_in[j];
end
end end
end end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin for (i = 0; i < DATA_WIDTH; i = i + 1) begin
data_out_reg[i] = 0; if (mask[i+LFSR_WIDTH]) begin
for (j = 0; j < LFSR_WIDTH; j = j + 1) begin state_reg = state_reg ^ data_in[i];
if (output_mask_state[i][j]) begin
data_out_reg[i] = data_out_reg[i] ^ state_in[j];
end end
end end
for (j = 0; j < DATA_WIDTH; j = j + 1) begin end
if (output_mask_data[i][j]) begin end
data_out_reg[i] = data_out_reg[i] ^ data_in[j]; for (n = 0; n < DATA_WIDTH; n = n + 1) begin : lfsr_data
wire [LFSR_WIDTH+DATA_WIDTH-1:0] mask = lfsr_mask(n+LFSR_WIDTH);
reg data_reg;
assign data_out[n] = data_reg;
integer i;
always @* begin
data_reg = 1'b0;
for (i = 0; i < LFSR_WIDTH; i = i + 1) begin
if (mask[i]) begin
data_reg = data_reg ^ state_in[i];
end
end
for (i = 0; i < DATA_WIDTH; i = i + 1) begin
if (mask[i+LFSR_WIDTH]) begin
data_reg = data_reg ^ data_in[i];
end end
end end
end end