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Update FPGA ID list and adjust part matching to handle multiple parts with the same JTAG ID

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-11-12 19:09:56 -08:00
parent 2cebcdfb2a
commit 45a6250e43
3 changed files with 36 additions and 9 deletions
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8
lib/mqnic/fpga_id.c
View File

@ -134,10 +134,10 @@ const struct fpga_id fpga_id_list[] =
// Kria SoM (Zynq UltraScale+) // Kria SoM (Zynq UltraScale+)
{FPGA_ID_XCK26, FPGA_ID_MASK_NOVER, "XCK26"}, {FPGA_ID_XCK26, FPGA_ID_MASK_NOVER, "XCK26"},
// Alveo (Virtex UltraScale+) // Alveo (Virtex UltraScale+)
{FPGA_ID_XCU50, FPGA_ID_MASK_NOVER, "XCU50"}, {FPGA_ID_XCU50_XCU55N, FPGA_ID_MASK_NOVER, "XCU50_XCU55N"},
{FPGA_ID_XCU200, FPGA_ID_MASK_NOVER, "XCU200"}, {FPGA_ID_XCU200, FPGA_ID_MASK_NOVER, "XCU200"},
{FPGA_ID_XCU250, FPGA_ID_MASK_NOVER, "XCU250"}, {FPGA_ID_XCU250, FPGA_ID_MASK_NOVER, "XCU250"},
{FPGA_ID_XCU280, FPGA_ID_MASK_NOVER, "XCU280"}, {FPGA_ID_XCU280_XCU55C, FPGA_ID_MASK_NOVER, "XCU280_XCU55C"},
// Versal AI Edge // Versal AI Edge
{FPGA_ID_XCVE1752, FPGA_ID_MASK_NOVER, "XCVE1752"}, {FPGA_ID_XCVE1752, FPGA_ID_MASK_NOVER, "XCVE1752"},
{FPGA_ID_XCVE2002, FPGA_ID_MASK_NOVER, "XCVE2002"}, {FPGA_ID_XCVE2002, FPGA_ID_MASK_NOVER, "XCVE2002"},

8
lib/mqnic/fpga_id.h
View File

@ -134,10 +134,10 @@
// Kria SoM (Zynq UltraScale+) // Kria SoM (Zynq UltraScale+)
#define FPGA_ID_XCK26 0x4A49093 #define FPGA_ID_XCK26 0x4A49093
// Alveo (Virtex UltraScale+) // Alveo (Virtex UltraScale+)
#define FPGA_ID_XCU50 0x4B77093 #define FPGA_ID_XCU50_XCU55N 0x4B77093
#define FPGA_ID_XCU200 0x4B37093 #define FPGA_ID_XCU200 0x4B37093
#define FPGA_ID_XCU250 0x4B57093 #define FPGA_ID_XCU250 0x4B57093
#define FPGA_ID_XCU280 0x4B7D093 #define FPGA_ID_XCU280_XCU55C 0x4B7D093
// Versal AI Edge // Versal AI Edge
#define FPGA_ID_XCVE1752 0x4C9A093 #define FPGA_ID_XCVE1752 0x4C9A093
#define FPGA_ID_XCVE2002 0x4CC1093 #define FPGA_ID_XCVE2002 0x4CC1093

29
utils/mqnic-fw.c
View File

@ -998,7 +998,11 @@ int main(int argc, char *argv[])
{ {
// read bit file // read bit file
struct bitfile *bf; struct bitfile *bf;
char fpga_part[128];
char *ptr1, *ptr2;
int match = 0;
printf("Reading bit file \"%s\"...\n", write_file_name);
bf = bitfile_create_from_file(write_file_name); bf = bitfile_create_from_file(write_file_name);
if (!bf) if (!bf)
@ -1009,7 +1013,29 @@ int main(int argc, char *argv[])
goto err; goto err;
} }
if (stristr(bf->part, dev->fpga_part) != bf->part) printf("Part: %s\n", bf->part);
printf("Date: %s %s\n", bf->date, bf->time);
// check device type
// dev->fpga_part may contain multiple possible device types, separated by underscores
strcpy(fpga_part, dev->fpga_part);
ptr1 = ptr2 = fpga_part;
while (ptr2)
{
ptr2 = strchr(ptr1, '_');
if (ptr2)
*ptr2 = 0;
if (stristr(bf->part, ptr1) == bf->part)
match = 1;
if (ptr2)
ptr1 = ptr2+1;
}
if (!match)
{ {
fprintf(stderr, "Device mismatch (target is %s, file is %s)\n", dev->fpga_part, bf->part); fprintf(stderr, "Device mismatch (target is %s, file is %s)\n", dev->fpga_part, bf->part);
bitfile_close(bf); bitfile_close(bf);
@ -1018,6 +1044,7 @@ int main(int argc, char *argv[])
goto err; goto err;
} }
// check for available space
if (bf->data_len > segment_size) if (bf->data_len > segment_size)
{ {
fprintf(stderr, "File larger than segment (%ld > %ld)\n", bf->data_len, segment_size); fprintf(stderr, "File larger than segment (%ld > %ld)\n", bf->data_len, segment_size);