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Use quad wrappers in VCU108 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
72de6c653a
commit
4618edcd8e
@ -130,22 +130,22 @@ set_input_delay 0 [get_ports {phy_int_n}]
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#set_input_delay 0 [get_ports {phy_mdio}]
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# Bullseye GTY
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#set_property -dict {LOC AR45} [get_ports bullseye_rx0_p] ;# MGTYRXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AR46} [get_ports bullseye_rx0_n] ;# MGTYRXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AT42} [get_ports bullseye_tx0_p] ;# MGTYTXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AT43} [get_ports bullseye_tx0_n] ;# MGTYTXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AN45} [get_ports bullseye_rx1_p] ;# MGTYRXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AN46} [get_ports bullseye_rx1_n] ;# MGTYRXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AP42} [get_ports bullseye_tx1_p] ;# MGTYTXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AP43} [get_ports bullseye_tx1_n] ;# MGTYTXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AL45} [get_ports bullseye_rx2_p] ;# MGTYRXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AL46} [get_ports bullseye_rx2_n] ;# MGTYRXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AM42} [get_ports bullseye_tx2_p] ;# MGTYTXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AM43} [get_ports bullseye_tx2_n] ;# MGTYTXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AJ45} [get_ports bullseye_rx3_p] ;# MGTYRXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AJ46} [get_ports bullseye_rx3_n] ;# MGTYRXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AL40} [get_ports bullseye_tx3_p] ;# MGTYTXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AL41} [get_ports bullseye_tx3_n] ;# MGTYTXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AR45} [get_ports {bullseye_rx_p[0]}] ;# MGTYRXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AR46} [get_ports {bullseye_rx_n[0]}] ;# MGTYRXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AT42} [get_ports {bullseye_tx_p[0]}] ;# MGTYTXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AT43} [get_ports {bullseye_tx_n[0]}] ;# MGTYTXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AN45} [get_ports {bullseye_rx_p[1]}] ;# MGTYRXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AN46} [get_ports {bullseye_rx_n[1]}] ;# MGTYRXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AP42} [get_ports {bullseye_tx_p[1]}] ;# MGTYTXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AP43} [get_ports {bullseye_tx_n[1]}] ;# MGTYTXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AL45} [get_ports {bullseye_rx_p[2]}] ;# MGTYRXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AL46} [get_ports {bullseye_rx_n[2]}] ;# MGTYRXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AM42} [get_ports {bullseye_tx_p[2]}] ;# MGTYTXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AM43} [get_ports {bullseye_tx_n[2]}] ;# MGTYTXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AJ45} [get_ports {bullseye_rx_p[3]}] ;# MGTYRXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AJ46} [get_ports {bullseye_rx_n[3]}] ;# MGTYRXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AL40} [get_ports {bullseye_tx_p[3]}] ;# MGTYTXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AL41} [get_ports {bullseye_tx_n[3]}] ;# MGTYTXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
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#set_property -dict {LOC AK38} [get_ports bullseye_mgt_refclk_0_p] ;# MGTREFCLK0P_126 from J87 P19
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#set_property -dict {LOC AK39} [get_ports bullseye_mgt_refclk_0_n] ;# MGTREFCLK0N_126 from J87 P20
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#set_property -dict {LOC AH38} [get_ports bullseye_mgt_refclk_1_p] ;# MGTREFCLK1P_126 from U32 SI570 via U104 SI53340
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@ -155,22 +155,22 @@ set_input_delay 0 [get_ports {phy_int_n}]
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#create_clock -period 6.4 -name bullseye_mgt_refclk [get_ports bullseye_mgt_refclk_1_p]
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# QSFP28 Interface
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set_property -dict {LOC AG45} [get_ports qsfp_rx1_p] ;# MGTYRXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AG46} [get_ports qsfp_rx1_n] ;# MGTYRXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AK42} [get_ports qsfp_tx1_p] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AK43} [get_ports qsfp_tx1_n] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AF43} [get_ports qsfp_rx2_p] ;# MGTYRXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AF44} [get_ports qsfp_rx2_n] ;# MGTYRXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AJ40} [get_ports qsfp_tx2_p] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AJ41} [get_ports qsfp_tx2_n] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AE45} [get_ports qsfp_rx3_p] ;# MGTYRXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AE46} [get_ports qsfp_rx3_n] ;# MGTYRXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AG40} [get_ports qsfp_tx3_p] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AG41} [get_ports qsfp_tx3_n] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AD43} [get_ports qsfp_rx4_p] ;# MGTYRXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AD44} [get_ports qsfp_rx4_n] ;# MGTYRXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AE40} [get_ports qsfp_tx4_p] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AE41} [get_ports qsfp_tx4_n] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AG45} [get_ports {qsfp_rx_p[0]}] ;# MGTYRXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AG46} [get_ports {qsfp_rx_n[0]}] ;# MGTYRXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AK42} [get_ports {qsfp_tx_p[0]}] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AK43} [get_ports {qsfp_tx_n[0]}] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AF43} [get_ports {qsfp_rx_p[1]}] ;# MGTYRXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AF44} [get_ports {qsfp_rx_n[1]}] ;# MGTYRXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AJ40} [get_ports {qsfp_tx_p[1]}] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AJ41} [get_ports {qsfp_tx_n[1]}] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AE45} [get_ports {qsfp_rx_p[2]}] ;# MGTYRXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AE46} [get_ports {qsfp_rx_n[2]}] ;# MGTYRXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AG40} [get_ports {qsfp_tx_p[2]}] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AG41} [get_ports {qsfp_tx_n[2]}] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AD43} [get_ports {qsfp_rx_p[3]}] ;# MGTYRXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AD44} [get_ports {qsfp_rx_n[3]}] ;# MGTYRXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AE40} [get_ports {qsfp_tx_p[3]}] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AE41} [get_ports {qsfp_tx_n[3]}] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
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set_property -dict {LOC AF38} [get_ports qsfp_mgt_refclk_0_p] ;# MGTREFCLK0P_127 from U32 SI570 via U102 SI53340
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set_property -dict {LOC AF39} [get_ports qsfp_mgt_refclk_0_n] ;# MGTREFCLK0N_127 from U32 SI570 via U102 SI53340
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#set_property -dict {LOC AD38} [get_ports qsfp_mgt_refclk_1_p] ;# MGTREFCLK1P_127 from U57 CKOUT2 SI5328
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@ -192,46 +192,46 @@ set_false_path -from [get_ports {qsfp_modprsl qsfp_intl}]
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set_input_delay 0 [get_ports {qsfp_modprsl qsfp_intl}]
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# CFP2 GTY
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#set_property -dict {LOC J45 } [get_ports cfp2_rx0_p] ;# MGTYRXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
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#set_property -dict {LOC J46 } [get_ports cfp2_rx0_n] ;# MGTYRXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
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#set_property -dict {LOC F42 } [get_ports cfp2_tx0_p] ;# MGTYTXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
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#set_property -dict {LOC F43 } [get_ports cfp2_tx0_n] ;# MGTYTXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
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#set_property -dict {LOC N45 } [get_ports cfp2_rx1_p] ;# MGTYRXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC N46 } [get_ports cfp2_rx1_n] ;# MGTYRXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC K42 } [get_ports cfp2_tx1_p] ;# MGTYTXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC K43 } [get_ports cfp2_tx1_n] ;# MGTYTXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC R45 } [get_ports cfp2_rx2_p] ;# MGTYRXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC R46 } [get_ports cfp2_rx2_n] ;# MGTYRXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC M42 } [get_ports cfp2_tx2_p] ;# MGTYTXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC M43 } [get_ports cfp2_tx2_n] ;# MGTYTXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC L45 } [get_ports cfp2_rx3_p] ;# MGTYRXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
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#set_property -dict {LOC L46 } [get_ports cfp2_rx3_n] ;# MGTYRXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
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#set_property -dict {LOC H42 } [get_ports cfp2_tx3_p] ;# MGTYTXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
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#set_property -dict {LOC H43 } [get_ports cfp2_tx3_n] ;# MGTYTXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
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#set_property -dict {LOC Y43 } [get_ports cfp2_rx4_p] ;# MGTYRXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC Y44 } [get_ports cfp2_rx4_n] ;# MGTYRXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC U40 } [get_ports cfp2_tx4_p] ;# MGTYTXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC U41 } [get_ports cfp2_tx4_n] ;# MGTYTXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC U45 } [get_ports cfp2_rx5_p] ;# MGTYRXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC U46 } [get_ports cfp2_rx5_n] ;# MGTYRXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC P42 } [get_ports cfp2_tx5_p] ;# MGTYTXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC P43 } [get_ports cfp2_tx5_n] ;# MGTYTXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC W45 } [get_ports cfp2_rx6_p] ;# MGTYRXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC W46 } [get_ports cfp2_rx6_n] ;# MGTYRXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC T42 } [get_ports cfp2_tx6_p] ;# MGTYTXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC T43 } [get_ports cfp2_tx6_n] ;# MGTYTXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC AA45} [get_ports cfp2_rx7_p] ;# MGTYRXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC AA46} [get_ports cfp2_rx7_n] ;# MGTYRXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC W40 } [get_ports cfp2_tx7_p] ;# MGTYTXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC W41 } [get_ports cfp2_tx7_n] ;# MGTYTXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC AB43} [get_ports cfp2_rx8_p] ;# MGTYRXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC AB44} [get_ports cfp2_rx8_n] ;# MGTYRXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC AA40} [get_ports cfp2_tx8_p] ;# MGTYTXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC AA41} [get_ports cfp2_tx8_n] ;# MGTYTXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC AC45} [get_ports cfp2_rx9_p] ;# MGTYRXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC AC46} [get_ports cfp2_rx9_n] ;# MGTYRXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC AC40} [get_ports cfp2_tx9_p] ;# MGTYTXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC AC41} [get_ports cfp2_tx9_n] ;# MGTYTXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
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#set_property -dict {LOC J45 } [get_ports {cfp2_rx_p[0]}] ;# MGTYRXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
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#set_property -dict {LOC J46 } [get_ports {cfp2_rx_n[0]}] ;# MGTYRXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
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#set_property -dict {LOC F42 } [get_ports {cfp2_tx_p[0]}] ;# MGTYTXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
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#set_property -dict {LOC F43 } [get_ports {cfp2_tx_n[0]}] ;# MGTYTXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
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#set_property -dict {LOC N45 } [get_ports {cfp2_rx_p[1]}] ;# MGTYRXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC N46 } [get_ports {cfp2_rx_n[1]}] ;# MGTYRXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC K42 } [get_ports {cfp2_tx_p[1]}] ;# MGTYTXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC K43 } [get_ports {cfp2_tx_n[1]}] ;# MGTYTXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
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#set_property -dict {LOC R45 } [get_ports {cfp2_rx_p[2]}] ;# MGTYRXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC R46 } [get_ports {cfp2_rx_n[2]}] ;# MGTYRXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC M42 } [get_ports {cfp2_tx_p[2]}] ;# MGTYTXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC M43 } [get_ports {cfp2_tx_n[2]}] ;# MGTYTXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC L45 } [get_ports {cfp2_rx_p[3]}] ;# MGTYRXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC L46 } [get_ports {cfp2_rx_n[3]}] ;# MGTYRXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC H42 } [get_ports {cfp2_tx_p[3]}] ;# MGTYTXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC H43 } [get_ports {cfp2_tx_n[3]}] ;# MGTYTXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC Y43 } [get_ports {cfp2_rx_p[4]}] ;# MGTYRXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC Y44 } [get_ports {cfp2_rx_n[4]}] ;# MGTYRXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC U40 } [get_ports {cfp2_tx_p[4]}] ;# MGTYTXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC U41 } [get_ports {cfp2_tx_n[4]}] ;# MGTYTXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC U45 } [get_ports {cfp2_rx_p[5]}] ;# MGTYRXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC U46 } [get_ports {cfp2_rx_n[5]}] ;# MGTYRXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC P42 } [get_ports {cfp2_tx_p[5]}] ;# MGTYTXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC P43 } [get_ports {cfp2_tx_n[5]}] ;# MGTYTXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC W45 } [get_ports {cfp2_rx_p[6]}] ;# MGTYRXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC W46 } [get_ports {cfp2_rx_n[6]}] ;# MGTYRXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC T42 } [get_ports {cfp2_tx_p[6]}] ;# MGTYTXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC T43 } [get_ports {cfp2_tx_n[6]}] ;# MGTYTXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC AA45} [get_ports {cfp2_rx_p[7]}] ;# MGTYRXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AA46} [get_ports {cfp2_rx_n[7]}] ;# MGTYRXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC W40 } [get_ports {cfp2_tx_p[7]}] ;# MGTYTXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC W41 } [get_ports {cfp2_tx_n[7]}] ;# MGTYTXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AB43} [get_ports {cfp2_rx_p[8]}] ;# MGTYRXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AB44} [get_ports {cfp2_rx_n[8]}] ;# MGTYRXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AA40} [get_ports {cfp2_tx_p[8]}] ;# MGTYTXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AA41} [get_ports {cfp2_tx_n[8]}] ;# MGTYTXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AC45} [get_ports {cfp2_rx_p[9]}] ;# MGTYRXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AC46} [get_ports {cfp2_rx_n[9]}] ;# MGTYRXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AC40} [get_ports {cfp2_tx_p[9]}] ;# MGTYTXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AC41} [get_ports {cfp2_tx_n[9]}] ;# MGTYTXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC V38 } [get_ports cfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_129 from U32 SI570 via U104 SI53340
|
||||
#set_property -dict {LOC V39 } [get_ports cfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_129 from U32 SI570 via U104 SI53340
|
||||
#set_property -dict {LOC T38 } [get_ports cfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_129 from U57 CKOUT1 SI5328
|
||||
|
||||
@ -8,6 +8,7 @@ FPGA_ARCH = VirtexUltrascale
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
|
||||
SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
|
||||
SYN_FILES += rtl/debounce_switch.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
|
||||
|
||||
395
example/VCU108/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v
Normal file
395
example/VCU108/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v
Normal file
@ -0,0 +1,395 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2023 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Transceiver and PHY quad wrapper
|
||||
*/
|
||||
module eth_xcvr_phy_quad_wrapper #
|
||||
(
|
||||
parameter COUNT = 4,
|
||||
parameter DATA_WIDTH = 64,
|
||||
parameter CTRL_WIDTH = (DATA_WIDTH/8),
|
||||
parameter HDR_WIDTH = 2,
|
||||
parameter PRBS31_ENABLE = 0,
|
||||
parameter TX_SERDES_PIPELINE = 0,
|
||||
parameter RX_SERDES_PIPELINE = 0,
|
||||
parameter BITSLIP_HIGH_CYCLES = 1,
|
||||
parameter BITSLIP_LOW_CYCLES = 8,
|
||||
parameter COUNT_125US = 125000/6.4
|
||||
)
|
||||
(
|
||||
input wire xcvr_ctrl_clk,
|
||||
input wire xcvr_ctrl_rst,
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
output wire xcvr_gtpowergood_out,
|
||||
|
||||
/*
|
||||
* PLL
|
||||
*/
|
||||
input wire xcvr_gtrefclk00_in,
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
output wire [COUNT-1:0] xcvr_txp,
|
||||
output wire [COUNT-1:0] xcvr_txn,
|
||||
input wire [COUNT-1:0] xcvr_rxp,
|
||||
input wire [COUNT-1:0] xcvr_rxn,
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
*/
|
||||
output wire phy_1_tx_clk,
|
||||
output wire phy_1_tx_rst,
|
||||
input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd,
|
||||
input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc,
|
||||
output wire phy_1_rx_clk,
|
||||
output wire phy_1_rx_rst,
|
||||
output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd,
|
||||
output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc,
|
||||
output wire phy_1_tx_bad_block,
|
||||
output wire [6:0] phy_1_rx_error_count,
|
||||
output wire phy_1_rx_bad_block,
|
||||
output wire phy_1_rx_sequence_error,
|
||||
output wire phy_1_rx_block_lock,
|
||||
output wire phy_1_rx_high_ber,
|
||||
output wire phy_1_rx_status,
|
||||
input wire phy_1_cfg_tx_prbs31_enable,
|
||||
input wire phy_1_cfg_rx_prbs31_enable,
|
||||
|
||||
output wire phy_2_tx_clk,
|
||||
output wire phy_2_tx_rst,
|
||||
input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd,
|
||||
input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc,
|
||||
output wire phy_2_rx_clk,
|
||||
output wire phy_2_rx_rst,
|
||||
output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd,
|
||||
output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc,
|
||||
output wire phy_2_tx_bad_block,
|
||||
output wire [6:0] phy_2_rx_error_count,
|
||||
output wire phy_2_rx_bad_block,
|
||||
output wire phy_2_rx_sequence_error,
|
||||
output wire phy_2_rx_block_lock,
|
||||
output wire phy_2_rx_high_ber,
|
||||
output wire phy_2_rx_status,
|
||||
input wire phy_2_cfg_tx_prbs31_enable,
|
||||
input wire phy_2_cfg_rx_prbs31_enable,
|
||||
|
||||
output wire phy_3_tx_clk,
|
||||
output wire phy_3_tx_rst,
|
||||
input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd,
|
||||
input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc,
|
||||
output wire phy_3_rx_clk,
|
||||
output wire phy_3_rx_rst,
|
||||
output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd,
|
||||
output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc,
|
||||
output wire phy_3_tx_bad_block,
|
||||
output wire [6:0] phy_3_rx_error_count,
|
||||
output wire phy_3_rx_bad_block,
|
||||
output wire phy_3_rx_sequence_error,
|
||||
output wire phy_3_rx_block_lock,
|
||||
output wire phy_3_rx_high_ber,
|
||||
output wire phy_3_rx_status,
|
||||
input wire phy_3_cfg_tx_prbs31_enable,
|
||||
input wire phy_3_cfg_rx_prbs31_enable,
|
||||
|
||||
output wire phy_4_tx_clk,
|
||||
output wire phy_4_tx_rst,
|
||||
input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd,
|
||||
input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc,
|
||||
output wire phy_4_rx_clk,
|
||||
output wire phy_4_rx_rst,
|
||||
output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd,
|
||||
output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc,
|
||||
output wire phy_4_tx_bad_block,
|
||||
output wire [6:0] phy_4_rx_error_count,
|
||||
output wire phy_4_rx_bad_block,
|
||||
output wire phy_4_rx_sequence_error,
|
||||
output wire phy_4_rx_block_lock,
|
||||
output wire phy_4_rx_high_ber,
|
||||
output wire phy_4_rx_status,
|
||||
input wire phy_4_cfg_tx_prbs31_enable,
|
||||
input wire phy_4_cfg_rx_prbs31_enable
|
||||
);
|
||||
|
||||
generate
|
||||
|
||||
wire xcvr_qpll0lock;
|
||||
wire xcvr_qpll0clk;
|
||||
wire xcvr_qpll0refclk;
|
||||
|
||||
if (COUNT > 0) begin : phy1
|
||||
|
||||
eth_xcvr_phy_wrapper #(
|
||||
.HAS_COMMON(1),
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.CTRL_WIDTH(CTRL_WIDTH),
|
||||
.HDR_WIDTH(HDR_WIDTH),
|
||||
.PRBS31_ENABLE(PRBS31_ENABLE),
|
||||
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
|
||||
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
|
||||
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
|
||||
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
|
||||
.COUNT_125US(COUNT_125US)
|
||||
)
|
||||
eth_xcvr_phy_1 (
|
||||
.xcvr_ctrl_clk(xcvr_ctrl_clk),
|
||||
.xcvr_ctrl_rst(xcvr_ctrl_rst),
|
||||
|
||||
// Common
|
||||
.xcvr_gtpowergood_out(xcvr_gtpowergood_out),
|
||||
|
||||
// PLL out
|
||||
.xcvr_gtrefclk00_in(xcvr_gtrefclk00_in),
|
||||
.xcvr_qpll0lock_out(xcvr_qpll0lock),
|
||||
.xcvr_qpll0clk_out(xcvr_qpll0clk),
|
||||
.xcvr_qpll0refclk_out(xcvr_qpll0refclk),
|
||||
|
||||
// PLL in
|
||||
.xcvr_qpll0lock_in(1'b0),
|
||||
.xcvr_qpll0clk_in(1'b0),
|
||||
.xcvr_qpll0refclk_in(1'b0),
|
||||
|
||||
// Serial data
|
||||
.xcvr_txp(xcvr_txp[0]),
|
||||
.xcvr_txn(xcvr_txn[0]),
|
||||
.xcvr_rxp(xcvr_rxp[0]),
|
||||
.xcvr_rxn(xcvr_rxn[0]),
|
||||
|
||||
// PHY connections
|
||||
.phy_tx_clk(phy_1_tx_clk),
|
||||
.phy_tx_rst(phy_1_tx_rst),
|
||||
.phy_xgmii_txd(phy_1_xgmii_txd),
|
||||
.phy_xgmii_txc(phy_1_xgmii_txc),
|
||||
.phy_rx_clk(phy_1_rx_clk),
|
||||
.phy_rx_rst(phy_1_rx_rst),
|
||||
.phy_xgmii_rxd(phy_1_xgmii_rxd),
|
||||
.phy_xgmii_rxc(phy_1_xgmii_rxc),
|
||||
.phy_tx_bad_block(phy_1_tx_bad_block),
|
||||
.phy_rx_error_count(phy_1_rx_error_count),
|
||||
.phy_rx_bad_block(phy_1_rx_bad_block),
|
||||
.phy_rx_sequence_error(phy_1_rx_sequence_error),
|
||||
.phy_rx_block_lock(phy_1_rx_block_lock),
|
||||
.phy_rx_high_ber(phy_1_rx_high_ber),
|
||||
.phy_rx_status(phy_1_rx_status),
|
||||
.phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable),
|
||||
.phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (COUNT > 1) begin : phy2
|
||||
|
||||
eth_xcvr_phy_wrapper #(
|
||||
.HAS_COMMON(0),
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.CTRL_WIDTH(CTRL_WIDTH),
|
||||
.HDR_WIDTH(HDR_WIDTH),
|
||||
.PRBS31_ENABLE(PRBS31_ENABLE),
|
||||
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
|
||||
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
|
||||
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
|
||||
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
|
||||
.COUNT_125US(COUNT_125US)
|
||||
)
|
||||
eth_xcvr_phy_2 (
|
||||
.xcvr_ctrl_clk(xcvr_ctrl_clk),
|
||||
.xcvr_ctrl_rst(xcvr_ctrl_rst),
|
||||
|
||||
// Common
|
||||
.xcvr_gtpowergood_out(),
|
||||
|
||||
// PLL out
|
||||
.xcvr_gtrefclk00_in(1'b0),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
// PLL in
|
||||
.xcvr_qpll0lock_in(xcvr_qpll0lock),
|
||||
.xcvr_qpll0clk_in(xcvr_qpll0clk),
|
||||
.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
|
||||
|
||||
// Serial data
|
||||
.xcvr_txp(xcvr_txp[1]),
|
||||
.xcvr_txn(xcvr_txn[1]),
|
||||
.xcvr_rxp(xcvr_rxp[1]),
|
||||
.xcvr_rxn(xcvr_rxn[1]),
|
||||
|
||||
// PHY connections
|
||||
.phy_tx_clk(phy_2_tx_clk),
|
||||
.phy_tx_rst(phy_2_tx_rst),
|
||||
.phy_xgmii_txd(phy_2_xgmii_txd),
|
||||
.phy_xgmii_txc(phy_2_xgmii_txc),
|
||||
.phy_rx_clk(phy_2_rx_clk),
|
||||
.phy_rx_rst(phy_2_rx_rst),
|
||||
.phy_xgmii_rxd(phy_2_xgmii_rxd),
|
||||
.phy_xgmii_rxc(phy_2_xgmii_rxc),
|
||||
.phy_tx_bad_block(phy_2_tx_bad_block),
|
||||
.phy_rx_error_count(phy_2_rx_error_count),
|
||||
.phy_rx_bad_block(phy_2_rx_bad_block),
|
||||
.phy_rx_sequence_error(phy_2_rx_sequence_error),
|
||||
.phy_rx_block_lock(phy_2_rx_block_lock),
|
||||
.phy_rx_high_ber(phy_2_rx_high_ber),
|
||||
.phy_rx_status(phy_2_rx_status),
|
||||
.phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable),
|
||||
.phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (COUNT > 2) begin : phy3
|
||||
|
||||
eth_xcvr_phy_wrapper #(
|
||||
.HAS_COMMON(0),
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.CTRL_WIDTH(CTRL_WIDTH),
|
||||
.HDR_WIDTH(HDR_WIDTH),
|
||||
.PRBS31_ENABLE(PRBS31_ENABLE),
|
||||
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
|
||||
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
|
||||
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
|
||||
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
|
||||
.COUNT_125US(COUNT_125US)
|
||||
)
|
||||
eth_xcvr_phy_3 (
|
||||
.xcvr_ctrl_clk(xcvr_ctrl_clk),
|
||||
.xcvr_ctrl_rst(xcvr_ctrl_rst),
|
||||
|
||||
// Common
|
||||
.xcvr_gtpowergood_out(),
|
||||
|
||||
// PLL out
|
||||
.xcvr_gtrefclk00_in(1'b0),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
// PLL in
|
||||
.xcvr_qpll0lock_in(xcvr_qpll0lock),
|
||||
.xcvr_qpll0clk_in(xcvr_qpll0clk),
|
||||
.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
|
||||
|
||||
// Serial data
|
||||
.xcvr_txp(xcvr_txp[2]),
|
||||
.xcvr_txn(xcvr_txn[2]),
|
||||
.xcvr_rxp(xcvr_rxp[2]),
|
||||
.xcvr_rxn(xcvr_rxn[2]),
|
||||
|
||||
// PHY connections
|
||||
.phy_tx_clk(phy_3_tx_clk),
|
||||
.phy_tx_rst(phy_3_tx_rst),
|
||||
.phy_xgmii_txd(phy_3_xgmii_txd),
|
||||
.phy_xgmii_txc(phy_3_xgmii_txc),
|
||||
.phy_rx_clk(phy_3_rx_clk),
|
||||
.phy_rx_rst(phy_3_rx_rst),
|
||||
.phy_xgmii_rxd(phy_3_xgmii_rxd),
|
||||
.phy_xgmii_rxc(phy_3_xgmii_rxc),
|
||||
.phy_tx_bad_block(phy_3_tx_bad_block),
|
||||
.phy_rx_error_count(phy_3_rx_error_count),
|
||||
.phy_rx_bad_block(phy_3_rx_bad_block),
|
||||
.phy_rx_sequence_error(phy_3_rx_sequence_error),
|
||||
.phy_rx_block_lock(phy_3_rx_block_lock),
|
||||
.phy_rx_high_ber(phy_3_rx_high_ber),
|
||||
.phy_rx_status(phy_3_rx_status),
|
||||
.phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable),
|
||||
.phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (COUNT > 3) begin : phy4
|
||||
|
||||
eth_xcvr_phy_wrapper #(
|
||||
.HAS_COMMON(0),
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.CTRL_WIDTH(CTRL_WIDTH),
|
||||
.HDR_WIDTH(HDR_WIDTH),
|
||||
.PRBS31_ENABLE(PRBS31_ENABLE),
|
||||
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
|
||||
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
|
||||
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
|
||||
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
|
||||
.COUNT_125US(COUNT_125US)
|
||||
)
|
||||
eth_xcvr_phy_4 (
|
||||
.xcvr_ctrl_clk(xcvr_ctrl_clk),
|
||||
.xcvr_ctrl_rst(xcvr_ctrl_rst),
|
||||
|
||||
// Common
|
||||
.xcvr_gtpowergood_out(),
|
||||
|
||||
// PLL out
|
||||
.xcvr_gtrefclk00_in(1'b0),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0clk_out(),
|
||||
.xcvr_qpll0refclk_out(),
|
||||
|
||||
// PLL in
|
||||
.xcvr_qpll0lock_in(xcvr_qpll0lock),
|
||||
.xcvr_qpll0clk_in(xcvr_qpll0clk),
|
||||
.xcvr_qpll0refclk_in(xcvr_qpll0refclk),
|
||||
|
||||
// Serial data
|
||||
.xcvr_txp(xcvr_txp[3]),
|
||||
.xcvr_txn(xcvr_txn[3]),
|
||||
.xcvr_rxp(xcvr_rxp[3]),
|
||||
.xcvr_rxn(xcvr_rxn[3]),
|
||||
|
||||
// PHY connections
|
||||
.phy_tx_clk(phy_4_tx_clk),
|
||||
.phy_tx_rst(phy_4_tx_rst),
|
||||
.phy_xgmii_txd(phy_4_xgmii_txd),
|
||||
.phy_xgmii_txc(phy_4_xgmii_txc),
|
||||
.phy_rx_clk(phy_4_rx_clk),
|
||||
.phy_rx_rst(phy_4_rx_rst),
|
||||
.phy_xgmii_rxd(phy_4_xgmii_rxd),
|
||||
.phy_xgmii_rxc(phy_4_xgmii_rxc),
|
||||
.phy_tx_bad_block(phy_4_tx_bad_block),
|
||||
.phy_rx_error_count(phy_4_rx_error_count),
|
||||
.phy_rx_bad_block(phy_4_rx_bad_block),
|
||||
.phy_rx_sequence_error(phy_4_rx_sequence_error),
|
||||
.phy_rx_block_lock(phy_4_rx_block_lock),
|
||||
.phy_rx_high_ber(phy_4_rx_high_ber),
|
||||
.phy_rx_status(phy_4_rx_status),
|
||||
.phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable),
|
||||
.phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
@ -1,6 +1,6 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2021 Alex Forencich
|
||||
Copyright (c) 2021-2023 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper #
|
||||
*/
|
||||
input wire xcvr_gtrefclk00_in,
|
||||
output wire xcvr_qpll0lock_out,
|
||||
output wire xcvr_qpll0outclk_out,
|
||||
output wire xcvr_qpll0outrefclk_out,
|
||||
output wire xcvr_qpll0clk_out,
|
||||
output wire xcvr_qpll0refclk_out,
|
||||
|
||||
/*
|
||||
* PLL in
|
||||
@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper #
|
||||
output wire phy_rx_sequence_error,
|
||||
output wire phy_rx_block_lock,
|
||||
output wire phy_rx_high_ber,
|
||||
output wire phy_rx_status,
|
||||
input wire phy_cfg_tx_prbs31_enable,
|
||||
input wire phy_cfg_rx_prbs31_enable
|
||||
);
|
||||
@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr
|
||||
// PLL
|
||||
.gtrefclk00_in(xcvr_gtrefclk00_in),
|
||||
.qpll0lock_out(xcvr_qpll0lock_out),
|
||||
.qpll0outclk_out(xcvr_qpll0outclk_out),
|
||||
.qpll0outrefclk_out(xcvr_qpll0outrefclk_out),
|
||||
.qpll0outclk_out(xcvr_qpll0clk_out),
|
||||
.qpll0outrefclk_out(xcvr_qpll0refclk_out),
|
||||
|
||||
// Serial data
|
||||
.gtytxp_out(xcvr_txp),
|
||||
@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr
|
||||
.rxstartofseq_out()
|
||||
);
|
||||
|
||||
assign xcvr_qpll0reset_out = 1'b0;
|
||||
|
||||
end else begin : xcvr
|
||||
|
||||
eth_xcvr_gt_channel
|
||||
@ -234,6 +237,10 @@ end else begin : xcvr
|
||||
.rxstartofseq_out()
|
||||
);
|
||||
|
||||
assign xcvr_qpll0lock_out = 1'b0;
|
||||
assign xcvr_qpll0clk_out = 1'b0;
|
||||
assign xcvr_qpll0refclk_out = 1'b0;
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
@ -290,6 +297,7 @@ phy_inst (
|
||||
.rx_sequence_error(phy_rx_sequence_error),
|
||||
.rx_block_lock(phy_rx_block_lock),
|
||||
.rx_high_ber(phy_rx_high_ber),
|
||||
.rx_status(phy_rx_status),
|
||||
.cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable),
|
||||
.cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable)
|
||||
);
|
||||
|
||||
@ -60,22 +60,10 @@ module fpga (
|
||||
/*
|
||||
* Ethernet: QSFP28
|
||||
*/
|
||||
input wire qsfp_rx1_p,
|
||||
input wire qsfp_rx1_n,
|
||||
input wire qsfp_rx2_p,
|
||||
input wire qsfp_rx2_n,
|
||||
input wire qsfp_rx3_p,
|
||||
input wire qsfp_rx3_n,
|
||||
input wire qsfp_rx4_p,
|
||||
input wire qsfp_rx4_n,
|
||||
output wire qsfp_tx1_p,
|
||||
output wire qsfp_tx1_n,
|
||||
output wire qsfp_tx2_p,
|
||||
output wire qsfp_tx2_n,
|
||||
output wire qsfp_tx3_p,
|
||||
output wire qsfp_tx3_n,
|
||||
output wire qsfp_tx4_p,
|
||||
output wire qsfp_tx4_n,
|
||||
input wire [3:0] qsfp_rx_p,
|
||||
input wire [3:0] qsfp_rx_n,
|
||||
output wire [3:0] qsfp_tx_p,
|
||||
output wire [3:0] qsfp_tx_n,
|
||||
input wire qsfp_mgt_refclk_0_p,
|
||||
input wire qsfp_mgt_refclk_0_n,
|
||||
// input wire qsfp_mgt_refclk_1_p,
|
||||
@ -321,196 +309,99 @@ IBUFDS_GTE3 ibufds_gte3_qsfp_mgt_refclk_0_inst (
|
||||
.ODIV2 ()
|
||||
);
|
||||
|
||||
wire qsfp_qpll0lock;
|
||||
wire qsfp_qpll0outclk;
|
||||
wire qsfp_qpll0outrefclk;
|
||||
|
||||
eth_xcvr_phy_wrapper #(
|
||||
.HAS_COMMON(1)
|
||||
)
|
||||
qsfp_phy_1_inst (
|
||||
eth_xcvr_phy_quad_wrapper
|
||||
qsfp_phy_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz_int),
|
||||
.xcvr_ctrl_rst(rst_125mhz_int),
|
||||
|
||||
// Common
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
.xcvr_gtpowergood_out(),
|
||||
|
||||
// PLL out
|
||||
/*
|
||||
* PLL
|
||||
*/
|
||||
.xcvr_gtrefclk00_in(qsfp_mgt_refclk_0),
|
||||
.xcvr_qpll0lock_out(qsfp_qpll0lock),
|
||||
.xcvr_qpll0outclk_out(qsfp_qpll0outclk),
|
||||
.xcvr_qpll0outrefclk_out(qsfp_qpll0outrefclk),
|
||||
|
||||
// PLL in
|
||||
.xcvr_qpll0lock_in(1'b0),
|
||||
.xcvr_qpll0reset_out(),
|
||||
.xcvr_qpll0clk_in(1'b0),
|
||||
.xcvr_qpll0refclk_in(1'b0),
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
.xcvr_txp(qsfp_tx_p),
|
||||
.xcvr_txn(qsfp_tx_n),
|
||||
.xcvr_rxp(qsfp_rx_p),
|
||||
.xcvr_rxn(qsfp_rx_n),
|
||||
|
||||
// Serial data
|
||||
.xcvr_txp(qsfp_tx1_p),
|
||||
.xcvr_txn(qsfp_tx1_n),
|
||||
.xcvr_rxp(qsfp_rx1_p),
|
||||
.xcvr_rxn(qsfp_rx1_n),
|
||||
/*
|
||||
* PHY connections
|
||||
*/
|
||||
.phy_1_tx_clk(qsfp_tx_clk_1_int),
|
||||
.phy_1_tx_rst(qsfp_tx_rst_1_int),
|
||||
.phy_1_xgmii_txd(qsfp_txd_1_int),
|
||||
.phy_1_xgmii_txc(qsfp_txc_1_int),
|
||||
.phy_1_rx_clk(qsfp_rx_clk_1_int),
|
||||
.phy_1_rx_rst(qsfp_rx_rst_1_int),
|
||||
.phy_1_xgmii_rxd(qsfp_rxd_1_int),
|
||||
.phy_1_xgmii_rxc(qsfp_rxc_1_int),
|
||||
.phy_1_tx_bad_block(),
|
||||
.phy_1_rx_error_count(),
|
||||
.phy_1_rx_bad_block(),
|
||||
.phy_1_rx_sequence_error(),
|
||||
.phy_1_rx_block_lock(qsfp_rx_block_lock_1),
|
||||
.phy_1_rx_status(),
|
||||
.phy_1_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_1_cfg_rx_prbs31_enable(1'b0),
|
||||
|
||||
// PHY connections
|
||||
.phy_tx_clk(qsfp_tx_clk_1_int),
|
||||
.phy_tx_rst(qsfp_tx_rst_1_int),
|
||||
.phy_xgmii_txd(qsfp_txd_1_int),
|
||||
.phy_xgmii_txc(qsfp_txc_1_int),
|
||||
.phy_rx_clk(qsfp_rx_clk_1_int),
|
||||
.phy_rx_rst(qsfp_rx_rst_1_int),
|
||||
.phy_xgmii_rxd(qsfp_rxd_1_int),
|
||||
.phy_xgmii_rxc(qsfp_rxc_1_int),
|
||||
.phy_tx_bad_block(),
|
||||
.phy_rx_error_count(),
|
||||
.phy_rx_bad_block(),
|
||||
.phy_rx_sequence_error(),
|
||||
.phy_rx_block_lock(qsfp_rx_block_lock_1),
|
||||
.phy_rx_high_ber(),
|
||||
.phy_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_cfg_rx_prbs31_enable(1'b0)
|
||||
);
|
||||
.phy_2_tx_clk(qsfp_tx_clk_2_int),
|
||||
.phy_2_tx_rst(qsfp_tx_rst_2_int),
|
||||
.phy_2_xgmii_txd(qsfp_txd_2_int),
|
||||
.phy_2_xgmii_txc(qsfp_txc_2_int),
|
||||
.phy_2_rx_clk(qsfp_rx_clk_2_int),
|
||||
.phy_2_rx_rst(qsfp_rx_rst_2_int),
|
||||
.phy_2_xgmii_rxd(qsfp_rxd_2_int),
|
||||
.phy_2_xgmii_rxc(qsfp_rxc_2_int),
|
||||
.phy_2_tx_bad_block(),
|
||||
.phy_2_rx_error_count(),
|
||||
.phy_2_rx_bad_block(),
|
||||
.phy_2_rx_sequence_error(),
|
||||
.phy_2_rx_block_lock(qsfp_rx_block_lock_2),
|
||||
.phy_2_rx_status(),
|
||||
.phy_2_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_2_cfg_rx_prbs31_enable(1'b0),
|
||||
|
||||
eth_xcvr_phy_wrapper #(
|
||||
.HAS_COMMON(0)
|
||||
)
|
||||
qsfp_phy_2_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz_int),
|
||||
.xcvr_ctrl_rst(rst_125mhz_int),
|
||||
.phy_3_tx_clk(qsfp_tx_clk_3_int),
|
||||
.phy_3_tx_rst(qsfp_tx_rst_3_int),
|
||||
.phy_3_xgmii_txd(qsfp_txd_3_int),
|
||||
.phy_3_xgmii_txc(qsfp_txc_3_int),
|
||||
.phy_3_rx_clk(qsfp_rx_clk_3_int),
|
||||
.phy_3_rx_rst(qsfp_rx_rst_3_int),
|
||||
.phy_3_xgmii_rxd(qsfp_rxd_3_int),
|
||||
.phy_3_xgmii_rxc(qsfp_rxc_3_int),
|
||||
.phy_3_tx_bad_block(),
|
||||
.phy_3_rx_error_count(),
|
||||
.phy_3_rx_bad_block(),
|
||||
.phy_3_rx_sequence_error(),
|
||||
.phy_3_rx_block_lock(qsfp_rx_block_lock_3),
|
||||
.phy_3_rx_status(),
|
||||
.phy_3_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_3_cfg_rx_prbs31_enable(1'b0),
|
||||
|
||||
// Common
|
||||
.xcvr_gtpowergood_out(),
|
||||
|
||||
// PLL out
|
||||
.xcvr_gtrefclk00_in(1'b0),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0outclk_out(),
|
||||
.xcvr_qpll0outrefclk_out(),
|
||||
|
||||
// PLL in
|
||||
.xcvr_qpll0lock_in(qsfp_qpll0lock),
|
||||
.xcvr_qpll0reset_out(),
|
||||
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
|
||||
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
|
||||
|
||||
// Serial data
|
||||
.xcvr_txp(qsfp_tx2_p),
|
||||
.xcvr_txn(qsfp_tx2_n),
|
||||
.xcvr_rxp(qsfp_rx2_p),
|
||||
.xcvr_rxn(qsfp_rx2_n),
|
||||
|
||||
// PHY connections
|
||||
.phy_tx_clk(qsfp_tx_clk_2_int),
|
||||
.phy_tx_rst(qsfp_tx_rst_2_int),
|
||||
.phy_xgmii_txd(qsfp_txd_2_int),
|
||||
.phy_xgmii_txc(qsfp_txc_2_int),
|
||||
.phy_rx_clk(qsfp_rx_clk_2_int),
|
||||
.phy_rx_rst(qsfp_rx_rst_2_int),
|
||||
.phy_xgmii_rxd(qsfp_rxd_2_int),
|
||||
.phy_xgmii_rxc(qsfp_rxc_2_int),
|
||||
.phy_tx_bad_block(),
|
||||
.phy_rx_error_count(),
|
||||
.phy_rx_bad_block(),
|
||||
.phy_rx_sequence_error(),
|
||||
.phy_rx_block_lock(qsfp_rx_block_lock_2),
|
||||
.phy_rx_high_ber(),
|
||||
.phy_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_cfg_rx_prbs31_enable(1'b0)
|
||||
);
|
||||
|
||||
eth_xcvr_phy_wrapper #(
|
||||
.HAS_COMMON(0)
|
||||
)
|
||||
qsfp_phy_3_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz_int),
|
||||
.xcvr_ctrl_rst(rst_125mhz_int),
|
||||
|
||||
// Common
|
||||
.xcvr_gtpowergood_out(),
|
||||
|
||||
// PLL out
|
||||
.xcvr_gtrefclk00_in(1'b0),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0outclk_out(),
|
||||
.xcvr_qpll0outrefclk_out(),
|
||||
|
||||
// PLL in
|
||||
.xcvr_qpll0lock_in(qsfp_qpll0lock),
|
||||
.xcvr_qpll0reset_out(),
|
||||
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
|
||||
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
|
||||
|
||||
// Serial data
|
||||
.xcvr_txp(qsfp_tx3_p),
|
||||
.xcvr_txn(qsfp_tx3_n),
|
||||
.xcvr_rxp(qsfp_rx3_p),
|
||||
.xcvr_rxn(qsfp_rx3_n),
|
||||
|
||||
// PHY connections
|
||||
.phy_tx_clk(qsfp_tx_clk_3_int),
|
||||
.phy_tx_rst(qsfp_tx_rst_3_int),
|
||||
.phy_xgmii_txd(qsfp_txd_3_int),
|
||||
.phy_xgmii_txc(qsfp_txc_3_int),
|
||||
.phy_rx_clk(qsfp_rx_clk_3_int),
|
||||
.phy_rx_rst(qsfp_rx_rst_3_int),
|
||||
.phy_xgmii_rxd(qsfp_rxd_3_int),
|
||||
.phy_xgmii_rxc(qsfp_rxc_3_int),
|
||||
.phy_tx_bad_block(),
|
||||
.phy_rx_error_count(),
|
||||
.phy_rx_bad_block(),
|
||||
.phy_rx_sequence_error(),
|
||||
.phy_rx_block_lock(qsfp_rx_block_lock_3),
|
||||
.phy_rx_high_ber(),
|
||||
.phy_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_cfg_rx_prbs31_enable(1'b0)
|
||||
);
|
||||
|
||||
eth_xcvr_phy_wrapper #(
|
||||
.HAS_COMMON(0)
|
||||
)
|
||||
qsfp_phy_4_inst (
|
||||
.xcvr_ctrl_clk(clk_125mhz_int),
|
||||
.xcvr_ctrl_rst(rst_125mhz_int),
|
||||
|
||||
// Common
|
||||
.xcvr_gtpowergood_out(),
|
||||
|
||||
// PLL out
|
||||
.xcvr_gtrefclk00_in(1'b0),
|
||||
.xcvr_qpll0lock_out(),
|
||||
.xcvr_qpll0outclk_out(),
|
||||
.xcvr_qpll0outrefclk_out(),
|
||||
|
||||
// PLL in
|
||||
.xcvr_qpll0lock_in(qsfp_qpll0lock),
|
||||
.xcvr_qpll0reset_out(),
|
||||
.xcvr_qpll0clk_in(qsfp_qpll0outclk),
|
||||
.xcvr_qpll0refclk_in(qsfp_qpll0outrefclk),
|
||||
|
||||
// Serial data
|
||||
.xcvr_txp(qsfp_tx4_p),
|
||||
.xcvr_txn(qsfp_tx4_n),
|
||||
.xcvr_rxp(qsfp_rx4_p),
|
||||
.xcvr_rxn(qsfp_rx4_n),
|
||||
|
||||
// PHY connections
|
||||
.phy_tx_clk(qsfp_tx_clk_4_int),
|
||||
.phy_tx_rst(qsfp_tx_rst_4_int),
|
||||
.phy_xgmii_txd(qsfp_txd_4_int),
|
||||
.phy_xgmii_txc(qsfp_txc_4_int),
|
||||
.phy_rx_clk(qsfp_rx_clk_4_int),
|
||||
.phy_rx_rst(qsfp_rx_rst_4_int),
|
||||
.phy_xgmii_rxd(qsfp_rxd_4_int),
|
||||
.phy_xgmii_rxc(qsfp_rxc_4_int),
|
||||
.phy_tx_bad_block(),
|
||||
.phy_rx_error_count(),
|
||||
.phy_rx_bad_block(),
|
||||
.phy_rx_sequence_error(),
|
||||
.phy_rx_block_lock(qsfp_rx_block_lock_4),
|
||||
.phy_rx_high_ber(),
|
||||
.phy_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_cfg_rx_prbs31_enable(1'b0)
|
||||
.phy_4_tx_clk(qsfp_tx_clk_4_int),
|
||||
.phy_4_tx_rst(qsfp_tx_rst_4_int),
|
||||
.phy_4_xgmii_txd(qsfp_txd_4_int),
|
||||
.phy_4_xgmii_txc(qsfp_txc_4_int),
|
||||
.phy_4_rx_clk(qsfp_rx_clk_4_int),
|
||||
.phy_4_rx_rst(qsfp_rx_rst_4_int),
|
||||
.phy_4_xgmii_rxd(qsfp_rxd_4_int),
|
||||
.phy_4_xgmii_rxc(qsfp_rxc_4_int),
|
||||
.phy_4_tx_bad_block(),
|
||||
.phy_4_rx_error_count(),
|
||||
.phy_4_rx_bad_block(),
|
||||
.phy_4_rx_sequence_error(),
|
||||
.phy_4_rx_block_lock(qsfp_rx_block_lock_4),
|
||||
.phy_4_rx_status(),
|
||||
.phy_4_cfg_tx_prbs31_enable(1'b0),
|
||||
.phy_4_cfg_rx_prbs31_enable(1'b0)
|
||||
);
|
||||
|
||||
// SGMII interface to PHY
|
||||
|
||||
@ -130,22 +130,22 @@ set_input_delay 0 [get_ports {phy_int_n}]
|
||||
#set_input_delay 0 [get_ports {phy_mdio}]
|
||||
|
||||
# Bullseye GTY
|
||||
#set_property -dict {LOC AR45} [get_ports bullseye_rx0_p] ;# MGTYRXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AR46} [get_ports bullseye_rx0_n] ;# MGTYRXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AT42} [get_ports bullseye_tx0_p] ;# MGTYTXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AT43} [get_ports bullseye_tx0_n] ;# MGTYTXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AN45} [get_ports bullseye_rx1_p] ;# MGTYRXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AN46} [get_ports bullseye_rx1_n] ;# MGTYRXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AP42} [get_ports bullseye_tx1_p] ;# MGTYTXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AP43} [get_ports bullseye_tx1_n] ;# MGTYTXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AL45} [get_ports bullseye_rx2_p] ;# MGTYRXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AL46} [get_ports bullseye_rx2_n] ;# MGTYRXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AM42} [get_ports bullseye_tx2_p] ;# MGTYTXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AM43} [get_ports bullseye_tx2_n] ;# MGTYTXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AJ45} [get_ports bullseye_rx3_p] ;# MGTYRXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AJ46} [get_ports bullseye_rx3_n] ;# MGTYRXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AL40} [get_ports bullseye_tx3_p] ;# MGTYTXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AL41} [get_ports bullseye_tx3_n] ;# MGTYTXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AR45} [get_ports {bullseye_rx_p[0]}] ;# MGTYRXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AR46} [get_ports {bullseye_rx_n[0]}] ;# MGTYRXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AT42} [get_ports {bullseye_tx_p[0]}] ;# MGTYTXP0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AT43} [get_ports {bullseye_tx_n[0]}] ;# MGTYTXN0_126 GTYE3_CHANNEL_X0Y8 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AN45} [get_ports {bullseye_rx_p[1]}] ;# MGTYRXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AN46} [get_ports {bullseye_rx_n[1]}] ;# MGTYRXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AP42} [get_ports {bullseye_tx_p[1]}] ;# MGTYTXP1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AP43} [get_ports {bullseye_tx_n[1]}] ;# MGTYTXN1_126 GTYE3_CHANNEL_X0Y9 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AL45} [get_ports {bullseye_rx_p[2]}] ;# MGTYRXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AL46} [get_ports {bullseye_rx_n[2]}] ;# MGTYRXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AM42} [get_ports {bullseye_tx_p[2]}] ;# MGTYTXP2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AM43} [get_ports {bullseye_tx_n[2]}] ;# MGTYTXN2_126 GTYE3_CHANNEL_X0Y10 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AJ45} [get_ports {bullseye_rx_p[3]}] ;# MGTYRXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AJ46} [get_ports {bullseye_rx_n[3]}] ;# MGTYRXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AL40} [get_ports {bullseye_tx_p[3]}] ;# MGTYTXP3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AL41} [get_ports {bullseye_tx_n[3]}] ;# MGTYTXN3_126 GTYE3_CHANNEL_X0Y11 / GTYE3_COMMON_X0Y2
|
||||
#set_property -dict {LOC AK38} [get_ports bullseye_mgt_refclk_0_p] ;# MGTREFCLK0P_126 from J87 P19
|
||||
#set_property -dict {LOC AK39} [get_ports bullseye_mgt_refclk_0_n] ;# MGTREFCLK0N_126 from J87 P20
|
||||
#set_property -dict {LOC AH38} [get_ports bullseye_mgt_refclk_1_p] ;# MGTREFCLK1P_126 from U32 SI570 via U104 SI53340
|
||||
@ -155,22 +155,22 @@ set_input_delay 0 [get_ports {phy_int_n}]
|
||||
#create_clock -period 6.4 -name bullseye_mgt_refclk [get_ports bullseye_mgt_refclk_1_p]
|
||||
|
||||
# QSFP28 Interface
|
||||
#set_property -dict {LOC AG45} [get_ports qsfp_rx1_p] ;# MGTYRXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AG46} [get_ports qsfp_rx1_n] ;# MGTYRXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AK42} [get_ports qsfp_tx1_p] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AK43} [get_ports qsfp_tx1_n] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AF43} [get_ports qsfp_rx2_p] ;# MGTYRXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AF44} [get_ports qsfp_rx2_n] ;# MGTYRXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AJ40} [get_ports qsfp_tx2_p] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AJ41} [get_ports qsfp_tx2_n] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AE45} [get_ports qsfp_rx3_p] ;# MGTYRXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AE46} [get_ports qsfp_rx3_n] ;# MGTYRXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AG40} [get_ports qsfp_tx3_p] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AG41} [get_ports qsfp_tx3_n] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AD43} [get_ports qsfp_rx4_p] ;# MGTYRXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AD44} [get_ports qsfp_rx4_n] ;# MGTYRXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AE40} [get_ports qsfp_tx4_p] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AE41} [get_ports qsfp_tx4_n] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AG45} [get_ports {qsfp_rx_p[0]}] ;# MGTYRXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AG46} [get_ports {qsfp_rx_n[0]}] ;# MGTYRXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AK42} [get_ports {qsfp_tx_p[0]}] ;# MGTYTXP0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AK43} [get_ports {qsfp_tx_n[0]}] ;# MGTYTXN0_127 GTYE3_CHANNEL_X0Y12 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AF43} [get_ports {qsfp_rx_p[1]}] ;# MGTYRXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AF44} [get_ports {qsfp_rx_n[1]}] ;# MGTYRXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AJ40} [get_ports {qsfp_tx_p[1]}] ;# MGTYTXP1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AJ41} [get_ports {qsfp_tx_n[1]}] ;# MGTYTXN1_127 GTYE3_CHANNEL_X0Y13 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AE45} [get_ports {qsfp_rx_p[2]}] ;# MGTYRXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AE46} [get_ports {qsfp_rx_n[2]}] ;# MGTYRXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AG40} [get_ports {qsfp_tx_p[2]}] ;# MGTYTXP2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AG41} [get_ports {qsfp_tx_n[2]}] ;# MGTYTXN2_127 GTYE3_CHANNEL_X0Y14 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AD43} [get_ports {qsfp_rx_p[3]}] ;# MGTYRXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AD44} [get_ports {qsfp_rx_n[3]}] ;# MGTYRXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AE40} [get_ports {qsfp_tx_p[3]}] ;# MGTYTXP3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AE41} [get_ports {qsfp_tx_n[3]}] ;# MGTYTXN3_127 GTYE3_CHANNEL_X0Y15 / GTYE3_COMMON_X0Y3
|
||||
#set_property -dict {LOC AF38} [get_ports qsfp_mgt_refclk_0_p] ;# MGTREFCLK0P_127 from U32 SI570 via U102 SI53340
|
||||
#set_property -dict {LOC AF39} [get_ports qsfp_mgt_refclk_0_n] ;# MGTREFCLK0N_127 from U32 SI570 via U102 SI53340
|
||||
#set_property -dict {LOC AD38} [get_ports qsfp_mgt_refclk_1_p] ;# MGTREFCLK1P_127 from U57 CKOUT2 SI5328
|
||||
@ -192,46 +192,46 @@ set_input_delay 0 [get_ports {phy_int_n}]
|
||||
#set_input_delay 0 [get_ports {qsfp_modprsl qsfp_intl}]
|
||||
|
||||
# CFP2 GTY
|
||||
#set_property -dict {LOC J45 } [get_ports cfp2_rx0_p] ;# MGTYRXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC J46 } [get_ports cfp2_rx0_n] ;# MGTYRXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC F42 } [get_ports cfp2_tx0_p] ;# MGTYTXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC F43 } [get_ports cfp2_tx0_n] ;# MGTYTXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC N45 } [get_ports cfp2_rx1_p] ;# MGTYRXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC N46 } [get_ports cfp2_rx1_n] ;# MGTYRXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC K42 } [get_ports cfp2_tx1_p] ;# MGTYTXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC K43 } [get_ports cfp2_tx1_n] ;# MGTYTXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC R45 } [get_ports cfp2_rx2_p] ;# MGTYRXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC R46 } [get_ports cfp2_rx2_n] ;# MGTYRXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC M42 } [get_ports cfp2_tx2_p] ;# MGTYTXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC M43 } [get_ports cfp2_tx2_n] ;# MGTYTXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC L45 } [get_ports cfp2_rx3_p] ;# MGTYRXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC L46 } [get_ports cfp2_rx3_n] ;# MGTYRXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC H42 } [get_ports cfp2_tx3_p] ;# MGTYTXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC H43 } [get_ports cfp2_tx3_n] ;# MGTYTXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC Y43 } [get_ports cfp2_rx4_p] ;# MGTYRXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC Y44 } [get_ports cfp2_rx4_n] ;# MGTYRXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC U40 } [get_ports cfp2_tx4_p] ;# MGTYTXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC U41 } [get_ports cfp2_tx4_n] ;# MGTYTXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC U45 } [get_ports cfp2_rx5_p] ;# MGTYRXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC U46 } [get_ports cfp2_rx5_n] ;# MGTYRXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC P42 } [get_ports cfp2_tx5_p] ;# MGTYTXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC P43 } [get_ports cfp2_tx5_n] ;# MGTYTXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC W45 } [get_ports cfp2_rx6_p] ;# MGTYRXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC W46 } [get_ports cfp2_rx6_n] ;# MGTYRXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC T42 } [get_ports cfp2_tx6_p] ;# MGTYTXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC T43 } [get_ports cfp2_tx6_n] ;# MGTYTXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC AA45} [get_ports cfp2_rx7_p] ;# MGTYRXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AA46} [get_ports cfp2_rx7_n] ;# MGTYRXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC W40 } [get_ports cfp2_tx7_p] ;# MGTYTXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC W41 } [get_ports cfp2_tx7_n] ;# MGTYTXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AB43} [get_ports cfp2_rx8_p] ;# MGTYRXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AB44} [get_ports cfp2_rx8_n] ;# MGTYRXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AA40} [get_ports cfp2_tx8_p] ;# MGTYTXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AA41} [get_ports cfp2_tx8_n] ;# MGTYTXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AC45} [get_ports cfp2_rx9_p] ;# MGTYRXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AC46} [get_ports cfp2_rx9_n] ;# MGTYRXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AC40} [get_ports cfp2_tx9_p] ;# MGTYTXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AC41} [get_ports cfp2_tx9_n] ;# MGTYTXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC J45 } [get_ports {cfp2_rx_p[0]}] ;# MGTYRXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC J46 } [get_ports {cfp2_rx_n[0]}] ;# MGTYRXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC F42 } [get_ports {cfp2_tx_p[0]}] ;# MGTYTXP1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC F43 } [get_ports {cfp2_tx_n[0]}] ;# MGTYTXN1_130 GTYE3_CHANNEL_X0Y25 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC N45 } [get_ports {cfp2_rx_p[1]}] ;# MGTYRXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC N46 } [get_ports {cfp2_rx_n[1]}] ;# MGTYRXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC K42 } [get_ports {cfp2_tx_p[1]}] ;# MGTYTXP3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC K43 } [get_ports {cfp2_tx_n[1]}] ;# MGTYTXN3_129 GTYE3_CHANNEL_X0Y23 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC R45 } [get_ports {cfp2_rx_p[2]}] ;# MGTYRXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC R46 } [get_ports {cfp2_rx_n[2]}] ;# MGTYRXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC M42 } [get_ports {cfp2_tx_p[2]}] ;# MGTYTXP2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC M43 } [get_ports {cfp2_tx_n[2]}] ;# MGTYTXN2_129 GTYE3_CHANNEL_X0Y22 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC L45 } [get_ports {cfp2_rx_p[3]}] ;# MGTYRXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC L46 } [get_ports {cfp2_rx_n[3]}] ;# MGTYRXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC H42 } [get_ports {cfp2_tx_p[3]}] ;# MGTYTXP0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC H43 } [get_ports {cfp2_tx_n[3]}] ;# MGTYTXN0_130 GTYE3_CHANNEL_X0Y24 / GTYE3_COMMON_X0Y6
|
||||
#set_property -dict {LOC Y43 } [get_ports {cfp2_rx_p[4]}] ;# MGTYRXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC Y44 } [get_ports {cfp2_rx_n[4]}] ;# MGTYRXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC U40 } [get_ports {cfp2_tx_p[4]}] ;# MGTYTXP3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC U41 } [get_ports {cfp2_tx_n[4]}] ;# MGTYTXN3_128 GTYE3_CHANNEL_X0Y19 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC U45 } [get_ports {cfp2_rx_p[5]}] ;# MGTYRXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC U46 } [get_ports {cfp2_rx_n[5]}] ;# MGTYRXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC P42 } [get_ports {cfp2_tx_p[5]}] ;# MGTYTXP1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC P43 } [get_ports {cfp2_tx_n[5]}] ;# MGTYTXN1_129 GTYE3_CHANNEL_X0Y21 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC W45 } [get_ports {cfp2_rx_p[6]}] ;# MGTYRXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC W46 } [get_ports {cfp2_rx_n[6]}] ;# MGTYRXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC T42 } [get_ports {cfp2_tx_p[6]}] ;# MGTYTXP0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC T43 } [get_ports {cfp2_tx_n[6]}] ;# MGTYTXN0_129 GTYE3_CHANNEL_X0Y20 / GTYE3_COMMON_X0Y5
|
||||
#set_property -dict {LOC AA45} [get_ports {cfp2_rx_p[7]}] ;# MGTYRXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AA46} [get_ports {cfp2_rx_n[7]}] ;# MGTYRXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC W40 } [get_ports {cfp2_tx_p[7]}] ;# MGTYTXP2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC W41 } [get_ports {cfp2_tx_n[7]}] ;# MGTYTXN2_128 GTYE3_CHANNEL_X0Y18 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AB43} [get_ports {cfp2_rx_p[8]}] ;# MGTYRXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AB44} [get_ports {cfp2_rx_n[8]}] ;# MGTYRXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AA40} [get_ports {cfp2_tx_p[8]}] ;# MGTYTXP1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AA41} [get_ports {cfp2_tx_n[8]}] ;# MGTYTXN1_128 GTYE3_CHANNEL_X0Y17 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AC45} [get_ports {cfp2_rx_p[9]}] ;# MGTYRXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AC46} [get_ports {cfp2_rx_n[9]}] ;# MGTYRXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AC40} [get_ports {cfp2_tx_p[9]}] ;# MGTYTXP0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC AC41} [get_ports {cfp2_tx_n[9]}] ;# MGTYTXN0_128 GTYE3_CHANNEL_X0Y16 / GTYE3_COMMON_X0Y4
|
||||
#set_property -dict {LOC V38 } [get_ports cfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_129 from U32 SI570 via U104 SI53340
|
||||
#set_property -dict {LOC V39 } [get_ports cfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_129 from U32 SI570 via U104 SI53340
|
||||
#set_property -dict {LOC T38 } [get_ports cfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_129 from U57 CKOUT1 SI5328
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user