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Add port register port_mtu

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This commit is contained in:
Alex Forencich 2019-11-18 16:30:32 -08:00
parent 03465b4b25
commit 463f2053b0
5 changed files with 9 additions and 0 deletions
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1
fpga/common/rtl/port.v
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@ -634,6 +634,7 @@ always @(posedge clk) begin
axil_ctrl_rdata_reg[8] <= TX_CHECKSUM_ENABLE;
axil_ctrl_rdata_reg[9] <= RX_CHECKSUM_ENABLE;
end
16'h0008: axil_ctrl_rdata_reg <= MAX_TX_SIZE; // port_mtu
16'h0010: axil_ctrl_rdata_reg <= SCHED_COUNT; // scheduler_count
16'h0014: axil_ctrl_rdata_reg <= 2**AXIL_SCHED_ADDR_WIDTH; // scheduler_offset
16'h0018: axil_ctrl_rdata_reg <= 2**AXIL_SCHED_ADDR_WIDTH; // scheduler_stride

4
fpga/common/tb/mqnic.py
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@ -128,6 +128,7 @@ MQNIC_IF_FEATURE_RX_CSUM = (1 << 9)
# Port CSRs
MQNIC_PORT_REG_PORT_ID = 0x0000
MQNIC_PORT_REG_PORT_FEATURES = 0x0004
MQNIC_PORT_REG_PORT_MTU = 0x0008
MQNIC_PORT_REG_SCHED_COUNT = 0x0010
MQNIC_PORT_REG_SCHED_OFFSET = 0x0014
@ -577,6 +578,7 @@ class Port(object):
self.port_id = None
self.port_features = None
self.port_mtu = 0
self.sched_count = None
self.sched_offset = None
self.sched_stride = None
@ -588,6 +590,8 @@ class Port(object):
print("Port ID: {:#010x}".format(self.port_id))
self.port_features = yield from self.driver.rc.mem_read_dword(self.hw_addr+MQNIC_PORT_REG_PORT_FEATURES)
print("Port features: {:#010x}".format(self.port_features))
self.port_mtu = yield from self.driver.rc.mem_read_dword(self.hw_addr+MQNIC_PORT_REG_PORT_MTU)
print("Port MTU: {}".format(self.port_mtu))
self.sched_count = yield from self.driver.rc.mem_read_dword(self.hw_addr+MQNIC_PORT_REG_SCHED_COUNT)
print("Scheduler count: {}".format(self.sched_count))

1
modules/mqnic/mqnic.h
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@ -225,6 +225,7 @@ struct mqnic_port {
u32 port_id;
u32 port_features;
u32 port_mtu;
u32 sched_count;
u32 sched_offset;
u32 sched_stride;

1
modules/mqnic/mqnic_hw.h
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@ -134,6 +134,7 @@ either expressed or implied, of The Regents of the University of California.
// Port CSRs
#define MQNIC_PORT_REG_PORT_ID 0x0000
#define MQNIC_PORT_REG_PORT_FEATURES 0x0004
#define MQNIC_PORT_REG_PORT_MTU 0x0008
#define MQNIC_PORT_REG_SCHED_COUNT 0x0010
#define MQNIC_PORT_REG_SCHED_OFFSET 0x0014

2
modules/mqnic/mqnic_port.c
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@ -61,6 +61,8 @@ int mqnic_create_port(struct mqnic_priv *priv, struct mqnic_port **port_ptr, int
dev_info(dev, "Port ID: 0x%08x", port->port_id);
port->port_features = ioread32(port->hw_addr+MQNIC_PORT_REG_PORT_FEATURES);
dev_info(dev, "Port features: 0x%08x", port->port_features);
port->port_mtu = ioread32(port->hw_addr+MQNIC_PORT_REG_PORT_MTU);
dev_info(dev, "Port MTU: %d", port->port_mtu);
port->sched_count = ioread32(port->hw_addr+MQNIC_PORT_REG_SCHED_COUNT);
dev_info(dev, "Scheduler count: %d", port->sched_count);