FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

fpga/mqnic/ADM_PCIE_9V3: Parameter clean-up, remove PCIE_TAG_COUNT from top level

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-05-19 13:34:33 -07:00
parent b7dad0e946
commit 47cfc828a2
8 changed files with 2 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl
View File

@ -161,9 +161,6 @@ dict set params DMA_TAG_WIDTH "16"
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
dict set params RAM_PIPELINE "2"
# PCIe interface configuration
dict set params PCIE_TAG_COUNT "256"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]

3
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/config.tcl
View File

@ -161,9 +161,6 @@ dict set params DMA_TAG_WIDTH "16"
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
dict set params RAM_PIPELINE "2"
# PCIe interface configuration
dict set params PCIE_TAG_COUNT "256"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]

3
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl
View File

@ -161,9 +161,6 @@ dict set params DMA_TAG_WIDTH "16"
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
dict set params RAM_PIPELINE "2"
# PCIe interface configuration
dict set params PCIE_TAG_COUNT "256"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
View File

@ -140,7 +140,6 @@ module fpga #
parameter AXIS_PCIE_DATA_WIDTH = 512,
parameter PF_COUNT = 1,
parameter VF_COUNT = 0,
parameter PCIE_TAG_COUNT = 256,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
@ -322,6 +321,7 @@ parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512;
parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512;
parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512;
parameter RQ_SEQ_NUM_WIDTH = 6;
parameter PCIE_TAG_COUNT = 256;
// Ethernet interface configuration
parameter AXIS_ETH_DATA_WIDTH = 512;

3
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl
View File

@ -173,9 +173,6 @@ dict set params DMA_TAG_WIDTH "16"
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
dict set params RAM_PIPELINE "2"
# PCIe interface configuration
dict set params PCIE_TAG_COUNT "256"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]

3
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl
View File

@ -173,9 +173,6 @@ dict set params DMA_TAG_WIDTH "16"
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
dict set params RAM_PIPELINE "2"
# PCIe interface configuration
dict set params PCIE_TAG_COUNT "256"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]

3
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl
View File

@ -173,9 +173,6 @@ dict set params DMA_TAG_WIDTH "16"
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
dict set params RAM_PIPELINE "2"
# PCIe interface configuration
dict set params PCIE_TAG_COUNT "256"
# Interrupt configuration
dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -143,7 +143,6 @@ module fpga #
parameter AXIS_PCIE_DATA_WIDTH = 512,
parameter PF_COUNT = 1,
parameter VF_COUNT = 0,
parameter PCIE_TAG_COUNT = 256,
// Interrupt configuration
parameter IRQ_INDEX_WIDTH = EVENT_QUEUE_INDEX_WIDTH,
@ -327,6 +326,7 @@ parameter RQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512;
parameter CQ_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512;
parameter CC_STRADDLE = AXIS_PCIE_DATA_WIDTH >= 512;
parameter RQ_SEQ_NUM_WIDTH = 6;
parameter PCIE_TAG_COUNT = 256;
// Ethernet interface configuration
parameter XGMII_DATA_WIDTH = 64;