Add FPGA ID register

fpga/common/tb/mqnic.py

@@ -60,6 +60,8 @@ MQNIC_REG_IF_COUNT               = 0x0020
 MQNIC_REG_IF_STRIDE              = 0x0024
 MQNIC_REG_IF_CSR_OFFSET          = 0x002C
 
+MQNIC_REG_FPGA_ID                = 0x0040
+
 MQNIC_REG_GPIO_OUT               = 0x0100
 MQNIC_REG_GPIO_IN                = 0x0104
 

fpga/mqnic/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v

@@ -276,6 +276,7 @@ parameter FW_ID = 32'd0;
 parameter FW_VER = {16'd0, 16'd1};
 parameter BOARD_ID = {16'h4144, 16'h9003};
 parameter BOARD_VER = {16'd0, 16'd1};
+parameter FPGA_ID = 32'h4B39093;
 
 // Structural parameters
 parameter IF_COUNT = 2;
@@ -657,6 +658,7 @@ always @(posedge clk_250mhz) begin
             16'h0020: axil_csr_rdata_reg <= IF_COUNT;   // if_count
             16'h0024: axil_csr_rdata_reg <= 2**IF_AXIL_ADDR_WIDTH; // if_stride
             16'h002C: axil_csr_rdata_reg <= 2**AXIL_CSR_ADDR_WIDTH; // if_csr_offset
+            16'h0040: axil_csr_rdata_reg <= FPGA_ID;    // fpga_id
             // GPIO
             16'h0100: begin
                 // GPIO out

fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v

@@ -276,6 +276,7 @@ parameter FW_ID = 32'd0;
 parameter FW_VER = {16'd0, 16'd1};
 parameter BOARD_ID = {16'h4144, 16'h9003};
 parameter BOARD_VER = {16'd0, 16'd1};
+parameter FPGA_ID = 32'h4B39093;
 
 // Structural parameters
 parameter IF_COUNT = 2;
@@ -657,6 +658,7 @@ always @(posedge clk_250mhz) begin
             16'h0020: axil_csr_rdata_reg <= IF_COUNT;   // if_count
             16'h0024: axil_csr_rdata_reg <= 2**IF_AXIL_ADDR_WIDTH; // if_stride
             16'h002C: axil_csr_rdata_reg <= 2**AXIL_CSR_ADDR_WIDTH; // if_csr_offset
+            16'h0040: axil_csr_rdata_reg <= FPGA_ID;    // fpga_id
             // GPIO
             16'h0100: begin
                 // GPIO out

fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v

@@ -201,6 +201,7 @@ parameter FW_ID = 32'd0;
 parameter FW_VER = {16'd0, 16'd1};
 parameter BOARD_ID = {16'h1ce4, 16'h0003};
 parameter BOARD_VER = {16'd0, 16'd1};
+parameter FPGA_ID = 32'h3823093;
 
 // Structural parameters
 parameter IF_COUNT = 2;
@@ -606,6 +607,7 @@ always @(posedge clk_250mhz) begin
             16'h0020: axil_csr_rdata_reg <= IF_COUNT;   // if_count
             16'h0024: axil_csr_rdata_reg <= 2**IF_AXIL_ADDR_WIDTH; // if_stride
             16'h002C: axil_csr_rdata_reg <= 2**AXIL_CSR_ADDR_WIDTH; // if_csr_offset
+            16'h0040: axil_csr_rdata_reg <= FPGA_ID;    // fpga_id
             // GPIO
             16'h0100: begin
                 // GPIO out

fpga/mqnic/ExaNIC_X25/fpga_10g/rtl/fpga_core.v

@@ -201,6 +201,7 @@ parameter FW_ID = 32'd0;
 parameter FW_VER = {16'd0, 16'd1};
 parameter BOARD_ID = {16'h1ce4, 16'h0009};
 parameter BOARD_VER = {16'd0, 16'd1};
+parameter FPGA_ID = 32'h4A63093;
 
 // Structural parameters
 parameter IF_COUNT = 2;
@@ -606,6 +607,7 @@ always @(posedge clk_250mhz) begin
             16'h0020: axil_csr_rdata_reg <= IF_COUNT;   // if_count
             16'h0024: axil_csr_rdata_reg <= 2**IF_AXIL_ADDR_WIDTH; // if_stride
             16'h002C: axil_csr_rdata_reg <= 2**AXIL_CSR_ADDR_WIDTH; // if_csr_offset
+            16'h0040: axil_csr_rdata_reg <= FPGA_ID;    // fpga_id
             // GPIO
             16'h0100: begin
                 // GPIO out

fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v

@@ -229,6 +229,7 @@ parameter FW_ID = 32'd0;
 parameter FW_VER = {16'd0, 16'd1};
 parameter BOARD_ID = {16'h10ee, 16'h806c};
 parameter BOARD_VER = {16'd0, 16'd1};
+parameter FPGA_ID = 32'h3842093;
 
 // Structural parameters
 parameter IF_COUNT = 1;
@@ -638,6 +639,7 @@ always @(posedge clk_250mhz) begin
             16'h0020: axil_csr_rdata_reg <= IF_COUNT;   // if_count
             16'h0024: axil_csr_rdata_reg <= 2**IF_AXIL_ADDR_WIDTH; // if_stride
             16'h002C: axil_csr_rdata_reg <= 2**AXIL_CSR_ADDR_WIDTH; // if_csr_offset
+            16'h0040: axil_csr_rdata_reg <= FPGA_ID;    // fpga_id
             // GPIO
             16'h0100: begin
                 // GPIO out

fpga/mqnic/VCU118/fpga_10g/rtl/fpga_core.v

@@ -266,6 +266,7 @@ parameter FW_ID = 32'd0;
 parameter FW_VER = {16'd0, 16'd1};
 parameter BOARD_ID = {16'h10ee, 16'h9076};
 parameter BOARD_VER = {16'd0, 16'd1};
+parameter FPGA_ID = 32'h4B31093;
 
 // Structural parameters
 parameter IF_COUNT = 2;
@@ -641,6 +642,7 @@ always @(posedge clk_250mhz) begin
             16'h0020: axil_csr_rdata_reg <= IF_COUNT;   // if_count
             16'h0024: axil_csr_rdata_reg <= 2**IF_AXIL_ADDR_WIDTH; // if_stride
             16'h002C: axil_csr_rdata_reg <= 2**AXIL_CSR_ADDR_WIDTH; // if_csr_offset
+            16'h0040: axil_csr_rdata_reg <= FPGA_ID;    // fpga_id
             // GPIO
             16'h0100: begin
                 // GPIO out

fpga/mqnic_tdma/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v

@@ -276,6 +276,7 @@ parameter FW_ID = 32'd0;
 parameter FW_VER = {16'd0, 16'd1};
 parameter BOARD_ID = {16'h4144, 16'h9003};
 parameter BOARD_VER = {16'd0, 16'd1};
+parameter FPGA_ID = 32'h4B39093;
 
 // Structural parameters
 parameter IF_COUNT = 2;
@@ -657,6 +658,7 @@ always @(posedge clk_250mhz) begin
             16'h0020: axil_csr_rdata_reg <= IF_COUNT;   // if_count
             16'h0024: axil_csr_rdata_reg <= 2**IF_AXIL_ADDR_WIDTH; // if_stride
             16'h002C: axil_csr_rdata_reg <= 2**AXIL_CSR_ADDR_WIDTH; // if_csr_offset
+            16'h0040: axil_csr_rdata_reg <= FPGA_ID;    // fpga_id
             // GPIO
             16'h0100: begin
                 // GPIO out

fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v

@@ -201,6 +201,7 @@ parameter FW_ID = 32'd0;
 parameter FW_VER = {16'd0, 16'd1};
 parameter BOARD_ID = {16'h1ce4, 16'h0003};
 parameter BOARD_VER = {16'd0, 16'd1};
+parameter FPGA_ID = 32'h3823093;
 
 // Structural parameters
 parameter IF_COUNT = 2;
@@ -606,6 +607,7 @@ always @(posedge clk_250mhz) begin
             16'h0020: axil_csr_rdata_reg <= IF_COUNT;   // if_count
             16'h0024: axil_csr_rdata_reg <= 2**IF_AXIL_ADDR_WIDTH; // if_stride
             16'h002C: axil_csr_rdata_reg <= 2**AXIL_CSR_ADDR_WIDTH; // if_csr_offset
+            16'h0040: axil_csr_rdata_reg <= FPGA_ID;    // fpga_id
             // GPIO
             16'h0100: begin
                 // GPIO out

fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v

@@ -229,6 +229,7 @@ parameter FW_ID = 32'd0;
 parameter FW_VER = {16'd0, 16'd1};
 parameter BOARD_ID = {16'h10ee, 16'h806c};
 parameter BOARD_VER = {16'd0, 16'd1};
+parameter FPGA_ID = 32'h3842093;
 
 // Structural parameters
 parameter IF_COUNT = 1;
@@ -638,6 +639,7 @@ always @(posedge clk_250mhz) begin
             16'h0020: axil_csr_rdata_reg <= IF_COUNT;   // if_count
             16'h0024: axil_csr_rdata_reg <= 2**IF_AXIL_ADDR_WIDTH; // if_stride
             16'h002C: axil_csr_rdata_reg <= 2**AXIL_CSR_ADDR_WIDTH; // if_csr_offset
+            16'h0040: axil_csr_rdata_reg <= FPGA_ID;    // fpga_id
             // GPIO
             16'h0100: begin
                 // GPIO out

fpga/mqnic_tdma/VCU118/fpga_10g/rtl/fpga_core.v

@@ -266,6 +266,7 @@ parameter FW_ID = 32'd0;
 parameter FW_VER = {16'd0, 16'd1};
 parameter BOARD_ID = {16'h10ee, 16'h9076};
 parameter BOARD_VER = {16'd0, 16'd1};
+parameter FPGA_ID = 32'h4B31093;
 
 // Structural parameters
 parameter IF_COUNT = 2;
@@ -641,6 +642,7 @@ always @(posedge clk_250mhz) begin
             16'h0020: axil_csr_rdata_reg <= IF_COUNT;   // if_count
             16'h0024: axil_csr_rdata_reg <= 2**IF_AXIL_ADDR_WIDTH; // if_stride
             16'h002C: axil_csr_rdata_reg <= 2**AXIL_CSR_ADDR_WIDTH; // if_csr_offset
+            16'h0040: axil_csr_rdata_reg <= FPGA_ID;    // fpga_id
             // GPIO
             16'h0100: begin
                 // GPIO out

modules/mqnic/mqnic_hw.h

@@ -66,6 +66,8 @@ either expressed or implied, of The Regents of the University of California.
 #define MQNIC_REG_IF_STRIDE               0x0024
 #define MQNIC_REG_IF_CSR_OFFSET           0x002C
 
+#define MQNIC_REG_FPGA_ID                 0x0040
+
 #define MQNIC_REG_GPIO_OUT                0x0100
 #define MQNIC_REG_GPIO_IN                 0x0104