diff --git a/example/VCU118/fpga_10g/Makefile b/example/VCU118/fpga_10g/Makefile deleted file mode 100644 index f504bd06f..000000000 --- a/example/VCU118/fpga_10g/Makefile +++ /dev/null @@ -1,25 +0,0 @@ -# Targets -TARGETS:= - -# Subdirectories -SUBDIRS = fpga -SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS)) - -# Rules -.PHONY: all -all: $(SUBDIRS) $(TARGETS) - -.PHONY: $(SUBDIRS) -$(SUBDIRS): - cd $@ && $(MAKE) - -.PHONY: $(SUBDIRS_CLEAN) -$(SUBDIRS_CLEAN): - cd $(@:.clean=) && $(MAKE) clean - -.PHONY: clean -clean: $(SUBDIRS_CLEAN) - -rm -rf $(TARGETS) - -program: - #djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit diff --git a/example/VCU118/fpga_10g/README.md b/example/VCU118/fpga_10g/README.md deleted file mode 100644 index 25d58478b..000000000 --- a/example/VCU118/fpga_10g/README.md +++ /dev/null @@ -1,40 +0,0 @@ -# Verilog Ethernet VCU118 Example Design - -## Introduction - -This example design targets the Xilinx VCU118 FPGA board. - -The design by default listens to UDP port 1234 at IP address 192.168.1.128 and -will echo back any packets received. The design will also respond correctly -to ARP requests. The design also enables the gigabit Ethernet interface for -testing with a QSFP loopback adapter. - -* FPGA: xcvu9p-flga2104-2L-e -* PHY: 10G BASE-R PHY IP core and internal GTY transceiver - -## How to build - -Run make to build. Ensure that the Xilinx Vivado toolchain components are -in PATH. - -## How to test - -Run make program to program the VCU118 board with Vivado. Then run - - netcat -u 192.168.1.128 1234 - -to open a UDP connection to port 1234. Any text entered into netcat will be -echoed back after pressing enter. - -It is also possible to use hping to test the design by running - - hping 192.168.1.128 -2 -p 1234 -d 1024 - -Note that the gigabit PHY is also enabled for debugging. The gigabit port can -be inserted into the 10G data path between the 10G MAC and 10G PHY so that the -10G interface can be tested with a QSFP loopback adapter. Turn on SW12.1 to -insert the gigabit port into the 10G data path, or off to bypass the gigabit -port. Turn on SW12.2 to place the port in the TX path or off to place the -port in the RX path. - - diff --git a/example/VCU118/fpga_10g/common/vivado.mk b/example/VCU118/fpga_10g/common/vivado.mk deleted file mode 100644 index 1402e2382..000000000 --- a/example/VCU118/fpga_10g/common/vivado.mk +++ /dev/null @@ -1,137 +0,0 @@ -################################################################### -# -# Xilinx Vivado FPGA Makefile -# -# Copyright (c) 2016 Alex Forencich -# -################################################################### -# -# Parameters: -# FPGA_TOP - Top module name -# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale) -# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e) -# SYN_FILES - space-separated list of source files -# INC_FILES - space-separated list of include files -# XDC_FILES - space-separated list of timing constraint files -# XCI_FILES - space-separated list of IP XCI files -# -# Example: -# -# FPGA_TOP = fpga -# FPGA_FAMILY = VirtexUltrascale -# FPGA_DEVICE = xcvu095-ffva2104-2-e -# SYN_FILES = rtl/fpga.v -# XDC_FILES = fpga.xdc -# XCI_FILES = ip/pcspma.xci -# include ../common/vivado.mk -# -################################################################### - -# phony targets -.PHONY: fpga vivado tmpclean clean distclean - -# prevent make from deleting intermediate files and reports -.PRECIOUS: %.xpr %.bit %.mcs %.prm -.SECONDARY: - -CONFIG ?= config.mk --include ../$(CONFIG) - -FPGA_TOP ?= fpga -PROJECT ?= $(FPGA_TOP) - -SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p)) - -ifdef XDC_FILES - XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p)) -else - XDC_FILES_REL = $(PROJECT).xdc -endif - -################################################################### -# Main Targets -# -# all: build everything -# clean: remove output files and project files -################################################################### - -all: fpga - -fpga: $(PROJECT).bit - -vivado: $(PROJECT).xpr - vivado $(PROJECT).xpr - -tmpclean:: - -rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v - -rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl - -clean:: tmpclean - -rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl - -rm -rf *_utilization.rpt *_utilization_hierarchical.rpt - -distclean:: clean - -rm -rf rev - -################################################################### -# Target implementations -################################################################### - -# Vivado project file -create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL) - rm -rf defines.v - touch defines.v - for x in $(DEFS); do echo '`define' $$x >> defines.v; done - echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@ - echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@ - echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@ - echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@ - for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done - for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) - echo "open_project -quiet $(PROJECT).xpr" > $@ - for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done - -$(PROJECT).xpr: create_project.tcl update_config.tcl - vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x) - -# synthesis run -$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr - echo "open_project $(PROJECT).xpr" > run_synth.tcl - echo "reset_run synth_1" >> run_synth.tcl - echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl - echo "wait_on_run synth_1" >> run_synth.tcl - vivado -nojournal -nolog -mode batch -source run_synth.tcl - -# implementation run -$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp - echo "open_project $(PROJECT).xpr" > run_impl.tcl - echo "reset_run impl_1" >> run_impl.tcl - echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl - echo "wait_on_run impl_1" >> run_impl.tcl - echo "open_run impl_1" >> run_impl.tcl - echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl - echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl - vivado -nojournal -nolog -mode batch -source run_impl.tcl - -# bit file -$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp - echo "open_project $(PROJECT).xpr" > generate_bit.tcl - echo "open_run impl_1" >> generate_bit.tcl - echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl - echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl - vivado -nojournal -nolog -mode batch -source generate_bit.tcl - ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit . - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi - mkdir -p rev - COUNT=100; \ - while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \ - do COUNT=$$((COUNT+1)); done; \ - cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \ - if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi diff --git a/example/VCU118/fpga_10g/fpga.xdc b/example/VCU118/fpga_10g/fpga.xdc deleted file mode 100644 index 6ad2c538a..000000000 --- a/example/VCU118/fpga_10g/fpga.xdc +++ /dev/null @@ -1,598 +0,0 @@ -# XDC constraints for the Xilinx VCU118 board -# part: xcvu9p-flga2104-2L-e - -# General configuration -set_property CFGBVS GND [current_design] -set_property CONFIG_VOLTAGE 1.8 [current_design] -set_property BITSTREAM.GENERAL.COMPRESS true [current_design] -set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design] -set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] -set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design] -set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] - -# System clocks -# 300 MHz -#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_p] -#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_n] -#create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p] - -# 250 MHz -#set_property -dict {LOC E12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_p] -#set_property -dict {LOC D12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_n] -#create_clock -period 4 -name clk_250mhz_1 [get_ports clk_250mhz_1_p] - -#set_property -dict {LOC AW26 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_p] -#set_property -dict {LOC AW27 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_n] -#create_clock -period 4 -name clk_250mhz_2 [get_ports clk_250mhz_2_p] - -# 125 MHz -set_property -dict {LOC AY24 IOSTANDARD LVDS} [get_ports clk_125mhz_p] -set_property -dict {LOC AY23 IOSTANDARD LVDS} [get_ports clk_125mhz_n] -create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] - -# 90 MHz -#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz] -#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz] - -# LEDs -set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] -set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] -set_property -dict {LOC AY30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}] -set_property -dict {LOC BB32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[3]}] -set_property -dict {LOC BF32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[4]}] -set_property -dict {LOC AU37 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[5]}] -set_property -dict {LOC AV36 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[6]}] -set_property -dict {LOC BA37 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[7]}] - -set_false_path -to [get_ports {led[*]}] -set_output_delay 0 [get_ports {led[*]}] - -# Reset button -set_property -dict {LOC L19 IOSTANDARD LVCMOS12} [get_ports reset] - -set_false_path -from [get_ports {reset}] -set_input_delay 0 [get_ports {reset}] - -# Push buttons -set_property -dict {LOC BB24 IOSTANDARD LVCMOS18} [get_ports btnu] -set_property -dict {LOC BF22 IOSTANDARD LVCMOS18} [get_ports btnl] -set_property -dict {LOC BE22 IOSTANDARD LVCMOS18} [get_ports btnd] -set_property -dict {LOC BE23 IOSTANDARD LVCMOS18} [get_ports btnr] -set_property -dict {LOC BD23 IOSTANDARD LVCMOS18} [get_ports btnc] - -set_false_path -from [get_ports {btnu btnl btnd btnr btnc}] -set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}] - -# DIP switches -set_property -dict {LOC B17 IOSTANDARD LVCMOS12} [get_ports {sw[0]}] -set_property -dict {LOC G16 IOSTANDARD LVCMOS12} [get_ports {sw[1]}] -set_property -dict {LOC J16 IOSTANDARD LVCMOS12} [get_ports {sw[2]}] -set_property -dict {LOC D21 IOSTANDARD LVCMOS12} [get_ports {sw[3]}] - -set_false_path -from [get_ports {sw[*]}] -set_input_delay 0 [get_ports {sw[*]}] - -# PMOD0 -#set_property -dict {LOC AY14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}] -#set_property -dict {LOC AY15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}] -#set_property -dict {LOC AW15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}] -#set_property -dict {LOC AV15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}] -#set_property -dict {LOC AV16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}] -#set_property -dict {LOC AU16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}] -#set_property -dict {LOC AT15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}] -#set_property -dict {LOC AT16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}] - -#set_false_path -to [get_ports {pmod0[*]}] -#set_output_delay 0 [get_ports {pmod0[*]}] - -# PMOD1 -#set_property -dict {LOC N28 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}] -#set_property -dict {LOC M30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}] -#set_property -dict {LOC N30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}] -#set_property -dict {LOC P30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}] -#set_property -dict {LOC P29 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}] -#set_property -dict {LOC L31 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}] -#set_property -dict {LOC M31 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}] -#set_property -dict {LOC R29 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}] - -#set_false_path -to [get_ports {pmod1[*]}] -#set_output_delay 0 [get_ports {pmod1[*]}] - -# UART -set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd] -set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports uart_rxd] -set_property -dict {LOC BB22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rts] -set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports uart_cts] - -set_false_path -to [get_ports {uart_txd uart_rts}] -set_output_delay 0 [get_ports {uart_txd uart_rts}] -set_false_path -from [get_ports {uart_rxd uart_cts}] -set_input_delay 0 [get_ports {uart_rxd uart_cts}] - -# Gigabit Ethernet SGMII PHY -set_property -dict {LOC AU24 IOSTANDARD LVDS} [get_ports phy_sgmii_rx_p] -set_property -dict {LOC AV24 IOSTANDARD LVDS} [get_ports phy_sgmii_rx_n] -set_property -dict {LOC AU21 IOSTANDARD LVDS} [get_ports phy_sgmii_tx_p] -set_property -dict {LOC AV21 IOSTANDARD LVDS} [get_ports phy_sgmii_tx_n] -set_property -dict {LOC AT22 IOSTANDARD LVDS} [get_ports phy_sgmii_clk_p] -set_property -dict {LOC AU22 IOSTANDARD LVDS} [get_ports phy_sgmii_clk_n] -set_property -dict {LOC BA21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_reset_n] -set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports phy_int_n] -set_property -dict {LOC AR23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdio] -set_property -dict {LOC AV23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdc] - -# 625 MHz ref clock from SGMII PHY -#create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p] - -set_false_path -to [get_ports {phy_reset_n phy_mdio phy_mdc}] -set_output_delay 0 [get_ports {phy_reset_n phy_mdio phy_mdc}] -set_false_path -from [get_ports {phy_int_n phy_mdio}] -set_input_delay 0 [get_ports {phy_int_n phy_mdio}] - -# QSFP28 Interfaces -set_property -dict {LOC Y2 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC Y1 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V6 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC W4 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC W3 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V2 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC V1 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC P7 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC P6 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC U4 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC U3 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC M6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12 -set_property -dict {LOC W9 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U38.4 -set_property -dict {LOC W8 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U38.5 -#set_property -dict {LOC U9 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U57.28 -#set_property -dict {LOC U8 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U57.29 -#set_property -dict {LOC AM23 IOSTANDARD LVDS} [get_ports qsfp1_recclk_p] ;# to U57.16 -#set_property -dict {LOC AM22 IOSTANDARD LVDS} [get_ports qsfp1_recclk_n] ;# to U57.17 -set_property -dict {LOC AM21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell] -set_property -dict {LOC BA22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] -set_property -dict {LOC AL21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_modprsl] -set_property -dict {LOC AP21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_intl] -set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode] - -# 156.25 MHz MGT reference clock -create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p] - -set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}] -set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}] -set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}] -set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}] - -set_property -dict {LOC T2 } [get_ports qsfp2_rx1_p] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC T1 } [get_ports qsfp2_rx1_n] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R4 } [get_ports qsfp2_rx2_p] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R3 } [get_ports qsfp2_rx2_n] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC K7 } [get_ports qsfp2_tx2_p] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC K6 } [get_ports qsfp2_tx2_n] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC P2 } [get_ports qsfp2_rx3_p] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC P1 } [get_ports qsfp2_rx3_n] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC J5 } [get_ports qsfp2_tx3_p] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC J4 } [get_ports qsfp2_tx3_n] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13 -set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13 -set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14 -#set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35 -#set_property -dict {LOC N8 } [get_ports qsfp2_mgt_refclk_1_n] ;# MGTREFCLK1N_232 from U57.34 -#set_property -dict {LOC AP23 IOSTANDARD LVDS} [get_ports qsfp2_recclk_p] ;# to U57.12 -#set_property -dict {LOC AP22 IOSTANDARD LVDS} [get_ports qsfp2_recclk_n] ;# to U57.13 -set_property -dict {LOC AN23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_modsell] -set_property -dict {LOC AY22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_resetl] -set_property -dict {LOC AN24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_modprsl] -set_property -dict {LOC AT21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_intl] -set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_lpmode] - -# 156.25 MHz MGT reference clock -create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p] - -set_false_path -to [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}] -set_output_delay 0 [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}] -set_false_path -from [get_ports {qsfp2_modprsl qsfp2_intl}] -set_input_delay 0 [get_ports {qsfp2_modprsl qsfp2_intl}] - -# I2C interface -set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl] -set_property -dict {LOC AL24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_sda] - -set_false_path -to [get_ports {i2c_sda i2c_scl}] -set_output_delay 0 [get_ports {i2c_sda i2c_scl}] -set_false_path -from [get_ports {i2c_sda i2c_scl}] -set_input_delay 0 [get_ports {i2c_sda i2c_scl}] - -# PCIe Interface -#set_property -dict {LOC AA4 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AA3 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC Y7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC Y6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AB7 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AB6 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AC4 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AC3 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8 -#set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AN5 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AN4 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7 -#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AR5 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AR4 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AU5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AU4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6 -#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AW5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AW4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BA5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BA4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AY2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AY1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BC5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BC4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BB2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BB1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BE5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC BE4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5 -#set_property -dict {LOC AC9 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_227 -#set_property -dict {LOC AC8 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_227 -#set_property -dict {LOC AL9 } [get_ports pcie_refclk_2_p] ;# MGTREFCLK0P_225 -#set_property -dict {LOC AL8 } [get_ports pcie_refclk_2_n] ;# MGTREFCLK0N_225 -#set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n] - -# 100 MHz MGT reference clock -#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p] -#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p] - -#set_false_path -from [get_ports {pcie_reset_n}] -#set_input_delay 0 [get_ports {pcie_reset_n}] - -# DDR4 C1 -# 5x MT40A256M16GE-075E -#set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] -#set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] -#set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] -#set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] -#set_property -dict {LOC C15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] -#set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] -#set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] -#set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] -#set_property -dict {LOC A16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] -#set_property -dict {LOC B12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] -#set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] -#set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] -#set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] -#set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] -#set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] -#set_property -dict {LOC H15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] -#set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] -#set_property -dict {LOC G15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] -#set_property -dict {LOC G13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] -#set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] -#set_property -dict {LOC F14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] -#set_property -dict {LOC E14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] -#set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] -#set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] -#set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] -#set_property -dict {LOC C8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] -#set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] -#set_property -dict {LOC N20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] -#set_property -dict {LOC R17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] -#set_property -dict {LOC A20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}] - -#set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] ;# U60.G2 DQL0 -#set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] ;# U60.F7 DQL1 -#set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] ;# U60.H3 DQL2 -#set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] ;# U60.H7 DQL3 -#set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] ;# U60.H2 DQL4 -#set_property -dict {LOC G12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] ;# U60.H8 DQL5 -#set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] ;# U60.J3 DQL6 -#set_property -dict {LOC D9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] ;# U60.J7 DQL7 -#set_property -dict {LOC R19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] ;# U60.A3 DQU0 -#set_property -dict {LOC P19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] ;# U60.B8 DQU1 -#set_property -dict {LOC M18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] ;# U60.C3 DQU2 -#set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] ;# U60.C7 DQU3 -#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] ;# U60.C2 DQU4 -#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] ;# U60.C8 DQU5 -#set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] ;# U60.D3 DQU6 -#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] ;# U60.D7 DQU7 -#set_property -dict {LOC D11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] ;# U60.G3 DQSL_T -#set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] ;# U60.F3 DQSL_C -#set_property -dict {LOC P17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] ;# U60.B7 DQSU_T -#set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] ;# U60.A7 DQSU_C -#set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] ;# U60.E7 DML_B/DBIL_B -#set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] ;# U60.E2 DMU_B/DBIU_B - -#set_property -dict {LOC L16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] ;# U61.G2 DQL0 -#set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] ;# U61.F7 DQL1 -#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] ;# U61.H3 DQL2 -#set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] ;# U61.H7 DQL3 -#set_property -dict {LOC J17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] ;# U61.H2 DQL4 -#set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] ;# U61.H8 DQL5 -#set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] ;# U61.J3 DQL6 -#set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] ;# U61.J7 DQL7 -#set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] ;# U61.A3 DQU0 -#set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] ;# U61.B8 DQU1 -#set_property -dict {LOC E19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] ;# U61.C3 DQU2 -#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] ;# U61.C7 DQU3 -#set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] ;# U61.C2 DQU4 -#set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] ;# U61.C8 DQU5 -#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] ;# U61.D3 DQU6 -#set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] ;# U61.D7 DQU7 -#set_property -dict {LOC K19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] ;# U61.G3 DQSL_T -#set_property -dict {LOC J19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] ;# U61.F3 DQSL_C -#set_property -dict {LOC F16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] ;# U61.B7 DQSU_T -#set_property -dict {LOC E16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] ;# U61.A7 DQSU_C -#set_property -dict {LOC K17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] ;# U61.E7 DML_B/DBIL_B -#set_property -dict {LOC G18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] ;# U61.E2 DMU_B/DBIU_B - -#set_property -dict {LOC D17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] ;# U62.G2 DQL0 -#set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] ;# U62.F7 DQL1 -#set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] ;# U62.H3 DQL2 -#set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] ;# U62.H7 DQL3 -#set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] ;# U62.H2 DQL4 -#set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] ;# U62.H8 DQL5 -#set_property -dict {LOC C20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] ;# U62.J3 DQL6 -#set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] ;# U62.J7 DQL7 -#set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] ;# U62.A3 DQU0 -#set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] ;# U62.B8 DQU1 -#set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] ;# U62.C3 DQU2 -#set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] ;# U62.C7 DQU3 -#set_property -dict {LOC R22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] ;# U62.C2 DQU4 -#set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] ;# U62.C8 DQU5 -#set_property -dict {LOC T23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] ;# U62.D3 DQU6 -#set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] ;# U62.D7 DQU7 -#set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] ;# U62.G3 DQSL_T -#set_property -dict {LOC A18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] ;# U62.F3 DQSL_C -#set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] ;# U62.B7 DQSU_T -#set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] ;# U62.A7 DQSU_C -#set_property -dict {LOC B18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] ;# U62.E7 DML_B/DBIL_B -#set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] ;# U62.E2 DMU_B/DBIU_B - -#set_property -dict {LOC K24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] ;# U63.G2 DQL0 -#set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] ;# U63.F7 DQL1 -#set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] ;# U63.H3 DQL2 -#set_property -dict {LOC L21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] ;# U63.H7 DQL3 -#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] ;# U63.H2 DQL4 -#set_property -dict {LOC J21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] ;# U63.H8 DQL5 -#set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] ;# U63.J3 DQL6 -#set_property -dict {LOC J22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] ;# U63.J7 DQL7 -#set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] ;# U63.A3 DQU0 -#set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] ;# U63.B8 DQU1 -#set_property -dict {LOC E23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] ;# U63.C3 DQU2 -#set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] ;# U63.C7 DQU3 -#set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] ;# U63.C2 DQU4 -#set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] ;# U63.C8 DQU5 -#set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] ;# U63.D3 DQU6 -#set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] ;# U63.D7 DQU7 -#set_property -dict {LOC M20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] ;# U63.G3 DQSL_T -#set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] ;# U63.F3 DQSL_C -#set_property -dict {LOC H24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] ;# U63.B7 DQSU_T -#set_property -dict {LOC G23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] ;# U63.A7 DQSU_C -#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] ;# U63.E7 DML_B/DBIL_B -#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] ;# U63.E2 DMU_B/DBIU_B - -#set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] ;# U64.G2 DQL0 -#set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] ;# U64.F7 DQL1 -#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] ;# U64.H3 DQL2 -#set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] ;# U64.H7 DQL3 -#set_property -dict {LOC B23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] ;# U64.H2 DQL4 -#set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] ;# U64.H8 DQL5 -#set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] ;# U64.J3 DQL6 -#set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] ;# U64.J7 DQL7 -#set_property -dict {LOC D7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[72]}] ;# U64.A3 DQU0 -#set_property -dict {LOC C7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[73]}] ;# U64.B8 DQU1 -#set_property -dict {LOC B8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[74]}] ;# U64.C3 DQU2 -#set_property -dict {LOC B7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[75]}] ;# U64.C7 DQU3 -#set_property -dict {LOC C10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[76]}] ;# U64.C2 DQU4 -#set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[77]}] ;# U64.C8 DQU5 -#set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[78]}] ;# U64.D3 DQU6 -#set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[79]}] ;# U64.D7 DQU7 -#set_property -dict {LOC D22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] ;# U64.G3 DQSL_T -#set_property -dict {LOC C22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] ;# U64.F3 DQSL_C -#set_property -dict {LOC A9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] ;# U64.B7 DQSU_T -#set_property -dict {LOC A8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] ;# U64.A7 DQSU_C -#set_property -dict {LOC E24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] ;# U64.E7 DML_B/DBIL_B -#set_property -dict {LOC C9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[9]}] ;# U64.E2 DMU_B/DBIU_B - -# DDR4 C2 -# 5x MT40A256M16GE-075E -#set_property -dict {LOC AM27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] -#set_property -dict {LOC AL27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] -#set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] -#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] -#set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] -#set_property -dict {LOC AM28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] -#set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] -#set_property -dict {LOC AP27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] -#set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] -#set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] -#set_property -dict {LOC AR28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] -#set_property -dict {LOC AR27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] -#set_property -dict {LOC AV25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] -#set_property -dict {LOC AT25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] -#set_property -dict {LOC AV28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] -#set_property -dict {LOC AU26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] -#set_property -dict {LOC AV26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] -#set_property -dict {LOC AR25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] -#set_property -dict {LOC AU28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] -#set_property -dict {LOC AU27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] -#set_property -dict {LOC AT26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}] -#set_property -dict {LOC AT27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}] -#set_property -dict {LOC AW28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}] -#set_property -dict {LOC AY29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}] -#set_property -dict {LOC AN25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] -#set_property -dict {LOC BB29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}] -#set_property -dict {LOC BF29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] -#set_property -dict {LOC BD35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] -#set_property -dict {LOC AR29 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}] -#set_property -dict {LOC AY35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_ten}] - -#set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] ;# U135.G2 DQL0 -#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] ;# U135.F7 DQL1 -#set_property -dict {LOC BD32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] ;# U135.H3 DQL2 -#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] ;# U135.H7 DQL3 -#set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] ;# U135.H2 DQL4 -#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] ;# U135.H8 DQL5 -#set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] ;# U135.J3 DQL6 -#set_property -dict {LOC BD31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] ;# U135.J7 DQL7 -#set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] ;# U135.A3 DQU0 -#set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] ;# U135.B8 DQU1 -#set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] ;# U135.C3 DQU2 -#set_property -dict {LOC BA31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] ;# U135.C7 DQU3 -#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] ;# U135.C2 DQU4 -#set_property -dict {LOC AW32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] ;# U135.C8 DQU5 -#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] ;# U135.D3 DQU6 -#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] ;# U135.D7 DQU7 -#set_property -dict {LOC BF30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] ;# U135.G3 DQSL_T -#set_property -dict {LOC BF31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] ;# U135.F3 DQSL_C -#set_property -dict {LOC AY34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] ;# U135.B7 DQSU_T -#set_property -dict {LOC BA34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] ;# U135.A7 DQSU_C -#set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] ;# U135.E7 DML_B/DBIL_B -#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] ;# U135.E2 DMU_B/DBIU_B - -#set_property -dict {LOC AV30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] ;# U136.G2 DQL0 -#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] ;# U136.F7 DQL1 -#set_property -dict {LOC AU33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] ;# U136.H3 DQL2 -#set_property -dict {LOC AU34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] ;# U136.H7 DQL3 -#set_property -dict {LOC AT31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] ;# U136.H2 DQL4 -#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] ;# U136.H8 DQL5 -#set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] ;# U136.J3 DQL6 -#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] ;# U136.J7 DQL7 -#set_property -dict {LOC AR33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] ;# U136.A3 DQU0 -#set_property -dict {LOC AT34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] ;# U136.B8 DQU1 -#set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] ;# U136.C3 DQU2 -#set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] ;# U136.C7 DQU3 -#set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] ;# U136.C2 DQU4 -#set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] ;# U136.C8 DQU5 -#set_property -dict {LOC AN30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] ;# U136.D3 DQU6 -#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] ;# U136.D7 DQU7 -#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] ;# U136.G3 DQSL_T -#set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] ;# U136.F3 DQSL_C -#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] ;# U136.B7 DQSU_T -#set_property -dict {LOC AP32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] ;# U136.A7 DQSU_C -#set_property -dict {LOC AV33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] ;# U136.E7 DML_B/DBIL_B -#set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] ;# U136.E2 DMU_B/DBIU_B - -#set_property -dict {LOC BE34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] ;# U137.G2 DQL0 -#set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] ;# U137.F7 DQL1 -#set_property -dict {LOC BC35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] ;# U137.H3 DQL2 -#set_property -dict {LOC BC36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] ;# U137.H7 DQL3 -#set_property -dict {LOC BD36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] ;# U137.H2 DQL4 -#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] ;# U137.H8 DQL5 -#set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] ;# U137.J3 DQL6 -#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] ;# U137.J7 DQL7 -#set_property -dict {LOC BD37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] ;# U137.A3 DQU0 -#set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] ;# U137.B8 DQU1 -#set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] ;# U137.C3 DQU2 -#set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] ;# U137.C7 DQU3 -#set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] ;# U137.C2 DQU4 -#set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] ;# U137.C8 DQU5 -#set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] ;# U137.D3 DQU6 -#set_property -dict {LOC BD38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] ;# U137.D7 DQU7 -#set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] ;# U137.G3 DQSL_T -#set_property -dict {LOC BF35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] ;# U137.F3 DQSL_C -#set_property -dict {LOC BE39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] ;# U137.B7 DQSU_T -#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] ;# U137.A7 DQSU_C -#set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] ;# U137.E7 DML_B/DBIL_B -#set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] ;# U137.E2 DMU_B/DBIU_B - -#set_property -dict {LOC BB36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] ;# U138.G2 DQL0 -#set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] ;# U138.F7 DQL1 -#set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] ;# U138.H3 DQL2 -#set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] ;# U138.H7 DQL3 -#set_property -dict {LOC AW40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] ;# U138.H2 DQL4 -#set_property -dict {LOC AY40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] ;# U138.H8 DQL5 -#set_property -dict {LOC AY38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] ;# U138.J3 DQL6 -#set_property -dict {LOC AY39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] ;# U138.J7 DQL7 -#set_property -dict {LOC AW35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] ;# U138.A3 DQU0 -#set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] ;# U138.B8 DQU1 -#set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] ;# U138.C3 DQU2 -#set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] ;# U138.C7 DQU3 -#set_property -dict {LOC AU38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] ;# U138.C2 DQU4 -#set_property -dict {LOC AU39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] ;# U138.C8 DQU5 -#set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] ;# U138.D3 DQU6 -#set_property -dict {LOC AV39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] ;# U138.D7 DQU7 -#set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] ;# U138.G3 DQSL_T -#set_property -dict {LOC BA36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] ;# U138.F3 DQSL_C -#set_property -dict {LOC AW37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] ;# U138.B7 DQSU_T -#set_property -dict {LOC AW38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] ;# U138.A7 DQSU_C -#set_property -dict {LOC AY37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] ;# U138.E7 DML_B/DBIL_B -#set_property -dict {LOC AV35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] ;# U138.E2 DMU_B/DBIU_B - -#set_property -dict {LOC BF26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] ;# U139.G2 DQL0 -#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] ;# U139.F7 DQL1 -#set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] ;# U139.H3 DQL2 -#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] ;# U139.H7 DQL3 -#set_property -dict {LOC BD27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] ;# U139.H2 DQL4 -#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] ;# U139.H8 DQL5 -#set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] ;# U139.J3 DQL6 -#set_property -dict {LOC BD26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] ;# U139.J7 DQL7 -#set_property -dict {LOC BC25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[72]}] ;# U139.A3 DQU0 -#set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[73]}] ;# U139.B8 DQU1 -#set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[74]}] ;# U139.C3 DQU2 -#set_property -dict {LOC BC28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[75]}] ;# U139.C7 DQU3 -#set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[76]}] ;# U139.C2 DQU4 -#set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[77]}] ;# U139.C8 DQU5 -#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[78]}] ;# U139.D3 DQU6 -#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[79]}] ;# U139.D7 DQU7 -#set_property -dict {LOC BE25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] ;# U139.G3 DQSL_T -#set_property -dict {LOC BF25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] ;# U139.F3 DQSL_C -#set_property -dict {LOC BA26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] ;# U139.B7 DQSU_T -#set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] ;# U139.A7 DQSU_C -#set_property -dict {LOC BE29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] ;# U139.E7 DML_B/DBIL_B -#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[9]}] ;# U139.E2 DMU_B/DBIU_B - -# QSPI flash -#set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}] -#set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}] -#set_property -dict {LOC AN20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[2]}] -#set_property -dict {LOC AP20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[3]}] -#set_property -dict {LOC BF16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_cs}] - -#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}] -#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}] -#set_false_path -from [get_ports {qspi_1_dq}] -#set_input_delay 0 [get_ports {qspi_1_dq}] diff --git a/example/VCU118/fpga_10g/ip/eth_xcvr_gt.tcl b/example/VCU118/fpga_10g/ip/eth_xcvr_gt.tcl deleted file mode 100644 index 7464143a6..000000000 --- a/example/VCU118/fpga_10g/ip/eth_xcvr_gt.tcl +++ /dev/null @@ -1,76 +0,0 @@ -# Copyright (c) 2021 Alex Forencich -# -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -# THE SOFTWARE. - -set base_name {eth_xcvr_gt} - -set preset {GTY-10GBASE-R} - -set freerun_freq {125} -set line_rate {10.3125} -set refclk_freq {156.25} -set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] -set user_data_width {64} -set int_data_width $user_data_width -set extra_ports [list] -set extra_pll_ports [list {qpll0lock_out}] - -set config [dict create] - -dict set config TX_LINE_RATE $line_rate -dict set config TX_REFCLK_FREQUENCY $refclk_freq -dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config TX_USER_DATA_WIDTH $user_data_width -dict set config TX_INT_DATA_WIDTH $int_data_width -dict set config RX_LINE_RATE $line_rate -dict set config RX_REFCLK_FREQUENCY $refclk_freq -dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn -dict set config RX_USER_DATA_WIDTH $user_data_width -dict set config RX_INT_DATA_WIDTH $int_data_width -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {CORE} -dict set config LOCATE_RESET_CONTROLLER {CORE} -dict set config LOCATE_TX_USER_CLOCKING {CORE} -dict set config LOCATE_RX_USER_CLOCKING {CORE} -dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} -dict set config FREERUN_FREQUENCY $freerun_freq -dict set config DISABLE_LOC_XDC {1} - -proc create_gtwizard_ip {name preset config} { - create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name - set ip [get_ips $name] - set_property CONFIG.preset $preset $ip - set config_list {} - dict for {name value} $config { - lappend config_list "CONFIG.${name}" $value - } - set_property -dict $config_list $ip -} - -# variant with channel and common -dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] -dict set config LOCATE_COMMON {CORE} - -create_gtwizard_ip "${base_name}_full" $preset $config - -# variant with channel only -dict set config ENABLE_OPTIONAL_PORTS $extra_ports -dict set config LOCATE_COMMON {EXAMPLE_DESIGN} - -create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.tcl b/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.tcl deleted file mode 100644 index 1a6f641e8..000000000 --- a/example/VCU118/fpga_10g/ip/gig_ethernet_pcs_pma_0.tcl +++ /dev/null @@ -1,13 +0,0 @@ - -create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0 - -set_property -dict [list \ - CONFIG.Standard {SGMII} \ - CONFIG.Physical_Interface {LVDS} \ - CONFIG.Management_Interface {false} \ - CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \ - CONFIG.LvdsRefClk {625} \ - CONFIG.TxLane0_Placement {DIFF_PAIR_2} \ - CONFIG.RxLane0_Placement {DIFF_PAIR_0} \ - CONFIG.Tx_In_Upper_Nibble {0} \ -] [get_ips gig_ethernet_pcs_pma_0] diff --git a/example/VCU118/fpga_10g/lib/eth b/example/VCU118/fpga_10g/lib/eth deleted file mode 120000 index 11a54ed36..000000000 --- a/example/VCU118/fpga_10g/lib/eth +++ /dev/null @@ -1 +0,0 @@ -../../../../ \ No newline at end of file diff --git a/example/VCU118/fpga_10g/rtl/debounce_switch.v b/example/VCU118/fpga_10g/rtl/debounce_switch.v deleted file mode 100644 index 8e93a50c4..000000000 --- a/example/VCU118/fpga_10g/rtl/debounce_switch.v +++ /dev/null @@ -1,93 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes switch and button inputs with a slow sampled shift register - */ -module debounce_switch #( - parameter WIDTH=1, // width of the input and output signals - parameter N=3, // length of shift register - parameter RATE=125000 // clock division factor -)( - input wire clk, - input wire rst, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [23:0] cnt_reg = 24'd0; - -reg [N-1:0] debounce_reg[WIDTH-1:0]; - -reg [WIDTH-1:0] state; - -/* - * The synchronized output is the state register - */ -assign out = state; - -integer k; - -always @(posedge clk or posedge rst) begin - if (rst) begin - cnt_reg <= 0; - state <= 0; - - for (k = 0; k < WIDTH; k = k + 1) begin - debounce_reg[k] <= 0; - end - end else begin - if (cnt_reg < RATE) begin - cnt_reg <= cnt_reg + 24'd1; - end else begin - cnt_reg <= 24'd0; - end - - if (cnt_reg == 24'd0) begin - for (k = 0; k < WIDTH; k = k + 1) begin - debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]}; - end - end - - for (k = 0; k < WIDTH; k = k + 1) begin - if (|debounce_reg[k] == 0) begin - state[k] <= 0; - end else if (&debounce_reg[k] == 1) begin - state[k] <= 1; - end else begin - state[k] <= state[k]; - end - end - end -end - -endmodule - -`resetall diff --git a/example/VCU118/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/example/VCU118/fpga_10g/rtl/eth_xcvr_phy_wrapper.v deleted file mode 100644 index acac5e3f9..000000000 --- a/example/VCU118/fpga_10g/rtl/eth_xcvr_phy_wrapper.v +++ /dev/null @@ -1,299 +0,0 @@ -/* - -Copyright (c) 2021 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * Transceiver and PHY wrapper - */ -module eth_xcvr_phy_wrapper # -( - parameter HAS_COMMON = 1, - parameter DATA_WIDTH = 64, - parameter CTRL_WIDTH = (DATA_WIDTH/8), - parameter HDR_WIDTH = 2, - parameter PRBS31_ENABLE = 0, - parameter TX_SERDES_PIPELINE = 0, - parameter RX_SERDES_PIPELINE = 0, - parameter BITSLIP_HIGH_CYCLES = 1, - parameter BITSLIP_LOW_CYCLES = 8, - parameter COUNT_125US = 125000/6.4 -) -( - input wire xcvr_ctrl_clk, - input wire xcvr_ctrl_rst, - - /* - * Common - */ - output wire xcvr_gtpowergood_out, - - /* - * PLL out - */ - input wire xcvr_gtrefclk00_in, - output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, - - /* - * PLL in - */ - input wire xcvr_qpll0lock_in, - output wire xcvr_qpll0reset_out, - input wire xcvr_qpll0clk_in, - input wire xcvr_qpll0refclk_in, - - /* - * Serial data - */ - output wire xcvr_txp, - output wire xcvr_txn, - input wire xcvr_rxp, - input wire xcvr_rxn, - - /* - * PHY connections - */ - output wire phy_tx_clk, - output wire phy_tx_rst, - input wire [DATA_WIDTH-1:0] phy_xgmii_txd, - input wire [CTRL_WIDTH-1:0] phy_xgmii_txc, - output wire phy_rx_clk, - output wire phy_rx_rst, - output wire [DATA_WIDTH-1:0] phy_xgmii_rxd, - output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc, - output wire phy_tx_bad_block, - output wire [6:0] phy_rx_error_count, - output wire phy_rx_bad_block, - output wire phy_rx_sequence_error, - output wire phy_rx_block_lock, - output wire phy_rx_high_ber, - input wire phy_tx_prbs31_enable, - input wire phy_rx_prbs31_enable -); - -wire phy_rx_reset_req; - -wire gt_reset_tx_datapath = 1'b0; -wire gt_reset_rx_datapath = phy_rx_reset_req; - -wire gt_reset_tx_done; -wire gt_reset_rx_done; - -wire [5:0] gt_txheader; -wire [63:0] gt_txdata; -wire gt_rxgearboxslip; -wire [5:0] gt_rxheader; -wire [1:0] gt_rxheadervalid; -wire [63:0] gt_rxdata; -wire [1:0] gt_rxdatavalid; - -generate - -if (HAS_COMMON) begin : xcvr - - eth_xcvr_gt_full - eth_xcvr_gt_full_inst ( - // Common - .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), - .gtwiz_reset_all_in(xcvr_ctrl_rst), - .gtpowergood_out(xcvr_gtpowergood_out), - - // PLL - .gtrefclk00_in(xcvr_gtrefclk00_in), - .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), - - // Serial data - .gtytxp_out(xcvr_txp), - .gtytxn_out(xcvr_txn), - .gtyrxp_in(xcvr_rxp), - .gtyrxn_in(xcvr_rxn), - - // Transmit - .gtwiz_userclk_tx_reset_in(1'b0), - .gtwiz_userclk_tx_srcclk_out(), - .gtwiz_userclk_tx_usrclk_out(), - .gtwiz_userclk_tx_usrclk2_out(phy_tx_clk), - .gtwiz_userclk_tx_active_out(), - .gtwiz_reset_tx_pll_and_datapath_in(1'b0), - .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), - .gtwiz_reset_tx_done_out(gt_reset_tx_done), - .txpmaresetdone_out(), - .txprgdivresetdone_out(), - - .gtwiz_userdata_tx_in(gt_txdata), - .txheader_in(gt_txheader), - .txsequence_in(7'b0), - - // Receive - .gtwiz_userclk_rx_reset_in(1'b0), - .gtwiz_userclk_rx_srcclk_out(), - .gtwiz_userclk_rx_usrclk_out(), - .gtwiz_userclk_rx_usrclk2_out(phy_rx_clk), - .gtwiz_userclk_rx_active_out(), - .gtwiz_reset_rx_pll_and_datapath_in(1'b0), - .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), - .gtwiz_reset_rx_cdr_stable_out(), - .gtwiz_reset_rx_done_out(gt_reset_rx_done), - .rxpmaresetdone_out(), - .rxprgdivresetdone_out(), - - .rxgearboxslip_in(gt_rxgearboxslip), - .gtwiz_userdata_rx_out(gt_rxdata), - .rxdatavalid_out(gt_rxdatavalid), - .rxheader_out(gt_rxheader), - .rxheadervalid_out(gt_rxheadervalid), - .rxstartofseq_out() - ); - -end else begin : xcvr - - eth_xcvr_gt_channel - eth_xcvr_gt_channel_inst ( - // Common - .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), - .gtwiz_reset_all_in(xcvr_ctrl_rst), - .gtpowergood_out(xcvr_gtpowergood_out), - - // PLL - .gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in), - .gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out), - .qpll0clk_in(xcvr_qpll0clk_in), - .qpll0refclk_in(xcvr_qpll0refclk_in), - .qpll1clk_in(1'b0), - .qpll1refclk_in(1'b0), - - // Serial data - .gtytxp_out(xcvr_txp), - .gtytxn_out(xcvr_txn), - .gtyrxp_in(xcvr_rxp), - .gtyrxn_in(xcvr_rxn), - - // Transmit - .gtwiz_userclk_tx_reset_in(1'b0), - .gtwiz_userclk_tx_srcclk_out(), - .gtwiz_userclk_tx_usrclk_out(), - .gtwiz_userclk_tx_usrclk2_out(phy_tx_clk), - .gtwiz_userclk_tx_active_out(), - .gtwiz_reset_tx_pll_and_datapath_in(1'b0), - .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), - .gtwiz_reset_tx_done_out(gt_reset_tx_done), - .txpmaresetdone_out(), - .txprgdivresetdone_out(), - - .gtwiz_userdata_tx_in(gt_txdata), - .txheader_in(gt_txheader), - .txsequence_in(7'b0), - - // Receive - .gtwiz_userclk_rx_reset_in(1'b0), - .gtwiz_userclk_rx_srcclk_out(), - .gtwiz_userclk_rx_usrclk_out(), - .gtwiz_userclk_rx_usrclk2_out(phy_rx_clk), - .gtwiz_userclk_rx_active_out(), - .gtwiz_reset_rx_pll_and_datapath_in(1'b0), - .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), - .gtwiz_reset_rx_cdr_stable_out(), - .gtwiz_reset_rx_done_out(gt_reset_rx_done), - .rxpmaresetdone_out(), - .rxprgdivresetdone_out(), - - .rxgearboxslip_in(gt_rxgearboxslip), - .gtwiz_userdata_rx_out(gt_rxdata), - .rxdatavalid_out(gt_rxdatavalid), - .rxheader_out(gt_rxheader), - .rxheadervalid_out(gt_rxheadervalid), - .rxstartofseq_out() - ); - -end - -endgenerate - -sync_reset #( - .N(4) -) -tx_reset_sync_inst ( - .clk(phy_tx_clk), - .rst(!gt_reset_tx_done), - .out(phy_tx_rst) -); - -sync_reset #( - .N(4) -) -rx_reset_sync_inst ( - .clk(phy_rx_clk), - .rst(!gt_reset_rx_done), - .out(phy_rx_rst) -); - -eth_phy_10g #( - .DATA_WIDTH(DATA_WIDTH), - .CTRL_WIDTH(CTRL_WIDTH), - .HDR_WIDTH(HDR_WIDTH), - .BIT_REVERSE(1), - .SCRAMBLER_DISABLE(0), - .PRBS31_ENABLE(PRBS31_ENABLE), - .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), - .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), - .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), - .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), - .COUNT_125US(COUNT_125US) -) -phy_inst ( - .tx_clk(phy_tx_clk), - .tx_rst(phy_tx_rst), - .rx_clk(phy_rx_clk), - .rx_rst(phy_rx_rst), - .xgmii_txd(phy_xgmii_txd), - .xgmii_txc(phy_xgmii_txc), - .xgmii_rxd(phy_xgmii_rxd), - .xgmii_rxc(phy_xgmii_rxc), - .serdes_tx_data(gt_txdata), - .serdes_tx_hdr(gt_txheader), - .serdes_rx_data(gt_rxdata), - .serdes_rx_hdr(gt_rxheader), - .serdes_rx_bitslip(gt_rxgearboxslip), - .serdes_rx_reset_req(phy_rx_reset_req), - .tx_bad_block(phy_tx_bad_block), - .rx_error_count(phy_rx_error_count), - .rx_bad_block(phy_rx_bad_block), - .rx_sequence_error(phy_rx_sequence_error), - .rx_block_lock(phy_rx_block_lock), - .rx_high_ber(phy_rx_high_ber), - .tx_prbs31_enable(phy_tx_prbs31_enable), - .rx_prbs31_enable(phy_rx_prbs31_enable) -); - -endmodule - -`resetall diff --git a/example/VCU118/fpga_10g/rtl/fpga.v b/example/VCU118/fpga_10g/rtl/fpga.v deleted file mode 100644 index eaeaa06eb..000000000 --- a/example/VCU118/fpga_10g/rtl/fpga.v +++ /dev/null @@ -1,1222 +0,0 @@ -/* - -Copyright (c) 2014-2021 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA top-level module - */ -module fpga ( - /* - * Clock: 125MHz LVDS - * Reset: Push button, active low - */ - input wire clk_125mhz_p, - input wire clk_125mhz_n, - input wire reset, - - /* - * GPIO - */ - input wire btnu, - input wire btnl, - input wire btnd, - input wire btnr, - input wire btnc, - input wire [3:0] sw, - output wire [7:0] led, - - /* - * I2C for board management - */ - inout wire i2c_scl, - inout wire i2c_sda, - - /* - * Ethernet: QSFP28 - */ - output wire qsfp1_tx1_p, - output wire qsfp1_tx1_n, - input wire qsfp1_rx1_p, - input wire qsfp1_rx1_n, - output wire qsfp1_tx2_p, - output wire qsfp1_tx2_n, - input wire qsfp1_rx2_p, - input wire qsfp1_rx2_n, - output wire qsfp1_tx3_p, - output wire qsfp1_tx3_n, - input wire qsfp1_rx3_p, - input wire qsfp1_rx3_n, - output wire qsfp1_tx4_p, - output wire qsfp1_tx4_n, - input wire qsfp1_rx4_p, - input wire qsfp1_rx4_n, - input wire qsfp1_mgt_refclk_0_p, - input wire qsfp1_mgt_refclk_0_n, - // input wire qsfp1_mgt_refclk_1_p, - // input wire qsfp1_mgt_refclk_1_n, - // output wire qsfp1_recclk_p, - // output wire qsfp1_recclk_n, - output wire qsfp1_modsell, - output wire qsfp1_resetl, - input wire qsfp1_modprsl, - input wire qsfp1_intl, - output wire qsfp1_lpmode, - - output wire qsfp2_tx1_p, - output wire qsfp2_tx1_n, - input wire qsfp2_rx1_p, - input wire qsfp2_rx1_n, - output wire qsfp2_tx2_p, - output wire qsfp2_tx2_n, - input wire qsfp2_rx2_p, - input wire qsfp2_rx2_n, - output wire qsfp2_tx3_p, - output wire qsfp2_tx3_n, - input wire qsfp2_rx3_p, - input wire qsfp2_rx3_n, - output wire qsfp2_tx4_p, - output wire qsfp2_tx4_n, - input wire qsfp2_rx4_p, - input wire qsfp2_rx4_n, - input wire qsfp2_mgt_refclk_0_p, - input wire qsfp2_mgt_refclk_0_n, - // input wire qsfp2_mgt_refclk_1_p, - // input wire qsfp2_mgt_refclk_1_n, - // output wire qsfp2_recclk_p, - // output wire qsfp2_recclk_n, - output wire qsfp2_modsell, - output wire qsfp2_resetl, - input wire qsfp2_modprsl, - input wire qsfp2_intl, - output wire qsfp2_lpmode, - - /* - * Ethernet: 1000BASE-T SGMII - */ - input wire phy_sgmii_rx_p, - input wire phy_sgmii_rx_n, - output wire phy_sgmii_tx_p, - output wire phy_sgmii_tx_n, - input wire phy_sgmii_clk_p, - input wire phy_sgmii_clk_n, - output wire phy_reset_n, - input wire phy_int_n, - inout wire phy_mdio, - output wire phy_mdc, - - /* - * UART: 500000 bps, 8N1 - */ - input wire uart_rxd, - output wire uart_txd, - output wire uart_rts, - input wire uart_cts -); - -// Clock and reset - -wire clk_125mhz_ibufg; - -// Internal 125 MHz clock -wire clk_125mhz_mmcm_out; -wire clk_125mhz_int; -wire rst_125mhz_int; - -// Internal 156.25 MHz clock -wire clk_156mhz_int; -wire rst_156mhz_int; - -wire mmcm_rst = reset; -wire mmcm_locked; -wire mmcm_clkfb; - -IBUFGDS #( - .DIFF_TERM("FALSE"), - .IBUF_LOW_PWR("FALSE") -) -clk_125mhz_ibufg_inst ( - .O (clk_125mhz_ibufg), - .I (clk_125mhz_p), - .IB (clk_125mhz_n) -); - -// MMCM instance -// 125 MHz in, 125 MHz out -// PFD range: 10 MHz to 500 MHz -// VCO range: 800 MHz to 1600 MHz -// M = 8, D = 1 sets Fvco = 1000 MHz (in range) -// Divide by 8 to get output frequency of 125 MHz -MMCME3_BASE #( - .BANDWIDTH("OPTIMIZED"), - .CLKOUT0_DIVIDE_F(8), - .CLKOUT0_DUTY_CYCLE(0.5), - .CLKOUT0_PHASE(0), - .CLKOUT1_DIVIDE(1), - .CLKOUT1_DUTY_CYCLE(0.5), - .CLKOUT1_PHASE(0), - .CLKOUT2_DIVIDE(1), - .CLKOUT2_DUTY_CYCLE(0.5), - .CLKOUT2_PHASE(0), - .CLKOUT3_DIVIDE(1), - .CLKOUT3_DUTY_CYCLE(0.5), - .CLKOUT3_PHASE(0), - .CLKOUT4_DIVIDE(1), - .CLKOUT4_DUTY_CYCLE(0.5), - .CLKOUT4_PHASE(0), - .CLKOUT5_DIVIDE(1), - .CLKOUT5_DUTY_CYCLE(0.5), - .CLKOUT5_PHASE(0), - .CLKOUT6_DIVIDE(1), - .CLKOUT6_DUTY_CYCLE(0.5), - .CLKOUT6_PHASE(0), - .CLKFBOUT_MULT_F(8), - .CLKFBOUT_PHASE(0), - .DIVCLK_DIVIDE(1), - .REF_JITTER1(0.010), - .CLKIN1_PERIOD(8.0), - .STARTUP_WAIT("FALSE"), - .CLKOUT4_CASCADE("FALSE") -) -clk_mmcm_inst ( - .CLKIN1(clk_125mhz_ibufg), - .CLKFBIN(mmcm_clkfb), - .RST(mmcm_rst), - .PWRDWN(1'b0), - .CLKOUT0(clk_125mhz_mmcm_out), - .CLKOUT0B(), - .CLKOUT1(), - .CLKOUT1B(), - .CLKOUT2(), - .CLKOUT2B(), - .CLKOUT3(), - .CLKOUT3B(), - .CLKOUT4(), - .CLKOUT5(), - .CLKOUT6(), - .CLKFBOUT(mmcm_clkfb), - .CLKFBOUTB(), - .LOCKED(mmcm_locked) -); - -BUFG -clk_125mhz_bufg_inst ( - .I(clk_125mhz_mmcm_out), - .O(clk_125mhz_int) -); - -sync_reset #( - .N(4) -) -sync_reset_125mhz_inst ( - .clk(clk_125mhz_int), - .rst(~mmcm_locked), - .out(rst_125mhz_int) -); - -// GPIO -wire btnu_int; -wire btnl_int; -wire btnd_int; -wire btnr_int; -wire btnc_int; -wire [3:0] sw_int; - -debounce_switch #( - .WIDTH(9), - .N(4), - .RATE(156000) -) -debounce_switch_inst ( - .clk(clk_156mhz_int), - .rst(rst_156mhz_int), - .in({btnu, - btnl, - btnd, - btnr, - btnc, - sw}), - .out({btnu_int, - btnl_int, - btnd_int, - btnr_int, - btnc_int, - sw_int}) -); - -wire uart_rxd_int; -wire uart_cts_int; - -sync_signal #( - .WIDTH(2), - .N(2) -) -sync_signal_inst ( - .clk(clk_156mhz_int), - .in({uart_rxd, uart_cts}), - .out({uart_rxd_int, uart_cts_int}) -); - -// SI570 I2C -wire i2c_scl_i; -wire i2c_scl_o = 1'b1; -wire i2c_scl_t = 1'b1; -wire i2c_sda_i; -wire i2c_sda_o = 1'b1; -wire i2c_sda_t = 1'b1; - -assign i2c_scl_i = i2c_scl; -assign i2c_scl = i2c_scl_t ? 1'bz : i2c_scl_o; -assign i2c_sda_i = i2c_sda; -assign i2c_sda = i2c_sda_t ? 1'bz : i2c_sda_o; - -// XGMII 10G PHY - -// QSFP1 -assign qsfp1_modsell = 1'b0; -assign qsfp1_resetl = 1'b1; -assign qsfp1_lpmode = 1'b0; - -wire qsfp1_tx_clk_1_int; -wire qsfp1_tx_rst_1_int; -wire [63:0] qsfp1_txd_1_int; -wire [7:0] qsfp1_txc_1_int; -wire qsfp1_rx_clk_1_int; -wire qsfp1_rx_rst_1_int; -wire [63:0] qsfp1_rxd_1_int; -wire [7:0] qsfp1_rxc_1_int; -wire qsfp1_tx_clk_2_int; -wire qsfp1_tx_rst_2_int; -wire [63:0] qsfp1_txd_2_int; -wire [7:0] qsfp1_txc_2_int; -wire qsfp1_rx_clk_2_int; -wire qsfp1_rx_rst_2_int; -wire [63:0] qsfp1_rxd_2_int; -wire [7:0] qsfp1_rxc_2_int; -wire qsfp1_tx_clk_3_int; -wire qsfp1_tx_rst_3_int; -wire [63:0] qsfp1_txd_3_int; -wire [7:0] qsfp1_txc_3_int; -wire qsfp1_rx_clk_3_int; -wire qsfp1_rx_rst_3_int; -wire [63:0] qsfp1_rxd_3_int; -wire [7:0] qsfp1_rxc_3_int; -wire qsfp1_tx_clk_4_int; -wire qsfp1_tx_rst_4_int; -wire [63:0] qsfp1_txd_4_int; -wire [7:0] qsfp1_txc_4_int; -wire qsfp1_rx_clk_4_int; -wire qsfp1_rx_rst_4_int; -wire [63:0] qsfp1_rxd_4_int; -wire [7:0] qsfp1_rxc_4_int; - -assign clk_156mhz_int = qsfp1_tx_clk_1_int; -assign rst_156mhz_int = qsfp1_tx_rst_1_int; - -wire qsfp1_rx_block_lock_1; -wire qsfp1_rx_block_lock_2; -wire qsfp1_rx_block_lock_3; -wire qsfp1_rx_block_lock_4; - -wire qsfp1_mgt_refclk_0; - -IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_0_inst ( - .I (qsfp1_mgt_refclk_0_p), - .IB (qsfp1_mgt_refclk_0_n), - .CEB (1'b0), - .O (qsfp1_mgt_refclk_0), - .ODIV2 () -); - -wire qsfp1_qpll0lock; -wire qsfp1_qpll0outclk; -wire qsfp1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp1_phy_1_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_0), - .xcvr_qpll0lock_out(qsfp1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk), - - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), - - // Serial data - .xcvr_txp(qsfp1_tx1_p), - .xcvr_txn(qsfp1_tx1_n), - .xcvr_rxp(qsfp1_rx1_p), - .xcvr_rxn(qsfp1_rx1_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_1_int), - .phy_tx_rst(qsfp1_tx_rst_1_int), - .phy_xgmii_txd(qsfp1_txd_1_int), - .phy_xgmii_txc(qsfp1_txc_1_int), - .phy_rx_clk(qsfp1_rx_clk_1_int), - .phy_rx_rst(qsfp1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp1_rxd_1_int), - .phy_xgmii_rxc(qsfp1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx2_p), - .xcvr_txn(qsfp1_tx2_n), - .xcvr_rxp(qsfp1_rx2_p), - .xcvr_rxn(qsfp1_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_2_int), - .phy_tx_rst(qsfp1_tx_rst_2_int), - .phy_xgmii_txd(qsfp1_txd_2_int), - .phy_xgmii_txc(qsfp1_txc_2_int), - .phy_rx_clk(qsfp1_rx_clk_2_int), - .phy_rx_rst(qsfp1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp1_rxd_2_int), - .phy_xgmii_rxc(qsfp1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx3_p), - .xcvr_txn(qsfp1_tx3_n), - .xcvr_rxp(qsfp1_rx3_p), - .xcvr_rxn(qsfp1_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_3_int), - .phy_tx_rst(qsfp1_tx_rst_3_int), - .phy_xgmii_txd(qsfp1_txd_3_int), - .phy_xgmii_txc(qsfp1_txc_3_int), - .phy_rx_clk(qsfp1_rx_clk_3_int), - .phy_rx_rst(qsfp1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp1_rxd_3_int), - .phy_xgmii_rxc(qsfp1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx4_p), - .xcvr_txn(qsfp1_tx4_n), - .xcvr_rxp(qsfp1_rx4_p), - .xcvr_rxn(qsfp1_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_4_int), - .phy_tx_rst(qsfp1_tx_rst_4_int), - .phy_xgmii_txd(qsfp1_txd_4_int), - .phy_xgmii_txc(qsfp1_txc_4_int), - .phy_rx_clk(qsfp1_rx_clk_4_int), - .phy_rx_rst(qsfp1_rx_rst_4_int), - .phy_xgmii_rxd(qsfp1_rxd_4_int), - .phy_xgmii_rxc(qsfp1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -// QSFP2 -assign qsfp2_modsell = 1'b0; -assign qsfp2_resetl = 1'b1; -assign qsfp2_lpmode = 1'b0; - -wire qsfp2_tx_clk_1_int; -wire qsfp2_tx_rst_1_int; -wire [63:0] qsfp2_txd_1_int; -wire [7:0] qsfp2_txc_1_int; -wire qsfp2_rx_clk_1_int; -wire qsfp2_rx_rst_1_int; -wire [63:0] qsfp2_rxd_1_int; -wire [7:0] qsfp2_rxc_1_int; -wire qsfp2_tx_clk_2_int; -wire qsfp2_tx_rst_2_int; -wire [63:0] qsfp2_txd_2_int; -wire [7:0] qsfp2_txc_2_int; -wire qsfp2_rx_clk_2_int; -wire qsfp2_rx_rst_2_int; -wire [63:0] qsfp2_rxd_2_int; -wire [7:0] qsfp2_rxc_2_int; -wire qsfp2_tx_clk_3_int; -wire qsfp2_tx_rst_3_int; -wire [63:0] qsfp2_txd_3_int; -wire [7:0] qsfp2_txc_3_int; -wire qsfp2_rx_clk_3_int; -wire qsfp2_rx_rst_3_int; -wire [63:0] qsfp2_rxd_3_int; -wire [7:0] qsfp2_rxc_3_int; -wire qsfp2_tx_clk_4_int; -wire qsfp2_tx_rst_4_int; -wire [63:0] qsfp2_txd_4_int; -wire [7:0] qsfp2_txc_4_int; -wire qsfp2_rx_clk_4_int; -wire qsfp2_rx_rst_4_int; -wire [63:0] qsfp2_rxd_4_int; -wire [7:0] qsfp2_rxc_4_int; - -wire qsfp2_rx_block_lock_1; -wire qsfp2_rx_block_lock_2; -wire qsfp2_rx_block_lock_3; -wire qsfp2_rx_block_lock_4; - -wire qsfp2_mgt_refclk_0; - -IBUFDS_GTE4 ibufds_gte4_qsfp2_mgt_refclk_0_inst ( - .I (qsfp2_mgt_refclk_0_p), - .IB (qsfp2_mgt_refclk_0_n), - .CEB (1'b0), - .O (qsfp2_mgt_refclk_0), - .ODIV2 () -); - -wire qsfp2_qpll0lock; -wire qsfp2_qpll0outclk; -wire qsfp2_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) -) -qsfp2_phy_1_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(qsfp2_mgt_refclk_0), - .xcvr_qpll0lock_out(qsfp2_qpll0lock), - .xcvr_qpll0outclk_out(qsfp2_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp2_qpll0outrefclk), - - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), - - // Serial data - .xcvr_txp(qsfp2_tx1_p), - .xcvr_txn(qsfp2_tx1_n), - .xcvr_rxp(qsfp2_rx1_p), - .xcvr_rxn(qsfp2_rx1_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_1_int), - .phy_tx_rst(qsfp2_tx_rst_1_int), - .phy_xgmii_txd(qsfp2_txd_1_int), - .phy_xgmii_txc(qsfp2_txc_1_int), - .phy_rx_clk(qsfp2_rx_clk_1_int), - .phy_rx_rst(qsfp2_rx_rst_1_int), - .phy_xgmii_rxd(qsfp2_rxd_1_int), - .phy_xgmii_rxc(qsfp2_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp2_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx2_p), - .xcvr_txn(qsfp2_tx2_n), - .xcvr_rxp(qsfp2_rx2_p), - .xcvr_rxn(qsfp2_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_2_int), - .phy_tx_rst(qsfp2_tx_rst_2_int), - .phy_xgmii_txd(qsfp2_txd_2_int), - .phy_xgmii_txc(qsfp2_txc_2_int), - .phy_rx_clk(qsfp2_rx_clk_2_int), - .phy_rx_rst(qsfp2_rx_rst_2_int), - .phy_xgmii_rxd(qsfp2_rxd_2_int), - .phy_xgmii_rxc(qsfp2_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp2_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx3_p), - .xcvr_txn(qsfp2_tx3_n), - .xcvr_rxp(qsfp2_rx3_p), - .xcvr_rxn(qsfp2_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_3_int), - .phy_tx_rst(qsfp2_tx_rst_3_int), - .phy_xgmii_txd(qsfp2_txd_3_int), - .phy_xgmii_txc(qsfp2_txc_3_int), - .phy_rx_clk(qsfp2_rx_clk_3_int), - .phy_rx_rst(qsfp2_rx_rst_3_int), - .phy_xgmii_rxd(qsfp2_rxd_3_int), - .phy_xgmii_rxc(qsfp2_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp2_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp2_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp2_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp2_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp2_tx4_p), - .xcvr_txn(qsfp2_tx4_n), - .xcvr_rxp(qsfp2_rx4_p), - .xcvr_rxn(qsfp2_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp2_tx_clk_4_int), - .phy_tx_rst(qsfp2_tx_rst_4_int), - .phy_xgmii_txd(qsfp2_txd_4_int), - .phy_xgmii_txc(qsfp2_txc_4_int), - .phy_rx_clk(qsfp2_rx_clk_4_int), - .phy_rx_rst(qsfp2_rx_rst_4_int), - .phy_xgmii_rxd(qsfp2_rxd_4_int), - .phy_xgmii_rxc(qsfp2_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp2_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_tx_prbs31_enable(), - .phy_rx_prbs31_enable() -); - -// SGMII interface to PHY -wire phy_gmii_clk_int; -wire phy_gmii_rst_int; -wire phy_gmii_clk_en_int; -wire [7:0] phy_gmii_txd_int; -wire phy_gmii_tx_en_int; -wire phy_gmii_tx_er_int; -wire [7:0] phy_gmii_rxd_int; -wire phy_gmii_rx_dv_int; -wire phy_gmii_rx_er_int; - -wire [15:0] gig_eth_pcspma_status_vector; - -wire gig_eth_pcspma_status_link_status = gig_eth_pcspma_status_vector[0]; -wire gig_eth_pcspma_status_link_synchronization = gig_eth_pcspma_status_vector[1]; -wire gig_eth_pcspma_status_rudi_c = gig_eth_pcspma_status_vector[2]; -wire gig_eth_pcspma_status_rudi_i = gig_eth_pcspma_status_vector[3]; -wire gig_eth_pcspma_status_rudi_invalid = gig_eth_pcspma_status_vector[4]; -wire gig_eth_pcspma_status_rxdisperr = gig_eth_pcspma_status_vector[5]; -wire gig_eth_pcspma_status_rxnotintable = gig_eth_pcspma_status_vector[6]; -wire gig_eth_pcspma_status_phy_link_status = gig_eth_pcspma_status_vector[7]; -wire [1:0] gig_eth_pcspma_status_remote_fault_encdg = gig_eth_pcspma_status_vector[9:8]; -wire [1:0] gig_eth_pcspma_status_speed = gig_eth_pcspma_status_vector[11:10]; -wire gig_eth_pcspma_status_duplex = gig_eth_pcspma_status_vector[12]; -wire gig_eth_pcspma_status_remote_fault = gig_eth_pcspma_status_vector[13]; -wire [1:0] gig_eth_pcspma_status_pause = gig_eth_pcspma_status_vector[15:14]; - -wire [4:0] gig_eth_pcspma_config_vector; - -assign gig_eth_pcspma_config_vector[4] = 1'b1; // autonegotiation enable -assign gig_eth_pcspma_config_vector[3] = 1'b0; // isolate -assign gig_eth_pcspma_config_vector[2] = 1'b0; // power down -assign gig_eth_pcspma_config_vector[1] = 1'b0; // loopback enable -assign gig_eth_pcspma_config_vector[0] = 1'b0; // unidirectional enable - -wire [15:0] gig_eth_pcspma_an_config_vector; - -assign gig_eth_pcspma_an_config_vector[15] = 1'b1; // SGMII link status -assign gig_eth_pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge -assign gig_eth_pcspma_an_config_vector[13:12] = 2'b01; // full duplex -assign gig_eth_pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed -assign gig_eth_pcspma_an_config_vector[9] = 1'b0; // reserved -assign gig_eth_pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved -assign gig_eth_pcspma_an_config_vector[6] = 1'b0; // reserved -assign gig_eth_pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved -assign gig_eth_pcspma_an_config_vector[4:1] = 4'b0000; // reserved -assign gig_eth_pcspma_an_config_vector[0] = 1'b1; // SGMII - -gig_ethernet_pcs_pma_0 -eth_pcspma ( - // SGMII - .txp_0 (phy_sgmii_tx_p), - .txn_0 (phy_sgmii_tx_n), - .rxp_0 (phy_sgmii_rx_p), - .rxn_0 (phy_sgmii_rx_n), - - // Ref clock from PHY - .refclk625_p (phy_sgmii_clk_p), - .refclk625_n (phy_sgmii_clk_n), - - // async reset - .reset (rst_125mhz_int), - - // clock and reset outputs - .clk125_out (phy_gmii_clk_int), - .clk312_out (), - .rst_125_out (phy_gmii_rst_int), - .tx_logic_reset (), - .rx_logic_reset (), - .tx_locked (), - .rx_locked (), - .tx_pll_clk_out (), - .rx_pll_clk_out (), - - // MAC clocking - .sgmii_clk_r_0 (), - .sgmii_clk_f_0 (), - .sgmii_clk_en_0 (phy_gmii_clk_en_int), - - // Speed control - .speed_is_10_100_0 (gig_eth_pcspma_status_speed != 2'b10), - .speed_is_100_0 (gig_eth_pcspma_status_speed == 2'b01), - - // Internal GMII - .gmii_txd_0 (phy_gmii_txd_int), - .gmii_tx_en_0 (phy_gmii_tx_en_int), - .gmii_tx_er_0 (phy_gmii_tx_er_int), - .gmii_rxd_0 (phy_gmii_rxd_int), - .gmii_rx_dv_0 (phy_gmii_rx_dv_int), - .gmii_rx_er_0 (phy_gmii_rx_er_int), - .gmii_isolate_0 (), - - // Configuration - .configuration_vector_0 (gig_eth_pcspma_config_vector), - - .an_interrupt_0 (), - .an_adv_config_vector_0 (gig_eth_pcspma_an_config_vector), - .an_restart_config_0 (1'b0), - - // Status - .status_vector_0 (gig_eth_pcspma_status_vector), - .signal_detect_0 (1'b1), - - // Cascade - .tx_bsc_rst_out (), - .rx_bsc_rst_out (), - .tx_bs_rst_out (), - .rx_bs_rst_out (), - .tx_rst_dly_out (), - .rx_rst_dly_out (), - .tx_bsc_en_vtc_out (), - .rx_bsc_en_vtc_out (), - .tx_bs_en_vtc_out (), - .rx_bs_en_vtc_out (), - .riu_clk_out (), - .riu_addr_out (), - .riu_wr_data_out (), - .riu_wr_en_out (), - .riu_nibble_sel_out (), - .riu_rddata_1 (16'b0), - .riu_valid_1 (1'b0), - .riu_prsnt_1 (1'b0), - .riu_rddata_2 (16'b0), - .riu_valid_2 (1'b0), - .riu_prsnt_2 (1'b0), - .riu_rddata_3 (16'b0), - .riu_valid_3 (1'b0), - .riu_prsnt_3 (1'b0), - .rx_btval_1 (), - .rx_btval_2 (), - .rx_btval_3 (), - .tx_dly_rdy_1 (1'b1), - .rx_dly_rdy_1 (1'b1), - .rx_vtc_rdy_1 (1'b1), - .tx_vtc_rdy_1 (1'b1), - .tx_dly_rdy_2 (1'b1), - .rx_dly_rdy_2 (1'b1), - .rx_vtc_rdy_2 (1'b1), - .tx_vtc_rdy_2 (1'b1), - .tx_dly_rdy_3 (1'b1), - .rx_dly_rdy_3 (1'b1), - .rx_vtc_rdy_3 (1'b1), - .tx_vtc_rdy_3 (1'b1), - .tx_rdclk_out () -); - -reg [19:0] delay_reg = 20'hfffff; - -reg [4:0] mdio_cmd_phy_addr = 5'h03; -reg [4:0] mdio_cmd_reg_addr = 5'h00; -reg [15:0] mdio_cmd_data = 16'd0; -reg [1:0] mdio_cmd_opcode = 2'b01; -reg mdio_cmd_valid = 1'b0; -wire mdio_cmd_ready; - -reg [3:0] state_reg = 0; - -always @(posedge clk_125mhz_int) begin - if (rst_125mhz_int) begin - state_reg <= 0; - delay_reg <= 20'hfffff; - mdio_cmd_reg_addr <= 5'h00; - mdio_cmd_data <= 16'd0; - mdio_cmd_valid <= 1'b0; - end else begin - mdio_cmd_valid <= mdio_cmd_valid & !mdio_cmd_ready; - if (delay_reg > 0) begin - delay_reg <= delay_reg - 1; - end else if (!mdio_cmd_ready) begin - // wait for ready - state_reg <= state_reg; - end else begin - mdio_cmd_valid <= 1'b0; - case (state_reg) - // set SGMII autonegotiation timer to 11 ms - // write 0x0070 to CFG4 (0x0031) - 4'd0: begin - // write to REGCR to load address - mdio_cmd_reg_addr <= 5'h0D; - mdio_cmd_data <= 16'h001F; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd1; - end - 4'd1: begin - // write address of CFG4 to ADDAR - mdio_cmd_reg_addr <= 5'h0E; - mdio_cmd_data <= 16'h0031; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd2; - end - 4'd2: begin - // write to REGCR to load data - mdio_cmd_reg_addr <= 5'h0D; - mdio_cmd_data <= 16'h401F; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd3; - end - 4'd3: begin - // write data for CFG4 to ADDAR - mdio_cmd_reg_addr <= 5'h0E; - mdio_cmd_data <= 16'h0070; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd4; - end - // enable SGMII clock output - // write 0x4000 to SGMIICTL1 (0x00D3) - 4'd4: begin - // write to REGCR to load address - mdio_cmd_reg_addr <= 5'h0D; - mdio_cmd_data <= 16'h001F; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd5; - end - 4'd5: begin - // write address of SGMIICTL1 to ADDAR - mdio_cmd_reg_addr <= 5'h0E; - mdio_cmd_data <= 16'h00D3; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd6; - end - 4'd6: begin - // write to REGCR to load data - mdio_cmd_reg_addr <= 5'h0D; - mdio_cmd_data <= 16'h401F; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd7; - end - 4'd7: begin - // write data for SGMIICTL1 to ADDAR - mdio_cmd_reg_addr <= 5'h0E; - mdio_cmd_data <= 16'h4000; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd8; - end - // enable 10Mbps operation - // write 0x0015 to 10M_SGMII_CFG (0x016F) - 4'd8: begin - // write to REGCR to load address - mdio_cmd_reg_addr <= 5'h0D; - mdio_cmd_data <= 16'h001F; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd9; - end - 4'd9: begin - // write address of 10M_SGMII_CFG to ADDAR - mdio_cmd_reg_addr <= 5'h0E; - mdio_cmd_data <= 16'h016F; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd10; - end - 4'd10: begin - // write to REGCR to load data - mdio_cmd_reg_addr <= 5'h0D; - mdio_cmd_data <= 16'h401F; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd11; - end - 4'd11: begin - // write data for 10M_SGMII_CFG to ADDAR - mdio_cmd_reg_addr <= 5'h0E; - mdio_cmd_data <= 16'h0015; - mdio_cmd_valid <= 1'b1; - state_reg <= 4'd12; - end - 4'd12: begin - // done - state_reg <= 4'd12; - end - endcase - end - end -end - -wire mdc; -wire mdio_i; -wire mdio_o; -wire mdio_t; - -mdio_master -mdio_master_inst ( - .clk(clk_125mhz_int), - .rst(rst_125mhz_int), - - .cmd_phy_addr(mdio_cmd_phy_addr), - .cmd_reg_addr(mdio_cmd_reg_addr), - .cmd_data(mdio_cmd_data), - .cmd_opcode(mdio_cmd_opcode), - .cmd_valid(mdio_cmd_valid), - .cmd_ready(mdio_cmd_ready), - - .data_out(), - .data_out_valid(), - .data_out_ready(1'b1), - - .mdc_o(mdc), - .mdio_i(mdio_i), - .mdio_o(mdio_o), - .mdio_t(mdio_t), - - .busy(), - - .prescale(8'd3) -); - -assign phy_mdc = mdc; -assign mdio_i = phy_mdio; -assign phy_mdio = mdio_t ? 1'bz : mdio_o; - -wire [7:0] led_int; - -assign led[0] = sw[0] ? qsfp1_rx_block_lock_1 : led_int[0]; -assign led[1] = sw[0] ? qsfp1_rx_block_lock_2 : led_int[1]; -assign led[2] = sw[0] ? qsfp1_rx_block_lock_3 : led_int[2]; -assign led[3] = sw[0] ? qsfp1_rx_block_lock_4 : led_int[3]; -assign led[4] = sw[0] ? qsfp2_rx_block_lock_1 : led_int[4]; -assign led[5] = sw[0] ? qsfp2_rx_block_lock_2 : led_int[5]; -assign led[6] = sw[0] ? qsfp2_rx_block_lock_3 : led_int[6]; -assign led[7] = sw[0] ? qsfp2_rx_block_lock_4 : led_int[7]; - -fpga_core -core_inst ( - /* - * Clock: 156.25 MHz - * Synchronous reset - */ - .clk(clk_156mhz_int), - .rst(rst_156mhz_int), - /* - * GPIO - */ - .btnu(btnu_int), - .btnl(btnl_int), - .btnd(btnd_int), - .btnr(btnr_int), - .btnc(btnc_int), - .sw(sw_int), - .led(led_int), - /* - * Ethernet: QSFP28 - */ - .qsfp1_tx_clk_1(qsfp1_tx_clk_1_int), - .qsfp1_tx_rst_1(qsfp1_tx_rst_1_int), - .qsfp1_txd_1(qsfp1_txd_1_int), - .qsfp1_txc_1(qsfp1_txc_1_int), - .qsfp1_rx_clk_1(qsfp1_rx_clk_1_int), - .qsfp1_rx_rst_1(qsfp1_rx_rst_1_int), - .qsfp1_rxd_1(qsfp1_rxd_1_int), - .qsfp1_rxc_1(qsfp1_rxc_1_int), - .qsfp1_tx_clk_2(qsfp1_tx_clk_2_int), - .qsfp1_tx_rst_2(qsfp1_tx_rst_2_int), - .qsfp1_txd_2(qsfp1_txd_2_int), - .qsfp1_txc_2(qsfp1_txc_2_int), - .qsfp1_rx_clk_2(qsfp1_rx_clk_2_int), - .qsfp1_rx_rst_2(qsfp1_rx_rst_2_int), - .qsfp1_rxd_2(qsfp1_rxd_2_int), - .qsfp1_rxc_2(qsfp1_rxc_2_int), - .qsfp1_tx_clk_3(qsfp1_tx_clk_3_int), - .qsfp1_tx_rst_3(qsfp1_tx_rst_3_int), - .qsfp1_txd_3(qsfp1_txd_3_int), - .qsfp1_txc_3(qsfp1_txc_3_int), - .qsfp1_rx_clk_3(qsfp1_rx_clk_3_int), - .qsfp1_rx_rst_3(qsfp1_rx_rst_3_int), - .qsfp1_rxd_3(qsfp1_rxd_3_int), - .qsfp1_rxc_3(qsfp1_rxc_3_int), - .qsfp1_tx_clk_4(qsfp1_tx_clk_4_int), - .qsfp1_tx_rst_4(qsfp1_tx_rst_4_int), - .qsfp1_txd_4(qsfp1_txd_4_int), - .qsfp1_txc_4(qsfp1_txc_4_int), - .qsfp1_rx_clk_4(qsfp1_rx_clk_4_int), - .qsfp1_rx_rst_4(qsfp1_rx_rst_4_int), - .qsfp1_rxd_4(qsfp1_rxd_4_int), - .qsfp1_rxc_4(qsfp1_rxc_4_int), - .qsfp2_tx_clk_1(qsfp2_tx_clk_1_int), - .qsfp2_tx_rst_1(qsfp2_tx_rst_1_int), - .qsfp2_txd_1(qsfp2_txd_1_int), - .qsfp2_txc_1(qsfp2_txc_1_int), - .qsfp2_rx_clk_1(qsfp2_rx_clk_1_int), - .qsfp2_rx_rst_1(qsfp2_rx_rst_1_int), - .qsfp2_rxd_1(qsfp2_rxd_1_int), - .qsfp2_rxc_1(qsfp2_rxc_1_int), - .qsfp2_tx_clk_2(qsfp2_tx_clk_2_int), - .qsfp2_tx_rst_2(qsfp2_tx_rst_2_int), - .qsfp2_txd_2(qsfp2_txd_2_int), - .qsfp2_txc_2(qsfp2_txc_2_int), - .qsfp2_rx_clk_2(qsfp2_rx_clk_2_int), - .qsfp2_rx_rst_2(qsfp2_rx_rst_2_int), - .qsfp2_rxd_2(qsfp2_rxd_2_int), - .qsfp2_rxc_2(qsfp2_rxc_2_int), - .qsfp2_tx_clk_3(qsfp2_tx_clk_3_int), - .qsfp2_tx_rst_3(qsfp2_tx_rst_3_int), - .qsfp2_txd_3(qsfp2_txd_3_int), - .qsfp2_txc_3(qsfp2_txc_3_int), - .qsfp2_rx_clk_3(qsfp2_rx_clk_3_int), - .qsfp2_rx_rst_3(qsfp2_rx_rst_3_int), - .qsfp2_rxd_3(qsfp2_rxd_3_int), - .qsfp2_rxc_3(qsfp2_rxc_3_int), - .qsfp2_tx_clk_4(qsfp2_tx_clk_4_int), - .qsfp2_tx_rst_4(qsfp2_tx_rst_4_int), - .qsfp2_txd_4(qsfp2_txd_4_int), - .qsfp2_txc_4(qsfp2_txc_4_int), - .qsfp2_rx_clk_4(qsfp2_rx_clk_4_int), - .qsfp2_rx_rst_4(qsfp2_rx_rst_4_int), - .qsfp2_rxd_4(qsfp2_rxd_4_int), - .qsfp2_rxc_4(qsfp2_rxc_4_int), - /* - * Ethernet: 1000BASE-T SGMII - */ - .phy_gmii_clk(phy_gmii_clk_int), - .phy_gmii_rst(phy_gmii_rst_int), - .phy_gmii_clk_en(phy_gmii_clk_en_int), - .phy_gmii_rxd(phy_gmii_rxd_int), - .phy_gmii_rx_dv(phy_gmii_rx_dv_int), - .phy_gmii_rx_er(phy_gmii_rx_er_int), - .phy_gmii_txd(phy_gmii_txd_int), - .phy_gmii_tx_en(phy_gmii_tx_en_int), - .phy_gmii_tx_er(phy_gmii_tx_er_int), - .phy_reset_n(phy_reset_n), - .phy_int_n(phy_int_n), - /* - * UART: 115200 bps, 8N1 - */ - .uart_rxd(uart_rxd_int), - .uart_txd(uart_txd), - .uart_rts(uart_rts), - .uart_cts(uart_cts_int) -); - -endmodule - -`resetall diff --git a/example/VCU118/fpga_10g/rtl/fpga_core.v b/example/VCU118/fpga_10g/rtl/fpga_core.v deleted file mode 100644 index d796f0cab..000000000 --- a/example/VCU118/fpga_10g/rtl/fpga_core.v +++ /dev/null @@ -1,916 +0,0 @@ -/* - -Copyright (c) 2014-2021 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * FPGA core logic - */ -module fpga_core # -( - parameter TARGET = "XILINX" -) -( - /* - * Clock: 156.25MHz - * Synchronous reset - */ - input wire clk, - input wire rst, - - /* - * GPIO - */ - input wire btnu, - input wire btnl, - input wire btnd, - input wire btnr, - input wire btnc, - input wire [3:0] sw, - output wire [7:0] led, - - /* - * Ethernet: QSFP28 - */ - input wire qsfp1_tx_clk_1, - input wire qsfp1_tx_rst_1, - output wire [63:0] qsfp1_txd_1, - output wire [7:0] qsfp1_txc_1, - input wire qsfp1_rx_clk_1, - input wire qsfp1_rx_rst_1, - input wire [63:0] qsfp1_rxd_1, - input wire [7:0] qsfp1_rxc_1, - input wire qsfp1_tx_clk_2, - input wire qsfp1_tx_rst_2, - output wire [63:0] qsfp1_txd_2, - output wire [7:0] qsfp1_txc_2, - input wire qsfp1_rx_clk_2, - input wire qsfp1_rx_rst_2, - input wire [63:0] qsfp1_rxd_2, - input wire [7:0] qsfp1_rxc_2, - input wire qsfp1_tx_clk_3, - input wire qsfp1_tx_rst_3, - output wire [63:0] qsfp1_txd_3, - output wire [7:0] qsfp1_txc_3, - input wire qsfp1_rx_clk_3, - input wire qsfp1_rx_rst_3, - input wire [63:0] qsfp1_rxd_3, - input wire [7:0] qsfp1_rxc_3, - input wire qsfp1_tx_clk_4, - input wire qsfp1_tx_rst_4, - output wire [63:0] qsfp1_txd_4, - output wire [7:0] qsfp1_txc_4, - input wire qsfp1_rx_clk_4, - input wire qsfp1_rx_rst_4, - input wire [63:0] qsfp1_rxd_4, - input wire [7:0] qsfp1_rxc_4, - input wire qsfp2_tx_clk_1, - input wire qsfp2_tx_rst_1, - output wire [63:0] qsfp2_txd_1, - output wire [7:0] qsfp2_txc_1, - input wire qsfp2_rx_clk_1, - input wire qsfp2_rx_rst_1, - input wire [63:0] qsfp2_rxd_1, - input wire [7:0] qsfp2_rxc_1, - input wire qsfp2_tx_clk_2, - input wire qsfp2_tx_rst_2, - output wire [63:0] qsfp2_txd_2, - output wire [7:0] qsfp2_txc_2, - input wire qsfp2_rx_clk_2, - input wire qsfp2_rx_rst_2, - input wire [63:0] qsfp2_rxd_2, - input wire [7:0] qsfp2_rxc_2, - input wire qsfp2_tx_clk_3, - input wire qsfp2_tx_rst_3, - output wire [63:0] qsfp2_txd_3, - output wire [7:0] qsfp2_txc_3, - input wire qsfp2_rx_clk_3, - input wire qsfp2_rx_rst_3, - input wire [63:0] qsfp2_rxd_3, - input wire [7:0] qsfp2_rxc_3, - input wire qsfp2_tx_clk_4, - input wire qsfp2_tx_rst_4, - output wire [63:0] qsfp2_txd_4, - output wire [7:0] qsfp2_txc_4, - input wire qsfp2_rx_clk_4, - input wire qsfp2_rx_rst_4, - input wire [63:0] qsfp2_rxd_4, - input wire [7:0] qsfp2_rxc_4, - - /* - * Ethernet: 1000BASE-T SGMII - */ - input wire phy_gmii_clk, - input wire phy_gmii_rst, - input wire phy_gmii_clk_en, - input wire [7:0] phy_gmii_rxd, - input wire phy_gmii_rx_dv, - input wire phy_gmii_rx_er, - output wire [7:0] phy_gmii_txd, - output wire phy_gmii_tx_en, - output wire phy_gmii_tx_er, - output wire phy_reset_n, - input wire phy_int_n, - - /* - * UART: 115200 bps, 8N1 - */ - input wire uart_rxd, - output wire uart_txd, - output wire uart_rts, - input wire uart_cts -); - -// AXI between MAC and Ethernet modules -wire [63:0] mac_rx_axis_tdata; -wire [7:0] mac_rx_axis_tkeep; -wire mac_rx_axis_tvalid; -wire mac_rx_axis_tready; -wire mac_rx_axis_tlast; -wire mac_rx_axis_tuser; - -wire [63:0] mac_tx_axis_tdata; -wire [7:0] mac_tx_axis_tkeep; -wire mac_tx_axis_tvalid; -wire mac_tx_axis_tready; -wire mac_tx_axis_tlast; -wire mac_tx_axis_tuser; - -wire [63:0] rx_axis_tdata; -wire [7:0] rx_axis_tkeep; -wire rx_axis_tvalid; -wire rx_axis_tready; -wire rx_axis_tlast; -wire rx_axis_tuser; - -wire [63:0] tx_axis_tdata; -wire [7:0] tx_axis_tkeep; -wire tx_axis_tvalid; -wire tx_axis_tready; -wire tx_axis_tlast; -wire tx_axis_tuser; - -// Ethernet frame between Ethernet modules and UDP stack -wire rx_eth_hdr_ready; -wire rx_eth_hdr_valid; -wire [47:0] rx_eth_dest_mac; -wire [47:0] rx_eth_src_mac; -wire [15:0] rx_eth_type; -wire [63:0] rx_eth_payload_axis_tdata; -wire [7:0] rx_eth_payload_axis_tkeep; -wire rx_eth_payload_axis_tvalid; -wire rx_eth_payload_axis_tready; -wire rx_eth_payload_axis_tlast; -wire rx_eth_payload_axis_tuser; - -wire tx_eth_hdr_ready; -wire tx_eth_hdr_valid; -wire [47:0] tx_eth_dest_mac; -wire [47:0] tx_eth_src_mac; -wire [15:0] tx_eth_type; -wire [63:0] tx_eth_payload_axis_tdata; -wire [7:0] tx_eth_payload_axis_tkeep; -wire tx_eth_payload_axis_tvalid; -wire tx_eth_payload_axis_tready; -wire tx_eth_payload_axis_tlast; -wire tx_eth_payload_axis_tuser; - -// IP frame connections -wire rx_ip_hdr_valid; -wire rx_ip_hdr_ready; -wire [47:0] rx_ip_eth_dest_mac; -wire [47:0] rx_ip_eth_src_mac; -wire [15:0] rx_ip_eth_type; -wire [3:0] rx_ip_version; -wire [3:0] rx_ip_ihl; -wire [5:0] rx_ip_dscp; -wire [1:0] rx_ip_ecn; -wire [15:0] rx_ip_length; -wire [15:0] rx_ip_identification; -wire [2:0] rx_ip_flags; -wire [12:0] rx_ip_fragment_offset; -wire [7:0] rx_ip_ttl; -wire [7:0] rx_ip_protocol; -wire [15:0] rx_ip_header_checksum; -wire [31:0] rx_ip_source_ip; -wire [31:0] rx_ip_dest_ip; -wire [63:0] rx_ip_payload_axis_tdata; -wire [7:0] rx_ip_payload_axis_tkeep; -wire rx_ip_payload_axis_tvalid; -wire rx_ip_payload_axis_tready; -wire rx_ip_payload_axis_tlast; -wire rx_ip_payload_axis_tuser; - -wire tx_ip_hdr_valid; -wire tx_ip_hdr_ready; -wire [5:0] tx_ip_dscp; -wire [1:0] tx_ip_ecn; -wire [15:0] tx_ip_length; -wire [7:0] tx_ip_ttl; -wire [7:0] tx_ip_protocol; -wire [31:0] tx_ip_source_ip; -wire [31:0] tx_ip_dest_ip; -wire [63:0] tx_ip_payload_axis_tdata; -wire [7:0] tx_ip_payload_axis_tkeep; -wire tx_ip_payload_axis_tvalid; -wire tx_ip_payload_axis_tready; -wire tx_ip_payload_axis_tlast; -wire tx_ip_payload_axis_tuser; - -// UDP frame connections -wire rx_udp_hdr_valid; -wire rx_udp_hdr_ready; -wire [47:0] rx_udp_eth_dest_mac; -wire [47:0] rx_udp_eth_src_mac; -wire [15:0] rx_udp_eth_type; -wire [3:0] rx_udp_ip_version; -wire [3:0] rx_udp_ip_ihl; -wire [5:0] rx_udp_ip_dscp; -wire [1:0] rx_udp_ip_ecn; -wire [15:0] rx_udp_ip_length; -wire [15:0] rx_udp_ip_identification; -wire [2:0] rx_udp_ip_flags; -wire [12:0] rx_udp_ip_fragment_offset; -wire [7:0] rx_udp_ip_ttl; -wire [7:0] rx_udp_ip_protocol; -wire [15:0] rx_udp_ip_header_checksum; -wire [31:0] rx_udp_ip_source_ip; -wire [31:0] rx_udp_ip_dest_ip; -wire [15:0] rx_udp_source_port; -wire [15:0] rx_udp_dest_port; -wire [15:0] rx_udp_length; -wire [15:0] rx_udp_checksum; -wire [63:0] rx_udp_payload_axis_tdata; -wire [7:0] rx_udp_payload_axis_tkeep; -wire rx_udp_payload_axis_tvalid; -wire rx_udp_payload_axis_tready; -wire rx_udp_payload_axis_tlast; -wire rx_udp_payload_axis_tuser; - -wire tx_udp_hdr_valid; -wire tx_udp_hdr_ready; -wire [5:0] tx_udp_ip_dscp; -wire [1:0] tx_udp_ip_ecn; -wire [7:0] tx_udp_ip_ttl; -wire [31:0] tx_udp_ip_source_ip; -wire [31:0] tx_udp_ip_dest_ip; -wire [15:0] tx_udp_source_port; -wire [15:0] tx_udp_dest_port; -wire [15:0] tx_udp_length; -wire [15:0] tx_udp_checksum; -wire [63:0] tx_udp_payload_axis_tdata; -wire [7:0] tx_udp_payload_axis_tkeep; -wire tx_udp_payload_axis_tvalid; -wire tx_udp_payload_axis_tready; -wire tx_udp_payload_axis_tlast; -wire tx_udp_payload_axis_tuser; - -wire [63:0] rx_fifo_udp_payload_axis_tdata; -wire [7:0] rx_fifo_udp_payload_axis_tkeep; -wire rx_fifo_udp_payload_axis_tvalid; -wire rx_fifo_udp_payload_axis_tready; -wire rx_fifo_udp_payload_axis_tlast; -wire rx_fifo_udp_payload_axis_tuser; - -wire [63:0] tx_fifo_udp_payload_axis_tdata; -wire [7:0] tx_fifo_udp_payload_axis_tkeep; -wire tx_fifo_udp_payload_axis_tvalid; -wire tx_fifo_udp_payload_axis_tready; -wire tx_fifo_udp_payload_axis_tlast; -wire tx_fifo_udp_payload_axis_tuser; - -// Configuration -wire [47:0] local_mac = 48'h02_00_00_00_00_00; -wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128}; -wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1}; -wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0}; - -// IP ports not used -assign rx_ip_hdr_ready = 1; -assign rx_ip_payload_axis_tready = 1; - -assign tx_ip_hdr_valid = 0; -assign tx_ip_dscp = 0; -assign tx_ip_ecn = 0; -assign tx_ip_length = 0; -assign tx_ip_ttl = 0; -assign tx_ip_protocol = 0; -assign tx_ip_source_ip = 0; -assign tx_ip_dest_ip = 0; -assign tx_ip_payload_axis_tdata = 0; -assign tx_ip_payload_axis_tkeep = 0; -assign tx_ip_payload_axis_tvalid = 0; -assign tx_ip_payload_axis_tlast = 0; -assign tx_ip_payload_axis_tuser = 0; - -// Loop back UDP -wire match_cond = rx_udp_dest_port == 1234; -wire no_match = !match_cond; - -reg match_cond_reg = 0; -reg no_match_reg = 0; - -always @(posedge clk) begin - if (rst) begin - match_cond_reg <= 0; - no_match_reg <= 0; - end else begin - if (rx_udp_payload_axis_tvalid) begin - if ((!match_cond_reg && !no_match_reg) || - (rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin - match_cond_reg <= match_cond; - no_match_reg <= no_match; - end - end else begin - match_cond_reg <= 0; - no_match_reg <= 0; - end - end -end - -assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond; -assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match; -assign tx_udp_ip_dscp = 0; -assign tx_udp_ip_ecn = 0; -assign tx_udp_ip_ttl = 64; -assign tx_udp_ip_source_ip = local_ip; -assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip; -assign tx_udp_source_port = rx_udp_dest_port; -assign tx_udp_dest_port = rx_udp_source_port; -assign tx_udp_length = rx_udp_length; -assign tx_udp_checksum = 0; - -assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata; -assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep; -assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid; -assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready; -assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast; -assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser; - -assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata; -assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep; -assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg; -assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg; -assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast; -assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser; - -// Place first payload byte onto LEDs -reg valid_last = 0; -reg [7:0] led_reg = 0; - -always @(posedge clk) begin - if (rst) begin - led_reg <= 0; - end else begin - valid_last <= tx_udp_payload_axis_tvalid; - if (tx_udp_payload_axis_tvalid && !valid_last) begin - led_reg <= tx_udp_payload_axis_tdata; - end - end -end - -//assign led = sw; -assign led = led_reg; -assign phy_reset_n = !rst; - -assign qsfp1_txd_2 = 64'h0707070707070707; -assign qsfp1_txc_2 = 8'hff; -assign qsfp1_txd_3 = 64'h0707070707070707; -assign qsfp1_txc_3 = 8'hff; -assign qsfp1_txd_4 = 64'h0707070707070707; -assign qsfp1_txc_4 = 8'hff; - -assign qsfp2_txd_1 = 64'h0707070707070707; -assign qsfp2_txc_1 = 8'hff; -assign qsfp2_txd_2 = 64'h0707070707070707; -assign qsfp2_txc_2 = 8'hff; -assign qsfp2_txd_3 = 64'h0707070707070707; -assign qsfp2_txc_3 = 8'hff; -assign qsfp2_txd_4 = 64'h0707070707070707; -assign qsfp2_txc_4 = 8'hff; - -eth_mac_10g_fifo #( - .ENABLE_PADDING(1), - .ENABLE_DIC(1), - .MIN_FRAME_LENGTH(64), - .TX_FIFO_DEPTH(4096), - .TX_FRAME_FIFO(1), - .RX_FIFO_DEPTH(4096), - .RX_FRAME_FIFO(1) -) -eth_mac_10g_fifo_inst ( - .rx_clk(qsfp1_rx_clk_1), - .rx_rst(qsfp1_rx_rst_1), - .tx_clk(qsfp1_tx_clk_1), - .tx_rst(qsfp1_tx_rst_1), - .logic_clk(clk), - .logic_rst(rst), - - .tx_axis_tdata(mac_tx_axis_tdata), - .tx_axis_tkeep(mac_tx_axis_tkeep), - .tx_axis_tvalid(mac_tx_axis_tvalid), - .tx_axis_tready(mac_tx_axis_tready), - .tx_axis_tlast(mac_tx_axis_tlast), - .tx_axis_tuser(mac_tx_axis_tuser), - - .rx_axis_tdata(mac_rx_axis_tdata), - .rx_axis_tkeep(mac_rx_axis_tkeep), - .rx_axis_tvalid(mac_rx_axis_tvalid), - .rx_axis_tready(mac_rx_axis_tready), - .rx_axis_tlast(mac_rx_axis_tlast), - .rx_axis_tuser(mac_rx_axis_tuser), - - .xgmii_rxd(qsfp1_rxd_1), - .xgmii_rxc(qsfp1_rxc_1), - .xgmii_txd(qsfp1_txd_1), - .xgmii_txc(qsfp1_txc_1), - - .tx_fifo_overflow(), - .tx_fifo_bad_frame(), - .tx_fifo_good_frame(), - .rx_error_bad_frame(), - .rx_error_bad_fcs(), - .rx_fifo_overflow(), - .rx_fifo_bad_frame(), - .rx_fifo_good_frame(), - - .ifg_delay(8'd12) -); - -// 1G interface for debugging -wire [7:0] gig_rx_axis_tdata; -wire gig_rx_axis_tvalid; -wire gig_rx_axis_tready; -wire gig_rx_axis_tlast; -wire gig_rx_axis_tuser; - -wire [7:0] gig_tx_axis_tdata; -wire gig_tx_axis_tvalid; -wire gig_tx_axis_tready; -wire gig_tx_axis_tlast; -wire gig_tx_axis_tuser; - -wire [63:0] gig_rx_axis_tdata_64; -wire [7:0] gig_rx_axis_tkeep_64; -wire gig_rx_axis_tvalid_64; -wire gig_rx_axis_tready_64; -wire gig_rx_axis_tlast_64; -wire gig_rx_axis_tuser_64; - -wire [63:0] gig_tx_axis_tdata_64; -wire [7:0] gig_tx_axis_tkeep_64; -wire gig_tx_axis_tvalid_64; -wire gig_tx_axis_tready_64; -wire gig_tx_axis_tlast_64; -wire gig_tx_axis_tuser_64; - -eth_mac_1g_fifo #( - .ENABLE_PADDING(1), - .MIN_FRAME_LENGTH(64), - .TX_FIFO_DEPTH(4096), - .TX_FRAME_FIFO(1), - .RX_FIFO_DEPTH(4096), - .RX_FRAME_FIFO(1) -) -eth_mac_1g_inst ( - .rx_clk(phy_gmii_clk), - .rx_rst(phy_gmii_rst), - .tx_clk(phy_gmii_clk), - .tx_rst(phy_gmii_rst), - .logic_clk(clk), - .logic_rst(rst), - - .tx_axis_tdata(gig_tx_axis_tdata), - .tx_axis_tvalid(gig_tx_axis_tvalid), - .tx_axis_tready(gig_tx_axis_tready), - .tx_axis_tlast(gig_tx_axis_tlast), - .tx_axis_tuser(gig_tx_axis_tuser), - - .rx_axis_tdata(gig_rx_axis_tdata), - .rx_axis_tvalid(gig_rx_axis_tvalid), - .rx_axis_tready(gig_rx_axis_tready), - .rx_axis_tlast(gig_rx_axis_tlast), - .rx_axis_tuser(gig_rx_axis_tuser), - - .gmii_rxd(phy_gmii_rxd), - .gmii_rx_dv(phy_gmii_rx_dv), - .gmii_rx_er(phy_gmii_rx_er), - .gmii_txd(phy_gmii_txd), - .gmii_tx_en(phy_gmii_tx_en), - .gmii_tx_er(phy_gmii_tx_er), - - .rx_clk_enable(phy_gmii_clk_en), - .tx_clk_enable(phy_gmii_clk_en), - .rx_mii_select(1'b0), - .tx_mii_select(1'b0), - - .tx_fifo_overflow(), - .tx_fifo_bad_frame(), - .tx_fifo_good_frame(), - .rx_error_bad_frame(), - .rx_error_bad_fcs(), - .rx_fifo_overflow(), - .rx_fifo_bad_frame(), - .rx_fifo_good_frame(), - - .ifg_delay(12) -); - -axis_adapter #( - .S_DATA_WIDTH(8), - .M_DATA_WIDTH(64), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(1), - .USER_WIDTH(1) -) -gig_rx_axis_adapter_inst ( - .clk(clk), - .rst(rst), - // AXI input - .s_axis_tdata(gig_rx_axis_tdata), - .s_axis_tkeep(1'b1), - .s_axis_tvalid(gig_rx_axis_tvalid), - .s_axis_tready(gig_rx_axis_tready), - .s_axis_tlast(gig_rx_axis_tlast), - .s_axis_tuser(gig_rx_axis_tuser), - // AXI output - .m_axis_tdata(gig_rx_axis_tdata_64), - .m_axis_tkeep(gig_rx_axis_tkeep_64), - .m_axis_tvalid(gig_rx_axis_tvalid_64), - .m_axis_tready(gig_rx_axis_tready_64), - .m_axis_tlast(gig_rx_axis_tlast_64), - .m_axis_tuser(gig_rx_axis_tuser_64) -); - -axis_adapter #( - .S_DATA_WIDTH(64), - .M_DATA_WIDTH(8), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(1), - .USER_WIDTH(1) -) -gig_tx_axis_adapter_inst ( - .clk(clk), - .rst(rst), - // AXI input - .s_axis_tdata(gig_tx_axis_tdata_64), - .s_axis_tkeep(gig_tx_axis_tkeep_64), - .s_axis_tvalid(gig_tx_axis_tvalid_64), - .s_axis_tready(gig_tx_axis_tready_64), - .s_axis_tlast(gig_tx_axis_tlast_64), - .s_axis_tuser(gig_tx_axis_tuser_64), - // AXI output - .m_axis_tdata(gig_tx_axis_tdata), - .m_axis_tkeep(), - .m_axis_tvalid(gig_tx_axis_tvalid), - .m_axis_tready(gig_tx_axis_tready), - .m_axis_tlast(gig_tx_axis_tlast), - .m_axis_tuser(gig_tx_axis_tuser) -); - -// tap port mux logic -// sw[3] enable -// sw[2] select 0 rx, 1 tx - -reg [1:0] mac_rx_tdest; -reg [1:0] tx_tdest; -reg [1:0] gig_rx_tdest; - -always @* begin - if (sw[3]) begin - if (sw[2]) begin - // Tap on TX path - // MAC RX out -> stack RX in - // stack TX out -> gig TX in - // gig RX out -> MAC TX in - mac_rx_tdest = 2'd1; - tx_tdest = 2'd2; - gig_rx_tdest = 2'd0; - end else begin - // Tap on RX path - // MAC RX out -> gig TX in - // stack TX out -> MAC TX in - // gig RX out -> stack RX in - mac_rx_tdest = 2'd2; - tx_tdest = 2'd0; - gig_rx_tdest = 2'd1; - end - end else begin - // Tap disabled - // MAC RX out -> stack RX in - // stack TX out -> MAC TX in - // gig RX out -> blackhole - mac_rx_tdest = 2'd1; - tx_tdest = 2'd0; - gig_rx_tdest = 2'd3; - end -end - -axis_switch #( - .S_COUNT(3), - .M_COUNT(3), - .DATA_WIDTH(64), - .KEEP_WIDTH(8), - .ID_ENABLE(0), - .S_DEST_WIDTH(2), - .USER_ENABLE(1), - .USER_WIDTH(1), - .M_BASE({2'd2, 2'd1, 2'd0}), - .M_TOP({2'd2, 2'd1, 2'd0}), - .M_CONNECT({3{3'b111}}), - .S_REG_TYPE(0), - .M_REG_TYPE(2), - .ARB_TYPE_ROUND_ROBIN(0), - .ARB_LSB_HIGH_PRIORITY(1) -) -axis_switch_inst ( - .clk(clk), - .rst(rst), - // AXI inputs - .s_axis_tdata({ gig_rx_axis_tdata_64, tx_axis_tdata, mac_rx_axis_tdata}), - .s_axis_tkeep({ gig_rx_axis_tkeep_64, tx_axis_tkeep, mac_rx_axis_tkeep}), - .s_axis_tvalid({gig_rx_axis_tvalid_64, tx_axis_tvalid, mac_rx_axis_tvalid}), - .s_axis_tready({gig_rx_axis_tready_64, tx_axis_tready, mac_rx_axis_tready}), - .s_axis_tlast({ gig_rx_axis_tlast_64, tx_axis_tlast, mac_rx_axis_tlast}), - .s_axis_tid(0), - .s_axis_tdest({ gig_rx_tdest, tx_tdest, mac_rx_tdest}), - .s_axis_tuser({ gig_rx_axis_tuser_64, tx_axis_tuser, mac_rx_axis_tuser}), - // AXI outputs - .m_axis_tdata({ gig_tx_axis_tdata_64, rx_axis_tdata, mac_tx_axis_tdata}), - .m_axis_tkeep({ gig_tx_axis_tkeep_64, rx_axis_tkeep, mac_tx_axis_tkeep}), - .m_axis_tvalid({gig_tx_axis_tvalid_64, rx_axis_tvalid, mac_tx_axis_tvalid}), - .m_axis_tready({gig_tx_axis_tready_64, rx_axis_tready, mac_tx_axis_tready}), - .m_axis_tlast({ gig_tx_axis_tlast_64, rx_axis_tlast, mac_tx_axis_tlast}), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser({ gig_tx_axis_tuser_64, rx_axis_tuser, mac_tx_axis_tuser}) -); - -eth_axis_rx #( - .DATA_WIDTH(64) -) -eth_axis_rx_inst ( - .clk(clk), - .rst(rst), - // AXI input - .s_axis_tdata(rx_axis_tdata), - .s_axis_tkeep(rx_axis_tkeep), - .s_axis_tvalid(rx_axis_tvalid), - .s_axis_tready(rx_axis_tready), - .s_axis_tlast(rx_axis_tlast), - .s_axis_tuser(rx_axis_tuser), - // Ethernet frame output - .m_eth_hdr_valid(rx_eth_hdr_valid), - .m_eth_hdr_ready(rx_eth_hdr_ready), - .m_eth_dest_mac(rx_eth_dest_mac), - .m_eth_src_mac(rx_eth_src_mac), - .m_eth_type(rx_eth_type), - .m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), - .m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep), - .m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), - .m_eth_payload_axis_tready(rx_eth_payload_axis_tready), - .m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), - .m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), - // Status signals - .busy(), - .error_header_early_termination() -); - -eth_axis_tx #( - .DATA_WIDTH(64) -) -eth_axis_tx_inst ( - .clk(clk), - .rst(rst), - // Ethernet frame input - .s_eth_hdr_valid(tx_eth_hdr_valid), - .s_eth_hdr_ready(tx_eth_hdr_ready), - .s_eth_dest_mac(tx_eth_dest_mac), - .s_eth_src_mac(tx_eth_src_mac), - .s_eth_type(tx_eth_type), - .s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), - .s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep), - .s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), - .s_eth_payload_axis_tready(tx_eth_payload_axis_tready), - .s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), - .s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), - // AXI output - .m_axis_tdata(tx_axis_tdata), - .m_axis_tkeep(tx_axis_tkeep), - .m_axis_tvalid(tx_axis_tvalid), - .m_axis_tready(tx_axis_tready), - .m_axis_tlast(tx_axis_tlast), - .m_axis_tuser(tx_axis_tuser), - // Status signals - .busy() -); - -udp_complete_64 -udp_complete_inst ( - .clk(clk), - .rst(rst), - // Ethernet frame input - .s_eth_hdr_valid(rx_eth_hdr_valid), - .s_eth_hdr_ready(rx_eth_hdr_ready), - .s_eth_dest_mac(rx_eth_dest_mac), - .s_eth_src_mac(rx_eth_src_mac), - .s_eth_type(rx_eth_type), - .s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata), - .s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep), - .s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid), - .s_eth_payload_axis_tready(rx_eth_payload_axis_tready), - .s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast), - .s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser), - // Ethernet frame output - .m_eth_hdr_valid(tx_eth_hdr_valid), - .m_eth_hdr_ready(tx_eth_hdr_ready), - .m_eth_dest_mac(tx_eth_dest_mac), - .m_eth_src_mac(tx_eth_src_mac), - .m_eth_type(tx_eth_type), - .m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata), - .m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep), - .m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid), - .m_eth_payload_axis_tready(tx_eth_payload_axis_tready), - .m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast), - .m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser), - // IP frame input - .s_ip_hdr_valid(tx_ip_hdr_valid), - .s_ip_hdr_ready(tx_ip_hdr_ready), - .s_ip_dscp(tx_ip_dscp), - .s_ip_ecn(tx_ip_ecn), - .s_ip_length(tx_ip_length), - .s_ip_ttl(tx_ip_ttl), - .s_ip_protocol(tx_ip_protocol), - .s_ip_source_ip(tx_ip_source_ip), - .s_ip_dest_ip(tx_ip_dest_ip), - .s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata), - .s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep), - .s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid), - .s_ip_payload_axis_tready(tx_ip_payload_axis_tready), - .s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast), - .s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser), - // IP frame output - .m_ip_hdr_valid(rx_ip_hdr_valid), - .m_ip_hdr_ready(rx_ip_hdr_ready), - .m_ip_eth_dest_mac(rx_ip_eth_dest_mac), - .m_ip_eth_src_mac(rx_ip_eth_src_mac), - .m_ip_eth_type(rx_ip_eth_type), - .m_ip_version(rx_ip_version), - .m_ip_ihl(rx_ip_ihl), - .m_ip_dscp(rx_ip_dscp), - .m_ip_ecn(rx_ip_ecn), - .m_ip_length(rx_ip_length), - .m_ip_identification(rx_ip_identification), - .m_ip_flags(rx_ip_flags), - .m_ip_fragment_offset(rx_ip_fragment_offset), - .m_ip_ttl(rx_ip_ttl), - .m_ip_protocol(rx_ip_protocol), - .m_ip_header_checksum(rx_ip_header_checksum), - .m_ip_source_ip(rx_ip_source_ip), - .m_ip_dest_ip(rx_ip_dest_ip), - .m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata), - .m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep), - .m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid), - .m_ip_payload_axis_tready(rx_ip_payload_axis_tready), - .m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast), - .m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser), - // UDP frame input - .s_udp_hdr_valid(tx_udp_hdr_valid), - .s_udp_hdr_ready(tx_udp_hdr_ready), - .s_udp_ip_dscp(tx_udp_ip_dscp), - .s_udp_ip_ecn(tx_udp_ip_ecn), - .s_udp_ip_ttl(tx_udp_ip_ttl), - .s_udp_ip_source_ip(tx_udp_ip_source_ip), - .s_udp_ip_dest_ip(tx_udp_ip_dest_ip), - .s_udp_source_port(tx_udp_source_port), - .s_udp_dest_port(tx_udp_dest_port), - .s_udp_length(tx_udp_length), - .s_udp_checksum(tx_udp_checksum), - .s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata), - .s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep), - .s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid), - .s_udp_payload_axis_tready(tx_udp_payload_axis_tready), - .s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast), - .s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser), - // UDP frame output - .m_udp_hdr_valid(rx_udp_hdr_valid), - .m_udp_hdr_ready(rx_udp_hdr_ready), - .m_udp_eth_dest_mac(rx_udp_eth_dest_mac), - .m_udp_eth_src_mac(rx_udp_eth_src_mac), - .m_udp_eth_type(rx_udp_eth_type), - .m_udp_ip_version(rx_udp_ip_version), - .m_udp_ip_ihl(rx_udp_ip_ihl), - .m_udp_ip_dscp(rx_udp_ip_dscp), - .m_udp_ip_ecn(rx_udp_ip_ecn), - .m_udp_ip_length(rx_udp_ip_length), - .m_udp_ip_identification(rx_udp_ip_identification), - .m_udp_ip_flags(rx_udp_ip_flags), - .m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset), - .m_udp_ip_ttl(rx_udp_ip_ttl), - .m_udp_ip_protocol(rx_udp_ip_protocol), - .m_udp_ip_header_checksum(rx_udp_ip_header_checksum), - .m_udp_ip_source_ip(rx_udp_ip_source_ip), - .m_udp_ip_dest_ip(rx_udp_ip_dest_ip), - .m_udp_source_port(rx_udp_source_port), - .m_udp_dest_port(rx_udp_dest_port), - .m_udp_length(rx_udp_length), - .m_udp_checksum(rx_udp_checksum), - .m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata), - .m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep), - .m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid), - .m_udp_payload_axis_tready(rx_udp_payload_axis_tready), - .m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast), - .m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser), - // Status signals - .ip_rx_busy(), - .ip_tx_busy(), - .udp_rx_busy(), - .udp_tx_busy(), - .ip_rx_error_header_early_termination(), - .ip_rx_error_payload_early_termination(), - .ip_rx_error_invalid_header(), - .ip_rx_error_invalid_checksum(), - .ip_tx_error_payload_early_termination(), - .ip_tx_error_arp_failed(), - .udp_rx_error_header_early_termination(), - .udp_rx_error_payload_early_termination(), - .udp_tx_error_payload_early_termination(), - // Configuration - .local_mac(local_mac), - .local_ip(local_ip), - .gateway_ip(gateway_ip), - .subnet_mask(subnet_mask), - .clear_arp_cache(1'b0) -); - -axis_fifo #( - .DEPTH(8192), - .DATA_WIDTH(64), - .KEEP_ENABLE(1), - .KEEP_WIDTH(8), - .ID_ENABLE(0), - .DEST_ENABLE(0), - .USER_ENABLE(1), - .USER_WIDTH(1), - .FRAME_FIFO(0) -) -udp_payload_fifo ( - .clk(clk), - .rst(rst), - - // AXI input - .s_axis_tdata(rx_fifo_udp_payload_axis_tdata), - .s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep), - .s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid), - .s_axis_tready(rx_fifo_udp_payload_axis_tready), - .s_axis_tlast(rx_fifo_udp_payload_axis_tlast), - .s_axis_tid(0), - .s_axis_tdest(0), - .s_axis_tuser(rx_fifo_udp_payload_axis_tuser), - - // AXI output - .m_axis_tdata(tx_fifo_udp_payload_axis_tdata), - .m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep), - .m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid), - .m_axis_tready(tx_fifo_udp_payload_axis_tready), - .m_axis_tlast(tx_fifo_udp_payload_axis_tlast), - .m_axis_tid(), - .m_axis_tdest(), - .m_axis_tuser(tx_fifo_udp_payload_axis_tuser), - - // Status - .status_overflow(), - .status_bad_frame(), - .status_good_frame() -); - -endmodule - -`resetall diff --git a/example/VCU118/fpga_10g/rtl/mdio_master.v b/example/VCU118/fpga_10g/rtl/mdio_master.v deleted file mode 100644 index d3098a885..000000000 --- a/example/VCU118/fpga_10g/rtl/mdio_master.v +++ /dev/null @@ -1,229 +0,0 @@ -/* - -Copyright (c) 2015-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog 2001 - -`resetall -`timescale 1ns / 1ps -`default_nettype none - -/* - * MDIO master - */ -module mdio_master ( - input wire clk, - input wire rst, - - /* - * Host interface - */ - input wire [4:0] cmd_phy_addr, - input wire [4:0] cmd_reg_addr, - input wire [15:0] cmd_data, - input wire [1:0] cmd_opcode, - input wire cmd_valid, - output wire cmd_ready, - - output wire [15:0] data_out, - output wire data_out_valid, - input wire data_out_ready, - - /* - * MDIO to PHY - */ - output wire mdc_o, - input wire mdio_i, - output wire mdio_o, - output wire mdio_t, - - /* - * Status - */ - output wire busy, - - /* - * Configuration - */ - input wire [7:0] prescale -); - -localparam [1:0] - STATE_IDLE = 2'd0, - STATE_PREAMBLE = 2'd1, - STATE_TRANSFER = 2'd2; - -reg [1:0] state_reg = STATE_IDLE, state_next; - -reg [16:0] count_reg = 16'd0, count_next; -reg [6:0] bit_count_reg = 6'd0, bit_count_next; -reg cycle_reg = 1'b0, cycle_next; - -reg [31:0] data_reg = 32'd0, data_next; - -reg [1:0] op_reg = 2'b00, op_next; - -reg cmd_ready_reg = 1'b0, cmd_ready_next; - -reg [15:0] data_out_reg = 15'd0, data_out_next; -reg data_out_valid_reg = 1'b0, data_out_valid_next; - -reg mdio_i_reg = 1'b1; - -reg mdc_o_reg = 1'b0, mdc_o_next; -reg mdio_o_reg = 1'b0, mdio_o_next; -reg mdio_t_reg = 1'b1, mdio_t_next; - -reg busy_reg = 1'b0; - -assign cmd_ready = cmd_ready_reg; - -assign data_out = data_out_reg; -assign data_out_valid = data_out_valid_reg; - -assign mdc_o = mdc_o_reg; -assign mdio_o = mdio_o_reg; -assign mdio_t = mdio_t_reg; - -assign busy = busy_reg; - -always @* begin - state_next = STATE_IDLE; - - count_next = count_reg; - bit_count_next = bit_count_reg; - cycle_next = cycle_reg; - - data_next = data_reg; - - op_next = op_reg; - - cmd_ready_next = 1'b0; - - data_out_next = data_out_reg; - data_out_valid_next = data_out_valid_reg & ~data_out_ready; - - mdc_o_next = mdc_o_reg; - mdio_o_next = mdio_o_reg; - mdio_t_next = mdio_t_reg; - - if (count_reg > 16'd0) begin - count_next = count_reg - 16'd1; - state_next = state_reg; - end else if (cycle_reg) begin - cycle_next = 1'b0; - mdc_o_next = 1'b1; - count_next = prescale; - state_next = state_reg; - end else begin - mdc_o_next = 1'b0; - case (state_reg) - STATE_IDLE: begin - // idle - accept new command - cmd_ready_next = ~data_out_valid; - - if (cmd_ready & cmd_valid) begin - cmd_ready_next = 1'b0; - data_next = {2'b01, cmd_opcode, cmd_phy_addr, cmd_reg_addr, 2'b10, cmd_data}; - op_next = cmd_opcode; - mdio_t_next = 1'b0; - mdio_o_next = 1'b1; - bit_count_next = 6'd32; - cycle_next = 1'b1; - count_next = prescale; - state_next = STATE_PREAMBLE; - end else begin - state_next = STATE_IDLE; - end - end - STATE_PREAMBLE: begin - cycle_next = 1'b1; - count_next = prescale; - if (bit_count_reg > 6'd1) begin - bit_count_next = bit_count_reg - 6'd1; - state_next = STATE_PREAMBLE; - end else begin - bit_count_next = 6'd32; - {mdio_o_next, data_next} = {data_reg, mdio_i_reg}; - state_next = STATE_TRANSFER; - end - end - STATE_TRANSFER: begin - cycle_next = 1'b1; - count_next = prescale; - if ((op_reg == 2'b10 || op_reg == 2'b11) && bit_count_reg == 6'd19) begin - mdio_t_next = 1'b1; - end - if (bit_count_reg > 6'd1) begin - bit_count_next = bit_count_reg - 6'd1; - {mdio_o_next, data_next} = {data_reg, mdio_i_reg}; - state_next = STATE_TRANSFER; - end else begin - if (op_reg == 2'b10 || op_reg == 2'b11) begin - data_out_next = data_reg[15:0]; - data_out_valid_next = 1'b1; - end - mdio_t_next = 1'b1; - state_next = STATE_IDLE; - end - end - endcase - end -end - -always @(posedge clk) begin - if (rst) begin - state_reg <= STATE_IDLE; - count_reg <= 16'd0; - bit_count_reg <= 6'd0; - cycle_reg <= 1'b0; - cmd_ready_reg <= 1'b0; - data_out_valid_reg <= 1'b0; - mdc_o_reg <= 1'b0; - mdio_o_reg <= 1'b0; - mdio_t_reg <= 1'b1; - busy_reg <= 1'b0; - end else begin - state_reg <= state_next; - count_reg <= count_next; - bit_count_reg <= bit_count_next; - cycle_reg <= cycle_next; - cmd_ready_reg <= cmd_ready_next; - data_out_valid_reg <= data_out_valid_next; - mdc_o_reg <= mdc_o_next; - mdio_o_reg <= mdio_o_next; - mdio_t_reg <= mdio_t_next; - busy_reg <= (state_next != STATE_IDLE || count_reg != 0 || cycle_reg || mdc_o); - end - - data_reg <= data_next; - op_reg <= op_next; - - data_out_reg <= data_out_next; - - mdio_i_reg <= mdio_i; -end - -endmodule - -`resetall diff --git a/example/VCU118/fpga_10g/rtl/sync_signal.v b/example/VCU118/fpga_10g/rtl/sync_signal.v deleted file mode 100644 index 74b855fa1..000000000 --- a/example/VCU118/fpga_10g/rtl/sync_signal.v +++ /dev/null @@ -1,62 +0,0 @@ -/* - -Copyright (c) 2014-2018 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -*/ - -// Language: Verilog-2001 - -`resetall -`timescale 1 ns / 1 ps -`default_nettype none - -/* - * Synchronizes an asyncronous signal to a given clock by using a pipeline of - * two registers. - */ -module sync_signal #( - parameter WIDTH=1, // width of the input and output signals - parameter N=2 // depth of synchronizer -)( - input wire clk, - input wire [WIDTH-1:0] in, - output wire [WIDTH-1:0] out -); - -reg [WIDTH-1:0] sync_reg[N-1:0]; - -/* - * The synchronized output is the last register in the pipeline. - */ -assign out = sync_reg[N-1]; - -integer k; - -always @(posedge clk) begin - sync_reg[0] <= in; - for (k = 1; k < N; k = k + 1) begin - sync_reg[k] <= sync_reg[k-1]; - end -end - -endmodule - -`resetall diff --git a/example/VCU118/fpga_10g/tb/fpga_core/Makefile b/example/VCU118/fpga_10g/tb/fpga_core/Makefile deleted file mode 100644 index 682ed9c2a..000000000 --- a/example/VCU118/fpga_10g/tb/fpga_core/Makefile +++ /dev/null @@ -1,102 +0,0 @@ -# Copyright (c) 2020 Alex Forencich -# -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: -# -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. -# -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -# THE SOFTWARE. - -TOPLEVEL_LANG = verilog - -SIM ?= icarus -WAVES ?= 0 - -COCOTB_HDL_TIMEUNIT = 1ns -COCOTB_HDL_TIMEPRECISION = 1ps - -DUT = fpga_core -TOPLEVEL = $(DUT) -MODULE = test_$(DUT) -VERILOG_SOURCES += ../../rtl/$(DUT).v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_1g_fifo.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_1g.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_gmii_rx.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_gmii_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g_fifo.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_axis_rx.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_axis_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/udp_complete_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/udp_checksum_gen_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/udp_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/udp_ip_rx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/udp_ip_tx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/ip_complete_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/ip_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/ip_eth_rx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/ip_eth_tx_64.v -VERILOG_SOURCES += ../../lib/eth/rtl/ip_arb_mux.v -VERILOG_SOURCES += ../../lib/eth/rtl/arp.v -VERILOG_SOURCES += ../../lib/eth/rtl/arp_cache.v -VERILOG_SOURCES += ../../lib/eth/rtl/arp_eth_rx.v -VERILOG_SOURCES += ../../lib/eth/rtl/arp_eth_tx.v -VERILOG_SOURCES += ../../lib/eth/rtl/eth_arb_mux.v -VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/arbiter.v -VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/priority_encoder.v -VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_adapter.v -VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_fifo.v -VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_switch.v -VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_register.v -VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v -VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v - -# module parameters -#export PARAM_A := value - -ifeq ($(SIM), icarus) - PLUSARGS += -fst - -# COMPILE_ARGS += -P $(TOPLEVEL).A=$(PARAM_A) - - ifeq ($(WAVES), 1) - VERILOG_SOURCES += iverilog_dump.v - COMPILE_ARGS += -s iverilog_dump - endif -else ifeq ($(SIM), verilator) - COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH - -# COMPILE_ARGS += -GA=$(PARAM_A) - - ifeq ($(WAVES), 1) - COMPILE_ARGS += --trace-fst - endif -endif - -include $(shell cocotb-config --makefiles)/Makefile.sim - -iverilog_dump.v: - echo 'module iverilog_dump();' > $@ - echo 'initial begin' >> $@ - echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@ - echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@ - echo 'end' >> $@ - echo 'endmodule' >> $@ - -clean:: - @rm -rf iverilog_dump.v - @rm -rf dump.fst $(TOPLEVEL).fst diff --git a/example/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py b/example/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py deleted file mode 100644 index 2ada7550b..000000000 --- a/example/VCU118/fpga_10g/tb/fpga_core/test_fpga_core.py +++ /dev/null @@ -1,402 +0,0 @@ -""" - -Copyright (c) 2020 Alex Forencich - -Permission is hereby granted, free of charge, to any person obtaining a copy -of this software and associated documentation files (the "Software"), to deal -in the Software without restriction, including without limitation the rights -to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -copies of the Software, and to permit persons to whom the Software is -furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice shall be included in -all copies or substantial portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY -FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -THE SOFTWARE. - -""" - -import logging -import os - -from scapy.layers.l2 import Ether, ARP -from scapy.layers.inet import IP, UDP - -import cocotb_test.simulator - -import cocotb -from cocotb.log import SimLog -from cocotb.clock import Clock -from cocotb.triggers import RisingEdge - -from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink -from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink - - -class TB: - def __init__(self, dut): - self.dut = dut - - self.log = SimLog("cocotb.tb") - self.log.setLevel(logging.DEBUG) - - cocotb.start_soon(Clock(dut.clk, 6.4, units="ns").start()) - - # Ethernet - cocotb.start_soon(Clock(dut.phy_gmii_clk, 8, units="ns").start()) - - self.gmii_source = GmiiSource(dut.phy_gmii_rxd, dut.phy_gmii_rx_er, dut.phy_gmii_rx_dv, - dut.phy_gmii_clk, dut.phy_gmii_rst, dut.phy_gmii_clk_en) - self.gmii_sink = GmiiSink(dut.phy_gmii_txd, dut.phy_gmii_tx_er, dut.phy_gmii_tx_en, - dut.phy_gmii_clk, dut.phy_gmii_rst, dut.phy_gmii_clk_en) - - dut.phy_gmii_clk_en.setimmediatevalue(1) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start()) - self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start()) - self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start()) - self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start()) - self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_1, 6.4, units="ns").start()) - self.qsfp2_1_source = XgmiiSource(dut.qsfp2_rxd_1, dut.qsfp2_rxc_1, dut.qsfp2_rx_clk_1, dut.qsfp2_rx_rst_1) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_1, 6.4, units="ns").start()) - self.qsfp2_1_sink = XgmiiSink(dut.qsfp2_txd_1, dut.qsfp2_txc_1, dut.qsfp2_tx_clk_1, dut.qsfp2_tx_rst_1) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_2, 6.4, units="ns").start()) - self.qsfp2_2_source = XgmiiSource(dut.qsfp2_rxd_2, dut.qsfp2_rxc_2, dut.qsfp2_rx_clk_2, dut.qsfp2_rx_rst_2) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_2, 6.4, units="ns").start()) - self.qsfp2_2_sink = XgmiiSink(dut.qsfp2_txd_2, dut.qsfp2_txc_2, dut.qsfp2_tx_clk_2, dut.qsfp2_tx_rst_2) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_3, 6.4, units="ns").start()) - self.qsfp2_3_source = XgmiiSource(dut.qsfp2_rxd_3, dut.qsfp2_rxc_3, dut.qsfp2_rx_clk_3, dut.qsfp2_rx_rst_3) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_3, 6.4, units="ns").start()) - self.qsfp2_3_sink = XgmiiSink(dut.qsfp2_txd_3, dut.qsfp2_txc_3, dut.qsfp2_tx_clk_3, dut.qsfp2_tx_rst_3) - - cocotb.start_soon(Clock(dut.qsfp2_rx_clk_4, 6.4, units="ns").start()) - self.qsfp2_4_source = XgmiiSource(dut.qsfp2_rxd_4, dut.qsfp2_rxc_4, dut.qsfp2_rx_clk_4, dut.qsfp2_rx_rst_4) - cocotb.start_soon(Clock(dut.qsfp2_tx_clk_4, 6.4, units="ns").start()) - self.qsfp2_4_sink = XgmiiSink(dut.qsfp2_txd_4, dut.qsfp2_txc_4, dut.qsfp2_tx_clk_4, dut.qsfp2_tx_rst_4) - - dut.btnu.setimmediatevalue(0) - dut.btnl.setimmediatevalue(0) - dut.btnd.setimmediatevalue(0) - dut.btnr.setimmediatevalue(0) - dut.btnc.setimmediatevalue(0) - dut.sw.setimmediatevalue(0) - dut.uart_rxd.setimmediatevalue(0) - dut.uart_cts.setimmediatevalue(0) - - async def init(self): - - self.dut.rst.setimmediatevalue(0) - self.dut.phy_gmii_rst.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp1_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp1_tx_rst_4.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_1.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_1.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_2.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_2.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_3.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_3.setimmediatevalue(0) - self.dut.qsfp2_rx_rst_4.setimmediatevalue(0) - self.dut.qsfp2_tx_rst_4.setimmediatevalue(0) - - for k in range(10): - await RisingEdge(self.dut.clk) - - self.dut.rst.value = 1 - self.dut.phy_gmii_rst.value = 1 - self.dut.qsfp1_rx_rst_1.value = 1 - self.dut.qsfp1_tx_rst_1.value = 1 - self.dut.qsfp1_rx_rst_2.value = 1 - self.dut.qsfp1_tx_rst_2.value = 1 - self.dut.qsfp1_rx_rst_3.value = 1 - self.dut.qsfp1_tx_rst_3.value = 1 - self.dut.qsfp1_rx_rst_4.value = 1 - self.dut.qsfp1_tx_rst_4.value = 1 - self.dut.qsfp2_rx_rst_1.value = 1 - self.dut.qsfp2_tx_rst_1.value = 1 - self.dut.qsfp2_rx_rst_2.value = 1 - self.dut.qsfp2_tx_rst_2.value = 1 - self.dut.qsfp2_rx_rst_3.value = 1 - self.dut.qsfp2_tx_rst_3.value = 1 - self.dut.qsfp2_rx_rst_4.value = 1 - self.dut.qsfp2_tx_rst_4.value = 1 - - for k in range(10): - await RisingEdge(self.dut.clk) - - self.dut.rst.value = 0 - self.dut.phy_gmii_rst.value = 0 - self.dut.qsfp1_rx_rst_1.value = 0 - self.dut.qsfp1_tx_rst_1.value = 0 - self.dut.qsfp1_rx_rst_2.value = 0 - self.dut.qsfp1_tx_rst_2.value = 0 - self.dut.qsfp1_rx_rst_3.value = 0 - self.dut.qsfp1_tx_rst_3.value = 0 - self.dut.qsfp1_rx_rst_4.value = 0 - self.dut.qsfp1_tx_rst_4.value = 0 - self.dut.qsfp2_rx_rst_1.value = 0 - self.dut.qsfp2_tx_rst_1.value = 0 - self.dut.qsfp2_rx_rst_2.value = 0 - self.dut.qsfp2_tx_rst_2.value = 0 - self.dut.qsfp2_rx_rst_3.value = 0 - self.dut.qsfp2_tx_rst_3.value = 0 - self.dut.qsfp2_rx_rst_4.value = 0 - self.dut.qsfp2_tx_rst_4.value = 0 - - -@cocotb.test() -async def run_test(dut): - - tb = TB(dut) - - await tb.init() - - tb.log.info("test UDP RX packet") - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') - ip = IP(src='192.168.1.100', dst='192.168.1.128') - udp = UDP(sport=5678, dport=1234) - test_pkt = eth / ip / udp / payload - - test_frame = XgmiiFrame.from_payload(test_pkt.build()) - - await tb.qsfp1_1_source.send(test_frame) - - tb.log.info("receive ARP request") - - rx_frame = await tb.qsfp1_1_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff' - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[ARP].hwtype == 1 - assert rx_pkt[ARP].ptype == 0x0800 - assert rx_pkt[ARP].hwlen == 6 - assert rx_pkt[ARP].plen == 4 - assert rx_pkt[ARP].op == 1 - assert rx_pkt[ARP].hwsrc == test_pkt.dst - assert rx_pkt[ARP].psrc == test_pkt[IP].dst - assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00' - assert rx_pkt[ARP].pdst == test_pkt[IP].src - - tb.log.info("send ARP response") - - eth = Ether(src=test_pkt.src, dst=test_pkt.dst) - arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2, - hwsrc=test_pkt.src, psrc=test_pkt[IP].src, - hwdst=test_pkt.dst, pdst=test_pkt[IP].dst) - resp_pkt = eth / arp - - resp_frame = XgmiiFrame.from_payload(resp_pkt.build()) - - await tb.qsfp1_1_source.send(resp_frame) - - tb.log.info("receive UDP packet") - - rx_frame = await tb.qsfp1_1_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == test_pkt.src - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[IP].dst == test_pkt[IP].src - assert rx_pkt[IP].src == test_pkt[IP].dst - assert rx_pkt[UDP].dport == test_pkt[UDP].sport - assert rx_pkt[UDP].sport == test_pkt[UDP].dport - assert rx_pkt[UDP].payload == test_pkt[UDP].payload - - tb.log.info("test gigabit tap, RX side") - - # insert tap - await RisingEdge(dut.clk) - dut.sw.value = 0x8 - await RisingEdge(dut.clk) - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') - ip = IP(src='192.168.1.100', dst='192.168.1.128') - udp = UDP(sport=5678, dport=1234) - test_pkt = eth / ip / udp / payload - - test_frame = GmiiFrame.from_payload(test_pkt.build()) - - await tb.gmii_source.send(test_frame) - - tb.log.info("loop back packet on XGMII interface") - - rx_frame = await tb.qsfp1_1_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - await tb.qsfp1_1_source.send(rx_frame) - - tb.log.info("receive UDP packet") - - rx_frame = await tb.gmii_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == test_pkt.src - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[IP].dst == test_pkt[IP].src - assert rx_pkt[IP].src == test_pkt[IP].dst - assert rx_pkt[UDP].dport == test_pkt[UDP].sport - assert rx_pkt[UDP].sport == test_pkt[UDP].dport - assert rx_pkt[UDP].payload == test_pkt[UDP].payload - - tb.log.info("test gigabit tap, TX side") - - # insert tap - await RisingEdge(dut.clk) - dut.sw.value = 0xC - await RisingEdge(dut.clk) - - payload = bytes([x % 256 for x in range(256)]) - eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00') - ip = IP(src='192.168.1.100', dst='192.168.1.128') - udp = UDP(sport=5678, dport=1234) - test_pkt = eth / ip / udp / payload - - test_frame = GmiiFrame.from_payload(test_pkt.build()) - - await tb.gmii_source.send(test_frame) - - tb.log.info("loop back packet on XGMII interface") - - rx_frame = await tb.qsfp1_1_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - await tb.qsfp1_1_source.send(rx_frame) - - tb.log.info("receive UDP packet") - - rx_frame = await tb.gmii_sink.recv() - - rx_pkt = Ether(bytes(rx_frame.get_payload())) - - tb.log.info("RX packet: %s", repr(rx_pkt)) - - assert rx_pkt.dst == test_pkt.src - assert rx_pkt.src == test_pkt.dst - assert rx_pkt[IP].dst == test_pkt[IP].src - assert rx_pkt[IP].src == test_pkt[IP].dst - assert rx_pkt[UDP].dport == test_pkt[UDP].sport - assert rx_pkt[UDP].sport == test_pkt[UDP].dport - assert rx_pkt[UDP].payload == test_pkt[UDP].payload - - await RisingEdge(dut.clk) - await RisingEdge(dut.clk) - - -# cocotb-test - -tests_dir = os.path.abspath(os.path.dirname(__file__)) -rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl')) -lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib')) -axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl')) -eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl')) - - -def test_fpga_core(request): - dut = "fpga_core" - module = os.path.splitext(os.path.basename(__file__))[0] - toplevel = dut - - verilog_sources = [ - os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(eth_rtl_dir, "eth_mac_1g_fifo.v"), - os.path.join(eth_rtl_dir, "eth_mac_1g.v"), - os.path.join(eth_rtl_dir, "axis_gmii_rx.v"), - os.path.join(eth_rtl_dir, "axis_gmii_tx.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"), - os.path.join(eth_rtl_dir, "eth_mac_10g.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"), - os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"), - os.path.join(eth_rtl_dir, "lfsr.v"), - os.path.join(eth_rtl_dir, "eth_axis_rx.v"), - os.path.join(eth_rtl_dir, "eth_axis_tx.v"), - os.path.join(eth_rtl_dir, "udp_complete_64.v"), - os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"), - os.path.join(eth_rtl_dir, "udp_64.v"), - os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"), - os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"), - os.path.join(eth_rtl_dir, "ip_complete_64.v"), - os.path.join(eth_rtl_dir, "ip_64.v"), - os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"), - os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"), - os.path.join(eth_rtl_dir, "ip_arb_mux.v"), - os.path.join(eth_rtl_dir, "arp.v"), - os.path.join(eth_rtl_dir, "arp_cache.v"), - os.path.join(eth_rtl_dir, "arp_eth_rx.v"), - os.path.join(eth_rtl_dir, "arp_eth_tx.v"), - os.path.join(eth_rtl_dir, "eth_arb_mux.v"), - os.path.join(axis_rtl_dir, "arbiter.v"), - os.path.join(axis_rtl_dir, "priority_encoder.v"), - os.path.join(axis_rtl_dir, "axis_adapter.v"), - os.path.join(axis_rtl_dir, "axis_fifo.v"), - os.path.join(axis_rtl_dir, "axis_switch.v"), - os.path.join(axis_rtl_dir, "axis_register.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo.v"), - os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"), - ] - - parameters = {} - - # parameters['A'] = val - - extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()} - - sim_build = os.path.join(tests_dir, "sim_build", - request.node.name.replace('[', '-').replace(']', '')) - - cocotb_test.simulator.run( - python_search=[tests_dir], - verilog_sources=verilog_sources, - toplevel=toplevel, - module=module, - parameters=parameters, - sim_build=sim_build, - extra_env=extra_env, - ) diff --git a/example/VCU118/fpga_25g/fpga/Makefile b/example/VCU118/fpga_25g/fpga/Makefile index d4f4ee3a7..81d9f3750 100644 --- a/example/VCU118/fpga_25g/fpga/Makefile +++ b/example/VCU118/fpga_25g/fpga/Makefile @@ -67,6 +67,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl IP_TCL_FILES += ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/example/VCU118/fpga_25g/fpga/config.tcl b/example/VCU118/fpga_25g/fpga/config.tcl new file mode 100644 index 000000000..1fda15c32 --- /dev/null +++ b/example/VCU118/fpga_25g/fpga/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {25.78125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {156.25} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel] diff --git a/example/VCU118/fpga_10g/fpga/Makefile b/example/VCU118/fpga_25g/fpga_10g/Makefile similarity index 99% rename from example/VCU118/fpga_10g/fpga/Makefile rename to example/VCU118/fpga_25g/fpga_10g/Makefile index d4f4ee3a7..81d9f3750 100644 --- a/example/VCU118/fpga_10g/fpga/Makefile +++ b/example/VCU118/fpga_25g/fpga_10g/Makefile @@ -67,6 +67,9 @@ XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl IP_TCL_FILES += ip/eth_xcvr_gt.tcl +# Configuration +CONFIG_TCL_FILES = ./config.tcl + include ../common/vivado.mk program: $(FPGA_TOP).bit diff --git a/example/VCU118/fpga_25g/fpga_10g/config.tcl b/example/VCU118/fpga_25g/fpga_10g/config.tcl new file mode 100644 index 000000000..9b95d246e --- /dev/null +++ b/example/VCU118/fpga_25g/fpga_10g/config.tcl @@ -0,0 +1,50 @@ +# Copyright (c) 2023 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +# Transceiver configuration +set eth_xcvr_freerun_freq {125} +set eth_xcvr_line_rate {10.3125} +set eth_xcvr_sec_line_rate {0} +set eth_xcvr_refclk_freq {156.25} +set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}] +set eth_xcvr_rx_eq_mode {DFE} + +set xcvr_config [dict create] + +dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate +dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn +dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode +if {$eth_xcvr_sec_line_rate != 0} { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true + dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn + dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate + dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq +} else { + dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false +} +dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq + +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full] +set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel]