From 268d0c66b8269d30d926d85d1106a60ae5bc0b02 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Fri, 13 May 2022 12:57:41 -0700
Subject: [PATCH 1/6] Rewrite resets

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 rtl/arbiter.v                  | 10 +++----
 rtl/axis_adapter.v             | 18 ++++++-------
 rtl/axis_arb_mux.v             | 18 ++++++-------
 rtl/axis_broadcast.v           | 18 ++++++-------
 rtl/axis_cobs_decode.v         | 37 +++++++++++++-------------
 rtl/axis_cobs_encode.v         | 32 +++++++++++------------
 rtl/axis_crosspoint.v          | 22 +++++++---------
 rtl/axis_demux.v               | 28 ++++++++++----------
 rtl/axis_frame_join.v          | 42 ++++++++++++++---------------
 rtl/axis_frame_length_adjust.v | 18 ++++++-------
 rtl/axis_mux.v                 | 26 +++++++++---------
 rtl/axis_rate_limit.v          | 26 +++++++++---------
 rtl/axis_register.v            | 32 +++++++++++------------
 rtl/axis_srl_fifo.v            | 28 ++++++++++----------
 rtl/axis_srl_register.v        | 36 ++++++++++++-------------
 rtl/axis_stat_counter.v        | 48 +++++++++++++++++-----------------
 rtl/axis_switch.v              | 11 ++++----
 rtl/axis_tap.v                 | 32 +++++++++++------------
 18 files changed, 240 insertions(+), 242 deletions(-)

diff --git a/rtl/arbiter.v b/rtl/arbiter.v
index cfac70d1c..762907788 100644
--- a/rtl/arbiter.v
+++ b/rtl/arbiter.v
@@ -141,16 +141,16 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    grant_reg <= grant_next;
+    grant_valid_reg <= grant_valid_next;
+    grant_encoded_reg <= grant_encoded_next;
+    mask_reg <= mask_next;
+
     if (rst) begin
         grant_reg <= 0;
         grant_valid_reg <= 0;
         grant_encoded_reg <= 0;
         mask_reg <= 0;
-    end else begin
-        grant_reg <= grant_next;
-        grant_valid_reg <= grant_valid_next;
-        grant_encoded_reg <= grant_encoded_next;
-        mask_reg <= mask_next;
     end
 end
 
diff --git a/rtl/axis_adapter.v b/rtl/axis_adapter.v
index 51aa226ac..288fa16c6 100644
--- a/rtl/axis_adapter.v
+++ b/rtl/axis_adapter.v
@@ -516,15 +516,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -551,6 +545,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/axis_arb_mux.v b/rtl/axis_arb_mux.v
index 43a588f41..54c1fda5c 100644
--- a/rtl/axis_arb_mux.v
+++ b/rtl/axis_arb_mux.v
@@ -238,15 +238,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -273,6 +267,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/axis_broadcast.v b/rtl/axis_broadcast.v
index 34fafd266..5fc7efff1 100644
--- a/rtl/axis_broadcast.v
+++ b/rtl/axis_broadcast.v
@@ -153,15 +153,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        s_axis_tready_reg <= 1'b0;
-        m_axis_tvalid_reg <= {M_COUNT{1'b0}};
-        temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
-    end else begin
-        s_axis_tready_reg <= s_axis_tready_early;
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    s_axis_tready_reg <= s_axis_tready_early;
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_input_to_output) begin
@@ -188,6 +182,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= s_axis_tdest;
         temp_m_axis_tuser_reg <= s_axis_tuser;
     end
+
+    if (rst) begin
+        s_axis_tready_reg <= 1'b0;
+        m_axis_tvalid_reg <= {M_COUNT{1'b0}};
+        temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
+    end
 end
 
 endmodule
diff --git a/rtl/axis_cobs_decode.v b/rtl/axis_cobs_decode.v
index 84f504705..6ed969896 100644
--- a/rtl/axis_cobs_decode.v
+++ b/rtl/axis_cobs_decode.v
@@ -230,20 +230,21 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    state_reg <= state_next;
+
+    count_reg <= count_next;
+    suppress_zero_reg <= suppress_zero_next;
+
+    temp_tdata_reg <= temp_tdata_next;
+    temp_tvalid_reg <= temp_tvalid_next;
+
+    s_axis_tready_reg <= s_axis_tready_next;
+
     if (rst) begin
         state_reg <= STATE_IDLE;
         temp_tvalid_reg <= 1'b0;
         s_axis_tready_reg <= 1'b0;
-    end else begin
-        state_reg <= state_next;
-        temp_tvalid_reg <= temp_tvalid_next;
-        s_axis_tready_reg <= s_axis_tready_next;
     end
-
-    temp_tdata_reg <= temp_tdata_next;
-
-    count_reg <= count_next;
-    suppress_zero_reg <= suppress_zero_next;
 end
 
 // output datapath logic
@@ -299,15 +300,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -325,6 +320,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/axis_cobs_encode.v b/rtl/axis_cobs_encode.v
index c88e95cbe..f3786e45d 100644
--- a/rtl/axis_cobs_encode.v
+++ b/rtl/axis_cobs_encode.v
@@ -411,17 +411,17 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        input_state_reg <= INPUT_STATE_IDLE;
-        output_state_reg <= OUTPUT_STATE_IDLE;
-    end else begin
-        input_state_reg <= input_state_next;
-        output_state_reg <= output_state_next;
-    end
+    input_state_reg <= input_state_next;
+    output_state_reg <= output_state_next;
 
     input_count_reg <= input_count_next;
     output_count_reg <= output_count_next;
     fail_frame_reg <= fail_frame_next;
+
+    if (rst) begin
+        input_state_reg <= INPUT_STATE_IDLE;
+        output_state_reg <= OUTPUT_STATE_IDLE;
+    end
 end
 
 // output datapath logic
@@ -477,15 +477,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -503,6 +497,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/axis_crosspoint.v b/rtl/axis_crosspoint.v
index 7fde4ab4e..9b84caa22 100644
--- a/rtl/axis_crosspoint.v
+++ b/rtl/axis_crosspoint.v
@@ -121,33 +121,31 @@ assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {M_COUNT*USER_WIDTH{1'b0
 integer i;
 
 always @(posedge clk) begin
-    if (rst) begin
-        s_axis_tvalid_reg <= {S_COUNT{1'b0}};
-        m_axis_tvalid_reg <= {S_COUNT{1'b0}};
-        select_reg <= {M_COUNT*CL_S_COUNT{1'b0}};
-    end else begin
-        s_axis_tvalid_reg <= s_axis_tvalid;
-        for (i = 0; i < M_COUNT; i = i + 1) begin
-            m_axis_tvalid_reg[i] <= s_axis_tvalid_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]];
-        end
-        select_reg <= select;
-    end
-
     s_axis_tdata_reg <= s_axis_tdata;
     s_axis_tkeep_reg <= s_axis_tkeep;
+    s_axis_tvalid_reg <= s_axis_tvalid;
     s_axis_tlast_reg <= s_axis_tlast;
     s_axis_tid_reg   <= s_axis_tid;
     s_axis_tdest_reg <= s_axis_tdest;
     s_axis_tuser_reg <= s_axis_tuser;
 
+    select_reg <= select;
+
     for (i = 0; i < M_COUNT; i = i + 1) begin
         m_axis_tdata_reg[i*DATA_WIDTH +: DATA_WIDTH] <= s_axis_tdata_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*DATA_WIDTH +: DATA_WIDTH];
         m_axis_tkeep_reg[i*KEEP_WIDTH +: KEEP_WIDTH] <= s_axis_tkeep_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*KEEP_WIDTH +: KEEP_WIDTH];
+        m_axis_tvalid_reg[i] <= s_axis_tvalid_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]];
         m_axis_tlast_reg[i]                          <= s_axis_tlast_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]];
         m_axis_tid_reg[i*ID_WIDTH +: ID_WIDTH]       <= s_axis_tid_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*ID_WIDTH +: ID_WIDTH];
         m_axis_tdest_reg[i*DEST_WIDTH +: DEST_WIDTH] <= s_axis_tdest_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*DEST_WIDTH +: DEST_WIDTH];
         m_axis_tuser_reg[i*USER_WIDTH +: USER_WIDTH] <= s_axis_tuser_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*USER_WIDTH +: USER_WIDTH];
     end
+
+    if (rst) begin
+        s_axis_tvalid_reg <= {S_COUNT{1'b0}};
+        m_axis_tvalid_reg <= {S_COUNT{1'b0}};
+        select_reg <= {M_COUNT*CL_S_COUNT{1'b0}};
+    end
 end
 
 endmodule
diff --git a/rtl/axis_demux.v b/rtl/axis_demux.v
index 7edd757f5..41076747b 100644
--- a/rtl/axis_demux.v
+++ b/rtl/axis_demux.v
@@ -184,16 +184,16 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    select_reg <= select_next;
+    drop_reg <= drop_next;
+    frame_reg <= frame_next;
+    s_axis_tready_reg <= s_axis_tready_next;
+
     if (rst) begin
         select_reg <= 2'd0;
         drop_reg <= 1'b0;
         frame_reg <= 1'b0;
         s_axis_tready_reg <= 1'b0;
-    end else begin
-        select_reg <= select_next;
-        drop_reg <= drop_next;
-        frame_reg <= frame_next;
-        s_axis_tready_reg <= s_axis_tready_next;
     end
 end
 
@@ -259,15 +259,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= {M_COUNT{1'b0}};
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -294,6 +288,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= {M_COUNT{1'b0}};
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= {M_COUNT{1'b0}};
+    end
 end
 
 endmodule
diff --git a/rtl/axis_frame_join.v b/rtl/axis_frame_join.v
index d25f5c6e6..03752995a 100644
--- a/rtl/axis_frame_join.v
+++ b/rtl/axis_frame_join.v
@@ -223,6 +223,18 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    state_reg <= state_next;
+
+    frame_ptr_reg <= frame_ptr_next;
+
+    port_sel_reg <= port_sel_next;
+
+    s_axis_tready_reg <= s_axis_tready_next;
+
+    output_tuser_reg <= output_tuser_next;
+
+    busy_reg <= state_next != STATE_IDLE;
+
     if (rst) begin
         state_reg <= STATE_IDLE;
         frame_ptr_reg <= {CL_TAG_WORD_WIDTH{1'b0}};
@@ -230,18 +242,6 @@ always @(posedge clk) begin
         s_axis_tready_reg <= {S_COUNT{1'b0}};
         output_tuser_reg <= 1'b0;
         busy_reg <= 1'b0;
-    end else begin
-        state_reg <= state_next;
-
-        frame_ptr_reg <= frame_ptr_next;
-
-        port_sel_reg <= port_sel_next;
-
-        s_axis_tready_reg <= s_axis_tready_next;
-
-        output_tuser_reg <= output_tuser_next;
-
-        busy_reg <= state_next != STATE_IDLE;
     end
 end
 
@@ -298,15 +298,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -324,6 +318,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/axis_frame_length_adjust.v b/rtl/axis_frame_length_adjust.v
index 92fb2ec11..6c2188bbc 100644
--- a/rtl/axis_frame_length_adjust.v
+++ b/rtl/axis_frame_length_adjust.v
@@ -575,15 +575,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -610,6 +604,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/axis_mux.v b/rtl/axis_mux.v
index ab021d3ef..f8f1d0851 100644
--- a/rtl/axis_mux.v
+++ b/rtl/axis_mux.v
@@ -152,14 +152,14 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    select_reg <= select_next;
+    frame_reg <= frame_next;
+    s_axis_tready_reg <= s_axis_tready_next;
+
     if (rst) begin
         select_reg <= 0;
         frame_reg <= 1'b0;
         s_axis_tready_reg <= 0;
-    end else begin
-        select_reg <= select_next;
-        frame_reg <= frame_next;
-        s_axis_tready_reg <= s_axis_tready_next;
     end
 end
 
@@ -225,15 +225,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -260,6 +254,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/axis_rate_limit.v b/rtl/axis_rate_limit.v
index 24ec9546a..e748a15c5 100644
--- a/rtl/axis_rate_limit.v
+++ b/rtl/axis_rate_limit.v
@@ -145,14 +145,14 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    acc_reg <= acc_next;
+    frame_reg <= frame_next;
+    s_axis_tready_reg <= s_axis_tready_next;
+
     if (rst) begin
         acc_reg <= 24'd0;
         frame_reg <= 1'b0;
         s_axis_tready_reg <= 1'b0;
-    end else begin
-        acc_reg <= acc_next;
-        frame_reg <= frame_next;
-        s_axis_tready_reg <= s_axis_tready_next;
     end
 end
 
@@ -218,15 +218,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -253,6 +247,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/axis_register.v b/rtl/axis_register.v
index 7e8f10931..93fe0bee6 100644
--- a/rtl/axis_register.v
+++ b/rtl/axis_register.v
@@ -157,15 +157,9 @@ if (REG_TYPE > 1) begin
     end
 
     always @(posedge clk) begin
-        if (rst) begin
-            s_axis_tready_reg <= 1'b0;
-            m_axis_tvalid_reg <= 1'b0;
-            temp_m_axis_tvalid_reg <= 1'b0;
-        end else begin
-            s_axis_tready_reg <= s_axis_tready_early;
-            m_axis_tvalid_reg <= m_axis_tvalid_next;
-            temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-        end
+        s_axis_tready_reg <= s_axis_tready_early;
+        m_axis_tvalid_reg <= m_axis_tvalid_next;
+        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
         // datapath
         if (store_axis_input_to_output) begin
@@ -192,6 +186,12 @@ if (REG_TYPE > 1) begin
             temp_m_axis_tdest_reg <= s_axis_tdest;
             temp_m_axis_tuser_reg <= s_axis_tuser;
         end
+
+        if (rst) begin
+            s_axis_tready_reg <= 1'b0;
+            m_axis_tvalid_reg <= 1'b0;
+            temp_m_axis_tvalid_reg <= 1'b0;
+        end
     end
 
 end else if (REG_TYPE == 1) begin
@@ -239,13 +239,8 @@ end else if (REG_TYPE == 1) begin
     end
 
     always @(posedge clk) begin
-        if (rst) begin
-            s_axis_tready_reg <= 1'b0;
-            m_axis_tvalid_reg <= 1'b0;
-        end else begin
-            s_axis_tready_reg <= s_axis_tready_early;
-            m_axis_tvalid_reg <= m_axis_tvalid_next;
-        end
+        s_axis_tready_reg <= s_axis_tready_early;
+        m_axis_tvalid_reg <= m_axis_tvalid_next;
 
         // datapath
         if (store_axis_input_to_output) begin
@@ -256,6 +251,11 @@ end else if (REG_TYPE == 1) begin
             m_axis_tdest_reg <= s_axis_tdest;
             m_axis_tuser_reg <= s_axis_tuser;
         end
+
+        if (rst) begin
+            s_axis_tready_reg <= 1'b0;
+            m_axis_tvalid_reg <= 1'b0;
+        end
     end
 
 end else begin
diff --git a/rtl/axis_srl_fifo.v b/rtl/axis_srl_fifo.v
index 7eabf8f45..5907dd448 100644
--- a/rtl/axis_srl_fifo.v
+++ b/rtl/axis_srl_fifo.v
@@ -169,29 +169,29 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        ptr_reg <= 0;
-        full_reg <= 1'b0;
-        empty_reg <= 1'b1;
+    if (inc) begin
+        ptr_reg <= ptr_reg + 1;
+    end else if (dec) begin
+        ptr_reg <= ptr_reg - 1;
     end else begin
-        if (inc) begin
-            ptr_reg <= ptr_reg + 1;
-        end else if (dec) begin
-            ptr_reg <= ptr_reg - 1;
-        end else begin
-            ptr_reg <= ptr_reg;
-        end
-
-        full_reg <= full_next;
-        empty_reg <= empty_next;
+        ptr_reg <= ptr_reg;
     end
 
+    full_reg <= full_next;
+    empty_reg <= empty_next;
+
     if (shift) begin
         data_reg[0] <= s_axis;
         for (i = 0; i < DEPTH-1; i = i + 1) begin
             data_reg[i+1] <= data_reg[i];
         end
     end
+
+    if (rst) begin
+        ptr_reg <= 0;
+        full_reg <= 1'b0;
+        empty_reg <= 1'b1;
+    end
 end
 
 endmodule
diff --git a/rtl/axis_srl_register.v b/rtl/axis_srl_register.v
index f0e9efee2..bfe945a5c 100644
--- a/rtl/axis_srl_register.v
+++ b/rtl/axis_srl_register.v
@@ -129,27 +129,27 @@ initial begin
 end
 
 always @(posedge clk) begin
+    // transfer empty to full
+    full_reg <= !m_axis_tready && m_axis_tvalid;
+
+    // transfer in if not full
+    if (s_axis_tready) begin
+        data_reg[0] <= s_axis;
+        valid_reg[0] <= s_axis_tvalid;
+        for (i = 0; i < 1; i = i + 1) begin
+            data_reg[i+1] <= data_reg[i];
+            valid_reg[i+1] <= valid_reg[i];
+        end
+        ptr_reg <= valid_reg[0];
+    end
+
+    if (m_axis_tready) begin
+        ptr_reg <= 0;
+    end
+
     if (rst) begin
         ptr_reg <= 0;
         full_reg <= 0;
-    end else begin
-        // transfer empty to full
-        full_reg <= !m_axis_tready && m_axis_tvalid;
-
-        // transfer in if not full
-        if (s_axis_tready) begin
-            data_reg[0] <= s_axis;
-            valid_reg[0] <= s_axis_tvalid;
-            for (i = 0; i < 1; i = i + 1) begin
-                data_reg[i+1] <= data_reg[i];
-                valid_reg[i+1] <= valid_reg[i];
-            end
-            ptr_reg <= valid_reg[0];
-        end
-
-        if (m_axis_tready) begin
-            ptr_reg <= 0;
-        end
     end
 end
 
diff --git a/rtl/axis_stat_counter.v b/rtl/axis_stat_counter.v
index cc0476083..9e64b5a58 100644
--- a/rtl/axis_stat_counter.v
+++ b/rtl/axis_stat_counter.v
@@ -258,6 +258,21 @@ always @* begin
 end
 
 always @(posedge clk) begin
+    state_reg <= state_next;
+    tick_count_reg <= tick_count_next;
+    byte_count_reg <= byte_count_next;
+    frame_count_reg <= frame_count_next;
+    frame_reg <= frame_next;
+    frame_ptr_reg <= frame_ptr_next;
+
+    busy_reg <= state_next != STATE_IDLE;
+
+    if (store_output) begin
+        tick_count_output_reg <= tick_count_reg;
+        byte_count_output_reg <= byte_count_reg;
+        frame_count_output_reg <= frame_count_reg;
+    end
+
     if (rst) begin
         state_reg <= STATE_IDLE;
         tick_count_reg <= 0;
@@ -266,21 +281,6 @@ always @(posedge clk) begin
         frame_reg <= 1'b0;
         frame_ptr_reg <= 0;
         busy_reg <= 1'b0;
-    end else begin
-        state_reg <= state_next;
-        tick_count_reg <= tick_count_next;
-        byte_count_reg <= byte_count_next;
-        frame_count_reg <= frame_count_next;
-        frame_reg <= frame_next;
-        frame_ptr_reg <= frame_ptr_next;
-
-        busy_reg <= state_next != STATE_IDLE;
-    end
-
-    if (store_output) begin
-        tick_count_output_reg <= tick_count_reg;
-        byte_count_output_reg <= byte_count_reg;
-        frame_count_output_reg <= frame_count_reg;
     end
 end
 
@@ -337,15 +337,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -363,6 +357,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/axis_switch.v b/rtl/axis_switch.v
index d791294bb..fae45fb19 100644
--- a/rtl/axis_switch.v
+++ b/rtl/axis_switch.v
@@ -258,14 +258,13 @@ generate
         end
 
         always @(posedge clk) begin
-            if (rst) begin
-                select_valid_reg <= 1'b0;
-            end else begin
-                select_valid_reg <= select_valid_next;
-            end
-
             select_reg <= select_next;
             drop_reg <= drop_next;
+            select_valid_reg <= select_valid_next;
+
+            if (rst) begin
+                select_valid_reg <= 1'b0;
+            end
         end
 
         // forwarding
diff --git a/rtl/axis_tap.v b/rtl/axis_tap.v
index 13966adcb..162ff6a35 100644
--- a/rtl/axis_tap.v
+++ b/rtl/axis_tap.v
@@ -213,19 +213,19 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        state_reg <= STATE_IDLE;
-        frame_reg <= 1'b0;
-    end else begin
-        state_reg <= state_next;
-        frame_reg <= frame_next;
-    end
+    state_reg <= state_next;
+    frame_reg <= frame_next;
 
     if (store_last_word) begin
         last_word_id_reg   <= tap_axis_tid;
         last_word_dest_reg <= tap_axis_tdest;
         last_word_user_reg <= tap_axis_tuser;
     end
+
+    if (rst) begin
+        state_reg <= STATE_IDLE;
+        frame_reg <= 1'b0;
+    end
 end
 
 // output datapath logic
@@ -290,15 +290,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -325,6 +319,12 @@ always @(posedge clk) begin
         temp_m_axis_tdest_reg <= m_axis_tdest_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

From 6d4458e5cc15df401b82a8fd615b3216e6a61d0e Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Sun, 15 May 2022 17:36:00 -0700
Subject: [PATCH 2/6] Rewrite early ready condition

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 rtl/axis_adapter.v             | 4 ++--
 rtl/axis_arb_mux.v             | 4 ++--
 rtl/axis_broadcast.v           | 4 ++--
 rtl/axis_cobs_decode.v         | 4 ++--
 rtl/axis_cobs_encode.v         | 4 ++--
 rtl/axis_demux.v               | 4 ++--
 rtl/axis_frame_join.v          | 4 ++--
 rtl/axis_frame_length_adjust.v | 4 ++--
 rtl/axis_mux.v                 | 4 ++--
 rtl/axis_rate_limit.v          | 4 ++--
 rtl/axis_register.v            | 4 ++--
 rtl/axis_stat_counter.v        | 4 ++--
 rtl/axis_tap.v                 | 4 ++--
 13 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/rtl/axis_adapter.v b/rtl/axis_adapter.v
index 288fa16c6..2cea00b74 100644
--- a/rtl/axis_adapter.v
+++ b/rtl/axis_adapter.v
@@ -484,8 +484,8 @@ assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
 assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_arb_mux.v b/rtl/axis_arb_mux.v
index 54c1fda5c..a544a31ac 100644
--- a/rtl/axis_arb_mux.v
+++ b/rtl/axis_arb_mux.v
@@ -206,8 +206,8 @@ assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {M_ID_WIDTH{1'b0}};
 assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_broadcast.v b/rtl/axis_broadcast.v
index 5fc7efff1..b5c41a39c 100644
--- a/rtl/axis_broadcast.v
+++ b/rtl/axis_broadcast.v
@@ -121,8 +121,8 @@ assign m_axis_tid    = ID_ENABLE   ? {M_COUNT{m_axis_tid_reg}}   : {M_COUNT*ID_W
 assign m_axis_tdest  = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid || !s_axis_tvalid));
+// enable ready input next cycle if output is ready or if both output registers are empty
+wire s_axis_tready_early = ((m_axis_tready & m_axis_tvalid) == m_axis_tvalid) || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_cobs_decode.v b/rtl/axis_cobs_decode.v
index 6ed969896..50c763b22 100644
--- a/rtl/axis_cobs_decode.v
+++ b/rtl/axis_cobs_decode.v
@@ -268,8 +268,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_cobs_encode.v b/rtl/axis_cobs_encode.v
index f3786e45d..4afdbacbc 100644
--- a/rtl/axis_cobs_encode.v
+++ b/rtl/axis_cobs_encode.v
@@ -445,8 +445,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_demux.v b/rtl/axis_demux.v
index 41076747b..89e33fe1f 100644
--- a/rtl/axis_demux.v
+++ b/rtl/axis_demux.v
@@ -227,8 +227,8 @@ assign m_axis_tid    = ID_ENABLE   ? {M_COUNT{m_axis_tid_reg}}   : {M_COUNT*ID_W
 assign m_axis_tdest  = DEST_ENABLE ? {M_COUNT{m_axis_tdest_reg}} : {M_COUNT*M_DEST_WIDTH_INT{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? {M_COUNT{m_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = (m_axis_tready & m_axis_tvalid) || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = (m_axis_tready & m_axis_tvalid) || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_frame_join.v b/rtl/axis_frame_join.v
index 03752995a..f22b5a4d4 100644
--- a/rtl/axis_frame_join.v
+++ b/rtl/axis_frame_join.v
@@ -266,8 +266,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_frame_length_adjust.v b/rtl/axis_frame_length_adjust.v
index 6c2188bbc..59fb0d9e2 100644
--- a/rtl/axis_frame_length_adjust.v
+++ b/rtl/axis_frame_length_adjust.v
@@ -543,8 +543,8 @@ assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
 assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_mux.v b/rtl/axis_mux.v
index f8f1d0851..bde07fd7c 100644
--- a/rtl/axis_mux.v
+++ b/rtl/axis_mux.v
@@ -193,8 +193,8 @@ assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
 assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_rate_limit.v b/rtl/axis_rate_limit.v
index e748a15c5..4b1a706ec 100644
--- a/rtl/axis_rate_limit.v
+++ b/rtl/axis_rate_limit.v
@@ -186,8 +186,8 @@ assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
 assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_register.v b/rtl/axis_register.v
index 93fe0bee6..6b98fb90f 100644
--- a/rtl/axis_register.v
+++ b/rtl/axis_register.v
@@ -125,8 +125,8 @@ if (REG_TYPE > 1) begin
     assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
     assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-    // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-    wire s_axis_tready_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !s_axis_tvalid));
+    // enable ready input next cycle if output is ready or if both output registers are empty
+    wire s_axis_tready_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
     always @* begin
         // transfer sink ready state to source
diff --git a/rtl/axis_stat_counter.v b/rtl/axis_stat_counter.v
index 9e64b5a58..01fefe6cc 100644
--- a/rtl/axis_stat_counter.v
+++ b/rtl/axis_stat_counter.v
@@ -305,8 +305,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_tap.v b/rtl/axis_tap.v
index 162ff6a35..05f4df522 100644
--- a/rtl/axis_tap.v
+++ b/rtl/axis_tap.v
@@ -258,8 +258,8 @@ assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
 assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source

From ce8dcdafe83af2ca610e353bb4cbb0e1afbed92b Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Sun, 15 May 2022 17:36:26 -0700
Subject: [PATCH 3/6] Pipeline arbitration delay in axis_arb_mux

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 rtl/axis_arb_mux.v | 50 ++++++++++++++++++++++++++++++++++++----------
 1 file changed, 40 insertions(+), 10 deletions(-)

diff --git a/rtl/axis_arb_mux.v b/rtl/axis_arb_mux.v
index a544a31ac..f7e39f3ba 100644
--- a/rtl/axis_arb_mux.v
+++ b/rtl/axis_arb_mux.v
@@ -118,6 +118,15 @@ wire [S_COUNT-1:0] grant;
 wire grant_valid;
 wire [CL_S_COUNT-1:0] grant_encoded;
 
+// input registers to pipeline arbitration delay
+reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata_reg = 0;
+reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep_reg = 0;
+reg [S_COUNT-1:0]            s_axis_tvalid_reg = 0;
+reg [S_COUNT-1:0]            s_axis_tlast_reg = 0;
+reg [S_COUNT*S_ID_WIDTH-1:0] s_axis_tid_reg = 0;
+reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest_reg = 0;
+reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser_reg = 0;
+
 // internal datapath
 reg  [DATA_WIDTH-1:0] m_axis_tdata_int;
 reg  [KEEP_WIDTH-1:0] m_axis_tkeep_int;
@@ -129,17 +138,17 @@ reg  [DEST_WIDTH-1:0] m_axis_tdest_int;
 reg  [USER_WIDTH-1:0] m_axis_tuser_int;
 wire                  m_axis_tready_int_early;
 
-assign s_axis_tready = (m_axis_tready_int_reg && grant_valid) << grant_encoded;
+assign s_axis_tready = ~s_axis_tvalid_reg | ({S_COUNT{m_axis_tready_int_reg}} & grant);
 
 // mux for incoming packet
-wire [DATA_WIDTH-1:0] current_s_tdata  = s_axis_tdata[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
-wire [KEEP_WIDTH-1:0] current_s_tkeep  = s_axis_tkeep[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
-wire                  current_s_tvalid = s_axis_tvalid[grant_encoded];
+wire [DATA_WIDTH-1:0] current_s_tdata  = s_axis_tdata_reg[grant_encoded*DATA_WIDTH +: DATA_WIDTH];
+wire [KEEP_WIDTH-1:0] current_s_tkeep  = s_axis_tkeep_reg[grant_encoded*KEEP_WIDTH +: KEEP_WIDTH];
+wire                  current_s_tvalid = s_axis_tvalid_reg[grant_encoded];
 wire                  current_s_tready = s_axis_tready[grant_encoded];
-wire                  current_s_tlast  = s_axis_tlast[grant_encoded];
-wire [S_ID_WIDTH-1:0] current_s_tid    = s_axis_tid[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH_INT];
-wire [DEST_WIDTH-1:0] current_s_tdest  = s_axis_tdest[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
-wire [USER_WIDTH-1:0] current_s_tuser  = s_axis_tuser[grant_encoded*USER_WIDTH +: USER_WIDTH];
+wire                  current_s_tlast  = s_axis_tlast_reg[grant_encoded];
+wire [S_ID_WIDTH-1:0] current_s_tid    = s_axis_tid_reg[grant_encoded*S_ID_WIDTH +: S_ID_WIDTH_INT];
+wire [DEST_WIDTH-1:0] current_s_tdest  = s_axis_tdest_reg[grant_encoded*DEST_WIDTH +: DEST_WIDTH];
+wire [USER_WIDTH-1:0] current_s_tuser  = s_axis_tuser_reg[grant_encoded*USER_WIDTH +: USER_WIDTH];
 
 // arbiter instance
 arbiter #(
@@ -159,8 +168,8 @@ arb_inst (
     .grant_encoded(grant_encoded)
 );
 
-assign request = s_axis_tvalid & ~grant;
-assign acknowledge = grant & s_axis_tvalid & s_axis_tready & (LAST_ENABLE ? s_axis_tlast : {S_COUNT{1'b1}});
+assign request = (s_axis_tvalid_reg & ~grant) | (s_axis_tvalid & grant);
+assign acknowledge = grant & s_axis_tvalid_reg & {S_COUNT{m_axis_tready_int_reg}} & (LAST_ENABLE ? s_axis_tlast_reg : {S_COUNT{1'b1}});
 
 always @* begin
     // pass through selected packet data
@@ -176,6 +185,27 @@ always @* begin
     m_axis_tuser_int  = current_s_tuser;
 end
 
+integer i;
+
+always @(posedge clk) begin
+    // register inputs
+    for (i = 0; i < S_COUNT; i = i + 1) begin
+        if (s_axis_tready[i]) begin
+            s_axis_tdata_reg[i*DATA_WIDTH +: DATA_WIDTH] <= s_axis_tdata[i*DATA_WIDTH +: DATA_WIDTH];
+            s_axis_tkeep_reg[i*KEEP_WIDTH +: KEEP_WIDTH] <= s_axis_tkeep[i*KEEP_WIDTH +: KEEP_WIDTH];
+            s_axis_tvalid_reg[i] <= s_axis_tvalid[i];
+            s_axis_tlast_reg[i] <= s_axis_tlast[i];
+            s_axis_tid_reg[i*S_ID_WIDTH +: S_ID_WIDTH_INT] <= s_axis_tid[i*S_ID_WIDTH +: S_ID_WIDTH_INT];
+            s_axis_tdest_reg[i*DEST_WIDTH +: DEST_WIDTH] <= s_axis_tdest[i*DEST_WIDTH +: DEST_WIDTH];
+            s_axis_tuser_reg[i*USER_WIDTH +: USER_WIDTH] <= s_axis_tuser[i*USER_WIDTH +: USER_WIDTH];
+        end
+    end
+
+    if (rst) begin
+        s_axis_tvalid_reg <= 0;
+    end
+end
+
 // output datapath logic
 reg [DATA_WIDTH-1:0] m_axis_tdata_reg  = {DATA_WIDTH{1'b0}};
 reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg  = {KEEP_WIDTH{1'b0}};

From 9b5a8cf24aeeeee9d0eadabb3136f7e7722544e2 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Sun, 15 May 2022 17:39:44 -0700
Subject: [PATCH 4/6] Rewrite resets

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 rtl/arp_eth_tx.v             | 18 +++++++++---------
 rtl/axis_eth_fcs_check.v     | 18 +++++++++---------
 rtl/axis_eth_fcs_check_64.v  | 18 +++++++++---------
 rtl/axis_eth_fcs_insert.v    | 18 +++++++++---------
 rtl/axis_eth_fcs_insert_64.v | 18 +++++++++---------
 rtl/eth_arb_mux.v            | 18 +++++++++---------
 rtl/eth_axis_rx.v            | 18 +++++++++---------
 rtl/eth_axis_tx.v            | 18 +++++++++---------
 rtl/eth_demux.v              | 18 +++++++++---------
 rtl/eth_mux.v                | 18 +++++++++---------
 rtl/ip_arb_mux.v             | 18 +++++++++---------
 rtl/ip_demux.v               | 18 +++++++++---------
 rtl/ip_eth_rx.v              | 18 +++++++++---------
 rtl/ip_eth_rx_64.v           | 18 +++++++++---------
 rtl/ip_eth_tx.v              | 18 +++++++++---------
 rtl/ip_eth_tx_64.v           | 18 +++++++++---------
 rtl/ip_mux.v                 | 18 +++++++++---------
 rtl/udp_arb_mux.v            | 18 +++++++++---------
 rtl/udp_demux.v              | 18 +++++++++---------
 rtl/udp_ip_rx.v              | 18 +++++++++---------
 rtl/udp_ip_rx_64.v           | 18 +++++++++---------
 rtl/udp_ip_tx.v              | 18 +++++++++---------
 rtl/udp_ip_tx_64.v           | 18 +++++++++---------
 rtl/udp_mux.v                | 18 +++++++++---------
 24 files changed, 216 insertions(+), 216 deletions(-)

diff --git a/rtl/arp_eth_tx.v b/rtl/arp_eth_tx.v
index 9ef78f5b4..727ea3b05 100644
--- a/rtl/arp_eth_tx.v
+++ b/rtl/arp_eth_tx.v
@@ -328,15 +328,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_eth_payload_axis_tvalid_reg <= 1'b0;
-        m_eth_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
-        m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
-        temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
-    end
+    m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
+    m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
+    temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
 
     // datapath
     if (store_eth_payload_int_to_output) begin
@@ -357,6 +351,12 @@ always @(posedge clk) begin
         temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
         temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_eth_payload_axis_tvalid_reg <= 1'b0;
+        m_eth_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/axis_eth_fcs_check.v b/rtl/axis_eth_fcs_check.v
index 5c731ade4..e9da7df9a 100644
--- a/rtl/axis_eth_fcs_check.v
+++ b/rtl/axis_eth_fcs_check.v
@@ -312,15 +312,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -338,6 +332,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/axis_eth_fcs_check_64.v b/rtl/axis_eth_fcs_check_64.v
index 4f157c083..0ddd5b7f1 100644
--- a/rtl/axis_eth_fcs_check_64.v
+++ b/rtl/axis_eth_fcs_check_64.v
@@ -446,15 +446,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -475,6 +469,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/axis_eth_fcs_insert.v b/rtl/axis_eth_fcs_insert.v
index 306cc8688..46735aec8 100644
--- a/rtl/axis_eth_fcs_insert.v
+++ b/rtl/axis_eth_fcs_insert.v
@@ -339,15 +339,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -365,6 +359,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/axis_eth_fcs_insert_64.v b/rtl/axis_eth_fcs_insert_64.v
index c20a16ee8..1ee919375 100644
--- a/rtl/axis_eth_fcs_insert_64.v
+++ b/rtl/axis_eth_fcs_insert_64.v
@@ -685,15 +685,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -714,6 +708,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/eth_arb_mux.v b/rtl/eth_arb_mux.v
index 1956f444b..7f5180864 100644
--- a/rtl/eth_arb_mux.v
+++ b/rtl/eth_arb_mux.v
@@ -273,15 +273,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_eth_payload_axis_tvalid_reg <= 1'b0;
-        m_eth_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
-        m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
-        temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
-    end
+    m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
+    m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
+    temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -308,6 +302,12 @@ always @(posedge clk) begin
         temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
         temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_eth_payload_axis_tvalid_reg <= 1'b0;
+        m_eth_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/eth_axis_rx.v b/rtl/eth_axis_rx.v
index f75fee232..c427ac29a 100644
--- a/rtl/eth_axis_rx.v
+++ b/rtl/eth_axis_rx.v
@@ -365,15 +365,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_eth_payload_axis_tvalid_reg <= 1'b0;
-        m_eth_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
-        m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
-        temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
-    end
+    m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
+    m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
+    temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
 
     // datapath
     if (store_eth_payload_int_to_output) begin
@@ -394,6 +388,12 @@ always @(posedge clk) begin
         temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
         temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_eth_payload_axis_tvalid_reg <= 1'b0;
+        m_eth_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/eth_axis_tx.v b/rtl/eth_axis_tx.v
index d6dac7e52..93d131a59 100644
--- a/rtl/eth_axis_tx.v
+++ b/rtl/eth_axis_tx.v
@@ -369,15 +369,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_axis_tvalid_reg <= 1'b0;
-        m_axis_tready_int_reg <= 1'b0;
-        temp_m_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_axis_tvalid_reg <= m_axis_tvalid_next;
-        m_axis_tready_int_reg <= m_axis_tready_int_early;
-        temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
-    end
+    m_axis_tvalid_reg <= m_axis_tvalid_next;
+    m_axis_tready_int_reg <= m_axis_tready_int_early;
+    temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -398,6 +392,12 @@ always @(posedge clk) begin
         temp_m_axis_tlast_reg <= m_axis_tlast_int;
         temp_m_axis_tuser_reg <= m_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_axis_tvalid_reg <= 1'b0;
+        m_axis_tready_int_reg <= 1'b0;
+        temp_m_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/eth_demux.v b/rtl/eth_demux.v
index 17ecfbec6..64b4c2fe3 100644
--- a/rtl/eth_demux.v
+++ b/rtl/eth_demux.v
@@ -267,15 +267,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_eth_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
-        m_eth_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
-        m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
-        temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
-    end
+    m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
+    m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
+    temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -302,6 +296,12 @@ always @(posedge clk) begin
         temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
         temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_eth_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
+        m_eth_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/eth_mux.v b/rtl/eth_mux.v
index 05bcd408e..0a69adcbd 100644
--- a/rtl/eth_mux.v
+++ b/rtl/eth_mux.v
@@ -261,15 +261,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_eth_payload_axis_tvalid_reg <= 1'b0;
-        m_eth_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
-        m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
-        temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
-    end
+    m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
+    m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
+    temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -296,6 +290,12 @@ always @(posedge clk) begin
         temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
         temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_eth_payload_axis_tvalid_reg <= 1'b0;
+        m_eth_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/ip_arb_mux.v b/rtl/ip_arb_mux.v
index eb55776e3..91de3cfd3 100644
--- a/rtl/ip_arb_mux.v
+++ b/rtl/ip_arb_mux.v
@@ -364,15 +364,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_ip_payload_axis_tvalid_reg <= 1'b0;
-        m_ip_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
-        m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
-        temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
-    end
+    m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
+    m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
+    temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -399,6 +393,12 @@ always @(posedge clk) begin
         temp_m_ip_payload_axis_tdest_reg <= m_ip_payload_axis_tdest_int;
         temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_ip_payload_axis_tvalid_reg <= 1'b0;
+        m_ip_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/ip_demux.v b/rtl/ip_demux.v
index 08f5cbac3..c7bea23fa 100644
--- a/rtl/ip_demux.v
+++ b/rtl/ip_demux.v
@@ -358,15 +358,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_ip_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
-        m_ip_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
-        m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
-        temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
-    end
+    m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
+    m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
+    temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -393,6 +387,12 @@ always @(posedge clk) begin
         temp_m_ip_payload_axis_tdest_reg <= m_ip_payload_axis_tdest_int;
         temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_ip_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
+        m_ip_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/ip_eth_rx.v b/rtl/ip_eth_rx.v
index c8bad790f..3f5b9e071 100644
--- a/rtl/ip_eth_rx.v
+++ b/rtl/ip_eth_rx.v
@@ -548,15 +548,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_ip_payload_axis_tvalid_reg <= 1'b0;
-        m_ip_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
-        m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
-        temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
-    end
+    m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
+    m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
+    temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
 
     // datapath
     if (store_ip_payload_int_to_output) begin
@@ -574,6 +568,12 @@ always @(posedge clk) begin
         temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
         temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_ip_payload_axis_tvalid_reg <= 1'b0;
+        m_ip_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/ip_eth_rx_64.v b/rtl/ip_eth_rx_64.v
index b33dd67d8..a77def5c8 100644
--- a/rtl/ip_eth_rx_64.v
+++ b/rtl/ip_eth_rx_64.v
@@ -654,15 +654,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_ip_payload_axis_tvalid_reg <= 1'b0;
-        m_ip_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
-        m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
-        temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
-    end
+    m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
+    m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
+    temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
 
     // datapath
     if (store_ip_payload_int_to_output) begin
@@ -683,6 +677,12 @@ always @(posedge clk) begin
         temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
         temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_ip_payload_axis_tvalid_reg <= 1'b0;
+        m_ip_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/ip_eth_tx.v b/rtl/ip_eth_tx.v
index bfe0c705c..60ac39a7c 100644
--- a/rtl/ip_eth_tx.v
+++ b/rtl/ip_eth_tx.v
@@ -468,15 +468,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_eth_payload_axis_tvalid_reg <= 1'b0;
-        m_eth_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
-        m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
-        temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
-    end
+    m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
+    m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
+    temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
 
     // datapath
     if (store_eth_payload_int_to_output) begin
@@ -494,6 +488,12 @@ always @(posedge clk) begin
         temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
         temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_eth_payload_axis_tvalid_reg <= 1'b0;
+        m_eth_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/ip_eth_tx_64.v b/rtl/ip_eth_tx_64.v
index 412447100..4677de98c 100644
--- a/rtl/ip_eth_tx_64.v
+++ b/rtl/ip_eth_tx_64.v
@@ -616,15 +616,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_eth_payload_axis_tvalid_reg <= 1'b0;
-        m_eth_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
-        m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
-        temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
-    end
+    m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
+    m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
+    temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
 
     // datapath
     if (store_eth_payload_int_to_output) begin
@@ -645,6 +639,12 @@ always @(posedge clk) begin
         temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
         temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_eth_payload_axis_tvalid_reg <= 1'b0;
+        m_eth_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/ip_mux.v b/rtl/ip_mux.v
index 86018a359..189692a8f 100644
--- a/rtl/ip_mux.v
+++ b/rtl/ip_mux.v
@@ -352,15 +352,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_ip_payload_axis_tvalid_reg <= 1'b0;
-        m_ip_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
-        m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
-        temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
-    end
+    m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
+    m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
+    temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -387,6 +381,12 @@ always @(posedge clk) begin
         temp_m_ip_payload_axis_tdest_reg <= m_ip_payload_axis_tdest_int;
         temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_ip_payload_axis_tvalid_reg <= 1'b0;
+        m_ip_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/udp_arb_mux.v b/rtl/udp_arb_mux.v
index e8abae123..49bc25efe 100644
--- a/rtl/udp_arb_mux.v
+++ b/rtl/udp_arb_mux.v
@@ -392,15 +392,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_udp_payload_axis_tvalid_reg <= 1'b0;
-        m_udp_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
-        m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
-        temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
-    end
+    m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
+    m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
+    temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -427,6 +421,12 @@ always @(posedge clk) begin
         temp_m_udp_payload_axis_tdest_reg <= m_udp_payload_axis_tdest_int;
         temp_m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_udp_payload_axis_tvalid_reg <= 1'b0;
+        m_udp_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/udp_demux.v b/rtl/udp_demux.v
index 64c5cbff9..17e3d00cf 100644
--- a/rtl/udp_demux.v
+++ b/rtl/udp_demux.v
@@ -386,15 +386,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_udp_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
-        m_udp_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
-        m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
-        temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
-    end
+    m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
+    m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
+    temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -421,6 +415,12 @@ always @(posedge clk) begin
         temp_m_udp_payload_axis_tdest_reg <= m_udp_payload_axis_tdest_int;
         temp_m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_udp_payload_axis_tvalid_reg <= {M_COUNT{1'b0}};
+        m_udp_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/udp_ip_rx.v b/rtl/udp_ip_rx.v
index 7096e5d4c..5212711d7 100644
--- a/rtl/udp_ip_rx.v
+++ b/rtl/udp_ip_rx.v
@@ -503,15 +503,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_udp_payload_axis_tvalid_reg <= 1'b0;
-        m_udp_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
-        m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
-        temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
-    end
+    m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
+    m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
+    temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
 
     // datapath
     if (store_udp_payload_int_to_output) begin
@@ -529,6 +523,12 @@ always @(posedge clk) begin
         temp_m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
         temp_m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_udp_payload_axis_tvalid_reg <= 1'b0;
+        m_udp_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/udp_ip_rx_64.v b/rtl/udp_ip_rx_64.v
index 352e91ce7..37fb3a56c 100644
--- a/rtl/udp_ip_rx_64.v
+++ b/rtl/udp_ip_rx_64.v
@@ -528,15 +528,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_udp_payload_axis_tvalid_reg <= 1'b0;
-        m_udp_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
-        m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
-        temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
-    end
+    m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
+    m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
+    temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
 
     // datapath
     if (store_udp_payload_int_to_output) begin
@@ -557,6 +551,12 @@ always @(posedge clk) begin
         temp_m_udp_payload_axis_tlast_reg <= m_udp_payload_axis_tlast_int;
         temp_m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_udp_payload_axis_tvalid_reg <= 1'b0;
+        m_udp_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/udp_ip_tx.v b/rtl/udp_ip_tx.v
index 8224cd831..ebf1a3b14 100644
--- a/rtl/udp_ip_tx.v
+++ b/rtl/udp_ip_tx.v
@@ -464,15 +464,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_ip_payload_axis_tvalid_reg <= 1'b0;
-        m_ip_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
-        m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
-        temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
-    end
+    m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
+    m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
+    temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
 
     // datapath
     if (store_ip_payload_int_to_output) begin
@@ -490,6 +484,12 @@ always @(posedge clk) begin
         temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
         temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_ip_payload_axis_tvalid_reg <= 1'b0;
+        m_ip_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/udp_ip_tx_64.v b/rtl/udp_ip_tx_64.v
index c3faa1c07..a209c17f6 100644
--- a/rtl/udp_ip_tx_64.v
+++ b/rtl/udp_ip_tx_64.v
@@ -517,15 +517,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_ip_payload_axis_tvalid_reg <= 1'b0;
-        m_ip_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
-        m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
-        temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
-    end
+    m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
+    m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
+    temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
 
     // datapath
     if (store_ip_payload_int_to_output) begin
@@ -546,6 +540,12 @@ always @(posedge clk) begin
         temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
         temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_ip_payload_axis_tvalid_reg <= 1'b0;
+        m_ip_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule
diff --git a/rtl/udp_mux.v b/rtl/udp_mux.v
index aab08024d..5b74cd9b2 100644
--- a/rtl/udp_mux.v
+++ b/rtl/udp_mux.v
@@ -380,15 +380,9 @@ always @* begin
 end
 
 always @(posedge clk) begin
-    if (rst) begin
-        m_udp_payload_axis_tvalid_reg <= 1'b0;
-        m_udp_payload_axis_tready_int_reg <= 1'b0;
-        temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
-    end else begin
-        m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
-        m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
-        temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
-    end
+    m_udp_payload_axis_tvalid_reg <= m_udp_payload_axis_tvalid_next;
+    m_udp_payload_axis_tready_int_reg <= m_udp_payload_axis_tready_int_early;
+    temp_m_udp_payload_axis_tvalid_reg <= temp_m_udp_payload_axis_tvalid_next;
 
     // datapath
     if (store_axis_int_to_output) begin
@@ -415,6 +409,12 @@ always @(posedge clk) begin
         temp_m_udp_payload_axis_tdest_reg <= m_udp_payload_axis_tdest_int;
         temp_m_udp_payload_axis_tuser_reg <= m_udp_payload_axis_tuser_int;
     end
+
+    if (rst) begin
+        m_udp_payload_axis_tvalid_reg <= 1'b0;
+        m_udp_payload_axis_tready_int_reg <= 1'b0;
+        temp_m_udp_payload_axis_tvalid_reg <= 1'b0;
+    end
 end
 
 endmodule

From 609aac39a017da77e2e6040d346d95f05154191c Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Sun, 15 May 2022 17:47:30 -0700
Subject: [PATCH 5/6] Rewrite early ready condition

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 rtl/arp_eth_tx.v             | 4 ++--
 rtl/axis_eth_fcs_check.v     | 4 ++--
 rtl/axis_eth_fcs_check_64.v  | 4 ++--
 rtl/axis_eth_fcs_insert.v    | 4 ++--
 rtl/axis_eth_fcs_insert_64.v | 4 ++--
 rtl/eth_arb_mux.v            | 4 ++--
 rtl/eth_axis_rx.v            | 4 ++--
 rtl/eth_axis_tx.v            | 4 ++--
 rtl/eth_demux.v              | 4 ++--
 rtl/eth_mux.v                | 4 ++--
 rtl/ip_arb_mux.v             | 4 ++--
 rtl/ip_demux.v               | 4 ++--
 rtl/ip_eth_rx.v              | 4 ++--
 rtl/ip_eth_rx_64.v           | 4 ++--
 rtl/ip_eth_tx.v              | 4 ++--
 rtl/ip_eth_tx_64.v           | 4 ++--
 rtl/ip_mux.v                 | 4 ++--
 rtl/udp_arb_mux.v            | 4 ++--
 rtl/udp_demux.v              | 4 ++--
 rtl/udp_ip_rx.v              | 4 ++--
 rtl/udp_ip_rx_64.v           | 4 ++--
 rtl/udp_ip_tx.v              | 4 ++--
 rtl/udp_ip_tx_64.v           | 4 ++--
 rtl/udp_mux.v                | 4 ++--
 24 files changed, 48 insertions(+), 48 deletions(-)

diff --git a/rtl/arp_eth_tx.v b/rtl/arp_eth_tx.v
index 727ea3b05..cd5400505 100644
--- a/rtl/arp_eth_tx.v
+++ b/rtl/arp_eth_tx.v
@@ -296,8 +296,8 @@ assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
 assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
 assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_eth_fcs_check.v b/rtl/axis_eth_fcs_check.v
index e9da7df9a..08233f0fc 100644
--- a/rtl/axis_eth_fcs_check.v
+++ b/rtl/axis_eth_fcs_check.v
@@ -280,8 +280,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_eth_fcs_check_64.v b/rtl/axis_eth_fcs_check_64.v
index 0ddd5b7f1..d0f407128 100644
--- a/rtl/axis_eth_fcs_check_64.v
+++ b/rtl/axis_eth_fcs_check_64.v
@@ -414,8 +414,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_eth_fcs_insert.v b/rtl/axis_eth_fcs_insert.v
index 46735aec8..98feed791 100644
--- a/rtl/axis_eth_fcs_insert.v
+++ b/rtl/axis_eth_fcs_insert.v
@@ -307,8 +307,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/axis_eth_fcs_insert_64.v b/rtl/axis_eth_fcs_insert_64.v
index 1ee919375..f83f89efc 100644
--- a/rtl/axis_eth_fcs_insert_64.v
+++ b/rtl/axis_eth_fcs_insert_64.v
@@ -653,8 +653,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/eth_arb_mux.v b/rtl/eth_arb_mux.v
index 7f5180864..7c604226f 100644
--- a/rtl/eth_arb_mux.v
+++ b/rtl/eth_arb_mux.v
@@ -241,8 +241,8 @@ assign m_eth_payload_axis_tid    = ID_ENABLE   ? m_eth_payload_axis_tid_reg   :
 assign m_eth_payload_axis_tdest  = DEST_ENABLE ? m_eth_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_eth_payload_axis_tuser  = USER_ENABLE ? m_eth_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/eth_axis_rx.v b/rtl/eth_axis_rx.v
index c427ac29a..3501841d1 100644
--- a/rtl/eth_axis_rx.v
+++ b/rtl/eth_axis_rx.v
@@ -333,8 +333,8 @@ assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
 assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
 assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/eth_axis_tx.v b/rtl/eth_axis_tx.v
index 93d131a59..fa742a62b 100644
--- a/rtl/eth_axis_tx.v
+++ b/rtl/eth_axis_tx.v
@@ -337,8 +337,8 @@ assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
 assign m_axis_tuser = m_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !m_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_axis_tready_int_early = m_axis_tready || (!temp_m_axis_tvalid_reg && !m_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/eth_demux.v b/rtl/eth_demux.v
index 64b4c2fe3..c1db47726 100644
--- a/rtl/eth_demux.v
+++ b/rtl/eth_demux.v
@@ -235,8 +235,8 @@ assign m_eth_payload_axis_tid    = ID_ENABLE   ? {M_COUNT{m_eth_payload_axis_tid
 assign m_eth_payload_axis_tdest  = DEST_ENABLE ? {M_COUNT{m_eth_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
 assign m_eth_payload_axis_tuser  = USER_ENABLE ? {M_COUNT{m_eth_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = (m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_eth_payload_axis_tready_int_early = (m_eth_payload_axis_tready & m_eth_payload_axis_tvalid) || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/eth_mux.v b/rtl/eth_mux.v
index 0a69adcbd..a54ed04b0 100644
--- a/rtl/eth_mux.v
+++ b/rtl/eth_mux.v
@@ -229,8 +229,8 @@ assign m_eth_payload_axis_tid    = ID_ENABLE   ? m_eth_payload_axis_tid_reg   :
 assign m_eth_payload_axis_tdest  = DEST_ENABLE ? m_eth_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_eth_payload_axis_tuser  = USER_ENABLE ? m_eth_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/ip_arb_mux.v b/rtl/ip_arb_mux.v
index 91de3cfd3..fbda910b7 100644
--- a/rtl/ip_arb_mux.v
+++ b/rtl/ip_arb_mux.v
@@ -332,8 +332,8 @@ assign m_ip_payload_axis_tid    = ID_ENABLE   ? m_ip_payload_axis_tid_reg   : {I
 assign m_ip_payload_axis_tdest  = DEST_ENABLE ? m_ip_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_ip_payload_axis_tuser  = USER_ENABLE ? m_ip_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/ip_demux.v b/rtl/ip_demux.v
index c7bea23fa..1897d0da8 100644
--- a/rtl/ip_demux.v
+++ b/rtl/ip_demux.v
@@ -326,8 +326,8 @@ assign m_ip_payload_axis_tid    = ID_ENABLE   ? {M_COUNT{m_ip_payload_axis_tid_r
 assign m_ip_payload_axis_tdest  = DEST_ENABLE ? {M_COUNT{m_ip_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
 assign m_ip_payload_axis_tuser  = USER_ENABLE ? {M_COUNT{m_ip_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = (m_ip_payload_axis_tready & m_ip_payload_axis_tvalid) || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_ip_payload_axis_tready_int_early = (m_ip_payload_axis_tready & m_ip_payload_axis_tvalid) || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/ip_eth_rx.v b/rtl/ip_eth_rx.v
index 3f5b9e071..d23844bb0 100644
--- a/rtl/ip_eth_rx.v
+++ b/rtl/ip_eth_rx.v
@@ -516,8 +516,8 @@ assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
 assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
 assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/ip_eth_rx_64.v b/rtl/ip_eth_rx_64.v
index a77def5c8..46429cc7c 100644
--- a/rtl/ip_eth_rx_64.v
+++ b/rtl/ip_eth_rx_64.v
@@ -622,8 +622,8 @@ assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
 assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
 assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/ip_eth_tx.v b/rtl/ip_eth_tx.v
index 60ac39a7c..558be2b7d 100644
--- a/rtl/ip_eth_tx.v
+++ b/rtl/ip_eth_tx.v
@@ -436,8 +436,8 @@ assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
 assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
 assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/ip_eth_tx_64.v b/rtl/ip_eth_tx_64.v
index 4677de98c..652519765 100644
--- a/rtl/ip_eth_tx_64.v
+++ b/rtl/ip_eth_tx_64.v
@@ -584,8 +584,8 @@ assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
 assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
 assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready | (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg | !m_eth_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && !m_eth_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/ip_mux.v b/rtl/ip_mux.v
index 189692a8f..70e64af9b 100644
--- a/rtl/ip_mux.v
+++ b/rtl/ip_mux.v
@@ -320,8 +320,8 @@ assign m_ip_payload_axis_tid    = ID_ENABLE   ? m_ip_payload_axis_tid_reg   : {I
 assign m_ip_payload_axis_tdest  = DEST_ENABLE ? m_ip_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_ip_payload_axis_tuser  = USER_ENABLE ? m_ip_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/udp_arb_mux.v b/rtl/udp_arb_mux.v
index 49bc25efe..29a39e8e4 100644
--- a/rtl/udp_arb_mux.v
+++ b/rtl/udp_arb_mux.v
@@ -360,8 +360,8 @@ assign m_udp_payload_axis_tid    = ID_ENABLE   ? m_udp_payload_axis_tid_reg   :
 assign m_udp_payload_axis_tdest  = DEST_ENABLE ? m_udp_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_udp_payload_axis_tuser  = USER_ENABLE ? m_udp_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && !m_udp_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/udp_demux.v b/rtl/udp_demux.v
index 17e3d00cf..3605052c9 100644
--- a/rtl/udp_demux.v
+++ b/rtl/udp_demux.v
@@ -354,8 +354,8 @@ assign m_udp_payload_axis_tid    = ID_ENABLE   ? {M_COUNT{m_udp_payload_axis_tid
 assign m_udp_payload_axis_tdest  = DEST_ENABLE ? {M_COUNT{m_udp_payload_axis_tdest_reg}} : {M_COUNT*DEST_WIDTH{1'b0}};
 assign m_udp_payload_axis_tuser  = USER_ENABLE ? {M_COUNT{m_udp_payload_axis_tuser_reg}} : {M_COUNT*USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = (m_udp_payload_axis_tready & m_udp_payload_axis_tvalid) || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_udp_payload_axis_tready_int_early = (m_udp_payload_axis_tready & m_udp_payload_axis_tvalid) || (!temp_m_udp_payload_axis_tvalid_reg && !m_udp_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/udp_ip_rx.v b/rtl/udp_ip_rx.v
index 5212711d7..2463a8113 100644
--- a/rtl/udp_ip_rx.v
+++ b/rtl/udp_ip_rx.v
@@ -471,8 +471,8 @@ assign m_udp_payload_axis_tvalid = m_udp_payload_axis_tvalid_reg;
 assign m_udp_payload_axis_tlast = m_udp_payload_axis_tlast_reg;
 assign m_udp_payload_axis_tuser = m_udp_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && !m_udp_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/udp_ip_rx_64.v b/rtl/udp_ip_rx_64.v
index 37fb3a56c..5c583d9e9 100644
--- a/rtl/udp_ip_rx_64.v
+++ b/rtl/udp_ip_rx_64.v
@@ -496,8 +496,8 @@ assign m_udp_payload_axis_tvalid = m_udp_payload_axis_tvalid_reg;
 assign m_udp_payload_axis_tlast = m_udp_payload_axis_tlast_reg;
 assign m_udp_payload_axis_tuser = m_udp_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && !m_udp_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/udp_ip_tx.v b/rtl/udp_ip_tx.v
index ebf1a3b14..7e316365e 100644
--- a/rtl/udp_ip_tx.v
+++ b/rtl/udp_ip_tx.v
@@ -432,8 +432,8 @@ assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
 assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
 assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/udp_ip_tx_64.v b/rtl/udp_ip_tx_64.v
index a209c17f6..5a77e9492 100644
--- a/rtl/udp_ip_tx_64.v
+++ b/rtl/udp_ip_tx_64.v
@@ -485,8 +485,8 @@ assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
 assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
 assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && !m_ip_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source
diff --git a/rtl/udp_mux.v b/rtl/udp_mux.v
index 5b74cd9b2..eaa76dcce 100644
--- a/rtl/udp_mux.v
+++ b/rtl/udp_mux.v
@@ -348,8 +348,8 @@ assign m_udp_payload_axis_tid    = ID_ENABLE   ? m_udp_payload_axis_tid_reg   :
 assign m_udp_payload_axis_tdest  = DEST_ENABLE ? m_udp_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
 assign m_udp_payload_axis_tuser  = USER_ENABLE ? m_udp_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
 
-// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
-assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && (!m_udp_payload_axis_tvalid_reg || !m_udp_payload_axis_tvalid_int));
+// enable ready input next cycle if output is ready or if both output registers are empty
+assign m_udp_payload_axis_tready_int_early = m_udp_payload_axis_tready || (!temp_m_udp_payload_axis_tvalid_reg && !m_udp_payload_axis_tvalid_reg);
 
 always @* begin
     // transfer sink ready state to source

From 80a25731b84818fb1ca2fa878ac5510a533d6f0a Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Sun, 15 May 2022 17:58:47 -0700
Subject: [PATCH 6/6] Fix MAC RX PTP timestamp in sideband

Signed-off-by: Alex Forencich <alex@alexforencich.com>
---
 rtl/axis_xgmii_rx_32.v | 23 ++++++++++++++---------
 rtl/axis_xgmii_rx_64.v | 26 ++++++++++++++++----------
 2 files changed, 30 insertions(+), 19 deletions(-)

diff --git a/rtl/axis_xgmii_rx_32.v b/rtl/axis_xgmii_rx_32.v
index 097ced18a..3f2df787e 100644
--- a/rtl/axis_xgmii_rx_32.v
+++ b/rtl/axis_xgmii_rx_32.v
@@ -120,7 +120,7 @@ reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}, m_axis_tdata_next;
 reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}, m_axis_tkeep_next;
 reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
 reg m_axis_tlast_reg = 1'b0, m_axis_tlast_next;
-reg m_axis_tuser_reg = 1'b0, m_axis_tuser_next;
+reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}, m_axis_tuser_next;
 
 reg start_packet_reg = 1'b0, start_packet_next;
 reg error_bad_frame_reg = 1'b0, error_bad_frame_next;
@@ -149,7 +149,7 @@ assign m_axis_tdata = m_axis_tdata_reg;
 assign m_axis_tkeep = m_axis_tkeep_reg;
 assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
-assign m_axis_tuser = PTP_TS_ENABLE ? {ptp_ts_reg, m_axis_tuser_reg} : m_axis_tuser_reg;
+assign m_axis_tuser = m_axis_tuser_reg;
 
 assign start_packet = start_packet_reg;
 assign error_bad_frame = error_bad_frame_reg;
@@ -272,7 +272,8 @@ always @* begin
     m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
     m_axis_tvalid_next = 1'b0;
     m_axis_tlast_next = 1'b0;
-    m_axis_tuser_next = 1'b0;
+    m_axis_tuser_next = m_axis_tuser_reg;
+    m_axis_tuser_next[0] = 1'b0;
 
     start_packet_next = 1'b0;
     error_bad_frame_next = 1'b0;
@@ -285,6 +286,10 @@ always @* begin
             // idle state - wait for packet
             reset_crc = 1'b1;
 
+            if (PTP_TS_ENABLE) begin
+                m_axis_tuser_next[1 +: PTP_TS_WIDTH] = ptp_ts_reg;
+            end
+
             if (xgmii_rxc_d2[0] && xgmii_rxd_d2[7:0] == XGMII_START) begin
                 // start condition
                 if (control_masked) begin
@@ -293,7 +298,7 @@ always @* begin
                     m_axis_tkeep_next = 4'h1;
                     m_axis_tvalid_next = 1'b1;
                     m_axis_tlast_next = 1'b1;
-                    m_axis_tuser_next = 1'b1;
+                    m_axis_tuser_next[0] = 1'b1;
                     error_bad_frame_next = 1'b1;
                     state_next = STATE_IDLE;
                 end else begin
@@ -316,14 +321,14 @@ always @* begin
             m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
             m_axis_tvalid_next = 1'b1;
             m_axis_tlast_next = 1'b0;
-            m_axis_tuser_next = 1'b0;
+            m_axis_tuser_next[0] = 1'b0;
 
             last_cycle_tkeep_next = tkeep_mask;
 
             if (control_masked) begin
                 // control or error characters in packet
                 m_axis_tlast_next = 1'b1;
-                m_axis_tuser_next = 1'b1;
+                m_axis_tuser_next[0] = 1'b1;
                 error_bad_frame_next = 1'b1;
                 reset_crc = 1'b1;
                 state_next = STATE_IDLE;
@@ -336,7 +341,7 @@ always @* begin
                     if (detect_term[0] && crc_valid3_save) begin
                         // CRC valid
                     end else begin
-                        m_axis_tuser_next = 1'b1;
+                        m_axis_tuser_next[0] = 1'b1;
                         error_bad_frame_next = 1'b1;
                         error_bad_fcs_next = 1'b1;
                     end
@@ -355,7 +360,7 @@ always @* begin
             m_axis_tkeep_next = last_cycle_tkeep_reg;
             m_axis_tvalid_next = 1'b1;
             m_axis_tlast_next = 1'b1;
-            m_axis_tuser_next = 1'b0;
+            m_axis_tuser_next[0] = 1'b0;
 
             reset_crc = 1'b1;
 
@@ -364,7 +369,7 @@ always @* begin
                 (detect_term_save[3] && crc_valid2_save)) begin
                 // CRC valid
             end else begin
-                m_axis_tuser_next = 1'b1;
+                m_axis_tuser_next[0] = 1'b1;
                 error_bad_frame_next = 1'b1;
                 error_bad_fcs_next = 1'b1;
             end
diff --git a/rtl/axis_xgmii_rx_64.v b/rtl/axis_xgmii_rx_64.v
index 9f0830064..ba7b118d4 100644
--- a/rtl/axis_xgmii_rx_64.v
+++ b/rtl/axis_xgmii_rx_64.v
@@ -125,7 +125,7 @@ reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}, m_axis_tdata_next;
 reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg = {KEEP_WIDTH{1'b0}}, m_axis_tkeep_next;
 reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
 reg m_axis_tlast_reg = 1'b0, m_axis_tlast_next;
-reg m_axis_tuser_reg = 1'b0, m_axis_tuser_next;
+reg [USER_WIDTH-1:0] m_axis_tuser_reg = {USER_WIDTH{1'b0}}, m_axis_tuser_next;
 
 reg [1:0] start_packet_reg = 2'b00;
 reg error_bad_frame_reg = 1'b0, error_bad_frame_next;
@@ -154,7 +154,7 @@ assign m_axis_tdata = m_axis_tdata_reg;
 assign m_axis_tkeep = m_axis_tkeep_reg;
 assign m_axis_tvalid = m_axis_tvalid_reg;
 assign m_axis_tlast = m_axis_tlast_reg;
-assign m_axis_tuser = PTP_TS_ENABLE ? {ptp_ts_reg, m_axis_tuser_reg} : m_axis_tuser_reg;
+assign m_axis_tuser = m_axis_tuser_reg;
 
 assign start_packet = start_packet_reg;
 assign error_bad_frame = error_bad_frame_reg;
@@ -308,7 +308,8 @@ always @* begin
     m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
     m_axis_tvalid_next = 1'b0;
     m_axis_tlast_next = 1'b0;
-    m_axis_tuser_next = 1'b0;
+    m_axis_tuser_next = m_axis_tuser_reg;
+    m_axis_tuser_next[0] = 1'b0;
 
     error_bad_frame_next = 1'b0;
     error_bad_fcs_next = 1'b0;
@@ -320,13 +321,18 @@ always @* begin
 
             if (xgmii_rxc_d1[0] && xgmii_rxd_d1[7:0] == XGMII_START) begin
                 // start condition
+
+                if (PTP_TS_ENABLE) begin
+                    m_axis_tuser_next[1 +: PTP_TS_WIDTH] = ptp_ts_reg;
+                end
+
                 if (control_masked) begin
                     // control or error characters in first data word
                     m_axis_tdata_next = {DATA_WIDTH{1'b0}};
                     m_axis_tkeep_next = 8'h01;
                     m_axis_tvalid_next = 1'b1;
                     m_axis_tlast_next = 1'b1;
-                    m_axis_tuser_next = 1'b1;
+                    m_axis_tuser_next[0] = 1'b1;
                     error_bad_frame_next = 1'b1;
                     state_next = STATE_IDLE;
                 end else begin
@@ -343,14 +349,14 @@ always @* begin
             m_axis_tkeep_next = {KEEP_WIDTH{1'b1}};
             m_axis_tvalid_next = 1'b1;
             m_axis_tlast_next = 1'b0;
-            m_axis_tuser_next = 1'b0;
+            m_axis_tuser_next[0] = 1'b0;
 
             last_cycle_tkeep_next = {4'b0000, tkeep_mask[7:4]};
 
             if (control_masked) begin
                 // control or error characters in packet
                 m_axis_tlast_next = 1'b1;
-                m_axis_tuser_next = 1'b1;
+                m_axis_tuser_next[0] = 1'b1;
                 error_bad_frame_next = 1'b1;
                 reset_crc = 1'b1;
                 state_next = STATE_IDLE;
@@ -367,7 +373,7 @@ always @* begin
                         (detect_term[4] && crc_valid3)) begin
                         // CRC valid
                     end else begin
-                        m_axis_tuser_next = 1'b1;
+                        m_axis_tuser_next[0] = 1'b1;
                         error_bad_frame_next = 1'b1;
                         error_bad_fcs_next = 1'b1;
                     end
@@ -387,7 +393,7 @@ always @* begin
             m_axis_tkeep_next = last_cycle_tkeep_reg;
             m_axis_tvalid_next = 1'b1;
             m_axis_tlast_next = 1'b1;
-            m_axis_tuser_next = 1'b0;
+            m_axis_tuser_next[0] = 1'b0;
 
             reset_crc = 1'b1;
 
@@ -396,7 +402,7 @@ always @* begin
                 (detect_term_save[7] && crc_valid2)) begin
                 // CRC valid
             end else begin
-                m_axis_tuser_next = 1'b1;
+                m_axis_tuser_next[0] = 1'b1;
                 error_bad_frame_next = 1'b1;
                 error_bad_fcs_next = 1'b1;
             end
@@ -409,7 +415,7 @@ always @* begin
                     m_axis_tkeep_next = 8'h01;
                     m_axis_tvalid_next = 1'b1;
                     m_axis_tlast_next = 1'b1;
-                    m_axis_tuser_next = 1'b1;
+                    m_axis_tuser_next[0] = 1'b1;
                     error_bad_frame_next = 1'b1;
                     state_next = STATE_IDLE;
                 end else begin