mirror of
https://github.com/corundum/corundum.git
synced 2025-01-16 08:12:53 +08:00
Use CMAC wrapper in 100G mqnic design for ADM-PCIE-9V3
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
f70f4d9b90
commit
49be896333
@ -73,7 +73,7 @@ set_property -dict {LOC F29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_0_
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set_property -dict {LOC D31 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_0_sel_l]
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# 161.1328125 MHz MGT reference clock
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#create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p]
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create_clock -period 6.206 -name qsfp_0_mgt_refclk [get_ports qsfp_0_mgt_refclk_p]
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set_property -dict {LOC R38 } [get_ports qsfp_1_rx_0_p] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
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set_property -dict {LOC R39 } [get_ports qsfp_1_rx_0_n] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
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@ -97,7 +97,7 @@ set_property -dict {LOC F33 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_1_
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set_property -dict {LOC D30 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_1_sel_l]
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# 161.1328125 MHz MGT reference clock
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#create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p]
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create_clock -period 6.206 -name qsfp_1_mgt_refclk [get_ports qsfp_1_mgt_refclk_p]
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set_property -dict {LOC B29 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports qsfp_reset_l]
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set_property -dict {LOC C29 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp_int_l]
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@ -43,6 +43,9 @@ SYN_FILES += rtl/common/rx_engine.v
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SYN_FILES += rtl/common/tx_checksum.v
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SYN_FILES += rtl/common/rx_hash.v
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SYN_FILES += rtl/common/rx_checksum.v
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SYN_FILES += rtl/common/rb_drp.v
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SYN_FILES += rtl/common/cmac_gty_wrapper.v
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SYN_FILES += rtl/common/cmac_gty_ch_wrapper.v
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SYN_FILES += rtl/common/stats_counter.v
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SYN_FILES += rtl/common/stats_collect.v
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SYN_FILES += rtl/common/stats_pcie_if.v
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@ -116,11 +119,14 @@ XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
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XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
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XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
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XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
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XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
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XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
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XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
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# IP
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IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
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IP_TCL_FILES += ip/cmac_usplus_0.tcl
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IP_TCL_FILES += ip/cmac_usplus_1.tcl
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IP_TCL_FILES += ip/cmac_usplus.tcl
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IP_TCL_FILES += ip/cmac_gty.tcl
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#IP_TCL_FILES += ip/ddr4_0.tcl
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# Configuration
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@ -43,6 +43,9 @@ SYN_FILES += rtl/common/rx_engine.v
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SYN_FILES += rtl/common/tx_checksum.v
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SYN_FILES += rtl/common/rx_hash.v
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SYN_FILES += rtl/common/rx_checksum.v
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SYN_FILES += rtl/common/rb_drp.v
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SYN_FILES += rtl/common/cmac_gty_wrapper.v
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SYN_FILES += rtl/common/cmac_gty_ch_wrapper.v
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SYN_FILES += rtl/common/stats_counter.v
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SYN_FILES += rtl/common/stats_collect.v
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SYN_FILES += rtl/common/stats_pcie_if.v
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@ -118,11 +121,14 @@ XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
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XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
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XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
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XDC_FILES += ../../../common/syn/vivado/mqnic_rb_clk_info.tcl
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XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
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XDC_FILES += ../../../common/syn/vivado/cmac_gty_wrapper.tcl
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XDC_FILES += ../../../common/syn/vivado/cmac_gty_ch_wrapper.tcl
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# IP
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IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
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IP_TCL_FILES += ip/cmac_usplus_0.tcl
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IP_TCL_FILES += ip/cmac_usplus_1.tcl
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IP_TCL_FILES += ip/cmac_usplus.tcl
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IP_TCL_FILES += ip/cmac_gty.tcl
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#IP_TCL_FILES += ip/ddr4_0.tcl
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# Configuration
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132
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/cmac_gty.tcl
Normal file
132
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/cmac_gty.tcl
Normal file
@ -0,0 +1,132 @@
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# Copyright 2022, The Regents of the University of California.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# 1. Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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#
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# 2. Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
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# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
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# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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# OF SUCH DAMAGE.
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#
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# The views and conclusions contained in the software and documentation are those
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# of the authors and should not be interpreted as representing official policies,
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# either expressed or implied, of The Regents of the University of California.
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set base_name {cmac_gty}
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set preset {GTY-CAUI_4}
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set freerun_freq {125}
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set line_rate {25.78125}
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set sec_line_rate {0}
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set refclk_freq {161.1328125}
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set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
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set sec_qpll_fracn [expr {int(fmod($sec_line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
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set user_data_width {80}
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set int_data_width $user_data_width
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set rx_eq_mode {LPM}
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set extra_ports [list]
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set extra_pll_ports [list]
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# DRP connections
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lappend extra_ports drpclk_in drpaddr_in drpdi_in drpen_in drpwe_in drpdo_out drprdy_out
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lappend extra_pll_ports drpclk_common_in drpaddr_common_in drpdi_common_in drpen_common_in drpwe_common_in drpdo_common_out drprdy_common_out
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# PLL reset and power down
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lappend extra_pll_ports qpll0reset_in qpll1reset_in
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lappend extra_pll_ports qpll0pd_in qpll1pd_in
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# PLL clocking
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lappend extra_pll_ports gtrefclk00_in qpll0lock_out qpll0outclk_out qpll0outrefclk_out
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lappend extra_pll_ports gtrefclk01_in qpll1lock_out qpll1outclk_out qpll1outrefclk_out
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# channel reset
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lappend extra_ports gttxreset_in txuserrdy_in txpmareset_in txpcsreset_in txresetdone_out txpmaresetdone_out txprgdivresetdone_out
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lappend extra_ports gtrxreset_in rxuserrdy_in rxpmareset_in rxdfelpmreset_in eyescanreset_in rxpcsreset_in rxresetdone_out rxpmaresetdone_out rxprgdivresetdone_out
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# channel power down
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lappend extra_ports txpd_in txpdelecidlemode_in rxpd_in
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# channel clock selection
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lappend extra_ports txsysclksel_in txpllclksel_in rxsysclksel_in rxpllclksel_in
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# channel polarity
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lappend extra_ports txpolarity_in rxpolarity_in
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# channel TX driver
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lappend extra_ports txelecidle_in txinhibit_in txdiffctrl_in txmaincursor_in txprecursor_in txpostcursor_in
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# channel CDR
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lappend extra_ports rxcdrlock_out rxcdrhold_in
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# channel EQ
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lappend extra_ports rxlpmen_in
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# channel digital monitor
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lappend extra_ports dmonitorout_out
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# channel PRBS
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lappend extra_ports txprbsforceerr_in txprbssel_in rxprbscntreset_in rxprbssel_in rxprbserr_out rxprbslocked_out
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# channel eye scan
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lappend extra_ports eyescandataerror_out
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# channel loopback
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lappend extra_ports loopback_in
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set config [dict create]
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dict set config TX_LINE_RATE $line_rate
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dict set config TX_REFCLK_FREQUENCY $refclk_freq
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dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
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dict set config TX_USER_DATA_WIDTH $user_data_width
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dict set config TX_INT_DATA_WIDTH $int_data_width
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dict set config RX_LINE_RATE $line_rate
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dict set config RX_REFCLK_FREQUENCY $refclk_freq
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dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
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dict set config RX_USER_DATA_WIDTH $user_data_width
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dict set config RX_INT_DATA_WIDTH $int_data_width
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dict set config RX_EQ_MODE $rx_eq_mode
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if {$sec_line_rate != 0} {
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dict set config SECONDARY_QPLL_ENABLE true
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dict set config SECONDARY_QPLL_FRACN_NUMERATOR $sec_qpll_fracn
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dict set config SECONDARY_QPLL_LINE_RATE $sec_line_rate
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dict set config SECONDARY_QPLL_REFCLK_FREQUENCY $refclk_freq
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} else {
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dict set config SECONDARY_QPLL_ENABLE false
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}
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dict set config ENABLE_OPTIONAL_PORTS $extra_ports
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dict set config LOCATE_COMMON {CORE}
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dict set config LOCATE_RESET_CONTROLLER {EXAMPLE_DESIGN}
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dict set config LOCATE_TX_USER_CLOCKING {EXAMPLE_DESIGN}
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dict set config LOCATE_RX_USER_CLOCKING {EXAMPLE_DESIGN}
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dict set config LOCATE_USER_DATA_WIDTH_SIZING {EXAMPLE_DESIGN}
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dict set config FREERUN_FREQUENCY $freerun_freq
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dict set config DISABLE_LOC_XDC {1}
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proc create_gtwizard_ip {name preset config} {
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create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
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set ip [get_ips $name]
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set_property CONFIG.preset $preset $ip
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set config_list {}
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dict for {name value} $config {
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lappend config_list "CONFIG.${name}" $value
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}
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set_property -dict $config_list $ip
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# enable only one site
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set_property CONFIG.CHANNEL_ENABLE [lindex [get_property CONFIG.CHANNEL_ENABLE $ip] 0] $ip
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}
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# variant with channel and common
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dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
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dict set config LOCATE_COMMON {CORE}
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create_gtwizard_ip "${base_name}_full" $preset $config
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# variant with channel only
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dict set config ENABLE_OPTIONAL_PORTS $extra_ports
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dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
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create_gtwizard_ip "${base_name}_channel" $preset $config
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19
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/cmac_usplus.tcl
Normal file
19
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/cmac_usplus.tcl
Normal file
@ -0,0 +1,19 @@
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create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usplus
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set_property -dict [list \
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CONFIG.CMAC_CAUI4_MODE {1} \
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CONFIG.NUM_LANES {4x25} \
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CONFIG.USER_INTERFACE {AXIS} \
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CONFIG.GT_DRP_CLK {125} \
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CONFIG.GT_LOCATION {0} \
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CONFIG.TX_FLOW_CONTROL {0} \
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CONFIG.RX_FLOW_CONTROL {0} \
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CONFIG.INCLUDE_RS_FEC {1} \
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CONFIG.ENABLE_TIME_STAMPING {1}
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] [get_ips cmac_usplus]
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# disable LOC constraint
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set_property generate_synth_checkpoint false [get_files [get_property IP_FILE [get_ips cmac_usplus]]]
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generate_target synthesis [get_files [get_property IP_FILE [get_ips cmac_usplus]]]
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set_property is_enabled false [get_files -of_objects [get_files [get_property IP_FILE [get_ips cmac_usplus]]] cmac_usplus.xdc]
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@ -1,21 +0,0 @@
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create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usplus_0
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set_property -dict [list \
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CONFIG.CMAC_CAUI4_MODE {1} \
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CONFIG.NUM_LANES {4x25} \
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CONFIG.GT_REF_CLK_FREQ {161.1328125} \
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CONFIG.USER_INTERFACE {AXIS} \
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CONFIG.GT_DRP_CLK {125} \
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CONFIG.TX_FLOW_CONTROL {0} \
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CONFIG.RX_FLOW_CONTROL {0} \
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CONFIG.INCLUDE_RS_FEC {1} \
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CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y2} \
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CONFIG.GT_GROUP_SELECT {X0Y16~X0Y19} \
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CONFIG.LANE1_GT_LOC {X0Y16} \
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CONFIG.LANE2_GT_LOC {X0Y17} \
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CONFIG.LANE3_GT_LOC {X0Y18} \
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CONFIG.LANE4_GT_LOC {X0Y19} \
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CONFIG.ENABLE_PIPELINE_REG {1} \
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CONFIG.ENABLE_TIME_STAMPING {1}
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] [get_ips cmac_usplus_0]
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@ -1,21 +0,0 @@
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create_ip -name cmac_usplus -vendor xilinx.com -library ip -module_name cmac_usplus_1
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set_property -dict [list \
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CONFIG.CMAC_CAUI4_MODE {1} \
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CONFIG.NUM_LANES {4x25} \
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CONFIG.GT_REF_CLK_FREQ {161.1328125} \
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CONFIG.USER_INTERFACE {AXIS} \
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CONFIG.GT_DRP_CLK {125} \
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CONFIG.TX_FLOW_CONTROL {0} \
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CONFIG.RX_FLOW_CONTROL {0} \
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CONFIG.INCLUDE_RS_FEC {1} \
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CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y1} \
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CONFIG.GT_GROUP_SELECT {X0Y12~X0Y15} \
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CONFIG.LANE1_GT_LOC {X0Y12} \
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CONFIG.LANE2_GT_LOC {X0Y13} \
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CONFIG.LANE3_GT_LOC {X0Y14} \
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CONFIG.LANE4_GT_LOC {X0Y15} \
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CONFIG.ENABLE_PIPELINE_REG {1} \
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CONFIG.ENABLE_TIME_STAMPING {1}
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] [get_ips cmac_usplus_1]
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@ -8,9 +8,13 @@ add_cells_to_pblock [get_pblocks pblock_pcie] [get_cells -quiet "core_inst/core_
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resize_pblock [get_pblocks pblock_pcie] -add {CLOCKREGION_X4Y0:CLOCKREGION_X5Y4}
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create_pblock pblock_eth
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add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_0_cmac_inst qsfp_0_cmac_pad_inst"]
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add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_1_cmac_inst qsfp_1_cmac_pad_inst"]
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add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_0_cmac_inst"]
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add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "qsfp_1_cmac_inst"]
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add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_async_fifo_inst"]
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add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_rx_inst/rx_async_fifo_inst"]
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add_cells_to_pblock [get_pblocks pblock_eth] [get_cells -quiet "core_inst/core_inst/core_pcie_inst/core_inst/iface[*].interface_inst/port[*].port_inst/port_tx_inst/tx_cpl_fifo_inst"]
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resize_pblock [get_pblocks pblock_eth] -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y4}
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# CMACs
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set_property LOC CMACE4_X0Y2 [get_cells -hierarchical -filter {NAME =~ qsfp_0_cmac_inst/cmac_inst/inst/i_cmac_usplus_top/* && REF_NAME==CMACE4}]
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set_property LOC CMACE4_X0Y1 [get_cells -hierarchical -filter {NAME =~ qsfp_1_cmac_inst/cmac_inst/inst/i_cmac_usplus_top/* && REF_NAME==CMACE4}]
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File diff suppressed because it is too large
Load Diff
@ -323,6 +323,15 @@ module fpga_core #
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input wire qsfp_0_rx_status,
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input wire qsfp_0_drp_clk,
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input wire qsfp_0_drp_rst,
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output wire [23:0] qsfp_0_drp_addr,
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output wire [15:0] qsfp_0_drp_di,
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output wire qsfp_0_drp_en,
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output wire qsfp_0_drp_we,
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input wire [15:0] qsfp_0_drp_do,
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input wire qsfp_0_drp_rdy,
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input wire qsfp_0_modprs_l,
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output wire qsfp_0_sel_l,
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@ -354,11 +363,20 @@ module fpga_core #
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output wire [79:0] qsfp_1_rx_ptp_time,
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input wire qsfp_1_rx_status,
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input wire qsfp_1_drp_clk,
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input wire qsfp_1_drp_rst,
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output wire [23:0] qsfp_1_drp_addr,
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output wire [15:0] qsfp_1_drp_di,
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output wire qsfp_1_drp_en,
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output wire qsfp_1_drp_we,
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input wire [15:0] qsfp_1_drp_do,
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input wire qsfp_1_drp_rdy,
|
||||
|
||||
input wire qsfp_1_modprs_l,
|
||||
output wire qsfp_1_sel_l,
|
||||
|
||||
input wire qsfp_1_rx_status,
|
||||
|
||||
output wire qsfp_reset_l,
|
||||
input wire qsfp_int_l,
|
||||
|
||||
@ -449,6 +467,9 @@ parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3
|
||||
localparam RB_BASE_ADDR = 16'h1000;
|
||||
localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}};
|
||||
|
||||
localparam RB_DRP_QSFP_0_BASE = RB_BASE_ADDR + 16'h50;
|
||||
localparam RB_DRP_QSFP_1_BASE = RB_DRP_QSFP_0_BASE + 16'h20;
|
||||
|
||||
initial begin
|
||||
if (PORT_COUNT > 2) begin
|
||||
$error("Error: Max port count exceeded (instance %m)");
|
||||
@ -482,6 +503,18 @@ wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data;
|
||||
wire ctrl_reg_rd_wait;
|
||||
wire ctrl_reg_rd_ack;
|
||||
|
||||
wire qsfp_0_drp_reg_wr_wait;
|
||||
wire qsfp_0_drp_reg_wr_ack;
|
||||
wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp_0_drp_reg_rd_data;
|
||||
wire qsfp_0_drp_reg_rd_wait;
|
||||
wire qsfp_0_drp_reg_rd_ack;
|
||||
|
||||
wire qsfp_1_drp_reg_wr_wait;
|
||||
wire qsfp_1_drp_reg_wr_ack;
|
||||
wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp_1_drp_reg_rd_data;
|
||||
wire qsfp_1_drp_reg_rd_wait;
|
||||
wire qsfp_1_drp_reg_rd_ack;
|
||||
|
||||
reg ctrl_reg_wr_ack_reg = 1'b0;
|
||||
reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}};
|
||||
reg ctrl_reg_rd_ack_reg = 1'b0;
|
||||
@ -507,11 +540,11 @@ reg qspi_1_cs_reg = 1'b1;
|
||||
reg [3:0] qspi_1_dq_o_reg = 4'd0;
|
||||
reg [3:0] qspi_1_dq_oe_reg = 4'd0;
|
||||
|
||||
assign ctrl_reg_wr_wait = 1'b0;
|
||||
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg;
|
||||
assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg;
|
||||
assign ctrl_reg_rd_wait = 1'b0;
|
||||
assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg;
|
||||
assign ctrl_reg_wr_wait = qsfp_0_drp_reg_wr_wait | qsfp_1_drp_reg_wr_wait;
|
||||
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp_0_drp_reg_wr_ack | qsfp_1_drp_reg_wr_ack;
|
||||
assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp_0_drp_reg_rd_data | qsfp_1_drp_reg_rd_data;
|
||||
assign ctrl_reg_rd_wait = qsfp_0_drp_reg_rd_wait | qsfp_1_drp_reg_rd_wait;
|
||||
assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp_0_drp_reg_rd_ack | qsfp_1_drp_reg_rd_ack;
|
||||
|
||||
assign qsfp_0_sel_l = !qsfp_0_sel_reg;
|
||||
assign qsfp_1_sel_l = !qsfp_1_sel_reg;
|
||||
@ -666,7 +699,7 @@ always @(posedge clk_250mhz) begin
|
||||
// QSPI flash
|
||||
RBB+8'h30: ctrl_reg_rd_data_reg <= 32'h0000C120; // SPI flash ctrl: Type
|
||||
RBB+8'h34: ctrl_reg_rd_data_reg <= 32'h00000200; // SPI flash ctrl: Version
|
||||
RBB+8'h38: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h50; // SPI flash ctrl: Next header
|
||||
RBB+8'h38: ctrl_reg_rd_data_reg <= RB_DRP_QSFP_0_BASE; // SPI flash ctrl: Next header
|
||||
RBB+8'h3C: begin
|
||||
// SPI flash ctrl: format
|
||||
ctrl_reg_rd_data_reg[3:0] <= 2; // configuration (two segments)
|
||||
@ -719,6 +752,90 @@ always @(posedge clk_250mhz) begin
|
||||
end
|
||||
end
|
||||
|
||||
rb_drp #(
|
||||
.DRP_ADDR_WIDTH(24),
|
||||
.DRP_DATA_WIDTH(16),
|
||||
.DRP_INFO({8'h09, 8'h03, 8'd2, 8'd4}),
|
||||
.REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
|
||||
.REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
|
||||
.REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
|
||||
.RB_BASE_ADDR(RB_DRP_QSFP_0_BASE),
|
||||
.RB_NEXT_PTR(RB_DRP_QSFP_1_BASE)
|
||||
)
|
||||
qsfp_0_rb_drp_inst (
|
||||
.clk(clk_250mhz),
|
||||
.rst(rst_250mhz),
|
||||
|
||||
/*
|
||||
* Register interface
|
||||
*/
|
||||
.reg_wr_addr(ctrl_reg_wr_addr),
|
||||
.reg_wr_data(ctrl_reg_wr_data),
|
||||
.reg_wr_strb(ctrl_reg_wr_strb),
|
||||
.reg_wr_en(ctrl_reg_wr_en),
|
||||
.reg_wr_wait(qsfp_0_drp_reg_wr_wait),
|
||||
.reg_wr_ack(qsfp_0_drp_reg_wr_ack),
|
||||
.reg_rd_addr(ctrl_reg_rd_addr),
|
||||
.reg_rd_en(ctrl_reg_rd_en),
|
||||
.reg_rd_data(qsfp_0_drp_reg_rd_data),
|
||||
.reg_rd_wait(qsfp_0_drp_reg_rd_wait),
|
||||
.reg_rd_ack(qsfp_0_drp_reg_rd_ack),
|
||||
|
||||
/*
|
||||
* DRP
|
||||
*/
|
||||
.drp_clk(qsfp_0_drp_clk),
|
||||
.drp_rst(qsfp_0_drp_rst),
|
||||
.drp_addr(qsfp_0_drp_addr),
|
||||
.drp_di(qsfp_0_drp_di),
|
||||
.drp_en(qsfp_0_drp_en),
|
||||
.drp_we(qsfp_0_drp_we),
|
||||
.drp_do(qsfp_0_drp_do),
|
||||
.drp_rdy(qsfp_0_drp_rdy)
|
||||
);
|
||||
|
||||
rb_drp #(
|
||||
.DRP_ADDR_WIDTH(24),
|
||||
.DRP_DATA_WIDTH(16),
|
||||
.DRP_INFO({8'h09, 8'h03, 8'd2, 8'd4}),
|
||||
.REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
|
||||
.REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
|
||||
.REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
|
||||
.RB_BASE_ADDR(RB_DRP_QSFP_1_BASE),
|
||||
.RB_NEXT_PTR(0)
|
||||
)
|
||||
qsfp_1_rb_drp_inst (
|
||||
.clk(clk_250mhz),
|
||||
.rst(rst_250mhz),
|
||||
|
||||
/*
|
||||
* Register interface
|
||||
*/
|
||||
.reg_wr_addr(ctrl_reg_wr_addr),
|
||||
.reg_wr_data(ctrl_reg_wr_data),
|
||||
.reg_wr_strb(ctrl_reg_wr_strb),
|
||||
.reg_wr_en(ctrl_reg_wr_en),
|
||||
.reg_wr_wait(qsfp_1_drp_reg_wr_wait),
|
||||
.reg_wr_ack(qsfp_1_drp_reg_wr_ack),
|
||||
.reg_rd_addr(ctrl_reg_rd_addr),
|
||||
.reg_rd_en(ctrl_reg_rd_en),
|
||||
.reg_rd_data(qsfp_1_drp_reg_rd_data),
|
||||
.reg_rd_wait(qsfp_1_drp_reg_rd_wait),
|
||||
.reg_rd_ack(qsfp_1_drp_reg_rd_ack),
|
||||
|
||||
/*
|
||||
* DRP
|
||||
*/
|
||||
.drp_clk(qsfp_1_drp_clk),
|
||||
.drp_rst(qsfp_1_drp_rst),
|
||||
.drp_addr(qsfp_1_drp_addr),
|
||||
.drp_di(qsfp_1_drp_di),
|
||||
.drp_en(qsfp_1_drp_en),
|
||||
.drp_we(qsfp_1_drp_we),
|
||||
.drp_do(qsfp_1_drp_do),
|
||||
.drp_rdy(qsfp_1_drp_rdy)
|
||||
);
|
||||
|
||||
assign user_led_g[0] = 1'b1;
|
||||
assign user_led_g[1] = !ptp_pps_str;
|
||||
assign user_led_r = 1'b1;
|
||||
|
||||
@ -73,6 +73,7 @@ VERILOG_SOURCES += ../../rtl/common/rx_engine.v
|
||||
VERILOG_SOURCES += ../../rtl/common/tx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_hash.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rx_checksum.v
|
||||
VERILOG_SOURCES += ../../rtl/common/rb_drp.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_counter.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_collect.v
|
||||
VERILOG_SOURCES += ../../rtl/common/stats_pcie_if.v
|
||||
|
||||
@ -343,8 +343,19 @@ class TB(object):
|
||||
)
|
||||
|
||||
dut.qsfp_0_rx_status.setimmediatevalue(1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp_0_drp_clk, 8, units="ns").start())
|
||||
dut.qsfp_0_drp_rst.setimmediatevalue(0)
|
||||
dut.qsfp_0_drp_do.setimmediatevalue(0)
|
||||
dut.qsfp_0_drp_rdy.setimmediatevalue(0)
|
||||
|
||||
dut.qsfp_1_rx_status.setimmediatevalue(1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp_1_drp_clk, 8, units="ns").start())
|
||||
dut.qsfp_1_drp_rst.setimmediatevalue(0)
|
||||
dut.qsfp_1_drp_do.setimmediatevalue(0)
|
||||
dut.qsfp_1_drp_rdy.setimmediatevalue(0)
|
||||
|
||||
dut.user_sw.setimmediatevalue(0)
|
||||
|
||||
dut.qsfp_0_modprs_l.setimmediatevalue(0)
|
||||
@ -651,6 +662,7 @@ def test_fpga_core(request):
|
||||
os.path.join(rtl_dir, "common", "tx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_hash.v"),
|
||||
os.path.join(rtl_dir, "common", "rx_checksum.v"),
|
||||
os.path.join(rtl_dir, "common", "rb_drp.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_counter.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_collect.v"),
|
||||
os.path.join(rtl_dir, "common", "stats_pcie_if.v"),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user