FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

Update testbenches

Browse Source
This commit is contained in:
Alex Forencich 2019-09-17 21:46:54 -07:00
parent e3ad96ef07
commit 49f9524aeb
6 changed files with 90 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
tb/test_pcie_us_axi_dma_wr_128.py
View File

@ -62,6 +62,11 @@ def bench():
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_rq_tvalid = Signal(bool(0))
s_axis_rq_tlast = Signal(bool(0))
s_axis_rq_tuser = Signal(intbv(0)[60:])
m_axis_rq_tready = Signal(bool(0))
s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:])
s_axis_write_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
@ -80,6 +85,7 @@ def bench():
max_payload_size = Signal(intbv(0)[3:])
# Outputs
s_axis_rq_tready = Signal(bool(0))
m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_rq_tvalid = Signal(bool(0))
@ -257,6 +263,12 @@ def bench():
clk=user_clk,
rst=user_reset,
current_test=current_test,
s_axis_rq_tdata=s_axis_rq_tdata,
s_axis_rq_tkeep=s_axis_rq_tkeep,
s_axis_rq_tvalid=s_axis_rq_tvalid,
s_axis_rq_tready=s_axis_rq_tready,
s_axis_rq_tlast=s_axis_rq_tlast,
s_axis_rq_tuser=s_axis_rq_tuser,
m_axis_rq_tdata=m_axis_rq_tdata,
m_axis_rq_tkeep=m_axis_rq_tkeep,
m_axis_rq_tvalid=m_axis_rq_tvalid,

18
tb/test_pcie_us_axi_dma_wr_128.v
View File

@ -48,6 +48,11 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rq_tdata = 0;
reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rq_tkeep = 0;
reg s_axis_rq_tvalid = 0;
reg s_axis_rq_tlast = 0;
reg [59:0] s_axis_rq_tuser = 0;
reg m_axis_rq_tready = 0;
reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0;
reg [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr = 0;
@ -66,6 +71,7 @@ reg requester_id_enable = 0;
reg [2:0] max_payload_size = 0;
// Outputs
wire s_axis_rq_tready;
wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep;
wire m_axis_rq_tvalid;
@ -91,6 +97,11 @@ initial begin
clk,
rst,
current_test,
s_axis_rq_tdata,
s_axis_rq_tkeep,
s_axis_rq_tvalid,
s_axis_rq_tlast,
s_axis_rq_tuser,
m_axis_rq_tready,
s_axis_write_desc_pcie_addr,
s_axis_write_desc_axi_addr,
@ -109,6 +120,7 @@ initial begin
max_payload_size
);
$to_myhdl(
s_axis_rq_tready,
m_axis_rq_tdata,
m_axis_rq_tkeep,
m_axis_rq_tvalid,
@ -149,6 +161,12 @@ pcie_us_axi_dma_wr #(
UUT (
.clk(clk),
.rst(rst),
.s_axis_rq_tdata(s_axis_rq_tdata),
.s_axis_rq_tkeep(s_axis_rq_tkeep),
.s_axis_rq_tvalid(s_axis_rq_tvalid),
.s_axis_rq_tready(s_axis_rq_tready),
.s_axis_rq_tlast(s_axis_rq_tlast),
.s_axis_rq_tuser(s_axis_rq_tuser),
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),

12
tb/test_pcie_us_axi_dma_wr_256.py
View File

@ -62,6 +62,11 @@ def bench():
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_rq_tvalid = Signal(bool(0))
s_axis_rq_tlast = Signal(bool(0))
s_axis_rq_tuser = Signal(intbv(0)[60:])
m_axis_rq_tready = Signal(bool(0))
s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:])
s_axis_write_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
@ -80,6 +85,7 @@ def bench():
max_payload_size = Signal(intbv(0)[3:])
# Outputs
s_axis_rq_tready = Signal(bool(0))
m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_rq_tvalid = Signal(bool(0))
@ -257,6 +263,12 @@ def bench():
clk=user_clk,
rst=user_reset,
current_test=current_test,
s_axis_rq_tdata=s_axis_rq_tdata,
s_axis_rq_tkeep=s_axis_rq_tkeep,
s_axis_rq_tvalid=s_axis_rq_tvalid,
s_axis_rq_tready=s_axis_rq_tready,
s_axis_rq_tlast=s_axis_rq_tlast,
s_axis_rq_tuser=s_axis_rq_tuser,
m_axis_rq_tdata=m_axis_rq_tdata,
m_axis_rq_tkeep=m_axis_rq_tkeep,
m_axis_rq_tvalid=m_axis_rq_tvalid,

18
tb/test_pcie_us_axi_dma_wr_256.v
View File

@ -48,6 +48,11 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rq_tdata = 0;
reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rq_tkeep = 0;
reg s_axis_rq_tvalid = 0;
reg s_axis_rq_tlast = 0;
reg [59:0] s_axis_rq_tuser = 0;
reg m_axis_rq_tready = 0;
reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0;
reg [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr = 0;
@ -66,6 +71,7 @@ reg requester_id_enable = 0;
reg [2:0] max_payload_size = 0;
// Outputs
wire s_axis_rq_tready;
wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep;
wire m_axis_rq_tvalid;
@ -91,6 +97,11 @@ initial begin
clk,
rst,
current_test,
s_axis_rq_tdata,
s_axis_rq_tkeep,
s_axis_rq_tvalid,
s_axis_rq_tlast,
s_axis_rq_tuser,
m_axis_rq_tready,
s_axis_write_desc_pcie_addr,
s_axis_write_desc_axi_addr,
@ -109,6 +120,7 @@ initial begin
max_payload_size
);
$to_myhdl(
s_axis_rq_tready,
m_axis_rq_tdata,
m_axis_rq_tkeep,
m_axis_rq_tvalid,
@ -149,6 +161,12 @@ pcie_us_axi_dma_wr #(
UUT (
.clk(clk),
.rst(rst),
.s_axis_rq_tdata(s_axis_rq_tdata),
.s_axis_rq_tkeep(s_axis_rq_tkeep),
.s_axis_rq_tvalid(s_axis_rq_tvalid),
.s_axis_rq_tready(s_axis_rq_tready),
.s_axis_rq_tlast(s_axis_rq_tlast),
.s_axis_rq_tuser(s_axis_rq_tuser),
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),

12
tb/test_pcie_us_axi_dma_wr_64.py
View File

@ -62,6 +62,11 @@ def bench():
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
s_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
s_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
s_axis_rq_tvalid = Signal(bool(0))
s_axis_rq_tlast = Signal(bool(0))
s_axis_rq_tuser = Signal(intbv(0)[60:])
m_axis_rq_tready = Signal(bool(0))
s_axis_write_desc_pcie_addr = Signal(intbv(0)[PCIE_ADDR_WIDTH:])
s_axis_write_desc_axi_addr = Signal(intbv(0)[AXI_ADDR_WIDTH:])
@ -80,6 +85,7 @@ def bench():
max_payload_size = Signal(intbv(0)[3:])
# Outputs
s_axis_rq_tready = Signal(bool(0))
m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
m_axis_rq_tvalid = Signal(bool(0))
@ -257,6 +263,12 @@ def bench():
clk=user_clk,
rst=user_reset,
current_test=current_test,
s_axis_rq_tdata=s_axis_rq_tdata,
s_axis_rq_tkeep=s_axis_rq_tkeep,
s_axis_rq_tvalid=s_axis_rq_tvalid,
s_axis_rq_tready=s_axis_rq_tready,
s_axis_rq_tlast=s_axis_rq_tlast,
s_axis_rq_tuser=s_axis_rq_tuser,
m_axis_rq_tdata=m_axis_rq_tdata,
m_axis_rq_tkeep=m_axis_rq_tkeep,
m_axis_rq_tvalid=m_axis_rq_tvalid,

18
tb/test_pcie_us_axi_dma_wr_64.v
View File

@ -48,6 +48,11 @@ reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rq_tdata = 0;
reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rq_tkeep = 0;
reg s_axis_rq_tvalid = 0;
reg s_axis_rq_tlast = 0;
reg [59:0] s_axis_rq_tuser = 0;
reg m_axis_rq_tready = 0;
reg [PCIE_ADDR_WIDTH-1:0] s_axis_write_desc_pcie_addr = 0;
reg [AXI_ADDR_WIDTH-1:0] s_axis_write_desc_axi_addr = 0;
@ -66,6 +71,7 @@ reg requester_id_enable = 0;
reg [2:0] max_payload_size = 0;
// Outputs
wire s_axis_rq_tready;
wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata;
wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep;
wire m_axis_rq_tvalid;
@ -91,6 +97,11 @@ initial begin
clk,
rst,
current_test,
s_axis_rq_tdata,
s_axis_rq_tkeep,
s_axis_rq_tvalid,
s_axis_rq_tlast,
s_axis_rq_tuser,
m_axis_rq_tready,
s_axis_write_desc_pcie_addr,
s_axis_write_desc_axi_addr,
@ -109,6 +120,7 @@ initial begin
max_payload_size
);
$to_myhdl(
s_axis_rq_tready,
m_axis_rq_tdata,
m_axis_rq_tkeep,
m_axis_rq_tvalid,
@ -149,6 +161,12 @@ pcie_us_axi_dma_wr #(
UUT (
.clk(clk),
.rst(rst),
.s_axis_rq_tdata(s_axis_rq_tdata),
.s_axis_rq_tkeep(s_axis_rq_tkeep),
.s_axis_rq_tvalid(s_axis_rq_tvalid),
.s_axis_rq_tready(s_axis_rq_tready),
.s_axis_rq_tlast(s_axis_rq_tlast),
.s_axis_rq_tuser(s_axis_rq_tuser),
.m_axis_rq_tdata(m_axis_rq_tdata),
.m_axis_rq_tkeep(m_axis_rq_tkeep),
.m_axis_rq_tvalid(m_axis_rq_tvalid),