From 4a65e3594cc69b7541ec2ffe1bcce62e73e82fa6 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 20 Jul 2023 01:17:49 -0700 Subject: [PATCH] Connect all PLL control lines on HTG-9200 board Signed-off-by: Alex Forencich --- example/HTG9200/fpga_25g/fpga.xdc | 12 ++++++------ example/HTG9200/fpga_25g/rtl/fpga.v | 12 ++++++++++++ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/example/HTG9200/fpga_25g/fpga.xdc b/example/HTG9200/fpga_25g/fpga.xdc index 12d0e5110..7cd6893ed 100644 --- a/example/HTG9200/fpga_25g/fpga.xdc +++ b/example/HTG9200/fpga_25g/fpga.xdc @@ -30,13 +30,13 @@ create_clock -period 5.000 -name ref_clk [get_ports ref_clk_p] #create_clock -period 12.5 -name emc_clk [get_ports emc_clk] # PLL control -# set_property -dict {LOC L24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_fdec}] -# set_property -dict {LOC K25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_finc}] -# set_property -dict {LOC K23 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_intr_n}] +set_property -dict {LOC L24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_fdec}] +set_property -dict {LOC K25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_finc}] +set_property -dict {LOC K23 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_intr_n}] set_property -dict {LOC L25 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_lol_n}] -# set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_oe_n}] -# set_property -dict {LOC L22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_sync_n}] -# set_property -dict {LOC K22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_rst_n}] +set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_oe_n}] +set_property -dict {LOC L22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_sync_n}] +set_property -dict {LOC K22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_rst_n}] # set_property -dict {LOC BE20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_sd_oe}] # set_property -dict {LOC BD20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_out0_sel_i2cb}] diff --git a/example/HTG9200/fpga_25g/rtl/fpga.v b/example/HTG9200/fpga_25g/rtl/fpga.v index d05252be8..9cefaefac 100644 --- a/example/HTG9200/fpga_25g/rtl/fpga.v +++ b/example/HTG9200/fpga_25g/rtl/fpga.v @@ -38,7 +38,13 @@ module fpga ( input wire ref_clk_p, input wire ref_clk_n, + output wire clk_gty2_fdec, + output wire clk_gty2_finc, + input wire clk_gty2_intr_n, input wire clk_gty2_lol_n, + output wire clk_gty2_oe_n, + output wire clk_gty2_sync_n, + output wire clk_gty2_rst_n, /* * GPIO @@ -373,6 +379,12 @@ si5341_i2c_init_inst ( .start(1'b1) ); +assign clk_gty2_fdec = 1'b0; +assign clk_gty2_finc = 1'b0; +assign clk_gty2_oe_n = 1'b1; +assign clk_gty2_sync_n = 1'b1; +assign clk_gty2_rst_n = btn[0]; + // XGMII 10G PHY wire qsfp_reset = rst_125mhz_int || si5341_i2c_busy || !clk_gty2_lol_n;