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Connect all PLL control lines on HTG-9200 board

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-07-20 01:17:49 -07:00
parent 375b12865f
commit 4a65e3594c
2 changed files with 18 additions and 6 deletions
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12
example/HTG9200/fpga_25g/fpga.xdc
View File

@ -30,13 +30,13 @@ create_clock -period 5.000 -name ref_clk [get_ports ref_clk_p]
#create_clock -period 12.5 -name emc_clk [get_ports emc_clk]
# PLL control
# set_property -dict {LOC L24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_fdec}]
# set_property -dict {LOC K25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_finc}]
# set_property -dict {LOC K23 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_intr_n}]
set_property -dict {LOC L24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_fdec}]
set_property -dict {LOC K25 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_finc}]
set_property -dict {LOC K23 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_intr_n}]
set_property -dict {LOC L25 IOSTANDARD LVCMOS18} [get_ports {clk_gty2_lol_n}]
# set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_oe_n}]
# set_property -dict {LOC L22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_sync_n}]
# set_property -dict {LOC K22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_rst_n}]
set_property -dict {LOC L23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_oe_n}]
set_property -dict {LOC L22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_sync_n}]
set_property -dict {LOC K22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {clk_gty2_rst_n}]
# set_property -dict {LOC BE20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_sd_oe}]
# set_property -dict {LOC BD20 IOSTANDARD LVCMOS18} [get_ports {clk_gth_out0_sel_i2cb}]

12
example/HTG9200/fpga_25g/rtl/fpga.v
View File

@ -38,7 +38,13 @@ module fpga (
input wire ref_clk_p,
input wire ref_clk_n,
output wire clk_gty2_fdec,
output wire clk_gty2_finc,
input wire clk_gty2_intr_n,
input wire clk_gty2_lol_n,
output wire clk_gty2_oe_n,
output wire clk_gty2_sync_n,
output wire clk_gty2_rst_n,
/*
* GPIO
@ -373,6 +379,12 @@ si5341_i2c_init_inst (
.start(1'b1)
);
assign clk_gty2_fdec = 1'b0;
assign clk_gty2_finc = 1'b0;
assign clk_gty2_oe_n = 1'b1;
assign clk_gty2_sync_n = 1'b1;
assign clk_gty2_rst_n = btn[0];
// XGMII 10G PHY
wire qsfp_reset = rst_125mhz_int || si5341_i2c_busy || !clk_gty2_lol_n;