mirror of
https://github.com/corundum/corundum.git
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Parametrize ARP components
This commit is contained in:
parent
815705f413
commit
4ac6d6803b
@ -36,10 +36,10 @@ SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp_64.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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@ -54,10 +54,10 @@ srcs.append("../lib/eth/rtl/ip_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/ip_arb_mux.v")
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srcs.append("../lib/eth/rtl/arp_64.v")
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srcs.append("../lib/eth/rtl/arp.v")
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srcs.append("../lib/eth/rtl/arp_cache.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx.v")
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srcs.append("../lib/eth/rtl/eth_arb_mux.v")
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srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
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srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
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@ -36,10 +36,10 @@ SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp_64.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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@ -54,10 +54,10 @@ srcs.append("../lib/eth/rtl/ip_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/ip_arb_mux.v")
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srcs.append("../lib/eth/rtl/arp_64.v")
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srcs.append("../lib/eth/rtl/arp.v")
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srcs.append("../lib/eth/rtl/arp_cache.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx.v")
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srcs.append("../lib/eth/rtl/eth_arb_mux.v")
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srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
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srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
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@ -29,10 +29,10 @@ SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp_64.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/rtl/xgmii_interleave.v
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SYN_FILES += lib/eth/rtl/xgmii_deinterleave.v
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@ -54,10 +54,10 @@ srcs.append("../lib/eth/rtl/ip_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/ip_arb_mux.v")
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srcs.append("../lib/eth/rtl/arp_64.v")
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srcs.append("../lib/eth/rtl/arp.v")
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srcs.append("../lib/eth/rtl/arp_cache.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx.v")
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srcs.append("../lib/eth/rtl/eth_arb_mux.v")
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srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
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srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
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@ -35,10 +35,10 @@ SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp_64.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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@ -56,10 +56,10 @@ srcs.append("../lib/eth/rtl/ip_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/ip_arb_mux.v")
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srcs.append("../lib/eth/rtl/arp_64.v")
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srcs.append("../lib/eth/rtl/arp.v")
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srcs.append("../lib/eth/rtl/arp_cache.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx.v")
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srcs.append("../lib/eth/rtl/eth_arb_mux.v")
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srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
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srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
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@ -35,10 +35,10 @@ SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp_64.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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@ -56,10 +56,10 @@ srcs.append("../lib/eth/rtl/ip_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/ip_arb_mux.v")
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srcs.append("../lib/eth/rtl/arp_64.v")
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srcs.append("../lib/eth/rtl/arp.v")
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srcs.append("../lib/eth/rtl/arp_cache.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx.v")
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srcs.append("../lib/eth/rtl/eth_arb_mux.v")
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srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
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srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
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@ -34,10 +34,10 @@ SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp_64.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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@ -54,10 +54,10 @@ srcs.append("../lib/eth/rtl/ip_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/ip_arb_mux.v")
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srcs.append("../lib/eth/rtl/arp_64.v")
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srcs.append("../lib/eth/rtl/arp.v")
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srcs.append("../lib/eth/rtl/arp_cache.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx.v")
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srcs.append("../lib/eth/rtl/eth_arb_mux.v")
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srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
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srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
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@ -40,10 +40,10 @@ SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp_64.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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@ -61,10 +61,10 @@ srcs.append("../lib/eth/rtl/ip_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/ip_arb_mux.v")
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srcs.append("../lib/eth/rtl/arp_64.v")
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srcs.append("../lib/eth/rtl/arp.v")
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srcs.append("../lib/eth/rtl/arp_cache.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx.v")
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srcs.append("../lib/eth/rtl/eth_arb_mux.v")
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srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
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srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
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@ -41,10 +41,10 @@ SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp_64.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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@ -61,10 +61,10 @@ srcs.append("../lib/eth/rtl/ip_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/ip_arb_mux.v")
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srcs.append("../lib/eth/rtl/arp_64.v")
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srcs.append("../lib/eth/rtl/arp.v")
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srcs.append("../lib/eth/rtl/arp_cache.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx.v")
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srcs.append("../lib/eth/rtl/eth_arb_mux.v")
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srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
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srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
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@ -41,10 +41,10 @@ SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp_64.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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@ -61,10 +61,10 @@ srcs.append("../lib/eth/rtl/ip_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/ip_arb_mux.v")
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srcs.append("../lib/eth/rtl/arp_64.v")
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srcs.append("../lib/eth/rtl/arp.v")
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srcs.append("../lib/eth/rtl/arp_cache.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx.v")
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srcs.append("../lib/eth/rtl/eth_arb_mux.v")
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srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
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srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
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@ -36,10 +36,10 @@ SYN_FILES += lib/eth/rtl/ip_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/ip_arb_mux.v
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SYN_FILES += lib/eth/rtl/arp_64.v
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SYN_FILES += lib/eth/rtl/arp.v
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SYN_FILES += lib/eth/rtl/arp_cache.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx_64.v
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SYN_FILES += lib/eth/rtl/arp_eth_rx.v
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SYN_FILES += lib/eth/rtl/arp_eth_tx.v
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SYN_FILES += lib/eth/rtl/eth_arb_mux.v
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SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
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SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
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@ -54,10 +54,10 @@ srcs.append("../lib/eth/rtl/ip_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/ip_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/ip_arb_mux.v")
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srcs.append("../lib/eth/rtl/arp_64.v")
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srcs.append("../lib/eth/rtl/arp.v")
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srcs.append("../lib/eth/rtl/arp_cache.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx_64.v")
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srcs.append("../lib/eth/rtl/arp_eth_rx.v")
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srcs.append("../lib/eth/rtl/arp_eth_tx.v")
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srcs.append("../lib/eth/rtl/eth_arb_mux.v")
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srcs.append("../lib/eth/lib/axis/rtl/arbiter.v")
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||||
srcs.append("../lib/eth/lib/axis/rtl/priority_encoder.v")
|
||||
|
100
rtl/arp.v
100
rtl/arp.v
@ -1,6 +1,6 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
Copyright (c) 2014-2020 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
@ -29,63 +29,77 @@ THE SOFTWARE.
|
||||
/*
|
||||
* ARP block for IPv4, ethernet frame interface
|
||||
*/
|
||||
module arp #(
|
||||
module arp #
|
||||
(
|
||||
// Width of AXI stream interfaces in bits
|
||||
parameter DATA_WIDTH = 8,
|
||||
// Propagate tkeep signal
|
||||
// If disabled, tkeep assumed to be 1'b1
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8),
|
||||
// tkeep signal width (words per cycle)
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8),
|
||||
// Log2 of ARP cache size
|
||||
parameter CACHE_ADDR_WIDTH = 9,
|
||||
// ARP request retry count
|
||||
parameter REQUEST_RETRY_COUNT = 4,
|
||||
// ARP request retry interval (in cycles)
|
||||
parameter REQUEST_RETRY_INTERVAL = 125000000*2,
|
||||
// ARP request timeout (in cycles)
|
||||
parameter REQUEST_TIMEOUT = 125000000*30
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* Ethernet frame input
|
||||
*/
|
||||
input wire s_eth_hdr_valid,
|
||||
output wire s_eth_hdr_ready,
|
||||
input wire [47:0] s_eth_dest_mac,
|
||||
input wire [47:0] s_eth_src_mac,
|
||||
input wire [15:0] s_eth_type,
|
||||
input wire [7:0] s_eth_payload_axis_tdata,
|
||||
input wire s_eth_payload_axis_tvalid,
|
||||
output wire s_eth_payload_axis_tready,
|
||||
input wire s_eth_payload_axis_tlast,
|
||||
input wire s_eth_payload_axis_tuser,
|
||||
input wire s_eth_hdr_valid,
|
||||
output wire s_eth_hdr_ready,
|
||||
input wire [47:0] s_eth_dest_mac,
|
||||
input wire [47:0] s_eth_src_mac,
|
||||
input wire [15:0] s_eth_type,
|
||||
input wire [DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
|
||||
input wire [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
|
||||
input wire s_eth_payload_axis_tvalid,
|
||||
output wire s_eth_payload_axis_tready,
|
||||
input wire s_eth_payload_axis_tlast,
|
||||
input wire s_eth_payload_axis_tuser,
|
||||
|
||||
/*
|
||||
* Ethernet frame output
|
||||
*/
|
||||
output wire m_eth_hdr_valid,
|
||||
input wire m_eth_hdr_ready,
|
||||
output wire [47:0] m_eth_dest_mac,
|
||||
output wire [47:0] m_eth_src_mac,
|
||||
output wire [15:0] m_eth_type,
|
||||
output wire [7:0] m_eth_payload_axis_tdata,
|
||||
output wire m_eth_payload_axis_tvalid,
|
||||
input wire m_eth_payload_axis_tready,
|
||||
output wire m_eth_payload_axis_tlast,
|
||||
output wire m_eth_payload_axis_tuser,
|
||||
output wire m_eth_hdr_valid,
|
||||
input wire m_eth_hdr_ready,
|
||||
output wire [47:0] m_eth_dest_mac,
|
||||
output wire [47:0] m_eth_src_mac,
|
||||
output wire [15:0] m_eth_type,
|
||||
output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
|
||||
output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
|
||||
output wire m_eth_payload_axis_tvalid,
|
||||
input wire m_eth_payload_axis_tready,
|
||||
output wire m_eth_payload_axis_tlast,
|
||||
output wire m_eth_payload_axis_tuser,
|
||||
|
||||
/*
|
||||
* ARP requests
|
||||
*/
|
||||
input wire arp_request_valid,
|
||||
output wire arp_request_ready,
|
||||
input wire [31:0] arp_request_ip,
|
||||
output wire arp_response_valid,
|
||||
input wire arp_response_ready,
|
||||
output wire arp_response_error,
|
||||
output wire [47:0] arp_response_mac,
|
||||
input wire arp_request_valid,
|
||||
output wire arp_request_ready,
|
||||
input wire [31:0] arp_request_ip,
|
||||
output wire arp_response_valid,
|
||||
input wire arp_response_ready,
|
||||
output wire arp_response_error,
|
||||
output wire [47:0] arp_response_mac,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire [47:0] local_mac,
|
||||
input wire [31:0] local_ip,
|
||||
input wire [31:0] gateway_ip,
|
||||
input wire [31:0] subnet_mask,
|
||||
input wire clear_cache
|
||||
input wire [47:0] local_mac,
|
||||
input wire [31:0] local_ip,
|
||||
input wire [31:0] gateway_ip,
|
||||
input wire [31:0] subnet_mask,
|
||||
input wire clear_cache
|
||||
);
|
||||
|
||||
localparam [15:0]
|
||||
@ -112,7 +126,11 @@ wire [31:0] incoming_arp_tpa;
|
||||
/*
|
||||
* ARP frame processing
|
||||
*/
|
||||
arp_eth_rx
|
||||
arp_eth_rx #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_ENABLE(KEEP_ENABLE),
|
||||
.KEEP_WIDTH(KEEP_WIDTH)
|
||||
)
|
||||
arp_eth_rx_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
@ -123,6 +141,7 @@ arp_eth_rx_inst (
|
||||
.s_eth_src_mac(s_eth_src_mac),
|
||||
.s_eth_type(s_eth_type),
|
||||
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
|
||||
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
|
||||
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
|
||||
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
|
||||
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
|
||||
@ -155,7 +174,11 @@ reg [15:0] outgoing_arp_oper_reg = 16'd0, outgoing_arp_oper_next;
|
||||
reg [47:0] outgoing_arp_tha_reg = 48'd0, outgoing_arp_tha_next;
|
||||
reg [31:0] outgoing_arp_tpa_reg = 32'd0, outgoing_arp_tpa_next;
|
||||
|
||||
arp_eth_tx
|
||||
arp_eth_tx #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_ENABLE(KEEP_ENABLE),
|
||||
.KEEP_WIDTH(KEEP_WIDTH)
|
||||
)
|
||||
arp_eth_tx_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
@ -179,6 +202,7 @@ arp_eth_tx_inst (
|
||||
.m_eth_src_mac(m_eth_src_mac),
|
||||
.m_eth_type(m_eth_type),
|
||||
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
|
||||
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
|
||||
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
|
||||
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
|
||||
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
|
||||
|
420
rtl/arp_64.v
420
rtl/arp_64.v
@ -1,420 +0,0 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* ARP block for IPv4, ethernet frame interface (64 bit datapath)
|
||||
*/
|
||||
module arp_64 #(
|
||||
parameter CACHE_ADDR_WIDTH = 9,
|
||||
parameter REQUEST_RETRY_COUNT = 4,
|
||||
parameter REQUEST_RETRY_INTERVAL = 156250000*2,
|
||||
parameter REQUEST_TIMEOUT = 156250000*30
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* Ethernet frame input
|
||||
*/
|
||||
input wire s_eth_hdr_valid,
|
||||
output wire s_eth_hdr_ready,
|
||||
input wire [47:0] s_eth_dest_mac,
|
||||
input wire [47:0] s_eth_src_mac,
|
||||
input wire [15:0] s_eth_type,
|
||||
input wire [63:0] s_eth_payload_axis_tdata,
|
||||
input wire [7:0] s_eth_payload_axis_tkeep,
|
||||
input wire s_eth_payload_axis_tvalid,
|
||||
output wire s_eth_payload_axis_tready,
|
||||
input wire s_eth_payload_axis_tlast,
|
||||
input wire s_eth_payload_axis_tuser,
|
||||
|
||||
/*
|
||||
* Ethernet frame output
|
||||
*/
|
||||
output wire m_eth_hdr_valid,
|
||||
input wire m_eth_hdr_ready,
|
||||
output wire [47:0] m_eth_dest_mac,
|
||||
output wire [47:0] m_eth_src_mac,
|
||||
output wire [15:0] m_eth_type,
|
||||
output wire [63:0] m_eth_payload_axis_tdata,
|
||||
output wire [7:0] m_eth_payload_axis_tkeep,
|
||||
output wire m_eth_payload_axis_tvalid,
|
||||
input wire m_eth_payload_axis_tready,
|
||||
output wire m_eth_payload_axis_tlast,
|
||||
output wire m_eth_payload_axis_tuser,
|
||||
|
||||
/*
|
||||
* ARP requests
|
||||
*/
|
||||
input wire arp_request_valid,
|
||||
output wire arp_request_ready,
|
||||
input wire [31:0] arp_request_ip,
|
||||
output wire arp_response_valid,
|
||||
input wire arp_response_ready,
|
||||
output wire arp_response_error,
|
||||
output wire [47:0] arp_response_mac,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire [47:0] local_mac,
|
||||
input wire [31:0] local_ip,
|
||||
input wire [31:0] gateway_ip,
|
||||
input wire [31:0] subnet_mask,
|
||||
input wire clear_cache
|
||||
);
|
||||
|
||||
localparam [15:0]
|
||||
ARP_OPER_ARP_REQUEST = 16'h0001,
|
||||
ARP_OPER_ARP_REPLY = 16'h0002,
|
||||
ARP_OPER_INARP_REQUEST = 16'h0008,
|
||||
ARP_OPER_INARP_REPLY = 16'h0009;
|
||||
|
||||
wire incoming_frame_valid;
|
||||
reg incoming_frame_ready;
|
||||
wire [47:0] incoming_eth_dest_mac;
|
||||
wire [47:0] incoming_eth_src_mac;
|
||||
wire [15:0] incoming_eth_type;
|
||||
wire [15:0] incoming_arp_htype;
|
||||
wire [15:0] incoming_arp_ptype;
|
||||
wire [7:0] incoming_arp_hlen;
|
||||
wire [7:0] incoming_arp_plen;
|
||||
wire [15:0] incoming_arp_oper;
|
||||
wire [47:0] incoming_arp_sha;
|
||||
wire [31:0] incoming_arp_spa;
|
||||
wire [47:0] incoming_arp_tha;
|
||||
wire [31:0] incoming_arp_tpa;
|
||||
|
||||
/*
|
||||
* ARP frame processing
|
||||
*/
|
||||
arp_eth_rx_64
|
||||
arp_eth_rx_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// Ethernet frame input
|
||||
.s_eth_hdr_valid(s_eth_hdr_valid),
|
||||
.s_eth_hdr_ready(s_eth_hdr_ready),
|
||||
.s_eth_dest_mac(s_eth_dest_mac),
|
||||
.s_eth_src_mac(s_eth_src_mac),
|
||||
.s_eth_type(s_eth_type),
|
||||
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
|
||||
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
|
||||
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
|
||||
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
|
||||
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
|
||||
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
|
||||
// ARP frame output
|
||||
.m_frame_valid(incoming_frame_valid),
|
||||
.m_frame_ready(incoming_frame_ready),
|
||||
.m_eth_dest_mac(incoming_eth_dest_mac),
|
||||
.m_eth_src_mac(incoming_eth_src_mac),
|
||||
.m_eth_type(incoming_eth_type),
|
||||
.m_arp_htype(incoming_arp_htype),
|
||||
.m_arp_ptype(incoming_arp_ptype),
|
||||
.m_arp_hlen(incoming_arp_hlen),
|
||||
.m_arp_plen(incoming_arp_plen),
|
||||
.m_arp_oper(incoming_arp_oper),
|
||||
.m_arp_sha(incoming_arp_sha),
|
||||
.m_arp_spa(incoming_arp_spa),
|
||||
.m_arp_tha(incoming_arp_tha),
|
||||
.m_arp_tpa(incoming_arp_tpa),
|
||||
// Status signals
|
||||
.busy(),
|
||||
.error_header_early_termination(),
|
||||
.error_invalid_header()
|
||||
);
|
||||
|
||||
reg outgoing_frame_valid_reg = 1'b0, outgoing_frame_valid_next;
|
||||
wire outgoing_frame_ready;
|
||||
reg [47:0] outgoing_eth_dest_mac_reg = 48'd0, outgoing_eth_dest_mac_next;
|
||||
reg [15:0] outgoing_arp_oper_reg = 16'd0, outgoing_arp_oper_next;
|
||||
reg [47:0] outgoing_arp_tha_reg = 48'd0, outgoing_arp_tha_next;
|
||||
reg [31:0] outgoing_arp_tpa_reg = 32'd0, outgoing_arp_tpa_next;
|
||||
|
||||
arp_eth_tx_64
|
||||
arp_eth_tx_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// ARP frame input
|
||||
.s_frame_valid(outgoing_frame_valid_reg),
|
||||
.s_frame_ready(outgoing_frame_ready),
|
||||
.s_eth_dest_mac(outgoing_eth_dest_mac_reg),
|
||||
.s_eth_src_mac(local_mac),
|
||||
.s_eth_type(16'h0806),
|
||||
.s_arp_htype(16'h0001),
|
||||
.s_arp_ptype(16'h0800),
|
||||
.s_arp_oper(outgoing_arp_oper_reg),
|
||||
.s_arp_sha(local_mac),
|
||||
.s_arp_spa(local_ip),
|
||||
.s_arp_tha(outgoing_arp_tha_reg),
|
||||
.s_arp_tpa(outgoing_arp_tpa_reg),
|
||||
// Ethernet frame output
|
||||
.m_eth_hdr_valid(m_eth_hdr_valid),
|
||||
.m_eth_hdr_ready(m_eth_hdr_ready),
|
||||
.m_eth_dest_mac(m_eth_dest_mac),
|
||||
.m_eth_src_mac(m_eth_src_mac),
|
||||
.m_eth_type(m_eth_type),
|
||||
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
|
||||
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
|
||||
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
|
||||
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
|
||||
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
|
||||
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
|
||||
// Status signals
|
||||
.busy()
|
||||
);
|
||||
|
||||
reg cache_query_request_valid_reg = 1'b0, cache_query_request_valid_next;
|
||||
reg [31:0] cache_query_request_ip_reg = 32'd0, cache_query_request_ip_next;
|
||||
wire cache_query_response_valid;
|
||||
wire cache_query_response_error;
|
||||
wire [47:0] cache_query_response_mac;
|
||||
|
||||
reg cache_write_request_valid_reg = 1'b0, cache_write_request_valid_next;
|
||||
reg [31:0] cache_write_request_ip_reg = 32'd0, cache_write_request_ip_next;
|
||||
reg [47:0] cache_write_request_mac_reg = 48'd0, cache_write_request_mac_next;
|
||||
|
||||
/*
|
||||
* ARP cache
|
||||
*/
|
||||
arp_cache #(
|
||||
.CACHE_ADDR_WIDTH(CACHE_ADDR_WIDTH)
|
||||
)
|
||||
arp_cache_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// Query cache
|
||||
.query_request_valid(cache_query_request_valid_reg),
|
||||
.query_request_ready(),
|
||||
.query_request_ip(cache_query_request_ip_reg),
|
||||
.query_response_valid(cache_query_response_valid),
|
||||
.query_response_ready(1'b1),
|
||||
.query_response_error(cache_query_response_error),
|
||||
.query_response_mac(cache_query_response_mac),
|
||||
// Write cache
|
||||
.write_request_valid(cache_write_request_valid_reg),
|
||||
.write_request_ready(),
|
||||
.write_request_ip(cache_write_request_ip_reg),
|
||||
.write_request_mac(cache_write_request_mac_reg),
|
||||
// Configuration
|
||||
.clear_cache(clear_cache)
|
||||
);
|
||||
|
||||
reg arp_request_operation_reg = 1'b0, arp_request_operation_next;
|
||||
|
||||
reg arp_request_ready_reg = 1'b0, arp_request_ready_next;
|
||||
reg [31:0] arp_request_ip_reg = 32'd0, arp_request_ip_next;
|
||||
|
||||
reg arp_response_valid_reg = 1'b0, arp_response_valid_next;
|
||||
reg arp_response_error_reg = 1'b0, arp_response_error_next;
|
||||
reg [47:0] arp_response_mac_reg = 48'd0, arp_response_mac_next;
|
||||
|
||||
reg [5:0] arp_request_retry_cnt_reg = 6'd0, arp_request_retry_cnt_next;
|
||||
reg [35:0] arp_request_timer_reg = 36'd0, arp_request_timer_next;
|
||||
|
||||
assign arp_request_ready = arp_request_ready_reg;
|
||||
|
||||
assign arp_response_valid = arp_response_valid_reg;
|
||||
assign arp_response_error = arp_response_error_reg;
|
||||
assign arp_response_mac = arp_response_mac_reg;
|
||||
|
||||
always @* begin
|
||||
incoming_frame_ready = 1'b0;
|
||||
|
||||
outgoing_frame_valid_next = outgoing_frame_valid_reg && !outgoing_frame_ready;
|
||||
outgoing_eth_dest_mac_next = outgoing_eth_dest_mac_reg;
|
||||
outgoing_arp_oper_next = outgoing_arp_oper_reg;
|
||||
outgoing_arp_tha_next = outgoing_arp_tha_reg;
|
||||
outgoing_arp_tpa_next = outgoing_arp_tpa_reg;
|
||||
|
||||
cache_query_request_valid_next = 1'b0;
|
||||
cache_query_request_ip_next = cache_query_request_ip_reg;
|
||||
|
||||
cache_write_request_valid_next = 1'b0;
|
||||
cache_write_request_mac_next = cache_write_request_mac_reg;
|
||||
cache_write_request_ip_next = cache_write_request_ip_reg;
|
||||
|
||||
arp_request_ready_next = 1'b0;
|
||||
arp_request_ip_next = arp_request_ip_reg;
|
||||
arp_request_operation_next = arp_request_operation_reg;
|
||||
arp_request_retry_cnt_next = arp_request_retry_cnt_reg;
|
||||
arp_request_timer_next = arp_request_timer_reg;
|
||||
arp_response_valid_next = arp_response_valid_reg && !arp_response_ready;
|
||||
arp_response_error_next = 1'b0;
|
||||
arp_response_mac_next = 48'd0;
|
||||
|
||||
// manage incoming frames
|
||||
incoming_frame_ready = outgoing_frame_ready;
|
||||
if (incoming_frame_valid && incoming_frame_ready) begin
|
||||
if (incoming_eth_type == 16'h0806 && incoming_arp_htype == 16'h0001 && incoming_arp_ptype == 16'h0800) begin
|
||||
// store sender addresses in cache
|
||||
cache_write_request_valid_next = 1'b1;
|
||||
cache_write_request_ip_next = incoming_arp_spa;
|
||||
cache_write_request_mac_next = incoming_arp_sha;
|
||||
if (incoming_arp_oper == ARP_OPER_ARP_REQUEST) begin
|
||||
// ARP request
|
||||
if (incoming_arp_tpa == local_ip) begin
|
||||
// send reply frame to valid incoming request
|
||||
outgoing_frame_valid_next = 1'b1;
|
||||
outgoing_eth_dest_mac_next = incoming_eth_src_mac;
|
||||
outgoing_arp_oper_next = ARP_OPER_ARP_REPLY;
|
||||
outgoing_arp_tha_next = incoming_arp_sha;
|
||||
outgoing_arp_tpa_next = incoming_arp_spa;
|
||||
end
|
||||
end else if (incoming_arp_oper == ARP_OPER_INARP_REQUEST) begin
|
||||
// INARP request
|
||||
if (incoming_arp_tha == local_mac) begin
|
||||
// send reply frame to valid incoming request
|
||||
outgoing_frame_valid_next = 1'b1;
|
||||
outgoing_eth_dest_mac_next = incoming_eth_src_mac;
|
||||
outgoing_arp_oper_next = ARP_OPER_INARP_REPLY;
|
||||
outgoing_arp_tha_next = incoming_arp_sha;
|
||||
outgoing_arp_tpa_next = incoming_arp_spa;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// manage ARP lookup requests
|
||||
if (arp_request_operation_reg) begin
|
||||
arp_request_ready_next = 1'b0;
|
||||
cache_query_request_valid_next = 1'b1;
|
||||
arp_request_timer_next = arp_request_timer_reg - 1;
|
||||
// if we got a response, it will go in the cache, so when the query succeds, we're done
|
||||
if (cache_query_response_valid && !cache_query_response_error) begin
|
||||
arp_request_operation_next = 1'b0;
|
||||
cache_query_request_valid_next = 1'b0;
|
||||
arp_response_valid_next = 1'b1;
|
||||
arp_response_error_next = 1'b0;
|
||||
arp_response_mac_next = cache_query_response_mac;
|
||||
end
|
||||
// timer timeout
|
||||
if (arp_request_timer_reg == 0) begin
|
||||
if (arp_request_retry_cnt_reg > 0) begin
|
||||
// have more retries
|
||||
// send ARP request frame
|
||||
outgoing_frame_valid_next = 1'b1;
|
||||
outgoing_eth_dest_mac_next = 48'hffffffffffff;
|
||||
outgoing_arp_oper_next = ARP_OPER_ARP_REQUEST;
|
||||
outgoing_arp_tha_next = 48'h000000000000;
|
||||
outgoing_arp_tpa_next = arp_request_ip_reg;
|
||||
arp_request_retry_cnt_next = arp_request_retry_cnt_reg - 1;
|
||||
if (arp_request_retry_cnt_reg > 1) begin
|
||||
arp_request_timer_next = REQUEST_RETRY_INTERVAL;
|
||||
end else begin
|
||||
arp_request_timer_next = REQUEST_TIMEOUT;
|
||||
end
|
||||
end else begin
|
||||
// out of retries
|
||||
arp_request_operation_next = 1'b0;
|
||||
arp_response_valid_next = 1'b1;
|
||||
arp_response_error_next = 1'b1;
|
||||
cache_query_request_valid_next = 1'b0;
|
||||
end
|
||||
end
|
||||
end else begin
|
||||
arp_request_ready_next = !arp_response_valid_next;
|
||||
if (cache_query_request_valid_reg) begin
|
||||
cache_query_request_valid_next = 1'b1;
|
||||
if (cache_query_response_valid) begin
|
||||
if (cache_query_response_error) begin
|
||||
arp_request_operation_next = 1'b1;
|
||||
// send ARP request frame
|
||||
outgoing_frame_valid_next = 1'b1;
|
||||
outgoing_eth_dest_mac_next = 48'hffffffffffff;
|
||||
outgoing_arp_oper_next = ARP_OPER_ARP_REQUEST;
|
||||
outgoing_arp_tha_next = 48'h000000000000;
|
||||
outgoing_arp_tpa_next = arp_request_ip_reg;
|
||||
arp_request_retry_cnt_next = REQUEST_RETRY_COUNT-1;
|
||||
arp_request_timer_next = REQUEST_RETRY_INTERVAL;
|
||||
end else begin
|
||||
cache_query_request_valid_next = 1'b0;
|
||||
arp_response_valid_next = 1'b1;
|
||||
arp_response_error_next = 1'b0;
|
||||
arp_response_mac_next = cache_query_response_mac;
|
||||
end
|
||||
end
|
||||
end else if (arp_request_valid && arp_request_ready) begin
|
||||
if (~(arp_request_ip | subnet_mask) == 0) begin
|
||||
// broadcast address
|
||||
// (all bits in request IP set where subnet mask is clear)
|
||||
arp_response_valid_next = 1'b1;
|
||||
arp_response_error_next = 1'b0;
|
||||
arp_response_mac_next = 48'hffffffffffff;
|
||||
end else if (((arp_request_ip ^ gateway_ip) & subnet_mask) == 0) begin
|
||||
// within subnet, look up IP directly
|
||||
// (no bits differ between request IP and gateway IP where subnet mask is set)
|
||||
cache_query_request_valid_next = 1'b1;
|
||||
cache_query_request_ip_next = arp_request_ip;
|
||||
arp_request_ip_next = arp_request_ip;
|
||||
end else begin
|
||||
// outside of subnet, so look up gateway address
|
||||
cache_query_request_valid_next = 1'b1;
|
||||
cache_query_request_ip_next = gateway_ip;
|
||||
arp_request_ip_next = gateway_ip;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
outgoing_frame_valid_reg <= 1'b0;
|
||||
cache_query_request_valid_reg <= 1'b0;
|
||||
cache_write_request_valid_reg <= 1'b0;
|
||||
arp_request_ready_reg <= 1'b0;
|
||||
arp_request_operation_reg <= 1'b0;
|
||||
arp_request_retry_cnt_reg <= 6'd0;
|
||||
arp_request_timer_reg <= 36'd0;
|
||||
arp_response_valid_reg <= 1'b0;
|
||||
end else begin
|
||||
outgoing_frame_valid_reg <= outgoing_frame_valid_next;
|
||||
cache_query_request_valid_reg <= cache_query_request_valid_next;
|
||||
cache_write_request_valid_reg <= cache_write_request_valid_next;
|
||||
arp_request_ready_reg <= arp_request_ready_next;
|
||||
arp_request_operation_reg <= arp_request_operation_next;
|
||||
arp_request_retry_cnt_reg <= arp_request_retry_cnt_next;
|
||||
arp_request_timer_reg <= arp_request_timer_next;
|
||||
arp_response_valid_reg <= arp_response_valid_next;
|
||||
end
|
||||
|
||||
cache_query_request_ip_reg <= cache_query_request_ip_next;
|
||||
outgoing_eth_dest_mac_reg <= outgoing_eth_dest_mac_next;
|
||||
outgoing_arp_oper_reg <= outgoing_arp_oper_next;
|
||||
outgoing_arp_tha_reg <= outgoing_arp_tha_next;
|
||||
outgoing_arp_tpa_reg <= outgoing_arp_tpa_next;
|
||||
cache_write_request_mac_reg <= cache_write_request_mac_next;
|
||||
cache_write_request_ip_reg <= cache_write_request_ip_next;
|
||||
arp_request_ip_reg <= arp_request_ip_next;
|
||||
arp_response_error_reg <= arp_response_error_next;
|
||||
arp_response_mac_reg <= arp_response_mac_next;
|
||||
end
|
||||
|
||||
endmodule
|
428
rtl/arp_eth_rx.v
428
rtl/arp_eth_rx.v
@ -1,6 +1,6 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
Copyright (c) 2014-2020 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
@ -29,51 +29,75 @@ THE SOFTWARE.
|
||||
/*
|
||||
* ARP ethernet frame receiver (Ethernet frame in, ARP frame out)
|
||||
*/
|
||||
module arp_eth_rx
|
||||
module arp_eth_rx #
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
// Width of AXI stream interfaces in bits
|
||||
parameter DATA_WIDTH = 8,
|
||||
// Propagate tkeep signal
|
||||
// If disabled, tkeep assumed to be 1'b1
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8),
|
||||
// tkeep signal width (words per cycle)
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* Ethernet frame input
|
||||
*/
|
||||
input wire s_eth_hdr_valid,
|
||||
output wire s_eth_hdr_ready,
|
||||
input wire [47:0] s_eth_dest_mac,
|
||||
input wire [47:0] s_eth_src_mac,
|
||||
input wire [15:0] s_eth_type,
|
||||
input wire [7:0] s_eth_payload_axis_tdata,
|
||||
input wire s_eth_payload_axis_tvalid,
|
||||
output wire s_eth_payload_axis_tready,
|
||||
input wire s_eth_payload_axis_tlast,
|
||||
input wire s_eth_payload_axis_tuser,
|
||||
input wire s_eth_hdr_valid,
|
||||
output wire s_eth_hdr_ready,
|
||||
input wire [47:0] s_eth_dest_mac,
|
||||
input wire [47:0] s_eth_src_mac,
|
||||
input wire [15:0] s_eth_type,
|
||||
input wire [DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
|
||||
input wire [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
|
||||
input wire s_eth_payload_axis_tvalid,
|
||||
output wire s_eth_payload_axis_tready,
|
||||
input wire s_eth_payload_axis_tlast,
|
||||
input wire s_eth_payload_axis_tuser,
|
||||
|
||||
/*
|
||||
* ARP frame output
|
||||
*/
|
||||
output wire m_frame_valid,
|
||||
input wire m_frame_ready,
|
||||
output wire [47:0] m_eth_dest_mac,
|
||||
output wire [47:0] m_eth_src_mac,
|
||||
output wire [15:0] m_eth_type,
|
||||
output wire [15:0] m_arp_htype,
|
||||
output wire [15:0] m_arp_ptype,
|
||||
output wire [7:0] m_arp_hlen,
|
||||
output wire [7:0] m_arp_plen,
|
||||
output wire [15:0] m_arp_oper,
|
||||
output wire [47:0] m_arp_sha,
|
||||
output wire [31:0] m_arp_spa,
|
||||
output wire [47:0] m_arp_tha,
|
||||
output wire [31:0] m_arp_tpa,
|
||||
output wire m_frame_valid,
|
||||
input wire m_frame_ready,
|
||||
output wire [47:0] m_eth_dest_mac,
|
||||
output wire [47:0] m_eth_src_mac,
|
||||
output wire [15:0] m_eth_type,
|
||||
output wire [15:0] m_arp_htype,
|
||||
output wire [15:0] m_arp_ptype,
|
||||
output wire [7:0] m_arp_hlen,
|
||||
output wire [7:0] m_arp_plen,
|
||||
output wire [15:0] m_arp_oper,
|
||||
output wire [47:0] m_arp_sha,
|
||||
output wire [31:0] m_arp_spa,
|
||||
output wire [47:0] m_arp_tha,
|
||||
output wire [31:0] m_arp_tpa,
|
||||
|
||||
/*
|
||||
* Status signals
|
||||
*/
|
||||
output wire busy,
|
||||
output wire error_header_early_termination,
|
||||
output wire error_invalid_header
|
||||
output wire busy,
|
||||
output wire error_header_early_termination,
|
||||
output wire error_invalid_header
|
||||
);
|
||||
|
||||
parameter CYCLE_COUNT = (28+KEEP_WIDTH-1)/KEEP_WIDTH;
|
||||
|
||||
parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
|
||||
|
||||
parameter OFFSET = 28 % KEEP_WIDTH;
|
||||
|
||||
// bus width assertions
|
||||
initial begin
|
||||
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
|
||||
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
/*
|
||||
|
||||
ARP Frame
|
||||
@ -98,45 +122,12 @@ produces the frame fields in parallel.
|
||||
|
||||
*/
|
||||
|
||||
localparam [2:0]
|
||||
STATE_IDLE = 3'd0,
|
||||
STATE_READ_HEADER = 3'd1,
|
||||
STATE_WAIT_LAST = 3'd2;
|
||||
|
||||
reg [2:0] state_reg = STATE_IDLE, state_next;
|
||||
|
||||
// datapath control signals
|
||||
reg store_eth_hdr;
|
||||
reg store_arp_htype_0;
|
||||
reg store_arp_htype_1;
|
||||
reg store_arp_ptype_0;
|
||||
reg store_arp_ptype_1;
|
||||
reg store_arp_hlen;
|
||||
reg store_arp_plen;
|
||||
reg store_arp_oper_0;
|
||||
reg store_arp_oper_1;
|
||||
reg store_arp_sha_0;
|
||||
reg store_arp_sha_1;
|
||||
reg store_arp_sha_2;
|
||||
reg store_arp_sha_3;
|
||||
reg store_arp_sha_4;
|
||||
reg store_arp_sha_5;
|
||||
reg store_arp_spa_0;
|
||||
reg store_arp_spa_1;
|
||||
reg store_arp_spa_2;
|
||||
reg store_arp_spa_3;
|
||||
reg store_arp_tha_0;
|
||||
reg store_arp_tha_1;
|
||||
reg store_arp_tha_2;
|
||||
reg store_arp_tha_3;
|
||||
reg store_arp_tha_4;
|
||||
reg store_arp_tha_5;
|
||||
reg store_arp_tpa_0;
|
||||
reg store_arp_tpa_1;
|
||||
reg store_arp_tpa_2;
|
||||
reg store_arp_tpa_3;
|
||||
|
||||
reg [7:0] frame_ptr_reg = 8'd0, frame_ptr_next;
|
||||
reg read_eth_header_reg = 1'b1, read_eth_header_next;
|
||||
reg read_arp_header_reg = 1'b0, read_arp_header_next;
|
||||
reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next;
|
||||
|
||||
reg s_eth_hdr_ready_reg = 1'b0, s_eth_hdr_ready_next;
|
||||
reg s_eth_payload_axis_tready_reg = 1'b0, s_eth_payload_axis_tready_next;
|
||||
@ -145,15 +136,15 @@ reg m_frame_valid_reg = 1'b0, m_frame_valid_next;
|
||||
reg [47:0] m_eth_dest_mac_reg = 48'd0;
|
||||
reg [47:0] m_eth_src_mac_reg = 48'd0;
|
||||
reg [15:0] m_eth_type_reg = 16'd0;
|
||||
reg [15:0] m_arp_htype_reg = 16'd0;
|
||||
reg [15:0] m_arp_ptype_reg = 16'd0;
|
||||
reg [7:0] m_arp_hlen_reg = 8'd0;
|
||||
reg [7:0] m_arp_plen_reg = 8'd0;
|
||||
reg [15:0] m_arp_oper_reg = 16'd0;
|
||||
reg [47:0] m_arp_sha_reg = 48'd0;
|
||||
reg [31:0] m_arp_spa_reg = 32'd0;
|
||||
reg [47:0] m_arp_tha_reg = 48'd0;
|
||||
reg [31:0] m_arp_tpa_reg = 32'd0;
|
||||
reg [15:0] m_arp_htype_reg = 16'd0, m_arp_htype_next;
|
||||
reg [15:0] m_arp_ptype_reg = 16'd0, m_arp_ptype_next;
|
||||
reg [7:0] m_arp_hlen_reg = 8'd0, m_arp_hlen_next;
|
||||
reg [7:0] m_arp_plen_reg = 8'd0, m_arp_plen_next;
|
||||
reg [15:0] m_arp_oper_reg = 16'd0, m_arp_oper_next;
|
||||
reg [47:0] m_arp_sha_reg = 48'd0, m_arp_sha_next;
|
||||
reg [31:0] m_arp_spa_reg = 32'd0, m_arp_spa_next;
|
||||
reg [47:0] m_arp_tha_reg = 48'd0, m_arp_tha_next;
|
||||
reg [31:0] m_arp_tpa_reg = 32'd0, m_arp_tpa_next;
|
||||
|
||||
reg busy_reg = 1'b0;
|
||||
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
|
||||
@ -181,175 +172,134 @@ assign error_header_early_termination = error_header_early_termination_reg;
|
||||
assign error_invalid_header = error_invalid_header_reg;
|
||||
|
||||
always @* begin
|
||||
state_next = STATE_IDLE;
|
||||
read_eth_header_next = read_eth_header_reg;
|
||||
read_arp_header_next = read_arp_header_reg;
|
||||
ptr_next = ptr_reg;
|
||||
|
||||
s_eth_hdr_ready_next = 1'b0;
|
||||
s_eth_payload_axis_tready_next = 1'b0;
|
||||
|
||||
store_eth_hdr = 1'b0;
|
||||
store_arp_htype_0 = 1'b0;
|
||||
store_arp_htype_1 = 1'b0;
|
||||
store_arp_ptype_0 = 1'b0;
|
||||
store_arp_ptype_1 = 1'b0;
|
||||
store_arp_hlen = 1'b0;
|
||||
store_arp_plen = 1'b0;
|
||||
store_arp_oper_0 = 1'b0;
|
||||
store_arp_oper_1 = 1'b0;
|
||||
store_arp_sha_0 = 1'b0;
|
||||
store_arp_sha_1 = 1'b0;
|
||||
store_arp_sha_2 = 1'b0;
|
||||
store_arp_sha_3 = 1'b0;
|
||||
store_arp_sha_4 = 1'b0;
|
||||
store_arp_sha_5 = 1'b0;
|
||||
store_arp_spa_0 = 1'b0;
|
||||
store_arp_spa_1 = 1'b0;
|
||||
store_arp_spa_2 = 1'b0;
|
||||
store_arp_spa_3 = 1'b0;
|
||||
store_arp_tha_0 = 1'b0;
|
||||
store_arp_tha_1 = 1'b0;
|
||||
store_arp_tha_2 = 1'b0;
|
||||
store_arp_tha_3 = 1'b0;
|
||||
store_arp_tha_4 = 1'b0;
|
||||
store_arp_tha_5 = 1'b0;
|
||||
store_arp_tpa_0 = 1'b0;
|
||||
store_arp_tpa_1 = 1'b0;
|
||||
store_arp_tpa_2 = 1'b0;
|
||||
store_arp_tpa_3 = 1'b0;
|
||||
|
||||
frame_ptr_next = frame_ptr_reg;
|
||||
|
||||
m_frame_valid_next = m_frame_valid_reg && !m_frame_ready;
|
||||
|
||||
m_arp_htype_next = m_arp_htype_reg;
|
||||
m_arp_ptype_next = m_arp_ptype_reg;
|
||||
m_arp_hlen_next = m_arp_hlen_reg;
|
||||
m_arp_plen_next = m_arp_plen_reg;
|
||||
m_arp_oper_next = m_arp_oper_reg;
|
||||
m_arp_sha_next = m_arp_sha_reg;
|
||||
m_arp_spa_next = m_arp_spa_reg;
|
||||
m_arp_tha_next = m_arp_tha_reg;
|
||||
m_arp_tpa_next = m_arp_tpa_reg;
|
||||
|
||||
error_header_early_termination_next = 1'b0;
|
||||
error_invalid_header_next = 1'b0;
|
||||
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
// idle state - wait for data
|
||||
frame_ptr_next = 8'd0;
|
||||
s_eth_hdr_ready_next = !m_frame_valid_next;
|
||||
|
||||
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
|
||||
s_eth_hdr_ready_next = 1'b0;
|
||||
s_eth_payload_axis_tready_next = 1'b1;
|
||||
store_eth_hdr = 1'b1;
|
||||
state_next = STATE_READ_HEADER;
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
|
||||
if (read_eth_header_reg) begin
|
||||
store_eth_hdr = 1'b1;
|
||||
ptr_next = 0;
|
||||
read_eth_header_next = 1'b0;
|
||||
read_arp_header_next = 1'b1;
|
||||
end
|
||||
STATE_READ_HEADER: begin
|
||||
// read header state
|
||||
s_eth_payload_axis_tready_next = 1'b1;
|
||||
end
|
||||
|
||||
if (s_eth_payload_axis_tvalid) begin
|
||||
// word transfer in - store it
|
||||
frame_ptr_next = frame_ptr_reg + 8'd1;
|
||||
state_next = STATE_READ_HEADER;
|
||||
case (frame_ptr_reg)
|
||||
8'h00: store_arp_htype_1 = 1'b1;
|
||||
8'h01: store_arp_htype_0 = 1'b1;
|
||||
8'h02: store_arp_ptype_1 = 1'b1;
|
||||
8'h03: store_arp_ptype_0 = 1'b1;
|
||||
8'h04: store_arp_hlen = 1'b1;
|
||||
8'h05: store_arp_plen = 1'b1;
|
||||
8'h06: store_arp_oper_1 = 1'b1;
|
||||
8'h07: store_arp_oper_0 = 1'b1;
|
||||
8'h08: store_arp_sha_5 = 1'b1;
|
||||
8'h09: store_arp_sha_4 = 1'b1;
|
||||
8'h0A: store_arp_sha_3 = 1'b1;
|
||||
8'h0B: store_arp_sha_2 = 1'b1;
|
||||
8'h0C: store_arp_sha_1 = 1'b1;
|
||||
8'h0D: store_arp_sha_0 = 1'b1;
|
||||
8'h0E: store_arp_spa_3 = 1'b1;
|
||||
8'h0F: store_arp_spa_2 = 1'b1;
|
||||
8'h10: store_arp_spa_1 = 1'b1;
|
||||
8'h11: store_arp_spa_0 = 1'b1;
|
||||
8'h12: store_arp_tha_5 = 1'b1;
|
||||
8'h13: store_arp_tha_4 = 1'b1;
|
||||
8'h14: store_arp_tha_3 = 1'b1;
|
||||
8'h15: store_arp_tha_2 = 1'b1;
|
||||
8'h16: store_arp_tha_1 = 1'b1;
|
||||
8'h17: store_arp_tha_0 = 1'b1;
|
||||
8'h18: store_arp_tpa_3 = 1'b1;
|
||||
8'h19: store_arp_tpa_2 = 1'b1;
|
||||
8'h1A: store_arp_tpa_1 = 1'b1;
|
||||
8'h1B: begin
|
||||
store_arp_tpa_0 = 1'b1;
|
||||
state_next = STATE_WAIT_LAST;
|
||||
end
|
||||
endcase
|
||||
if (s_eth_payload_axis_tlast) begin
|
||||
// end of frame
|
||||
if (frame_ptr_reg != 8'h1B) begin
|
||||
// don't have the whole header
|
||||
error_header_early_termination_next = 1'b1;
|
||||
end else if (m_arp_hlen != 4'd6 || m_arp_plen != 4'd4) begin
|
||||
// lengths not valid
|
||||
error_invalid_header_next = 1'b1;
|
||||
end else begin
|
||||
// otherwise, transfer tuser
|
||||
m_frame_valid_next = !s_eth_payload_axis_tuser;
|
||||
end
|
||||
s_eth_hdr_ready_next = !m_frame_valid_next;
|
||||
s_eth_payload_axis_tready_next = 1'b0;
|
||||
state_next = STATE_IDLE;
|
||||
if (s_eth_payload_axis_tready && s_eth_payload_axis_tvalid) begin
|
||||
if (read_arp_header_reg) begin
|
||||
// word transfer in - store it
|
||||
ptr_next = ptr_reg + 1;
|
||||
|
||||
`define _HEADER_FIELD_(offset, field) \
|
||||
if (ptr_reg == offset/KEEP_WIDTH && (!KEEP_ENABLE || s_eth_payload_axis_tkeep[offset%KEEP_WIDTH])) begin \
|
||||
field = s_eth_payload_axis_tdata[(offset%KEEP_WIDTH)*8 +: 8]; \
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_READ_HEADER;
|
||||
end
|
||||
end
|
||||
STATE_WAIT_LAST: begin
|
||||
// wait for end of frame; read and discard
|
||||
s_eth_payload_axis_tready_next = 1'b1;
|
||||
|
||||
if (s_eth_payload_axis_tvalid) begin
|
||||
if (s_eth_payload_axis_tlast) begin
|
||||
if (m_arp_hlen != 4'd6 || m_arp_plen != 4'd4) begin
|
||||
// lengths not valid
|
||||
error_invalid_header_next = 1'b1;
|
||||
end else begin
|
||||
// otherwise, transfer tuser
|
||||
m_frame_valid_next = !s_eth_payload_axis_tuser;
|
||||
end
|
||||
s_eth_hdr_ready_next = !m_frame_valid_next;
|
||||
s_eth_payload_axis_tready_next = 1'b0;
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_WAIT_LAST;
|
||||
end
|
||||
end else begin
|
||||
// wait for end of frame; read and discard
|
||||
state_next = STATE_WAIT_LAST;
|
||||
`_HEADER_FIELD_(0, m_arp_htype_next[1*8 +: 8])
|
||||
`_HEADER_FIELD_(1, m_arp_htype_next[0*8 +: 8])
|
||||
`_HEADER_FIELD_(2, m_arp_ptype_next[1*8 +: 8])
|
||||
`_HEADER_FIELD_(3, m_arp_ptype_next[0*8 +: 8])
|
||||
`_HEADER_FIELD_(4, m_arp_hlen_next[0*8 +: 8])
|
||||
`_HEADER_FIELD_(5, m_arp_plen_next[0*8 +: 8])
|
||||
`_HEADER_FIELD_(6, m_arp_oper_next[1*8 +: 8])
|
||||
`_HEADER_FIELD_(7, m_arp_oper_next[0*8 +: 8])
|
||||
`_HEADER_FIELD_(8, m_arp_sha_next[5*8 +: 8])
|
||||
`_HEADER_FIELD_(9, m_arp_sha_next[4*8 +: 8])
|
||||
`_HEADER_FIELD_(10, m_arp_sha_next[3*8 +: 8])
|
||||
`_HEADER_FIELD_(11, m_arp_sha_next[2*8 +: 8])
|
||||
`_HEADER_FIELD_(12, m_arp_sha_next[1*8 +: 8])
|
||||
`_HEADER_FIELD_(13, m_arp_sha_next[0*8 +: 8])
|
||||
`_HEADER_FIELD_(14, m_arp_spa_next[3*8 +: 8])
|
||||
`_HEADER_FIELD_(15, m_arp_spa_next[2*8 +: 8])
|
||||
`_HEADER_FIELD_(16, m_arp_spa_next[1*8 +: 8])
|
||||
`_HEADER_FIELD_(17, m_arp_spa_next[0*8 +: 8])
|
||||
`_HEADER_FIELD_(18, m_arp_tha_next[5*8 +: 8])
|
||||
`_HEADER_FIELD_(19, m_arp_tha_next[4*8 +: 8])
|
||||
`_HEADER_FIELD_(20, m_arp_tha_next[3*8 +: 8])
|
||||
`_HEADER_FIELD_(21, m_arp_tha_next[2*8 +: 8])
|
||||
`_HEADER_FIELD_(22, m_arp_tha_next[1*8 +: 8])
|
||||
`_HEADER_FIELD_(23, m_arp_tha_next[0*8 +: 8])
|
||||
`_HEADER_FIELD_(24, m_arp_tpa_next[3*8 +: 8])
|
||||
`_HEADER_FIELD_(25, m_arp_tpa_next[2*8 +: 8])
|
||||
`_HEADER_FIELD_(26, m_arp_tpa_next[1*8 +: 8])
|
||||
`_HEADER_FIELD_(27, m_arp_tpa_next[0*8 +: 8])
|
||||
|
||||
if (ptr_reg == 27/KEEP_WIDTH && (!KEEP_ENABLE || s_eth_payload_axis_tkeep[27%KEEP_WIDTH])) begin
|
||||
read_arp_header_next = 1'b0;
|
||||
end
|
||||
|
||||
`undef _HEADER_FIELD_
|
||||
end
|
||||
endcase
|
||||
|
||||
if (s_eth_payload_axis_tlast) begin
|
||||
if (read_arp_header_next) begin
|
||||
// don't have the whole header
|
||||
error_header_early_termination_next = 1'b1;
|
||||
end else if (m_arp_hlen_next != 4'd6 || m_arp_plen_next != 4'd4) begin
|
||||
// lengths not valid
|
||||
error_invalid_header_next = 1'b1;
|
||||
end else begin
|
||||
// otherwise, transfer tuser
|
||||
m_frame_valid_next = !s_eth_payload_axis_tuser;
|
||||
end
|
||||
|
||||
ptr_next = 1'b0;
|
||||
read_eth_header_next = 1'b1;
|
||||
read_arp_header_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
if (read_eth_header_next) begin
|
||||
s_eth_hdr_ready_next = !m_frame_valid_next;
|
||||
end else begin
|
||||
s_eth_payload_axis_tready_next = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
frame_ptr_reg <= 8'd0;
|
||||
s_eth_payload_axis_tready_reg <= 1'b0;
|
||||
m_frame_valid_reg <= 1'b0;
|
||||
busy_reg <= 1'b0;
|
||||
error_header_early_termination_reg <= 1'b0;
|
||||
error_invalid_header_reg <= 1'b0;
|
||||
end else begin
|
||||
state_reg <= state_next;
|
||||
read_eth_header_reg <= read_eth_header_next;
|
||||
read_arp_header_reg <= read_arp_header_next;
|
||||
ptr_reg <= ptr_next;
|
||||
|
||||
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
|
||||
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
|
||||
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
|
||||
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
|
||||
|
||||
frame_ptr_reg <= frame_ptr_next;
|
||||
m_frame_valid_reg <= m_frame_valid_next;
|
||||
|
||||
m_frame_valid_reg <= m_frame_valid_next;
|
||||
m_arp_htype_reg <= m_arp_htype_next;
|
||||
m_arp_ptype_reg <= m_arp_ptype_next;
|
||||
m_arp_hlen_reg <= m_arp_hlen_next;
|
||||
m_arp_plen_reg <= m_arp_plen_next;
|
||||
m_arp_oper_reg <= m_arp_oper_next;
|
||||
m_arp_sha_reg <= m_arp_sha_next;
|
||||
m_arp_spa_reg <= m_arp_spa_next;
|
||||
m_arp_tha_reg <= m_arp_tha_next;
|
||||
m_arp_tpa_reg <= m_arp_tpa_next;
|
||||
|
||||
error_header_early_termination_reg <= error_header_early_termination_next;
|
||||
error_invalid_header_reg <= error_invalid_header_next;
|
||||
error_header_early_termination_reg <= error_header_early_termination_next;
|
||||
error_invalid_header_reg <= error_invalid_header_next;
|
||||
|
||||
busy_reg <= state_next != STATE_IDLE;
|
||||
end
|
||||
busy_reg <= read_arp_header_next;
|
||||
|
||||
// datapath
|
||||
if (store_eth_hdr) begin
|
||||
@ -358,34 +308,16 @@ always @(posedge clk) begin
|
||||
m_eth_type_reg <= s_eth_type;
|
||||
end
|
||||
|
||||
if (store_arp_htype_0) m_arp_htype_reg[ 7: 0] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_htype_1) m_arp_htype_reg[15: 8] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_ptype_0) m_arp_ptype_reg[ 7: 0] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_ptype_1) m_arp_ptype_reg[15: 8] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_hlen) m_arp_hlen_reg <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_plen) m_arp_plen_reg <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_oper_0) m_arp_oper_reg[ 7: 0] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_oper_1) m_arp_oper_reg[15: 8] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_sha_0) m_arp_sha_reg[ 7: 0] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_sha_1) m_arp_sha_reg[15: 8] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_sha_2) m_arp_sha_reg[23:16] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_sha_3) m_arp_sha_reg[31:24] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_sha_4) m_arp_sha_reg[39:32] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_sha_5) m_arp_sha_reg[47:40] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_spa_0) m_arp_spa_reg[ 7: 0] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_spa_1) m_arp_spa_reg[15: 8] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_spa_2) m_arp_spa_reg[23:16] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_spa_3) m_arp_spa_reg[31:24] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_tha_0) m_arp_tha_reg[ 7: 0] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_tha_1) m_arp_tha_reg[15: 8] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_tha_2) m_arp_tha_reg[23:16] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_tha_3) m_arp_tha_reg[31:24] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_tha_4) m_arp_tha_reg[39:32] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_tha_5) m_arp_tha_reg[47:40] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_tpa_0) m_arp_tpa_reg[ 7: 0] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_tpa_1) m_arp_tpa_reg[15: 8] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_tpa_2) m_arp_tpa_reg[23:16] <= s_eth_payload_axis_tdata;
|
||||
if (store_arp_tpa_3) m_arp_tpa_reg[31:24] <= s_eth_payload_axis_tdata;
|
||||
if (rst) begin
|
||||
read_eth_header_reg <= 1'b1;
|
||||
read_arp_header_reg <= 1'b0;
|
||||
ptr_reg <= 0;
|
||||
s_eth_payload_axis_tready_reg <= 1'b0;
|
||||
m_frame_valid_reg <= 1'b0;
|
||||
busy_reg <= 1'b0;
|
||||
error_header_early_termination_reg <= 1'b0;
|
||||
error_invalid_header_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
@ -1,324 +0,0 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* ARP ethernet frame receiver (Ethernet frame in, ARP frame out, 64 bit datapath)
|
||||
*/
|
||||
module arp_eth_rx_64
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* Ethernet frame input
|
||||
*/
|
||||
input wire s_eth_hdr_valid,
|
||||
output wire s_eth_hdr_ready,
|
||||
input wire [47:0] s_eth_dest_mac,
|
||||
input wire [47:0] s_eth_src_mac,
|
||||
input wire [15:0] s_eth_type,
|
||||
input wire [63:0] s_eth_payload_axis_tdata,
|
||||
input wire [7:0] s_eth_payload_axis_tkeep,
|
||||
input wire s_eth_payload_axis_tvalid,
|
||||
output wire s_eth_payload_axis_tready,
|
||||
input wire s_eth_payload_axis_tlast,
|
||||
input wire s_eth_payload_axis_tuser,
|
||||
|
||||
/*
|
||||
* ARP frame output
|
||||
*/
|
||||
output wire m_frame_valid,
|
||||
input wire m_frame_ready,
|
||||
output wire [47:0] m_eth_dest_mac,
|
||||
output wire [47:0] m_eth_src_mac,
|
||||
output wire [15:0] m_eth_type,
|
||||
output wire [15:0] m_arp_htype,
|
||||
output wire [15:0] m_arp_ptype,
|
||||
output wire [7:0] m_arp_hlen,
|
||||
output wire [7:0] m_arp_plen,
|
||||
output wire [15:0] m_arp_oper,
|
||||
output wire [47:0] m_arp_sha,
|
||||
output wire [31:0] m_arp_spa,
|
||||
output wire [47:0] m_arp_tha,
|
||||
output wire [31:0] m_arp_tpa,
|
||||
|
||||
/*
|
||||
* Status signals
|
||||
*/
|
||||
output wire busy,
|
||||
output wire error_header_early_termination,
|
||||
output wire error_invalid_header
|
||||
);
|
||||
|
||||
/*
|
||||
|
||||
ARP Frame
|
||||
|
||||
Field Length
|
||||
Destination MAC address 6 octets
|
||||
Source MAC address 6 octets
|
||||
Ethertype (0x0806) 2 octets
|
||||
HTYPE (1) 2 octets
|
||||
PTYPE (0x0800) 2 octets
|
||||
HLEN (6) 1 octets
|
||||
PLEN (4) 1 octets
|
||||
OPER 2 octets
|
||||
SHA Sender MAC 6 octets
|
||||
SPA Sender IP 4 octets
|
||||
THA Target MAC 6 octets
|
||||
TPA Target IP 4 octets
|
||||
|
||||
This module receives an Ethernet frame with header fields in parallel and
|
||||
payload on an AXI stream interface, decodes the ARP packet fields, and
|
||||
produces the frame fields in parallel.
|
||||
|
||||
*/
|
||||
|
||||
localparam [2:0]
|
||||
STATE_IDLE = 3'd0,
|
||||
STATE_READ_HEADER = 3'd1,
|
||||
STATE_WAIT_LAST = 3'd2;
|
||||
|
||||
reg [2:0] state_reg = STATE_IDLE, state_next;
|
||||
|
||||
// datapath control signals
|
||||
reg store_eth_hdr;
|
||||
reg store_arp_hdr_word_0;
|
||||
reg store_arp_hdr_word_1;
|
||||
reg store_arp_hdr_word_2;
|
||||
reg store_arp_hdr_word_3;
|
||||
|
||||
reg [7:0] frame_ptr_reg = 8'd0, frame_ptr_next;
|
||||
|
||||
reg s_eth_hdr_ready_reg = 1'b0, s_eth_hdr_ready_next;
|
||||
reg s_eth_payload_axis_tready_reg = 1'b0, s_eth_payload_axis_tready_next;
|
||||
|
||||
reg m_frame_valid_reg = 1'b0, m_frame_valid_next;
|
||||
reg [47:0] m_eth_dest_mac_reg = 48'd0;
|
||||
reg [47:0] m_eth_src_mac_reg = 48'd0;
|
||||
reg [15:0] m_eth_type_reg = 16'd0;
|
||||
reg [15:0] m_arp_htype_reg = 16'd0;
|
||||
reg [15:0] m_arp_ptype_reg = 16'd0;
|
||||
reg [7:0] m_arp_hlen_reg = 8'd0;
|
||||
reg [7:0] m_arp_plen_reg = 8'd0;
|
||||
reg [15:0] m_arp_oper_reg = 16'd0;
|
||||
reg [47:0] m_arp_sha_reg = 48'd0;
|
||||
reg [31:0] m_arp_spa_reg = 32'd0;
|
||||
reg [47:0] m_arp_tha_reg = 48'd0;
|
||||
reg [31:0] m_arp_tpa_reg = 32'd0;
|
||||
|
||||
reg busy_reg = 1'b0;
|
||||
reg error_header_early_termination_reg = 1'b0, error_header_early_termination_next;
|
||||
reg error_invalid_header_reg = 1'b0, error_invalid_header_next;
|
||||
|
||||
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
|
||||
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg;
|
||||
|
||||
assign m_frame_valid = m_frame_valid_reg;
|
||||
assign m_eth_dest_mac = m_eth_dest_mac_reg;
|
||||
assign m_eth_src_mac = m_eth_src_mac_reg;
|
||||
assign m_eth_type = m_eth_type_reg;
|
||||
assign m_arp_htype = m_arp_htype_reg;
|
||||
assign m_arp_ptype = m_arp_ptype_reg;
|
||||
assign m_arp_hlen = m_arp_hlen_reg;
|
||||
assign m_arp_plen = m_arp_plen_reg;
|
||||
assign m_arp_oper = m_arp_oper_reg;
|
||||
assign m_arp_sha = m_arp_sha_reg;
|
||||
assign m_arp_spa = m_arp_spa_reg;
|
||||
assign m_arp_tha = m_arp_tha_reg;
|
||||
assign m_arp_tpa = m_arp_tpa_reg;
|
||||
|
||||
assign busy = busy_reg;
|
||||
assign error_header_early_termination = error_header_early_termination_reg;
|
||||
assign error_invalid_header = error_invalid_header_reg;
|
||||
|
||||
always @* begin
|
||||
state_next = STATE_IDLE;
|
||||
|
||||
s_eth_hdr_ready_next = 1'b0;
|
||||
s_eth_payload_axis_tready_next = 1'b0;
|
||||
|
||||
store_eth_hdr = 1'b0;
|
||||
store_arp_hdr_word_0 = 1'b0;
|
||||
store_arp_hdr_word_1 = 1'b0;
|
||||
store_arp_hdr_word_2 = 1'b0;
|
||||
store_arp_hdr_word_3 = 1'b0;
|
||||
|
||||
frame_ptr_next = frame_ptr_reg;
|
||||
|
||||
m_frame_valid_next = m_frame_valid_reg && !m_frame_ready;
|
||||
|
||||
error_header_early_termination_next = 1'b0;
|
||||
error_invalid_header_next = 1'b0;
|
||||
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
// idle state - wait for data
|
||||
frame_ptr_next = 8'd0;
|
||||
s_eth_hdr_ready_next = !m_frame_valid_next;
|
||||
|
||||
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
|
||||
s_eth_hdr_ready_next = 1'b0;
|
||||
s_eth_payload_axis_tready_next = 1'b1;
|
||||
store_eth_hdr = 1'b1;
|
||||
state_next = STATE_READ_HEADER;
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end
|
||||
STATE_READ_HEADER: begin
|
||||
// read header state
|
||||
s_eth_payload_axis_tready_next = 1'b1;
|
||||
|
||||
if (s_eth_payload_axis_tvalid) begin
|
||||
// word transfer in - store it
|
||||
frame_ptr_next = frame_ptr_reg + 8'd1;
|
||||
state_next = STATE_READ_HEADER;
|
||||
case (frame_ptr_reg)
|
||||
8'h00: store_arp_hdr_word_0 = 1'b1;
|
||||
8'h01: store_arp_hdr_word_1 = 1'b1;
|
||||
8'h02: store_arp_hdr_word_2 = 1'b1;
|
||||
8'h03: begin
|
||||
store_arp_hdr_word_3 = 1'b1;
|
||||
state_next = STATE_WAIT_LAST;
|
||||
end
|
||||
endcase
|
||||
if (s_eth_payload_axis_tlast) begin
|
||||
if (frame_ptr_reg != 8'h03 || (s_eth_payload_axis_tkeep & 8'h0F) != 8'h0F) begin
|
||||
error_header_early_termination_next = 1'b1;
|
||||
end else if (m_arp_hlen != 4'd6 || m_arp_plen != 4'd4) begin
|
||||
error_invalid_header_next = 1'b1;
|
||||
end else begin
|
||||
m_frame_valid_next = !s_eth_payload_axis_tuser;
|
||||
end
|
||||
s_eth_hdr_ready_next = !m_frame_valid_next;
|
||||
s_eth_payload_axis_tready_next = 1'b0;
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_READ_HEADER;
|
||||
end
|
||||
end
|
||||
STATE_WAIT_LAST: begin
|
||||
// wait for end of frame; read and discard
|
||||
s_eth_payload_axis_tready_next = 1'b1;
|
||||
|
||||
if (s_eth_payload_axis_tvalid) begin
|
||||
if (s_eth_payload_axis_tlast) begin
|
||||
if (m_arp_hlen != 4'd6 || m_arp_plen != 4'd4) begin
|
||||
// lengths not valid
|
||||
error_invalid_header_next = 1'b1;
|
||||
end else begin
|
||||
// otherwise, transfer tuser
|
||||
m_frame_valid_next = !s_eth_payload_axis_tuser;
|
||||
end
|
||||
s_eth_hdr_ready_next = !m_frame_valid_next;
|
||||
s_eth_payload_axis_tready_next = 1'b0;
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_WAIT_LAST;
|
||||
end
|
||||
end else begin
|
||||
// wait for end of frame; read and discard
|
||||
state_next = STATE_WAIT_LAST;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
frame_ptr_reg <= 8'd0;
|
||||
s_eth_payload_axis_tready_reg <= 1'b0;
|
||||
m_frame_valid_reg <= 1'b0;
|
||||
busy_reg <= 1'b0;
|
||||
error_header_early_termination_reg <= 1'b0;
|
||||
error_invalid_header_reg <= 1'b0;
|
||||
end else begin
|
||||
state_reg <= state_next;
|
||||
|
||||
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
|
||||
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
|
||||
|
||||
frame_ptr_reg <= frame_ptr_next;
|
||||
|
||||
m_frame_valid_reg <= m_frame_valid_next;
|
||||
|
||||
error_header_early_termination_reg <= error_header_early_termination_next;
|
||||
error_invalid_header_reg <= error_invalid_header_next;
|
||||
|
||||
busy_reg <= state_next != STATE_IDLE;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_eth_hdr) begin
|
||||
m_eth_dest_mac_reg <= s_eth_dest_mac;
|
||||
m_eth_src_mac_reg <= s_eth_src_mac;
|
||||
m_eth_type_reg <= s_eth_type;
|
||||
end
|
||||
|
||||
if (store_arp_hdr_word_0) begin
|
||||
m_arp_htype_reg[15: 8] <= s_eth_payload_axis_tdata[ 7: 0];
|
||||
m_arp_htype_reg[ 7: 0] <= s_eth_payload_axis_tdata[15: 8];
|
||||
m_arp_ptype_reg[15: 8] <= s_eth_payload_axis_tdata[23:16];
|
||||
m_arp_ptype_reg[ 7: 0] <= s_eth_payload_axis_tdata[31:24];
|
||||
m_arp_hlen_reg <= s_eth_payload_axis_tdata[39:32];
|
||||
m_arp_plen_reg <= s_eth_payload_axis_tdata[47:40];
|
||||
m_arp_oper_reg[15: 8] <= s_eth_payload_axis_tdata[55:48];
|
||||
m_arp_oper_reg[ 7: 0] <= s_eth_payload_axis_tdata[63:56];
|
||||
end
|
||||
if (store_arp_hdr_word_1) begin
|
||||
m_arp_sha_reg[47:40] <= s_eth_payload_axis_tdata[ 7: 0];
|
||||
m_arp_sha_reg[39:32] <= s_eth_payload_axis_tdata[15: 8];
|
||||
m_arp_sha_reg[31:24] <= s_eth_payload_axis_tdata[23:16];
|
||||
m_arp_sha_reg[23:16] <= s_eth_payload_axis_tdata[31:24];
|
||||
m_arp_sha_reg[15: 8] <= s_eth_payload_axis_tdata[39:32];
|
||||
m_arp_sha_reg[ 7: 0] <= s_eth_payload_axis_tdata[47:40];
|
||||
m_arp_spa_reg[31:24] <= s_eth_payload_axis_tdata[55:48];
|
||||
m_arp_spa_reg[23:16] <= s_eth_payload_axis_tdata[63:56];
|
||||
end
|
||||
if (store_arp_hdr_word_2) begin
|
||||
m_arp_spa_reg[15: 8] <= s_eth_payload_axis_tdata[ 7: 0];
|
||||
m_arp_spa_reg[ 7: 0] <= s_eth_payload_axis_tdata[15: 8];
|
||||
m_arp_tha_reg[47:40] <= s_eth_payload_axis_tdata[23:16];
|
||||
m_arp_tha_reg[39:32] <= s_eth_payload_axis_tdata[31:24];
|
||||
m_arp_tha_reg[31:24] <= s_eth_payload_axis_tdata[39:32];
|
||||
m_arp_tha_reg[23:16] <= s_eth_payload_axis_tdata[47:40];
|
||||
m_arp_tha_reg[15: 8] <= s_eth_payload_axis_tdata[55:48];
|
||||
m_arp_tha_reg[ 7: 0] <= s_eth_payload_axis_tdata[63:56];
|
||||
end
|
||||
if (store_arp_hdr_word_3) begin
|
||||
m_arp_tpa_reg[31:24] <= s_eth_payload_axis_tdata[ 7: 0];
|
||||
m_arp_tpa_reg[23:16] <= s_eth_payload_axis_tdata[15: 8];
|
||||
m_arp_tpa_reg[15: 8] <= s_eth_payload_axis_tdata[23:16];
|
||||
m_arp_tpa_reg[ 7: 0] <= s_eth_payload_axis_tdata[31:24];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
280
rtl/arp_eth_tx.v
280
rtl/arp_eth_tx.v
@ -1,6 +1,6 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
Copyright (c) 2014-2020 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
@ -29,47 +29,71 @@ THE SOFTWARE.
|
||||
/*
|
||||
* ARP ethernet frame transmitter (ARP frame in, Ethernet frame out)
|
||||
*/
|
||||
module arp_eth_tx
|
||||
module arp_eth_tx #
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
// Width of AXI stream interfaces in bits
|
||||
parameter DATA_WIDTH = 8,
|
||||
// Propagate tkeep signal
|
||||
// If disabled, tkeep assumed to be 1'b1
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8),
|
||||
// tkeep signal width (words per cycle)
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* ARP frame input
|
||||
*/
|
||||
input wire s_frame_valid,
|
||||
output wire s_frame_ready,
|
||||
input wire [47:0] s_eth_dest_mac,
|
||||
input wire [47:0] s_eth_src_mac,
|
||||
input wire [15:0] s_eth_type,
|
||||
input wire [15:0] s_arp_htype,
|
||||
input wire [15:0] s_arp_ptype,
|
||||
input wire [15:0] s_arp_oper,
|
||||
input wire [47:0] s_arp_sha,
|
||||
input wire [31:0] s_arp_spa,
|
||||
input wire [47:0] s_arp_tha,
|
||||
input wire [31:0] s_arp_tpa,
|
||||
input wire s_frame_valid,
|
||||
output wire s_frame_ready,
|
||||
input wire [47:0] s_eth_dest_mac,
|
||||
input wire [47:0] s_eth_src_mac,
|
||||
input wire [15:0] s_eth_type,
|
||||
input wire [15:0] s_arp_htype,
|
||||
input wire [15:0] s_arp_ptype,
|
||||
input wire [15:0] s_arp_oper,
|
||||
input wire [47:0] s_arp_sha,
|
||||
input wire [31:0] s_arp_spa,
|
||||
input wire [47:0] s_arp_tha,
|
||||
input wire [31:0] s_arp_tpa,
|
||||
|
||||
/*
|
||||
* Ethernet frame output
|
||||
*/
|
||||
output wire m_eth_hdr_valid,
|
||||
input wire m_eth_hdr_ready,
|
||||
output wire [47:0] m_eth_dest_mac,
|
||||
output wire [47:0] m_eth_src_mac,
|
||||
output wire [15:0] m_eth_type,
|
||||
output wire [7:0] m_eth_payload_axis_tdata,
|
||||
output wire m_eth_payload_axis_tvalid,
|
||||
input wire m_eth_payload_axis_tready,
|
||||
output wire m_eth_payload_axis_tlast,
|
||||
output wire m_eth_payload_axis_tuser,
|
||||
output wire m_eth_hdr_valid,
|
||||
input wire m_eth_hdr_ready,
|
||||
output wire [47:0] m_eth_dest_mac,
|
||||
output wire [47:0] m_eth_src_mac,
|
||||
output wire [15:0] m_eth_type,
|
||||
output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
|
||||
output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
|
||||
output wire m_eth_payload_axis_tvalid,
|
||||
input wire m_eth_payload_axis_tready,
|
||||
output wire m_eth_payload_axis_tlast,
|
||||
output wire m_eth_payload_axis_tuser,
|
||||
|
||||
/*
|
||||
* Status signals
|
||||
*/
|
||||
output wire busy
|
||||
output wire busy
|
||||
);
|
||||
|
||||
parameter CYCLE_COUNT = (28+KEEP_WIDTH-1)/KEEP_WIDTH;
|
||||
|
||||
parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
|
||||
|
||||
parameter OFFSET = 28 % KEEP_WIDTH;
|
||||
|
||||
// bus width assertions
|
||||
initial begin
|
||||
if (KEEP_WIDTH * 8 != DATA_WIDTH) begin
|
||||
$error("Error: AXI stream interface requires byte (8-bit) granularity (instance %m)");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
/*
|
||||
|
||||
ARP Frame
|
||||
@ -93,16 +117,11 @@ transmits the complete Ethernet payload on an AXI interface.
|
||||
|
||||
*/
|
||||
|
||||
localparam [1:0]
|
||||
STATE_IDLE = 2'd0,
|
||||
STATE_WRITE_HEADER = 2'd1;
|
||||
|
||||
reg [1:0] state_reg = STATE_IDLE, state_next;
|
||||
|
||||
// datapath control signals
|
||||
reg store_frame;
|
||||
|
||||
reg [7:0] frame_ptr_reg = 8'd0, frame_ptr_next;
|
||||
reg send_arp_header_reg = 1'b0, send_arp_header_next;
|
||||
reg [PTR_WIDTH-1:0] ptr_reg = 0, ptr_next;
|
||||
|
||||
reg [15:0] arp_htype_reg = 16'd0;
|
||||
reg [15:0] arp_ptype_reg = 16'd0;
|
||||
@ -122,12 +141,13 @@ reg [15:0] m_eth_type_reg = 16'd0;
|
||||
reg busy_reg = 1'b0;
|
||||
|
||||
// internal datapath
|
||||
reg [7:0] m_eth_payload_axis_tdata_int;
|
||||
reg m_eth_payload_axis_tvalid_int;
|
||||
reg m_eth_payload_axis_tready_int_reg = 1'b0;
|
||||
reg m_eth_payload_axis_tlast_int;
|
||||
reg m_eth_payload_axis_tuser_int;
|
||||
wire m_eth_payload_axis_tready_int_early;
|
||||
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
|
||||
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
|
||||
reg m_eth_payload_axis_tvalid_int;
|
||||
reg m_eth_payload_axis_tready_int_reg = 1'b0;
|
||||
reg m_eth_payload_axis_tlast_int;
|
||||
reg m_eth_payload_axis_tuser_int;
|
||||
wire m_eth_payload_axis_tready_int_early;
|
||||
|
||||
assign s_frame_ready = s_frame_ready_reg;
|
||||
|
||||
@ -139,108 +159,94 @@ assign m_eth_type = m_eth_type_reg;
|
||||
assign busy = busy_reg;
|
||||
|
||||
always @* begin
|
||||
state_next = STATE_IDLE;
|
||||
send_arp_header_next = send_arp_header_reg;
|
||||
ptr_next = ptr_reg;
|
||||
|
||||
s_frame_ready_next = 1'b0;
|
||||
|
||||
store_frame = 1'b0;
|
||||
|
||||
frame_ptr_next = frame_ptr_reg;
|
||||
|
||||
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
|
||||
|
||||
m_eth_payload_axis_tdata_int = 8'd0;
|
||||
m_eth_payload_axis_tdata_int = {DATA_WIDTH{1'b0}};
|
||||
m_eth_payload_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
|
||||
m_eth_payload_axis_tvalid_int = 1'b0;
|
||||
m_eth_payload_axis_tlast_int = 1'b0;
|
||||
m_eth_payload_axis_tuser_int = 1'b0;
|
||||
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
// idle state - wait for data
|
||||
frame_ptr_next = 8'd0;
|
||||
s_frame_ready_next = !m_eth_hdr_valid_next;
|
||||
if (s_frame_ready && s_frame_valid) begin
|
||||
store_frame = 1'b1;
|
||||
m_eth_hdr_valid_next = 1'b1;
|
||||
ptr_next = 0;
|
||||
send_arp_header_next = 1'b1;
|
||||
end
|
||||
|
||||
if (s_frame_ready && s_frame_valid) begin
|
||||
store_frame = 1'b1;
|
||||
s_frame_ready_next = 1'b0;
|
||||
m_eth_hdr_valid_next = 1'b1;
|
||||
if (m_eth_payload_axis_tready_int_reg) begin
|
||||
m_eth_payload_axis_tvalid_int = 1'b1;
|
||||
m_eth_payload_axis_tdata_int = s_arp_htype[15: 8];
|
||||
frame_ptr_next = 8'd1;
|
||||
if (m_eth_payload_axis_tready_int_reg) begin
|
||||
if (send_arp_header_reg) begin
|
||||
ptr_next = ptr_reg + 1;
|
||||
|
||||
m_eth_payload_axis_tdata_int = {DATA_WIDTH{1'b0}};
|
||||
m_eth_payload_axis_tkeep_int = {KEEP_WIDTH{1'b0}};
|
||||
m_eth_payload_axis_tvalid_int = 1'b1;
|
||||
m_eth_payload_axis_tlast_int = 1'b0;
|
||||
m_eth_payload_axis_tuser_int = 1'b0;
|
||||
|
||||
`define _HEADER_FIELD_(offset, field) \
|
||||
if (ptr_reg == offset/KEEP_WIDTH) begin \
|
||||
m_eth_payload_axis_tdata_int[(offset%KEEP_WIDTH)*8 +: 8] = field; \
|
||||
m_eth_payload_axis_tkeep_int[offset%KEEP_WIDTH] = 1'b1; \
|
||||
end
|
||||
state_next = STATE_WRITE_HEADER;
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
|
||||
`_HEADER_FIELD_(0, arp_htype_reg[1*8 +: 8])
|
||||
`_HEADER_FIELD_(1, arp_htype_reg[0*8 +: 8])
|
||||
`_HEADER_FIELD_(2, arp_ptype_reg[1*8 +: 8])
|
||||
`_HEADER_FIELD_(3, arp_ptype_reg[0*8 +: 8])
|
||||
`_HEADER_FIELD_(4, 8'd6)
|
||||
`_HEADER_FIELD_(5, 8'd4)
|
||||
`_HEADER_FIELD_(6, arp_oper_reg[1*8 +: 8])
|
||||
`_HEADER_FIELD_(7, arp_oper_reg[0*8 +: 8])
|
||||
`_HEADER_FIELD_(8, arp_sha_reg[5*8 +: 8])
|
||||
`_HEADER_FIELD_(9, arp_sha_reg[4*8 +: 8])
|
||||
`_HEADER_FIELD_(10, arp_sha_reg[3*8 +: 8])
|
||||
`_HEADER_FIELD_(11, arp_sha_reg[2*8 +: 8])
|
||||
`_HEADER_FIELD_(12, arp_sha_reg[1*8 +: 8])
|
||||
`_HEADER_FIELD_(13, arp_sha_reg[0*8 +: 8])
|
||||
`_HEADER_FIELD_(14, arp_spa_reg[3*8 +: 8])
|
||||
`_HEADER_FIELD_(15, arp_spa_reg[2*8 +: 8])
|
||||
`_HEADER_FIELD_(16, arp_spa_reg[1*8 +: 8])
|
||||
`_HEADER_FIELD_(17, arp_spa_reg[0*8 +: 8])
|
||||
`_HEADER_FIELD_(18, arp_tha_reg[5*8 +: 8])
|
||||
`_HEADER_FIELD_(19, arp_tha_reg[4*8 +: 8])
|
||||
`_HEADER_FIELD_(20, arp_tha_reg[3*8 +: 8])
|
||||
`_HEADER_FIELD_(21, arp_tha_reg[2*8 +: 8])
|
||||
`_HEADER_FIELD_(22, arp_tha_reg[1*8 +: 8])
|
||||
`_HEADER_FIELD_(23, arp_tha_reg[0*8 +: 8])
|
||||
`_HEADER_FIELD_(24, arp_tpa_reg[3*8 +: 8])
|
||||
`_HEADER_FIELD_(25, arp_tpa_reg[2*8 +: 8])
|
||||
`_HEADER_FIELD_(26, arp_tpa_reg[1*8 +: 8])
|
||||
`_HEADER_FIELD_(27, arp_tpa_reg[0*8 +: 8])
|
||||
|
||||
if (ptr_reg == 27/KEEP_WIDTH) begin
|
||||
m_eth_payload_axis_tlast_int = 1'b1;
|
||||
send_arp_header_next = 1'b0;
|
||||
end
|
||||
|
||||
`undef _HEADER_FIELD_
|
||||
end
|
||||
STATE_WRITE_HEADER: begin
|
||||
// read header state
|
||||
if (m_eth_payload_axis_tready_int_reg) begin
|
||||
// word transfer out
|
||||
frame_ptr_next = frame_ptr_reg + 8'd1;
|
||||
m_eth_payload_axis_tvalid_int = 1'b1;
|
||||
state_next = STATE_WRITE_HEADER;
|
||||
case (frame_ptr_reg)
|
||||
8'h00: m_eth_payload_axis_tdata_int = arp_htype_reg[15: 8];
|
||||
8'h01: m_eth_payload_axis_tdata_int = arp_htype_reg[ 7: 0];
|
||||
8'h02: m_eth_payload_axis_tdata_int = arp_ptype_reg[15: 8];
|
||||
8'h03: m_eth_payload_axis_tdata_int = arp_ptype_reg[ 7: 0];
|
||||
8'h04: m_eth_payload_axis_tdata_int = 8'd6; // hlen
|
||||
8'h05: m_eth_payload_axis_tdata_int = 8'd4; // plen
|
||||
8'h06: m_eth_payload_axis_tdata_int = arp_oper_reg[15: 8];
|
||||
8'h07: m_eth_payload_axis_tdata_int = arp_oper_reg[ 7: 0];
|
||||
8'h08: m_eth_payload_axis_tdata_int = arp_sha_reg[47:40];
|
||||
8'h09: m_eth_payload_axis_tdata_int = arp_sha_reg[39:32];
|
||||
8'h0A: m_eth_payload_axis_tdata_int = arp_sha_reg[31:24];
|
||||
8'h0B: m_eth_payload_axis_tdata_int = arp_sha_reg[23:16];
|
||||
8'h0C: m_eth_payload_axis_tdata_int = arp_sha_reg[15: 8];
|
||||
8'h0D: m_eth_payload_axis_tdata_int = arp_sha_reg[ 7: 0];
|
||||
8'h0E: m_eth_payload_axis_tdata_int = arp_spa_reg[31:24];
|
||||
8'h0F: m_eth_payload_axis_tdata_int = arp_spa_reg[23:16];
|
||||
8'h10: m_eth_payload_axis_tdata_int = arp_spa_reg[15: 8];
|
||||
8'h11: m_eth_payload_axis_tdata_int = arp_spa_reg[ 7: 0];
|
||||
8'h12: m_eth_payload_axis_tdata_int = arp_tha_reg[47:40];
|
||||
8'h13: m_eth_payload_axis_tdata_int = arp_tha_reg[39:32];
|
||||
8'h14: m_eth_payload_axis_tdata_int = arp_tha_reg[31:24];
|
||||
8'h15: m_eth_payload_axis_tdata_int = arp_tha_reg[23:16];
|
||||
8'h16: m_eth_payload_axis_tdata_int = arp_tha_reg[15: 8];
|
||||
8'h17: m_eth_payload_axis_tdata_int = arp_tha_reg[ 7: 0];
|
||||
8'h18: m_eth_payload_axis_tdata_int = arp_tpa_reg[31:24];
|
||||
8'h19: m_eth_payload_axis_tdata_int = arp_tpa_reg[23:16];
|
||||
8'h1A: m_eth_payload_axis_tdata_int = arp_tpa_reg[15: 8];
|
||||
8'h1B: begin
|
||||
m_eth_payload_axis_tdata_int = arp_tpa_reg[ 7: 0];
|
||||
m_eth_payload_axis_tlast_int = 1'b1;
|
||||
s_frame_ready_next = !m_eth_hdr_valid_next;
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
state_next = STATE_WRITE_HEADER;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
s_frame_ready_next = !m_eth_hdr_valid_next && !send_arp_header_next;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
frame_ptr_reg <= 8'd0;
|
||||
s_frame_ready_reg <= 1'b0;
|
||||
m_eth_hdr_valid_reg <= 1'b0;
|
||||
busy_reg <= 1'b0;
|
||||
end else begin
|
||||
state_reg <= state_next;
|
||||
send_arp_header_reg <= send_arp_header_next;
|
||||
ptr_reg <= ptr_next;
|
||||
|
||||
frame_ptr_reg <= frame_ptr_next;
|
||||
s_frame_ready_reg <= s_frame_ready_next;
|
||||
|
||||
s_frame_ready_reg <= s_frame_ready_next;
|
||||
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
|
||||
|
||||
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
|
||||
|
||||
busy_reg <= state_next != STATE_IDLE;
|
||||
end
|
||||
busy_reg <= send_arp_header_next;
|
||||
|
||||
if (store_frame) begin
|
||||
m_eth_dest_mac_reg <= s_eth_dest_mac;
|
||||
@ -254,18 +260,28 @@ always @(posedge clk) begin
|
||||
arp_tha_reg <= s_arp_tha;
|
||||
arp_tpa_reg <= s_arp_tpa;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
send_arp_header_reg <= 1'b0;
|
||||
ptr_reg <= 0;
|
||||
s_frame_ready_reg <= 1'b0;
|
||||
m_eth_hdr_valid_reg <= 1'b0;
|
||||
busy_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
reg [7:0] m_eth_payload_axis_tdata_reg = 8'd0;
|
||||
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
|
||||
reg m_eth_payload_axis_tlast_reg = 1'b0;
|
||||
reg m_eth_payload_axis_tuser_reg = 1'b0;
|
||||
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
|
||||
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
|
||||
reg m_eth_payload_axis_tlast_reg = 1'b0;
|
||||
reg m_eth_payload_axis_tuser_reg = 1'b0;
|
||||
|
||||
reg [7:0] temp_m_eth_payload_axis_tdata_reg = 8'd0;
|
||||
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
|
||||
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
|
||||
reg temp_m_eth_payload_axis_tuser_reg = 1'b0;
|
||||
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
|
||||
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
|
||||
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
|
||||
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
|
||||
reg temp_m_eth_payload_axis_tuser_reg = 1'b0;
|
||||
|
||||
// datapath control
|
||||
reg store_eth_payload_int_to_output;
|
||||
@ -273,6 +289,7 @@ reg store_eth_payload_int_to_temp;
|
||||
reg store_eth_payload_axis_temp_to_output;
|
||||
|
||||
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
|
||||
assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
|
||||
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
|
||||
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
|
||||
assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
|
||||
@ -288,7 +305,7 @@ always @* begin
|
||||
store_eth_payload_int_to_output = 1'b0;
|
||||
store_eth_payload_int_to_temp = 1'b0;
|
||||
store_eth_payload_axis_temp_to_output = 1'b0;
|
||||
|
||||
|
||||
if (m_eth_payload_axis_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin
|
||||
@ -322,16 +339,19 @@ always @(posedge clk) begin
|
||||
// datapath
|
||||
if (store_eth_payload_int_to_output) begin
|
||||
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
|
||||
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
|
||||
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
|
||||
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
|
||||
end else if (store_eth_payload_axis_temp_to_output) begin
|
||||
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
|
||||
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
|
||||
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
|
||||
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_eth_payload_int_to_temp) begin
|
||||
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
|
||||
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
|
||||
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
|
||||
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
|
||||
end
|
||||
|
@ -1,371 +0,0 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* ARP ethernet frame transmitter (ARP frame in, Ethernet frame out, 64 bit datapath)
|
||||
*/
|
||||
module arp_eth_tx_64
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* ARP frame input
|
||||
*/
|
||||
input wire s_frame_valid,
|
||||
output wire s_frame_ready,
|
||||
input wire [47:0] s_eth_dest_mac,
|
||||
input wire [47:0] s_eth_src_mac,
|
||||
input wire [15:0] s_eth_type,
|
||||
input wire [15:0] s_arp_htype,
|
||||
input wire [15:0] s_arp_ptype,
|
||||
input wire [15:0] s_arp_oper,
|
||||
input wire [47:0] s_arp_sha,
|
||||
input wire [31:0] s_arp_spa,
|
||||
input wire [47:0] s_arp_tha,
|
||||
input wire [31:0] s_arp_tpa,
|
||||
|
||||
/*
|
||||
* Ethernet frame output
|
||||
*/
|
||||
output wire m_eth_hdr_valid,
|
||||
input wire m_eth_hdr_ready,
|
||||
output wire [47:0] m_eth_dest_mac,
|
||||
output wire [47:0] m_eth_src_mac,
|
||||
output wire [15:0] m_eth_type,
|
||||
output wire [63:0] m_eth_payload_axis_tdata,
|
||||
output wire [7:0] m_eth_payload_axis_tkeep,
|
||||
output wire m_eth_payload_axis_tvalid,
|
||||
input wire m_eth_payload_axis_tready,
|
||||
output wire m_eth_payload_axis_tlast,
|
||||
output wire m_eth_payload_axis_tuser,
|
||||
|
||||
/*
|
||||
* Status signals
|
||||
*/
|
||||
output wire busy
|
||||
);
|
||||
|
||||
/*
|
||||
|
||||
ARP Frame
|
||||
|
||||
Field Length
|
||||
Destination MAC address 6 octets
|
||||
Source MAC address 6 octets
|
||||
Ethertype (0x0806) 2 octets
|
||||
HTYPE (1) 2 octets
|
||||
PTYPE (0x0800) 2 octets
|
||||
HLEN (6) 1 octets
|
||||
PLEN (4) 1 octets
|
||||
OPER 2 octets
|
||||
SHA Sender MAC 6 octets
|
||||
SPA Sender IP 4 octets
|
||||
THA Target MAC 6 octets
|
||||
TPA Target IP 4 octets
|
||||
|
||||
This module receives an ARP frame with header fields in parallel and
|
||||
transmits the complete Ethernet payload on an AXI interface.
|
||||
|
||||
*/
|
||||
|
||||
localparam [1:0]
|
||||
STATE_IDLE = 2'd0,
|
||||
STATE_WRITE_HEADER = 2'd1;
|
||||
|
||||
reg [1:0] state_reg = STATE_IDLE, state_next;
|
||||
|
||||
// datapath control signals
|
||||
reg store_frame;
|
||||
|
||||
reg [7:0] frame_ptr_reg = 8'd0, frame_ptr_next;
|
||||
|
||||
reg [15:0] arp_htype_reg = 16'd0;
|
||||
reg [15:0] arp_ptype_reg = 16'd0;
|
||||
reg [15:0] arp_oper_reg = 16'd0;
|
||||
reg [47:0] arp_sha_reg = 48'd0;
|
||||
reg [31:0] arp_spa_reg = 32'd0;
|
||||
reg [47:0] arp_tha_reg = 48'd0;
|
||||
reg [31:0] arp_tpa_reg = 32'd0;
|
||||
|
||||
reg s_frame_ready_reg = 1'b0, s_frame_ready_next;
|
||||
|
||||
reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next;
|
||||
reg [47:0] m_eth_dest_mac_reg = 48'd0;
|
||||
reg [47:0] m_eth_src_mac_reg = 48'd0;
|
||||
reg [15:0] m_eth_type_reg = 16'd0;
|
||||
|
||||
reg busy_reg = 1'b0;
|
||||
|
||||
// internal datapath
|
||||
reg [63:0] m_eth_payload_axis_tdata_int;
|
||||
reg [7:0] m_eth_payload_axis_tkeep_int;
|
||||
reg m_eth_payload_axis_tvalid_int;
|
||||
reg m_eth_payload_axis_tready_int_reg = 1'b0;
|
||||
reg m_eth_payload_axis_tlast_int;
|
||||
reg m_eth_payload_axis_tuser_int;
|
||||
wire m_eth_payload_axis_tready_int_early;
|
||||
|
||||
assign s_frame_ready = s_frame_ready_reg;
|
||||
|
||||
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
|
||||
assign m_eth_dest_mac = m_eth_dest_mac_reg;
|
||||
assign m_eth_src_mac = m_eth_src_mac_reg;
|
||||
assign m_eth_type = m_eth_type_reg;
|
||||
|
||||
assign busy = busy_reg;
|
||||
|
||||
always @* begin
|
||||
state_next = STATE_IDLE;
|
||||
|
||||
s_frame_ready_next = 1'b0;
|
||||
|
||||
store_frame = 1'b0;
|
||||
|
||||
frame_ptr_next = frame_ptr_reg;
|
||||
|
||||
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
|
||||
|
||||
m_eth_payload_axis_tdata_int = 64'd0;
|
||||
m_eth_payload_axis_tkeep_int = 8'd0;
|
||||
m_eth_payload_axis_tvalid_int = 1'b0;
|
||||
m_eth_payload_axis_tlast_int = 1'b0;
|
||||
m_eth_payload_axis_tuser_int = 1'b0;
|
||||
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
// idle state - wait for data
|
||||
frame_ptr_next = 8'd0;
|
||||
s_frame_ready_next = !m_eth_hdr_valid_next;
|
||||
|
||||
if (s_frame_ready && s_frame_valid) begin
|
||||
store_frame = 1'b1;
|
||||
s_frame_ready_next = 1'b0;
|
||||
m_eth_hdr_valid_next = 1'b1;
|
||||
if (m_eth_payload_axis_tready_int_reg) begin
|
||||
m_eth_payload_axis_tvalid_int = 1'b1;
|
||||
m_eth_payload_axis_tdata_int[ 7: 0] = s_arp_htype[15: 8];
|
||||
m_eth_payload_axis_tdata_int[15: 8] = s_arp_htype[ 7: 0];
|
||||
m_eth_payload_axis_tdata_int[23:16] = s_arp_ptype[15: 8];
|
||||
m_eth_payload_axis_tdata_int[31:24] = s_arp_ptype[ 7: 0];
|
||||
m_eth_payload_axis_tdata_int[39:32] = 8'd6; // hlen
|
||||
m_eth_payload_axis_tdata_int[47:40] = 8'd4; // plen
|
||||
m_eth_payload_axis_tdata_int[55:48] = s_arp_oper[15: 8];
|
||||
m_eth_payload_axis_tdata_int[63:56] = s_arp_oper[ 7: 0];
|
||||
m_eth_payload_axis_tkeep_int = 8'hff;
|
||||
frame_ptr_next = 8'd8;
|
||||
end
|
||||
state_next = STATE_WRITE_HEADER;
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end
|
||||
STATE_WRITE_HEADER: begin
|
||||
// read header state
|
||||
if (m_eth_payload_axis_tready_int_reg) begin
|
||||
// word transfer out
|
||||
frame_ptr_next = frame_ptr_reg + 8'd8;
|
||||
m_eth_payload_axis_tvalid_int = 1'b1;
|
||||
state_next = STATE_WRITE_HEADER;
|
||||
case (frame_ptr_reg)
|
||||
8'h00: begin
|
||||
m_eth_payload_axis_tdata_int[ 7: 0] = arp_htype_reg[15: 8];
|
||||
m_eth_payload_axis_tdata_int[15: 8] = arp_htype_reg[ 7: 0];
|
||||
m_eth_payload_axis_tdata_int[23:16] = arp_ptype_reg[15: 8];
|
||||
m_eth_payload_axis_tdata_int[31:24] = arp_ptype_reg[ 7: 0];
|
||||
m_eth_payload_axis_tdata_int[39:32] = 8'd6; // hlen
|
||||
m_eth_payload_axis_tdata_int[47:40] = 8'd4; // plen
|
||||
m_eth_payload_axis_tdata_int[55:48] = arp_oper_reg[15: 8];
|
||||
m_eth_payload_axis_tdata_int[63:56] = arp_oper_reg[ 7: 0];
|
||||
m_eth_payload_axis_tkeep_int = 8'hff;
|
||||
end
|
||||
8'h08: begin
|
||||
m_eth_payload_axis_tdata_int[ 7: 0] = arp_sha_reg[47:40];
|
||||
m_eth_payload_axis_tdata_int[15: 8] = arp_sha_reg[39:32];
|
||||
m_eth_payload_axis_tdata_int[23:16] = arp_sha_reg[31:24];
|
||||
m_eth_payload_axis_tdata_int[31:24] = arp_sha_reg[23:16];
|
||||
m_eth_payload_axis_tdata_int[39:32] = arp_sha_reg[15: 8];
|
||||
m_eth_payload_axis_tdata_int[47:40] = arp_sha_reg[ 7: 0];
|
||||
m_eth_payload_axis_tdata_int[55:48] = arp_spa_reg[31:24];
|
||||
m_eth_payload_axis_tdata_int[63:56] = arp_spa_reg[23:16];
|
||||
m_eth_payload_axis_tkeep_int = 8'hff;
|
||||
end
|
||||
8'h10: begin
|
||||
m_eth_payload_axis_tdata_int[ 7: 0] = arp_spa_reg[15: 8];
|
||||
m_eth_payload_axis_tdata_int[15: 8] = arp_spa_reg[ 7: 0];
|
||||
m_eth_payload_axis_tdata_int[23:16] = arp_tha_reg[47:40];
|
||||
m_eth_payload_axis_tdata_int[31:24] = arp_tha_reg[39:32];
|
||||
m_eth_payload_axis_tdata_int[39:32] = arp_tha_reg[31:24];
|
||||
m_eth_payload_axis_tdata_int[47:40] = arp_tha_reg[23:16];
|
||||
m_eth_payload_axis_tdata_int[55:48] = arp_tha_reg[15: 8];
|
||||
m_eth_payload_axis_tdata_int[63:56] = arp_tha_reg[ 7: 0];
|
||||
m_eth_payload_axis_tkeep_int = 8'hff;
|
||||
end
|
||||
8'h18: begin
|
||||
m_eth_payload_axis_tdata_int[ 7: 0] = arp_tpa_reg[31:24];
|
||||
m_eth_payload_axis_tdata_int[15: 8] = arp_tpa_reg[23:16];
|
||||
m_eth_payload_axis_tdata_int[23:16] = arp_tpa_reg[15: 8];
|
||||
m_eth_payload_axis_tdata_int[31:24] = arp_tpa_reg[ 7: 0];
|
||||
m_eth_payload_axis_tdata_int[39:32] = 0;
|
||||
m_eth_payload_axis_tdata_int[47:40] = 0;
|
||||
m_eth_payload_axis_tdata_int[55:48] = 0;
|
||||
m_eth_payload_axis_tdata_int[63:56] = 0;
|
||||
m_eth_payload_axis_tkeep_int = 8'h0f;
|
||||
m_eth_payload_axis_tlast_int = 1'b1;
|
||||
s_frame_ready_next = !m_eth_hdr_valid_next;
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
endcase
|
||||
end else begin
|
||||
state_next = STATE_WRITE_HEADER;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
frame_ptr_reg <= 8'd0;
|
||||
s_frame_ready_reg <= 1'b0;
|
||||
m_eth_hdr_valid_reg <= 1'b0;
|
||||
busy_reg <= 1'b0;
|
||||
end else begin
|
||||
state_reg <= state_next;
|
||||
|
||||
frame_ptr_reg <= frame_ptr_next;
|
||||
|
||||
s_frame_ready_reg <= s_frame_ready_next;
|
||||
|
||||
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
|
||||
|
||||
busy_reg <= state_next != STATE_IDLE;
|
||||
end
|
||||
|
||||
if (store_frame) begin
|
||||
m_eth_dest_mac_reg <= s_eth_dest_mac;
|
||||
m_eth_src_mac_reg <= s_eth_src_mac;
|
||||
m_eth_type_reg <= s_eth_type;
|
||||
arp_htype_reg <= s_arp_htype;
|
||||
arp_ptype_reg <= s_arp_ptype;
|
||||
arp_oper_reg <= s_arp_oper;
|
||||
arp_sha_reg <= s_arp_sha;
|
||||
arp_spa_reg <= s_arp_spa;
|
||||
arp_tha_reg <= s_arp_tha;
|
||||
arp_tpa_reg <= s_arp_tpa;
|
||||
end
|
||||
end
|
||||
|
||||
// output datapath logic
|
||||
reg [63:0] m_eth_payload_axis_tdata_reg = 64'd0;
|
||||
reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0;
|
||||
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
|
||||
reg m_eth_payload_axis_tlast_reg = 1'b0;
|
||||
reg m_eth_payload_axis_tuser_reg = 1'b0;
|
||||
|
||||
reg [63:0] temp_m_eth_payload_axis_tdata_reg = 64'd0;
|
||||
reg [7:0] temp_m_eth_payload_axis_tkeep_reg = 8'd0;
|
||||
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
|
||||
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
|
||||
reg temp_m_eth_payload_axis_tuser_reg = 1'b0;
|
||||
|
||||
// datapath control
|
||||
reg store_eth_payload_int_to_output;
|
||||
reg store_eth_payload_int_to_temp;
|
||||
reg store_eth_payload_axis_temp_to_output;
|
||||
|
||||
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
|
||||
assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
|
||||
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
|
||||
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
|
||||
assign m_eth_payload_axis_tuser = m_eth_payload_axis_tuser_reg;
|
||||
|
||||
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
|
||||
assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
|
||||
|
||||
always @* begin
|
||||
// transfer sink ready state to source
|
||||
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
|
||||
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
|
||||
|
||||
store_eth_payload_int_to_output = 1'b0;
|
||||
store_eth_payload_int_to_temp = 1'b0;
|
||||
store_eth_payload_axis_temp_to_output = 1'b0;
|
||||
|
||||
if (m_eth_payload_axis_tready_int_reg) begin
|
||||
// input is ready
|
||||
if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin
|
||||
// output is ready or currently not valid, transfer data to output
|
||||
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
|
||||
store_eth_payload_int_to_output = 1'b1;
|
||||
end else begin
|
||||
// output is not ready, store input in temp
|
||||
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
|
||||
store_eth_payload_int_to_temp = 1'b1;
|
||||
end
|
||||
end else if (m_eth_payload_axis_tready) begin
|
||||
// input is not ready, but output is ready
|
||||
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
|
||||
temp_m_eth_payload_axis_tvalid_next = 1'b0;
|
||||
store_eth_payload_axis_temp_to_output = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
m_eth_payload_axis_tvalid_reg <= 1'b0;
|
||||
m_eth_payload_axis_tready_int_reg <= 1'b0;
|
||||
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
|
||||
end else begin
|
||||
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
|
||||
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
|
||||
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
|
||||
end
|
||||
|
||||
// datapath
|
||||
if (store_eth_payload_int_to_output) begin
|
||||
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
|
||||
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
|
||||
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
|
||||
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
|
||||
end else if (store_eth_payload_axis_temp_to_output) begin
|
||||
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
|
||||
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
|
||||
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
|
||||
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
|
||||
end
|
||||
|
||||
if (store_eth_payload_int_to_temp) begin
|
||||
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
|
||||
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
|
||||
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
|
||||
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
@ -404,7 +404,10 @@ ip_inst (
|
||||
/*
|
||||
* ARP module
|
||||
*/
|
||||
arp_64 #(
|
||||
arp #(
|
||||
.DATA_WIDTH(64),
|
||||
.KEEP_ENABLE(1),
|
||||
.KEEP_WIDTH(8),
|
||||
.CACHE_ADDR_WIDTH(ARP_CACHE_ADDR_WIDTH),
|
||||
.REQUEST_RETRY_COUNT(ARP_REQUEST_RETRY_COUNT),
|
||||
.REQUEST_RETRY_INTERVAL(ARP_REQUEST_RETRY_INTERVAL),
|
||||
|
@ -48,6 +48,15 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
DATA_WIDTH = 8
|
||||
KEEP_ENABLE = (DATA_WIDTH>8)
|
||||
KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
CACHE_ADDR_WIDTH = 2
|
||||
REQUEST_RETRY_COUNT = 4
|
||||
REQUEST_RETRY_INTERVAL = 150
|
||||
REQUEST_TIMEOUT = 400
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
@ -57,7 +66,8 @@ def bench():
|
||||
s_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
s_eth_src_mac = Signal(intbv(0)[48:])
|
||||
s_eth_type = Signal(intbv(0)[16:])
|
||||
s_eth_payload_axis_tdata = Signal(intbv(0)[8:])
|
||||
s_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
s_eth_payload_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
s_eth_payload_axis_tvalid = Signal(bool(0))
|
||||
s_eth_payload_axis_tlast = Signal(bool(0))
|
||||
s_eth_payload_axis_tuser = Signal(bool(0))
|
||||
@ -83,7 +93,8 @@ def bench():
|
||||
m_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
m_eth_src_mac = Signal(intbv(0)[48:])
|
||||
m_eth_type = Signal(intbv(0)[16:])
|
||||
m_eth_payload_axis_tdata = Signal(intbv(0)[8:])
|
||||
m_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
m_eth_payload_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
m_eth_payload_axis_tvalid = Signal(bool(0))
|
||||
m_eth_payload_axis_tlast = Signal(bool(0))
|
||||
m_eth_payload_axis_tuser = Signal(bool(0))
|
||||
@ -108,6 +119,7 @@ def bench():
|
||||
eth_src_mac=s_eth_src_mac,
|
||||
eth_type=s_eth_type,
|
||||
eth_payload_tdata=s_eth_payload_axis_tdata,
|
||||
eth_payload_tkeep=s_eth_payload_axis_tkeep,
|
||||
eth_payload_tvalid=s_eth_payload_axis_tvalid,
|
||||
eth_payload_tready=s_eth_payload_axis_tready,
|
||||
eth_payload_tlast=s_eth_payload_axis_tlast,
|
||||
@ -127,6 +139,7 @@ def bench():
|
||||
eth_src_mac=m_eth_src_mac,
|
||||
eth_type=m_eth_type,
|
||||
eth_payload_tdata=m_eth_payload_axis_tdata,
|
||||
eth_payload_tkeep=m_eth_payload_axis_tkeep,
|
||||
eth_payload_tvalid=m_eth_payload_axis_tvalid,
|
||||
eth_payload_tready=m_eth_payload_axis_tready,
|
||||
eth_payload_tlast=m_eth_payload_axis_tlast,
|
||||
@ -173,6 +186,7 @@ def bench():
|
||||
s_eth_src_mac=s_eth_src_mac,
|
||||
s_eth_type=s_eth_type,
|
||||
s_eth_payload_axis_tdata=s_eth_payload_axis_tdata,
|
||||
s_eth_payload_axis_tkeep=s_eth_payload_axis_tkeep,
|
||||
s_eth_payload_axis_tvalid=s_eth_payload_axis_tvalid,
|
||||
s_eth_payload_axis_tready=s_eth_payload_axis_tready,
|
||||
s_eth_payload_axis_tlast=s_eth_payload_axis_tlast,
|
||||
@ -184,6 +198,7 @@ def bench():
|
||||
m_eth_src_mac=m_eth_src_mac,
|
||||
m_eth_type=m_eth_type,
|
||||
m_eth_payload_axis_tdata=m_eth_payload_axis_tdata,
|
||||
m_eth_payload_axis_tkeep=m_eth_payload_axis_tkeep,
|
||||
m_eth_payload_axis_tvalid=m_eth_payload_axis_tvalid,
|
||||
m_eth_payload_axis_tready=m_eth_payload_axis_tready,
|
||||
m_eth_payload_axis_tlast=m_eth_payload_axis_tlast,
|
||||
|
@ -31,6 +31,15 @@ THE SOFTWARE.
|
||||
*/
|
||||
module test_arp;
|
||||
|
||||
// Parameters
|
||||
parameter DATA_WIDTH = 8;
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8);
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8);
|
||||
parameter CACHE_ADDR_WIDTH = 2;
|
||||
parameter REQUEST_RETRY_COUNT = 4;
|
||||
parameter REQUEST_RETRY_INTERVAL = 150;
|
||||
parameter REQUEST_TIMEOUT = 400;
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
@ -40,7 +49,8 @@ reg s_eth_hdr_valid = 0;
|
||||
reg [47:0] s_eth_dest_mac = 0;
|
||||
reg [47:0] s_eth_src_mac = 0;
|
||||
reg [15:0] s_eth_type = 0;
|
||||
reg [7:0] s_eth_payload_axis_tdata = 0;
|
||||
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
|
||||
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
|
||||
reg s_eth_payload_axis_tvalid = 0;
|
||||
reg s_eth_payload_axis_tlast = 0;
|
||||
reg s_eth_payload_axis_tuser = 0;
|
||||
@ -66,7 +76,8 @@ wire m_eth_hdr_valid;
|
||||
wire [47:0] m_eth_dest_mac;
|
||||
wire [47:0] m_eth_src_mac;
|
||||
wire [15:0] m_eth_type;
|
||||
wire [7:0] m_eth_payload_axis_tdata;
|
||||
wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
|
||||
wire m_eth_payload_axis_tvalid;
|
||||
wire m_eth_payload_axis_tlast;
|
||||
wire m_eth_payload_axis_tuser;
|
||||
@ -87,6 +98,7 @@ initial begin
|
||||
s_eth_src_mac,
|
||||
s_eth_type,
|
||||
s_eth_payload_axis_tdata,
|
||||
s_eth_payload_axis_tkeep,
|
||||
s_eth_payload_axis_tvalid,
|
||||
s_eth_payload_axis_tlast,
|
||||
s_eth_payload_axis_tuser,
|
||||
@ -109,6 +121,7 @@ initial begin
|
||||
m_eth_src_mac,
|
||||
m_eth_type,
|
||||
m_eth_payload_axis_tdata,
|
||||
m_eth_payload_axis_tkeep,
|
||||
m_eth_payload_axis_tvalid,
|
||||
m_eth_payload_axis_tlast,
|
||||
m_eth_payload_axis_tuser,
|
||||
@ -124,10 +137,13 @@ initial begin
|
||||
end
|
||||
|
||||
arp #(
|
||||
.CACHE_ADDR_WIDTH(2),
|
||||
.REQUEST_RETRY_COUNT(4),
|
||||
.REQUEST_RETRY_INTERVAL(150),
|
||||
.REQUEST_TIMEOUT(400)
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_ENABLE(KEEP_ENABLE),
|
||||
.KEEP_WIDTH(KEEP_WIDTH),
|
||||
.CACHE_ADDR_WIDTH(CACHE_ADDR_WIDTH),
|
||||
.REQUEST_RETRY_COUNT(REQUEST_RETRY_COUNT),
|
||||
.REQUEST_RETRY_INTERVAL(REQUEST_RETRY_INTERVAL),
|
||||
.REQUEST_TIMEOUT(REQUEST_TIMEOUT)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
@ -139,6 +155,7 @@ UUT (
|
||||
.s_eth_src_mac(s_eth_src_mac),
|
||||
.s_eth_type(s_eth_type),
|
||||
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
|
||||
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
|
||||
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
|
||||
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
|
||||
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
|
||||
@ -150,6 +167,7 @@ UUT (
|
||||
.m_eth_src_mac(m_eth_src_mac),
|
||||
.m_eth_type(m_eth_type),
|
||||
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
|
||||
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
|
||||
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
|
||||
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
|
||||
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
|
||||
|
@ -30,16 +30,16 @@ import axis_ep
|
||||
import eth_ep
|
||||
import arp_ep
|
||||
|
||||
module = 'arp_64'
|
||||
testbench = 'test_%s' % module
|
||||
module = 'arp'
|
||||
testbench = 'test_%s_64' % module
|
||||
|
||||
srcs = []
|
||||
|
||||
srcs.append("../rtl/%s.v" % module)
|
||||
srcs.append("../rtl/lfsr.v")
|
||||
srcs.append("../rtl/arp_cache.v")
|
||||
srcs.append("../rtl/arp_eth_rx_64.v")
|
||||
srcs.append("../rtl/arp_eth_tx_64.v")
|
||||
srcs.append("../rtl/arp_eth_rx.v")
|
||||
srcs.append("../rtl/arp_eth_tx.v")
|
||||
srcs.append("%s.v" % testbench)
|
||||
|
||||
src = ' '.join(srcs)
|
||||
@ -48,6 +48,15 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
DATA_WIDTH = 64
|
||||
KEEP_ENABLE = (DATA_WIDTH>8)
|
||||
KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
CACHE_ADDR_WIDTH = 2
|
||||
REQUEST_RETRY_COUNT = 4
|
||||
REQUEST_RETRY_INTERVAL = 150
|
||||
REQUEST_TIMEOUT = 400
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
@ -57,8 +66,8 @@ def bench():
|
||||
s_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
s_eth_src_mac = Signal(intbv(0)[48:])
|
||||
s_eth_type = Signal(intbv(0)[16:])
|
||||
s_eth_payload_axis_tdata = Signal(intbv(0)[64:])
|
||||
s_eth_payload_axis_tkeep = Signal(intbv(0)[8:])
|
||||
s_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
s_eth_payload_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
s_eth_payload_axis_tvalid = Signal(bool(0))
|
||||
s_eth_payload_axis_tlast = Signal(bool(0))
|
||||
s_eth_payload_axis_tuser = Signal(bool(0))
|
||||
@ -84,8 +93,8 @@ def bench():
|
||||
m_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
m_eth_src_mac = Signal(intbv(0)[48:])
|
||||
m_eth_type = Signal(intbv(0)[16:])
|
||||
m_eth_payload_axis_tdata = Signal(intbv(0)[64:])
|
||||
m_eth_payload_axis_tkeep = Signal(intbv(0)[8:])
|
||||
m_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
m_eth_payload_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
m_eth_payload_axis_tvalid = Signal(bool(0))
|
||||
m_eth_payload_axis_tlast = Signal(bool(0))
|
||||
m_eth_payload_axis_tuser = Signal(bool(0))
|
||||
|
@ -27,10 +27,19 @@ THE SOFTWARE.
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for arp_64
|
||||
* Testbench for arp
|
||||
*/
|
||||
module test_arp_64;
|
||||
|
||||
// Parameters
|
||||
parameter DATA_WIDTH = 64;
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8);
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8);
|
||||
parameter CACHE_ADDR_WIDTH = 2;
|
||||
parameter REQUEST_RETRY_COUNT = 4;
|
||||
parameter REQUEST_RETRY_INTERVAL = 150;
|
||||
parameter REQUEST_TIMEOUT = 400;
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
@ -40,8 +49,8 @@ reg s_eth_hdr_valid = 0;
|
||||
reg [47:0] s_eth_dest_mac = 0;
|
||||
reg [47:0] s_eth_src_mac = 0;
|
||||
reg [15:0] s_eth_type = 0;
|
||||
reg [63:0] s_eth_payload_axis_tdata = 0;
|
||||
reg [7:0] s_eth_payload_axis_tkeep = 0;
|
||||
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
|
||||
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
|
||||
reg s_eth_payload_axis_tvalid = 0;
|
||||
reg s_eth_payload_axis_tlast = 0;
|
||||
reg s_eth_payload_axis_tuser = 0;
|
||||
@ -67,8 +76,8 @@ wire m_eth_hdr_valid;
|
||||
wire [47:0] m_eth_dest_mac;
|
||||
wire [47:0] m_eth_src_mac;
|
||||
wire [15:0] m_eth_type;
|
||||
wire [63:0] m_eth_payload_axis_tdata;
|
||||
wire [7:0] m_eth_payload_axis_tkeep;
|
||||
wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
|
||||
wire m_eth_payload_axis_tvalid;
|
||||
wire m_eth_payload_axis_tlast;
|
||||
wire m_eth_payload_axis_tuser;
|
||||
@ -127,11 +136,14 @@ initial begin
|
||||
$dumpvars(0, test_arp_64);
|
||||
end
|
||||
|
||||
arp_64 #(
|
||||
.CACHE_ADDR_WIDTH(2),
|
||||
.REQUEST_RETRY_COUNT(4),
|
||||
.REQUEST_RETRY_INTERVAL(150),
|
||||
.REQUEST_TIMEOUT(400)
|
||||
arp #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_ENABLE(KEEP_ENABLE),
|
||||
.KEEP_WIDTH(KEEP_WIDTH),
|
||||
.CACHE_ADDR_WIDTH(CACHE_ADDR_WIDTH),
|
||||
.REQUEST_RETRY_COUNT(REQUEST_RETRY_COUNT),
|
||||
.REQUEST_RETRY_INTERVAL(REQUEST_RETRY_INTERVAL),
|
||||
.REQUEST_TIMEOUT(REQUEST_TIMEOUT)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
|
@ -43,6 +43,11 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
DATA_WIDTH = 8
|
||||
KEEP_ENABLE = (DATA_WIDTH>8)
|
||||
KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
@ -52,7 +57,8 @@ def bench():
|
||||
s_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
s_eth_src_mac = Signal(intbv(0)[48:])
|
||||
s_eth_type = Signal(intbv(0)[16:])
|
||||
s_eth_payload_axis_tdata = Signal(intbv(0)[8:])
|
||||
s_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
s_eth_payload_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
s_eth_payload_axis_tvalid = Signal(bool(0))
|
||||
s_eth_payload_axis_tlast = Signal(bool(0))
|
||||
s_eth_payload_axis_tuser = Signal(bool(0))
|
||||
@ -93,6 +99,7 @@ def bench():
|
||||
eth_src_mac=s_eth_src_mac,
|
||||
eth_type=s_eth_type,
|
||||
eth_payload_tdata=s_eth_payload_axis_tdata,
|
||||
eth_payload_tkeep=s_eth_payload_axis_tkeep,
|
||||
eth_payload_tvalid=s_eth_payload_axis_tvalid,
|
||||
eth_payload_tready=s_eth_payload_axis_tready,
|
||||
eth_payload_tlast=s_eth_payload_axis_tlast,
|
||||
@ -140,6 +147,7 @@ def bench():
|
||||
s_eth_src_mac=s_eth_src_mac,
|
||||
s_eth_type=s_eth_type,
|
||||
s_eth_payload_axis_tdata=s_eth_payload_axis_tdata,
|
||||
s_eth_payload_axis_tkeep=s_eth_payload_axis_tkeep,
|
||||
s_eth_payload_axis_tvalid=s_eth_payload_axis_tvalid,
|
||||
s_eth_payload_axis_tready=s_eth_payload_axis_tready,
|
||||
s_eth_payload_axis_tlast=s_eth_payload_axis_tlast,
|
||||
|
@ -31,6 +31,11 @@ THE SOFTWARE.
|
||||
*/
|
||||
module test_arp_eth_rx;
|
||||
|
||||
// Parameters
|
||||
parameter DATA_WIDTH = 8;
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8);
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8);
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
@ -40,7 +45,8 @@ reg s_eth_hdr_valid = 0;
|
||||
reg [47:0] s_eth_dest_mac = 0;
|
||||
reg [47:0] s_eth_src_mac = 0;
|
||||
reg [15:0] s_eth_type = 0;
|
||||
reg [7:0] s_eth_payload_axis_tdata = 0;
|
||||
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
|
||||
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
|
||||
reg s_eth_payload_axis_tvalid = 0;
|
||||
reg s_eth_payload_axis_tlast = 0;
|
||||
reg s_eth_payload_axis_tuser = 0;
|
||||
@ -77,6 +83,7 @@ initial begin
|
||||
s_eth_src_mac,
|
||||
s_eth_type,
|
||||
s_eth_payload_axis_tdata,
|
||||
s_eth_payload_axis_tkeep,
|
||||
s_eth_payload_axis_tvalid,
|
||||
s_eth_payload_axis_tlast,
|
||||
s_eth_payload_axis_tuser,
|
||||
@ -108,7 +115,11 @@ initial begin
|
||||
$dumpvars(0, test_arp_eth_rx);
|
||||
end
|
||||
|
||||
arp_eth_rx
|
||||
arp_eth_rx #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_ENABLE(KEEP_ENABLE),
|
||||
.KEEP_WIDTH(KEEP_WIDTH)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
@ -119,6 +130,7 @@ UUT (
|
||||
.s_eth_src_mac(s_eth_src_mac),
|
||||
.s_eth_type(s_eth_type),
|
||||
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
|
||||
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
|
||||
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
|
||||
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
|
||||
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
|
||||
|
@ -29,8 +29,8 @@ import os
|
||||
import arp_ep
|
||||
import eth_ep
|
||||
|
||||
module = 'arp_eth_rx_64'
|
||||
testbench = 'test_%s' % module
|
||||
module = 'arp_eth_rx'
|
||||
testbench = 'test_%s_64' % module
|
||||
|
||||
srcs = []
|
||||
|
||||
@ -43,6 +43,11 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
DATA_WIDTH = 64
|
||||
KEEP_ENABLE = (DATA_WIDTH>8)
|
||||
KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
@ -52,8 +57,8 @@ def bench():
|
||||
s_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
s_eth_src_mac = Signal(intbv(0)[48:])
|
||||
s_eth_type = Signal(intbv(0)[16:])
|
||||
s_eth_payload_axis_tdata = Signal(intbv(0)[64:])
|
||||
s_eth_payload_axis_tkeep = Signal(intbv(0)[8:])
|
||||
s_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
s_eth_payload_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
s_eth_payload_axis_tvalid = Signal(bool(0))
|
||||
s_eth_payload_axis_tlast = Signal(bool(0))
|
||||
s_eth_payload_axis_tuser = Signal(bool(0))
|
||||
@ -259,14 +264,14 @@ def bench():
|
||||
source.send(test_frame.build_eth())
|
||||
yield clk.posedge
|
||||
|
||||
yield delay(16)
|
||||
yield delay(64)
|
||||
yield clk.posedge
|
||||
source_pause.next = True
|
||||
yield delay(32)
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
|
||||
yield delay(16)
|
||||
yield delay(64)
|
||||
yield clk.posedge
|
||||
sink_pause.next = True
|
||||
yield delay(32)
|
||||
|
@ -27,10 +27,15 @@ THE SOFTWARE.
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for arp_eth_rx_64
|
||||
* Testbench for arp_eth_rx
|
||||
*/
|
||||
module test_arp_eth_rx_64;
|
||||
|
||||
// Parameters
|
||||
parameter DATA_WIDTH = 64;
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8);
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8);
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
@ -40,8 +45,8 @@ reg s_eth_hdr_valid = 0;
|
||||
reg [47:0] s_eth_dest_mac = 0;
|
||||
reg [47:0] s_eth_src_mac = 0;
|
||||
reg [15:0] s_eth_type = 0;
|
||||
reg [63:0] s_eth_payload_axis_tdata = 0;
|
||||
reg [7:0] s_eth_payload_axis_tkeep = 0;
|
||||
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
|
||||
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
|
||||
reg s_eth_payload_axis_tvalid = 0;
|
||||
reg s_eth_payload_axis_tlast = 0;
|
||||
reg s_eth_payload_axis_tuser = 0;
|
||||
@ -110,7 +115,11 @@ initial begin
|
||||
$dumpvars(0, test_arp_eth_rx_64);
|
||||
end
|
||||
|
||||
arp_eth_rx_64
|
||||
arp_eth_rx #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_ENABLE(KEEP_ENABLE),
|
||||
.KEEP_WIDTH(KEEP_WIDTH)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
@ -43,6 +43,11 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
DATA_WIDTH = 8
|
||||
KEEP_ENABLE = (DATA_WIDTH>8)
|
||||
KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
@ -68,7 +73,8 @@ def bench():
|
||||
m_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
m_eth_src_mac = Signal(intbv(0)[48:])
|
||||
m_eth_type = Signal(intbv(0)[16:])
|
||||
m_eth_payload_axis_tdata = Signal(intbv(0)[8:])
|
||||
m_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
m_eth_payload_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
m_eth_payload_axis_tvalid = Signal(bool(0))
|
||||
m_eth_payload_axis_tlast = Signal(bool(0))
|
||||
m_eth_payload_axis_tuser = Signal(bool(0))
|
||||
@ -110,6 +116,7 @@ def bench():
|
||||
eth_src_mac=m_eth_src_mac,
|
||||
eth_type=m_eth_type,
|
||||
eth_payload_tdata=m_eth_payload_axis_tdata,
|
||||
eth_payload_tkeep=m_eth_payload_axis_tkeep,
|
||||
eth_payload_tvalid=m_eth_payload_axis_tvalid,
|
||||
eth_payload_tready=m_eth_payload_axis_tready,
|
||||
eth_payload_tlast=m_eth_payload_axis_tlast,
|
||||
@ -147,6 +154,7 @@ def bench():
|
||||
m_eth_src_mac=m_eth_src_mac,
|
||||
m_eth_type=m_eth_type,
|
||||
m_eth_payload_axis_tdata=m_eth_payload_axis_tdata,
|
||||
m_eth_payload_axis_tkeep=m_eth_payload_axis_tkeep,
|
||||
m_eth_payload_axis_tvalid=m_eth_payload_axis_tvalid,
|
||||
m_eth_payload_axis_tready=m_eth_payload_axis_tready,
|
||||
m_eth_payload_axis_tlast=m_eth_payload_axis_tlast,
|
||||
|
@ -31,6 +31,11 @@ THE SOFTWARE.
|
||||
*/
|
||||
module test_arp_eth_tx;
|
||||
|
||||
// Parameters
|
||||
parameter DATA_WIDTH = 8;
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8);
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8);
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
@ -56,7 +61,8 @@ wire m_eth_hdr_valid;
|
||||
wire [47:0] m_eth_dest_mac;
|
||||
wire [47:0] m_eth_src_mac;
|
||||
wire [15:0] m_eth_type;
|
||||
wire [7:0] m_eth_payload_axis_tdata;
|
||||
wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
|
||||
wire m_eth_payload_axis_tvalid;
|
||||
wire m_eth_payload_axis_tlast;
|
||||
wire m_eth_payload_axis_tuser;
|
||||
@ -89,6 +95,7 @@ initial begin
|
||||
m_eth_src_mac,
|
||||
m_eth_type,
|
||||
m_eth_payload_axis_tdata,
|
||||
m_eth_payload_axis_tkeep,
|
||||
m_eth_payload_axis_tvalid,
|
||||
m_eth_payload_axis_tlast,
|
||||
m_eth_payload_axis_tuser,
|
||||
@ -100,7 +107,11 @@ initial begin
|
||||
$dumpvars(0, test_arp_eth_tx);
|
||||
end
|
||||
|
||||
arp_eth_tx
|
||||
arp_eth_tx #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_ENABLE(KEEP_ENABLE),
|
||||
.KEEP_WIDTH(KEEP_WIDTH)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
@ -124,6 +135,7 @@ UUT (
|
||||
.m_eth_src_mac(m_eth_src_mac),
|
||||
.m_eth_type(m_eth_type),
|
||||
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
|
||||
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
|
||||
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
|
||||
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
|
||||
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
|
||||
|
@ -29,8 +29,8 @@ import os
|
||||
import eth_ep
|
||||
import arp_ep
|
||||
|
||||
module = 'arp_eth_tx_64'
|
||||
testbench = 'test_%s' % module
|
||||
module = 'arp_eth_tx'
|
||||
testbench = 'test_%s_64' % module
|
||||
|
||||
srcs = []
|
||||
|
||||
@ -43,6 +43,11 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
DATA_WIDTH = 64
|
||||
KEEP_ENABLE = (DATA_WIDTH>8)
|
||||
KEEP_WIDTH = (DATA_WIDTH/8)
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
@ -68,8 +73,8 @@ def bench():
|
||||
m_eth_dest_mac = Signal(intbv(0)[48:])
|
||||
m_eth_src_mac = Signal(intbv(0)[48:])
|
||||
m_eth_type = Signal(intbv(0)[16:])
|
||||
m_eth_payload_axis_tdata = Signal(intbv(0)[64:])
|
||||
m_eth_payload_axis_tkeep = Signal(intbv(0)[8:])
|
||||
m_eth_payload_axis_tdata = Signal(intbv(0)[DATA_WIDTH:])
|
||||
m_eth_payload_axis_tkeep = Signal(intbv(0)[KEEP_WIDTH:])
|
||||
m_eth_payload_axis_tvalid = Signal(bool(0))
|
||||
m_eth_payload_axis_tlast = Signal(bool(0))
|
||||
m_eth_payload_axis_tuser = Signal(bool(0))
|
||||
@ -221,7 +226,7 @@ def bench():
|
||||
source.send(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield delay(16)
|
||||
yield delay(64)
|
||||
yield clk.posedge
|
||||
sink_pause.next = True
|
||||
yield delay(32)
|
||||
|
@ -27,10 +27,15 @@ THE SOFTWARE.
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for arp_eth_tx_64
|
||||
* Testbench for arp_eth_tx
|
||||
*/
|
||||
module test_arp_eth_tx_64;
|
||||
|
||||
// Parameters
|
||||
parameter DATA_WIDTH = 64;
|
||||
parameter KEEP_ENABLE = (DATA_WIDTH>8);
|
||||
parameter KEEP_WIDTH = (DATA_WIDTH/8);
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
@ -56,8 +61,8 @@ wire m_eth_hdr_valid;
|
||||
wire [47:0] m_eth_dest_mac;
|
||||
wire [47:0] m_eth_src_mac;
|
||||
wire [15:0] m_eth_type;
|
||||
wire [63:0] m_eth_payload_axis_tdata;
|
||||
wire [7:0] m_eth_payload_axis_tkeep;
|
||||
wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
|
||||
wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
|
||||
wire m_eth_payload_axis_tvalid;
|
||||
wire m_eth_payload_axis_tlast;
|
||||
wire m_eth_payload_axis_tuser;
|
||||
@ -102,7 +107,11 @@ initial begin
|
||||
$dumpvars(0, test_arp_eth_tx_64);
|
||||
end
|
||||
|
||||
arp_eth_tx_64
|
||||
arp_eth_tx #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.KEEP_ENABLE(KEEP_ENABLE),
|
||||
.KEEP_WIDTH(KEEP_WIDTH)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
@ -39,10 +39,10 @@ srcs.append("../rtl/%s.v" % module)
|
||||
srcs.append("../rtl/ip_64.v")
|
||||
srcs.append("../rtl/ip_eth_rx_64.v")
|
||||
srcs.append("../rtl/ip_eth_tx_64.v")
|
||||
srcs.append("../rtl/arp_64.v")
|
||||
srcs.append("../rtl/arp.v")
|
||||
srcs.append("../rtl/arp_cache.v")
|
||||
srcs.append("../rtl/arp_eth_rx_64.v")
|
||||
srcs.append("../rtl/arp_eth_tx_64.v")
|
||||
srcs.append("../rtl/arp_eth_rx.v")
|
||||
srcs.append("../rtl/arp_eth_tx.v")
|
||||
srcs.append("../rtl/eth_arb_mux.v")
|
||||
srcs.append("../rtl/lfsr.v")
|
||||
srcs.append("../lib/axis/rtl/arbiter.v")
|
||||
|
@ -46,10 +46,10 @@ srcs.append("../rtl/ip_64.v")
|
||||
srcs.append("../rtl/ip_eth_rx_64.v")
|
||||
srcs.append("../rtl/ip_eth_tx_64.v")
|
||||
srcs.append("../rtl/ip_arb_mux.v")
|
||||
srcs.append("../rtl/arp_64.v")
|
||||
srcs.append("../rtl/arp.v")
|
||||
srcs.append("../rtl/arp_cache.v")
|
||||
srcs.append("../rtl/arp_eth_rx_64.v")
|
||||
srcs.append("../rtl/arp_eth_tx_64.v")
|
||||
srcs.append("../rtl/arp_eth_rx.v")
|
||||
srcs.append("../rtl/arp_eth_tx.v")
|
||||
srcs.append("../rtl/eth_arb_mux.v")
|
||||
srcs.append("../rtl/lfsr.v")
|
||||
srcs.append("../lib/axis/rtl/arbiter.v")
|
||||
|
Loading…
x
Reference in New Issue
Block a user