From 4ae9ec818cda186b7275b19231649b430d812a25 Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Tue, 22 Sep 2020 22:13:54 -0700
Subject: [PATCH] Add timing constraints for LED driver

---
 example/fb2CG/fpga_axi/fpga/Makefile |  1 +
 example/fb2CG/fpga_axi/led.tcl       | 12 ++++++++++++
 2 files changed, 13 insertions(+)
 create mode 100644 example/fb2CG/fpga_axi/led.tcl

diff --git a/example/fb2CG/fpga_axi/fpga/Makefile b/example/fb2CG/fpga_axi/fpga/Makefile
index 73644b7a1..e252a9a9d 100644
--- a/example/fb2CG/fpga_axi/fpga/Makefile
+++ b/example/fb2CG/fpga_axi/fpga/Makefile
@@ -30,6 +30,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
 
 # XDC files
 XDC_FILES = fpga.xdc
+XDC_FILES += led.tcl
 
 # IP
 IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
diff --git a/example/fb2CG/fpga_axi/led.tcl b/example/fb2CG/fpga_axi/led.tcl
new file mode 100644
index 000000000..e430903ef
--- /dev/null
+++ b/example/fb2CG/fpga_axi/led.tcl
@@ -0,0 +1,12 @@
+# Timing constraints for led_sreg_driver
+
+foreach inst [get_cells -hier -filter {(ORIG_REF_NAME == led_sreg_driver || REF_NAME == led_sreg_driver)}] {
+    puts "Inserting timing constraints for led_sreg_driver instance $inst"
+
+    set select_ffs [get_cells "$inst/led_sync_reg_1_reg[*] $inst/led_sync_reg_2_reg[*]"]
+
+    if {[llength $select_ffs]} {
+        set_property ASYNC_REG TRUE $select_ffs
+        set_false_path -from [all_registers] -to [get_cells "$inst/led_sync_reg_1_reg[*]"]
+    }
+}